diff options
| author | Tuan Phan <tphan@ventanamicro.com> | 2023-06-07 10:30:21 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-06-15 05:32:51 +0000 |
| commit | ea55bd8f66eeca5f4e80c3679bcf1b1007286b8a (patch) | |
| tree | 5f006c11a0409b290f073227e196a71510a467b1 | |
| parent | 4dba2a9d08653a25750c9c74822adb6003c38e77 (diff) | |
| download | edk2-ea55bd8f66eeca5f4e80c3679bcf1b1007286b8a.tar.gz | |
UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit
The timer compare register is 64-bit so simplifying the delay
function.
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
| -rw-r--r-- | MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c | 53 |
2 files changed, 23 insertions, 31 deletions
diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h index ee5c2ba603..6997de6cc0 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVImpl.h +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -20,6 +20,5 @@ Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
-#define RISCV_TIMER_COMPARE_BITS 32
#endif
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c index 9c8efc0f35..27d7276aaa 100644 --- a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c +++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c @@ -22,26 +22,19 @@ @param Delay A period of time to delay in ticks.
**/
+STATIC
VOID
InternalRiscVTimerDelay (
- IN UINT32 Delay
+ IN UINT64 Delay
)
{
- UINT32 Ticks;
- UINT32 Times;
-
- Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
- Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
- do {
- //
- // The target timer count is calculated here
- //
- Ticks = RiscVReadTimer () + Delay;
- Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
- while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
- CpuPause ();
- }
- } while (Times-- > 0);
+ UINT64 Ticks;
+
+ Ticks = RiscVReadTimer () + Delay;
+
+ while (RiscVReadTimer () <= Ticks) {
+ CpuPause ();
+ }
}
/**
@@ -61,13 +54,13 @@ MicroSecondDelay ( )
{
InternalRiscVTimerDelay (
- (UINT32)DivU64x32 (
- MultU64x32 (
- MicroSeconds,
- PcdGet64 (PcdCpuCoreCrystalClockFrequency)
- ),
- 1000000u
- )
+ DivU64x32 (
+ MultU64x32 (
+ MicroSeconds,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 1000000u
+ )
);
return MicroSeconds;
}
@@ -89,13 +82,13 @@ NanoSecondDelay ( )
{
InternalRiscVTimerDelay (
- (UINT32)DivU64x32 (
- MultU64x32 (
- NanoSeconds,
- PcdGet64 (PcdCpuCoreCrystalClockFrequency)
- ),
- 1000000000u
- )
+ DivU64x32 (
+ MultU64x32 (
+ NanoSeconds,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 1000000000u
+ )
);
return NanoSeconds;
}
|