diff options
| author | Dhaval <dhaval@rivosinc.com> | 2023-12-13 20:29:29 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-12-19 12:48:14 +0000 |
| commit | 26727c2ae2a8883b7f4be23c26b6209ea763c816 (patch) | |
| tree | af3ecdffb261840db0d01e46b602ab5d35a93e7c | |
| parent | 30faafd0247af0a6534caf2a6ac3231fa8e63d86 (diff) | |
| download | edk2-26727c2ae2a8883b7f4be23c26b6209ea763c816.tar.gz | |
MdePkg: Implement RISC-V Cache Management Operations
Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.
Notes:
1. CMO only supports block based Operations. Meaning cache
flush/invd/clean Operations are not available for the entire
range. In that case we fallback on fence.i instructions.
2. Operations are implemented using Opcodes to make them compiler
independent. binutils 2.39+ compilers support CMO instructions.
Test:
1. Ensured correct instructions are refelecting in asm
2. Qemu implements basic support for CMO operations in that it allwos
instructions without exceptions. Verified it works properly in
that sense.
3. SG2042Pkg implements CMO-like instructions. It was verified that
CpuFlushCpuDataCache works fine. This more of less
confirms that framework is alright.
4. TODO: Once Silicon is available with exact instructions, we will
further verify this.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Pedro Falcato <pedro.falcato@gmail.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Sunil V L <sunilvl@...>
Reviewed-by: Jingyu Li <jingyu.li01@...>
| -rw-r--r-- | MdePkg/Include/Library/BaseLib.h | 33 | ||||
| -rw-r--r-- | MdePkg/Include/RiscV64/RiscVasm.inc | 19 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/BaseLib.inf | 2 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S (renamed from MdePkg/Library/BaseLib/RiscV64/FlushCache.S) | 17 |
4 files changed, 70 insertions, 1 deletions
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index c5e7f6dff0..b71e47f41b 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -226,6 +226,39 @@ RiscVInvalidateDataCacheFenceAsm ( VOID
);
+/**
+ RISC-V flush cache block. Atomically perform a clean operation
+ followed by an invalidate operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheFlushCmoAsm (
+ IN UINTN
+ );
+
+/**
+Perform a write transfer to another cache or to memory if the
+data in the copy of the cache block have been modified by a store
+operation
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheCleanCmoAsm (
+ IN UINTN
+ );
+
+/**
+Deallocate the copy of the cache block
+
+**/
+VOID
+EFIAPI
+RiscVCpuCacheInvalCmoAsm (
+ IN UINTN
+ );
+
#endif // defined (MDE_CPU_RISCV64)
#if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Include/RiscV64/RiscVasm.inc b/MdePkg/Include/RiscV64/RiscVasm.inc new file mode 100644 index 0000000000..29de735885 --- /dev/null +++ b/MdePkg/Include/RiscV64/RiscVasm.inc @@ -0,0 +1,19 @@ +/*
+ *
+ * RISC-V cache operation encoding.
+ * Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ */
+
+.macro RISCVCMOFLUSH
+ .word 0x25200f
+.endm
+
+.macro RISCVCMOINVALIDATE
+ .word 0x05200f
+.endm
+
+.macro RISCVCMOCLEAN
+ .word 0x15200f
+.endm
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 03c7b02e82..5338938944 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -400,7 +400,7 @@ RiscV64/RiscVCpuBreakpoint.S | GCC
RiscV64/RiscVCpuPause.S | GCC
RiscV64/RiscVInterrupt.S | GCC
- RiscV64/FlushCache.S | GCC
+ RiscV64/RiscVCacheMgmt.S | GCC
RiscV64/CpuScratch.S | GCC
RiscV64/ReadTimer.S | GCC
RiscV64/RiscVMmu.S | GCC
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S index 8cfb850979..4752aa72d9 100644 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S @@ -3,10 +3,12 @@ // RISC-V cache operation.
//
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
+.include "RiscVasm.inc"
.align 3
ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
@@ -19,3 +21,18 @@ ASM_PFX(RiscVInvalidateInstCacheFenceAsm): ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
fence
ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheFlushCmoAsm)
+ASM_PFX (RiscVCpuCacheFlushCmoAsm):
+ RISCVCMOFLUSH
+ ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheCleanCmoAsm)
+ASM_PFX (RiscVCpuCacheCleanCmoAsm):
+ RISCVCMOCLEAN
+ ret
+
+ASM_GLOBAL ASM_PFX (RiscVCpuCacheInvalCmoAsm)
+ASM_PFX (RiscVCpuCacheInvalCmoAsm):
+ RISCVCMOINVALIDATE
+ ret
|