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| author | Yuquan Wang <wangyuquan1236@phytium.com.cn> | 2024-08-20 18:16:13 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2025-02-03 00:34:06 +0000 |
| commit | 074f61e4c66e6aaa9e160d3468dd9e40611fd2a1 (patch) | |
| tree | c56737284cbafb78459c95b03a42c73828110c27 | |
| parent | 62b0698309cdffa1ed11eca3ebc389e0cb452c70 (diff) | |
| download | edk2-074f61e4c66e6aaa9e160d3468dd9e40611fd2a1.tar.gz | |
MdePkg/IndustryStandard: add definitions for CXL CEDT
This adds #defines and struct typedefs for the various structure
types in the CXL Early Discovery Table (CEDT).
Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
| -rwxr-xr-x | MdePkg/Include/IndustryStandard/Cxl20.h | 41 | ||||
| -rw-r--r-- | MdePkg/Include/IndustryStandard/Cxl30.h | 59 | ||||
| -rw-r--r-- | MdePkg/Include/IndustryStandard/Cxl31.h | 47 |
3 files changed, 147 insertions, 0 deletions
diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h b/MdePkg/Include/IndustryStandard/Cxl20.h index 574f786881..641103d9b0 100755 --- a/MdePkg/Include/IndustryStandard/Cxl20.h +++ b/MdePkg/Include/IndustryStandard/Cxl20.h @@ -14,6 +14,7 @@ #define CXL20_H_
#include <IndustryStandard/Cxl11.h>
+#include <IndustryStandard/Acpi.h>
//
// CXL DVSEC IDs
@@ -103,6 +104,16 @@ #define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED 0x3
//
+// "CEDT" CXL Early Discovery Table
+// Compute Express Link Specification Revision 2.0 - Chapter 9.14.1
+//
+#define CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32 ('C', 'E', 'D', 'T')
+
+#define CXL_EARLY_DISCOVERY_TABLE_REVISION_01 0x1
+
+#define CEDT_TYPE_CHBS 0x0
+
+//
// Ensure proper structure formats
//
#pragma pack(1)
@@ -458,6 +469,36 @@ typedef union { UINT64 Uint64;
} CXL_MEMORY_DEVICE_STATUS_REGISTER;
+//
+// CEDT header
+// Compute Express Link Specification Revision 2.0 - Chapter 9.14.1.1
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+} CXL_EARLY_DISCOVERY_TABLE;
+
+//
+// Node header definition shared by all CEDT structure types
+//
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved;
+ UINT16 Length;
+} CEDT_STRUCTURE;
+
+//
+// Definition for CXL Host Bridge Structure (CHBS)
+// Compute Express Link Specification Revision 2.0 - Chapter 9.14.1.2
+//
+typedef struct {
+ CEDT_STRUCTURE Header;
+ UINT32 Uid;
+ UINT32 CxlVersion;
+ UINT32 Reserved;
+ UINT64 Base;
+ UINT64 Length;
+} CXL_HOST_BRIDGE_STRUCTURE;
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/Cxl30.h b/MdePkg/Include/IndustryStandard/Cxl30.h index 7a9a6d6940..2b8574355c 100644 --- a/MdePkg/Include/IndustryStandard/Cxl30.h +++ b/MdePkg/Include/IndustryStandard/Cxl30.h @@ -46,6 +46,14 @@ #define CXL_HDM_12_WAY_INTERLEAVING 0xA
//
+// "CEDT" CXL Early Discovery Table
+// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1
+//
+#define CEDT_TYPE_CFMWS 0x1
+#define CEDT_TYPE_CXIMS 0x2
+#define CEDT_TYPE_RDPAS 0x3
+
+//
// Ensure proper structure formats
//
#pragma pack(1)
@@ -311,6 +319,57 @@ typedef struct { CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS TimeoutAndIsolationStatus;
} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE;
+//
+// Definition for CXL Fixed Memory Window Structure (CFMWS)
+// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1.3
+//
+// The number of entries in TargetList (Interleave Target List) shall
+// match the Number of Interleave Ways (NIW). The current maximum is 16.
+//
+typedef struct {
+ CEDT_STRUCTURE Header;
+ UINT32 Reserved;
+ UINT64 BaseHpa;
+ UINT64 WindowSize;
+ UINT8 EncodedInterleaveWays;
+ UINT8 InterleaveArithmetic;
+ UINT16 Reserved1;
+ UINT32 Granularity;
+ UINT16 Restrictions;
+ UINT16 QtgId;
+ UINT32 TargetList[16];
+} CXL_FIXED_MEMORY_WINDOW_STRUCTURE;
+
+//
+// Definition for CXL XOR Interleave Math Structure (CXIMS)
+// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1.4
+//
+// The number of entries in XORMAPList depends on NIB. 4 is the current
+// maximum for 16-way interleaving.
+//
+typedef struct {
+ CEDT_STRUCTURE Header;
+ UINT16 Reserved;
+ UINT8 HBIG;
+ UINT8 NIB;
+ UINT64 XORMAPList[4];
+} CXL_XOR_INTERLEAVE_MATH_STRUCTURE;
+
+//
+// Definition for RCEC Downstream Port Association Structure (RDPAS)
+// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1.5
+//
+// The errata released at CXL 3.2 fixed that RCEC BDF field overlaps
+// Protocol Type field.
+//
+typedef struct {
+ CEDT_STRUCTURE Header;
+ UINT16 SegmentNumber;
+ UINT16 Bdf;
+ UINT64 BaseAddress;
+ UINT8 ProtocolType;
+} RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE;
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/Cxl31.h b/MdePkg/Include/IndustryStandard/Cxl31.h new file mode 100644 index 0000000000..1c40aa27fd --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl31.h @@ -0,0 +1,47 @@ +/** @file
+ CXL 3.1 definitions
+
+ This file contains the register definitions and firmware interface based
+ on the Compute Express Link (CXL) Specification Revision 3.1.
+
+ Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - Compute Express Link (CXL) Specification Revision 3.1.
+ (https://computeexpresslink.org/cxl-specification/)
+
+**/
+
+#ifndef CXL31_H_
+#define CXL31_H_
+
+#include <IndustryStandard/Cxl30.h>
+
+//
+// "CEDT" CXL Early Discovery Table
+// Compute Express Link Specification Revision 3.1 - Chapter 9.18.1
+//
+#define CXL_EARLY_DISCOVERY_TABLE_REVISION_02 0x2
+
+#define CEDT_TYPE_CSDS 0x4
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+//
+// Definition for CXL System Description Structure (CSDS)
+// Compute Express Link Specification Revision 3.1 - Chapter 9.18.6
+//
+typedef struct {
+ CEDT_STRUCTURE Header;
+ UINT16 Capabilities;
+ UINT16 Reserved;
+} CXL_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE;
+
+#pragma pack()
+
+#endif
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