diff options
| author | Kun Qin <kuqin@microsoft.com> | 2024-10-10 15:19:45 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-12-11 18:21:29 +0000 |
| commit | 957fcbe7a3396dbd568f685d6c967514bdfb59f1 (patch) | |
| tree | b8f9488d575a31396f731c81e26f295aa47c454b | |
| parent | 95972f966ebf4b61de8faf214809ef881f4ac129 (diff) | |
| download | edk2-957fcbe7a3396dbd568f685d6c967514bdfb59f1.tar.gz | |
ArmPkg: ArmGic: Cast CpuTarget to UINT32 for legacy GIC
The current code path supporting `PcdArmGicV3WithV2Legacy` will read 32
bit CPU target and try to program ARM_GIC_ICDIPTR. However, all these
operations are 32bit wide.
This change casts the CpuTarget variable to be UINT32 before calling
MMIO read.
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
| -rw-r--r-- | ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 41aec70481..71f8a4211e 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -374,7 +374,6 @@ GicV3DxeInitialize ( {
EFI_STATUS Status;
UINTN Index;
- UINT64 CpuTarget;
UINT64 MpId;
// Make sure the Interrupt Controller Protocol is not already installed in
@@ -406,6 +405,8 @@ GicV3DxeInitialize ( // Targets the interrupts to the Primary Cpu
if (FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {
+ UINT32 CpuTarget;
+
// Only Primary CPU will run this code. We can identify our GIC CPU ID by
// reading the GIC Distributor Target register. The 8 first
// GICD_ITARGETSRn are banked to each connected CPU. These 8 registers
@@ -428,6 +429,8 @@ GicV3DxeInitialize ( }
}
} else {
+ UINT64 CpuTarget;
+
MpId = ArmReadMpidr ();
CpuTarget = MpId &
(ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
|