diff options
| author | Dhaval <dhaval@rivosinc.com> | 2023-12-13 20:29:28 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-12-19 12:48:14 +0000 |
| commit | 30faafd0247af0a6534caf2a6ac3231fa8e63d86 (patch) | |
| tree | 02c7e7818dc32e1cb51c47d089f5e11068f20e8d | |
| parent | 286b30f517ef35ae2764f13f077f0f120372a286 (diff) | |
| download | edk2-30faafd0247af0a6534caf2a6ac3231fa8e63d86.tar.gz | |
MdePkg: Rename Cache Management Function To Clarify Fence Based Op
There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, rename the
function accordingly to add that clarity.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Pedro Falcato <pedro.falcato@gmail.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
| -rw-r--r-- | MdePkg/Include/Library/BaseLib.h | 4 | ||||
| -rw-r--r-- | MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 4 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 8 |
3 files changed, 8 insertions, 8 deletions
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 2c69c5f528..c5e7f6dff0 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -212,7 +212,7 @@ RiscVClearPendingTimerInterrupt ( **/
VOID
EFIAPI
-RiscVInvalidateInstCacheAsm (
+RiscVInvalidateInstCacheFenceAsm (
VOID
);
@@ -222,7 +222,7 @@ RiscVInvalidateInstCacheAsm ( **/
VOID
EFIAPI
-RiscVInvalidateDataCacheAsm (
+RiscVInvalidateDataCacheFenceAsm (
VOID
);
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c index d5efcf49a4..ac2a3c23a2 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c @@ -21,7 +21,7 @@ InvalidateInstructionCache ( VOID
)
{
- RiscVInvalidateInstCacheAsm ();
+ RiscVInvalidateInstCacheFenceAsm ();
}
/**
@@ -193,7 +193,7 @@ InvalidateDataCache ( VOID
)
{
- RiscVInvalidateDataCacheAsm ();
+ RiscVInvalidateDataCacheFenceAsm ();
}
/**
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S index 7c10fdd268..8cfb850979 100644 --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -9,13 +9,13 @@ //------------------------------------------------------------------------------
.align 3
-ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
-ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheFenceAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheFenceAsm)
-ASM_PFX(RiscVInvalidateInstCacheAsm):
+ASM_PFX(RiscVInvalidateInstCacheFenceAsm):
fence.i
ret
-ASM_PFX(RiscVInvalidateDataCacheAsm):
+ASM_PFX(RiscVInvalidateDataCacheFenceAsm):
fence
ret
|