diff options
| author | Ray Ni <ray.ni@intel.com> | 2022-07-14 18:00:47 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-09 07:08:05 +0000 |
| commit | 13a0471bfdcc1c7b18e182ca554d2ce98116e500 (patch) | |
| tree | 6df2991f58367a596a0dde27e0a2c458af37601d | |
| parent | bf334513b3eb02ef98e5b38e0b7b5d7408492fdd (diff) | |
| download | edk2-13a0471bfdcc1c7b18e182ca554d2ce98116e500.tar.gz | |
CpuPageTableLib: Refactor the logic
The patch replaces
LinearAddress + Offset == RegionStart
with
((LinearAddress + Offset) & RegionMask) == 0
The replace should not cause any behavior change.
Because:
1. In first loop of while when LinearAddress + Offset == RegionStart,
because the lower "BitStart" bits of RegionStart are all-zero,
all lower "BitStart" bits of (LinearAddress + Offset) are all-zero.
Because all lower "BitStart" bits of RegionMask is all-one and
bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0.
2. In following loops of the while, even RegionStart is increased
by RegionLength, the lower "BitStart" bits are still all-zero.
So the two expressions still semantically equal to each other.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
| -rw-r--r-- | UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index e23158c17e..5f751048a3 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -360,7 +360,7 @@ PageTableLibMapInLevel ( PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);
while (Offset < Length && Index < 512) {
SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
- if ((Level <= MaxLeafLevel) && (LinearAddress + Offset == RegionStart) && (SubLength == RegionLength)) {
+ if ((Level <= MaxLeafLevel) && (((LinearAddress + Offset) & RegionMask) == 0) && (SubLength == RegionLength)) {
//
// Create one entry mapping the entire region (1G, 2M or 4K).
//
|