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| author | Chasel Chiu <chasel.chiu@intel.com> | 2022-08-14 23:13:01 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-15 08:03:06 +0000 |
| commit | a2b61de2f6f6bbfb71c9430634f2ec365d82667b (patch) | |
| tree | 7b54fba550d9c93696f462e5279adf60a2b3dbfa | |
| parent | 803ed060ee2b22cc136ae97308d494a9d6716947 (diff) | |
| download | edk2-a2b61de2f6f6bbfb71c9430634f2ec365d82667b.tar.gz | |
IntelFsp2Pkg: FSPM_ARCH2_UPD mismatching bug.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4019
FSPM_ARCH2_UPD in FspApiEntryM.nasm was not up-to-date and
should be fixed for both IA32 and X64 builds.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 3 | ||||
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm index 5dada2af54..61ab4612a3 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -40,12 +40,13 @@ struc FSPM_UPD_COMMON_FSP24 .Revision: resb 1
.Reserved: resb 3
.Length resd 1
+ .NvsBufferPtr resq 1
.StackBase: resq 1
.StackSize: resq 1
.BootLoaderTolumSize: resd 1
.BootMode: resd 1
.FspEventHandler resq 1
- .Reserved1: resb 24
+ .Reserved1: resb 16
; }
.size:
endstruc
diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm index dacf515845..2d2f75b1f0 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm @@ -22,12 +22,13 @@ struc FSPM_UPD_COMMON_FSP24 .Revision: resb 1
.Reserved: resb 3
.Length resd 1
+ .NvsBufferPtr resq 1
.StackBase: resq 1
.StackSize: resq 1
.BootLoaderTolumSize: resd 1
.BootMode: resd 1
.FspEventHandler resq 1
- .Reserved1: resb 24
+ .Reserved1: resb 16
; }
.size:
endstruc
|