diff options
| author | Ray Ni <ray.ni@intel.com> | 2022-07-18 17:00:29 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-09 07:08:05 +0000 |
| commit | e9e2ecab2d931069d5f9afaae313e09d42bee6e9 (patch) | |
| tree | 6eb152cbb30bf0fc69fed9f0382b85a880e24ddb | |
| parent | 927113c83b4106aedf57fd1c8dc6dad5f1fe6a69 (diff) | |
| download | edk2-e9e2ecab2d931069d5f9afaae313e09d42bee6e9.tar.gz | |
CpuPageTableLib: define IA32_PAGE_LEVEL enum type internally
The change doesn't change functionality behavior.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
| -rw-r--r-- | UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h | 8 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 12 |
2 files changed, 14 insertions, 6 deletions
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h index 627f84e4e2..8d856d7c7e 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h @@ -20,6 +20,14 @@ #define REGION_LENGTH(l) LShiftU64 (1, (l) * 9 + 3)
+typedef enum {
+ Pte = 1,
+ Pde = 2,
+ Pdpte = 3,
+ Pml4 = 4,
+ Pml5 = 5
+} IA32_PAGE_LEVEL;
+
typedef struct {
UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 13af9a8cdd..37713ec659 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -245,8 +245,8 @@ PageTableLibMapInLevel ( IN BOOLEAN Modify,
IN VOID *Buffer,
IN OUT INTN *BufferSize,
- IN UINTN Level,
- IN UINTN MaxLeafLevel,
+ IN IA32_PAGE_LEVEL Level,
+ IN IA32_PAGE_LEVEL MaxLeafLevel,
IN UINT64 LinearAddress,
IN UINT64 Length,
IN UINT64 Offset,
@@ -572,8 +572,8 @@ PageTableMap ( IA32_PAGING_ENTRY TopPagingEntry;
INTN RequiredSize;
UINT64 MaxLinearAddress;
- UINTN MaxLevel;
- UINTN MaxLeafLevel;
+ IA32_PAGE_LEVEL MaxLevel;
+ IA32_PAGE_LEVEL MaxLeafLevel;
IA32_MAP_ATTRIBUTE ParentAttribute;
if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || (PagingMode >= PagingModeMax)) {
@@ -606,8 +606,8 @@ PageTableMap ( return RETURN_INVALID_PARAMETER;
}
- MaxLeafLevel = (UINT8)PagingMode;
- MaxLevel = (UINT8)(PagingMode >> 8);
+ MaxLeafLevel = (IA32_PAGE_LEVEL)(UINT8)PagingMode;
+ MaxLevel = (IA32_PAGE_LEVEL)(UINT8)(PagingMode >> 8);
MaxLinearAddress = LShiftU64 (1, 12 + MaxLevel * 9);
if ((LinearAddress > MaxLinearAddress) || (Length > MaxLinearAddress - LinearAddress)) {
|