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| author | Olivier Martin <olivier.martin@arm.com> | 2013-08-06 10:59:19 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-08-06 10:59:19 +0000 |
| commit | d6dc67ba1b592b08ef1c0ff2e327d8c4d33aea55 (patch) | |
| tree | 0a3b0e886334372c8864b53fa789f084a11556d8 /ArmPkg/ArmPkg.dec | |
| parent | 3cc033c51f62983cb13901bfd24a74f7aa241a24 (diff) | |
| download | edk2-d6dc67ba1b592b08ef1c0ff2e327d8c4d33aea55.tar.gz | |
ARM: Remove NSACR from the common code
NSACR (Non-Secure Access Control Register) is AArch32 specific.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/ArmPkg.dec')
| -rw-r--r-- | ArmPkg/ArmPkg.dec | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 3326e7b584..39f264251b 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -128,15 +128,7 @@ # - BIT9 : SIF - Secure Instruction Fetch
# 0x31 = NS | EA | FW
gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
-
- # Non Secure Access Control Register
- # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
- # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
- # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
- # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
- # 0xC00 = cp10 | cp11
- gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
-
+
# System Memory (DRAM): These PCDs define the region of in-built system memory
# Some platforms can get DRAM extensions, these additional regions will be declared
# to UEFI by ArmPLatformPlib
@@ -182,6 +174,14 @@ # The FDT blob must be loaded at a 64bit aligned address.
gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
+ # Non Secure Access Control Register
+ # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
+ # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
+ # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
+ # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
+ # 0xC00 = cp10 | cp11
+ gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
+
[PcdsFixedAtBuild.AARCH64]
# By default we do transition to EL2 non-secure mode with Stack for EL2.
# Mode Description Bits
|