diff options
author | Star Zeng <star.zeng@intel.com> | 2017-08-28 09:45:39 +0800 |
---|---|---|
committer | Star Zeng <star.zeng@intel.com> | 2017-08-28 17:19:53 +0800 |
commit | 51ce27fd8c583845480858eda503f38e8b42d619 (patch) | |
tree | ecc4f565b1cc1ac51fb5b04289e4067b08d9f2cd /UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | |
parent | dd4205f8ba41282c8afb4805aed3e34f16aaa7f2 (diff) | |
download | edk2-51ce27fd8c583845480858eda503f38e8b42d619.tar.gz |
UefiCpuPkg/PiSmmCpuDxeSmm: Centralize mPhysicalAddressBits definition
Originally (before 714c2603018a99a514c42c2b511c821f30ba9cdf),
mPhysicalAddressBits was only defined in X64 PageTbl.c, after
714c2603018a99a514c42c2b511c821f30ba9cdf, mPhysicalAddressBits is
also defined in Ia32 PageTbl.c, then mPhysicalAddressBits is used in
ConvertMemoryPageAttributes() for address check.
This patch is to centralize mPhysicalAddressBits definition to
PiSmmCpuDxeSmm.c from Ia32 and X64 PageTbl.c.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c')
-rwxr-xr-x | UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index 8e79642711..282d2e6981 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -114,6 +114,8 @@ SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL; EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
UINTN mSmmCpuSmramRangeCount;
+UINT8 mPhysicalAddressBits;
+
/**
Initialize IDT to setup exception handlers for SMM.
|