diff options
| author | Ray Ni <ray.ni@intel.com> | 2022-07-18 16:41:37 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-09 07:08:05 +0000 |
| commit | 927113c83b4106aedf57fd1c8dc6dad5f1fe6a69 (patch) | |
| tree | bb181ab175024bad4ef8cec139f890ebab1c8ee0 /UefiCpuPkg | |
| parent | 9f53fd4ba7ac4abe82365f310e0a4bcccc4448b3 (diff) | |
| download | edk2-927113c83b4106aedf57fd1c8dc6dad5f1fe6a69.tar.gz | |
CpuPageTableLib: Fix bug that wrongly requires extra size for mapping
With following paging structure to map
[2M-4K, 2M] as P = 1, RW = 0,
[2M, 4M] as P = 1, RW = 1:
PML4[0] -> PDPTE[0] -> PDE[0](RW = 0) -> PTE[255](P = 0, RW = 0)
-> PDE[1](RW = 1)
When a new request to map [2M-4K, 2M+4K] as P = 1, RW = 1,
CpuPageTableMap() wrongly requests 4K buffer size for the new mapping
request.
But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place,
for [2M, 2M+4K], no change is needed because PDE[1].RW = 1 already.
The change fixes the bug.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index b1ff14e2b0..13af9a8cdd 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -272,6 +272,7 @@ PageTableLibMapInLevel ( IA32_MAP_ATTRIBUTE ChildAttribute;
IA32_MAP_ATTRIBUTE ChildMask;
IA32_MAP_ATTRIBUTE CurrentMask;
+ IA32_MAP_ATTRIBUTE LocalParentAttribute;
ASSERT (Level != 0);
ASSERT ((Attribute != NULL) && (Mask != NULL));
@@ -284,6 +285,9 @@ PageTableLibMapInLevel ( NopAttribute.Bits.ReadWrite = 1;
NopAttribute.Bits.UserSupervisor = 1;
+ LocalParentAttribute.Uint64 = ParentAttribute->Uint64;
+ ParentAttribute = &LocalParentAttribute;
+
//
// ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne bits
// when Modify is FALSE.
@@ -420,7 +424,7 @@ PageTableLibMapInLevel ( }
if (IsPle (&PagingEntry[Index], Level)) {
- PageTableLibSetPle (Level - 1, &PagingEntry[Index], 0, &ChildAttribute, &ChildMask);
+ PageTableLibSetPle (Level, &PagingEntry[Index], 0, &ChildAttribute, &ChildMask);
} else {
PageTableLibSetPnle (&PagingEntry[Index].Pnle, &ChildAttribute, &ChildMask);
}
@@ -664,13 +668,6 @@ PageTableMap ( //
// Update the page table when the supplied buffer is sufficient.
//
- ParentAttribute.Uint64 = 0;
- ParentAttribute.Bits.PageTableBaseAddress = 1;
- ParentAttribute.Bits.Present = 1;
- ParentAttribute.Bits.ReadWrite = 1;
- ParentAttribute.Bits.UserSupervisor = 1;
- ParentAttribute.Bits.Nx = 0;
-
Status = PageTableLibMapInLevel (
&TopPagingEntry,
&ParentAttribute,
|