diff options
| author | Ray Ni <ray.ni@intel.com> | 2022-07-14 20:08:29 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-09 07:08:05 +0000 |
| commit | 9cb8974f06c6cc2545a66e696a58911122dec9fd (patch) | |
| tree | 02e9da1e6de12737b5cd0862c31c716aa4cb90ea /UefiCpuPkg | |
| parent | 13a0471bfdcc1c7b18e182ca554d2ce98116e500 (diff) | |
| download | edk2-9cb8974f06c6cc2545a66e696a58911122dec9fd.tar.gz | |
CpuPageTableLib: Split the page entry when LA is aligned but PA is not
When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.
The patch fixes the bug.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c index 5f751048a3..d02fd5efa2 100644 --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c @@ -360,7 +360,12 @@ PageTableLibMapInLevel ( PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);
while (Offset < Length && Index < 512) {
SubLength = MIN (Length - Offset, RegionStart + RegionLength - (LinearAddress + Offset));
- if ((Level <= MaxLeafLevel) && (((LinearAddress + Offset) & RegionMask) == 0) && (SubLength == RegionLength)) {
+ if ((Level <= MaxLeafLevel) &&
+ (((LinearAddress + Offset) & RegionMask) == 0) &&
+ (((IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & RegionMask) == 0) &&
+ (SubLength == RegionLength)
+ )
+ {
//
// Create one entry mapping the entire region (1G, 2M or 4K).
//
|