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authorWu, MingliangX <mingliangx.wu@intel.com>2023-08-21 16:50:25 +0800
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2023-08-30 10:26:38 +0000
commite8aa4c6546ad5b04a1100fa2618e424f58e354f5 (patch)
tree74402532196ac712729906f7debb104b0a66d5bb /UefiCpuPkg
parenta481c1114474160f53b1662fd3726b48c88ae82e (diff)
downloadedk2-e8aa4c6546ad5b04a1100fa2618e424f58e354f5.tar.gz
UefiCpuPkg/ResetVector: Cache Disable should not be set by default in CR0
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4511 With 64 bit build we are seeing the CD in control register CR 0 set. This causes the NEM to disabled for some specific bios profiles. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Wu, Mingliang <mingliangx.wu@intel.com>
Diffstat (limited to 'UefiCpuPkg')
-rw-r--r--UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm2
1 files changed, 1 insertions, 1 deletions
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
index f59fc6ead4..4af2e875c3 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm
@@ -7,7 +7,7 @@
;
;------------------------------------------------------------------------------
-%define SEC_DEFAULT_CR0 0x40000023
+%define SEC_DEFAULT_CR0 0x00000023
%define SEC_DEFAULT_CR4 0x640
BITS 16