diff options
Diffstat (limited to 'ArmPlatformPkg')
45 files changed, 1553 insertions, 702 deletions
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 7b5d7e6cb5..e8be550a8a 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -50,8 +50,6 @@ gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
[PcdsFeatureFlag.common]
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
-
# Disable the GOP controller on ExitBootServices(). By default the value is FALSE,
# we assume the OS will handle the FrameBuffer from the UEFI GOP information.
gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
@@ -63,7 +61,6 @@ # Stack for CPU Cores in Non Secure Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dsc b/ArmPlatformPkg/ArmPlatformPkg.dsc index ddd128f9e6..bc6f2b5ede 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dsc +++ b/ArmPlatformPkg/ArmPlatformPkg.dsc @@ -120,10 +120,10 @@ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ ArmPlatformPkg/Sec/Sec.inf
- ArmPlatformPkg/PrePi/PeiMPCore.inf
ArmPlatformPkg/PrePi/PeiUniCore.inf
+ ArmPlatformPkg/PeilessSec/PeilessSec.inf
ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf
diff --git a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c index d87ab3d3de..fc062204c0 100644 --- a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c +++ b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c @@ -177,13 +177,16 @@ Get ( EFI_STATUS Status;
UINTN Index, Offset, RegisterBase;
- Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
- ASSERT_EFI_ERROR (Status);
-
if (Value == NULL) {
return EFI_INVALID_PARAMETER;
}
+ Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
if (PL061GetPins (RegisterBase, GPIO_PIN_MASK (Offset)) != 0) {
*Value = 1;
} else {
@@ -223,7 +226,10 @@ Set ( UINTN Index, Offset, RegisterBase;
Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
- ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
switch (Mode) {
case GPIO_MODE_INPUT:
@@ -285,14 +291,17 @@ GetMode ( EFI_STATUS Status;
UINTN Index, Offset, RegisterBase;
- Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
- ASSERT_EFI_ERROR (Status);
-
// Check for errors
if (Mode == NULL) {
return EFI_INVALID_PARAMETER;
}
+ Status = PL061Locate (Gpio, &Index, &Offset, &RegisterBase);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
// Check if it is input or output
if (MmioRead8 (RegisterBase + PL061_GPIO_DIR_REG) & GPIO_PIN_MASK (Offset)) {
// Pin set to output
diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h index b5628ece56..2049e5ef60 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -220,7 +220,7 @@ typedef struct { @param[in] Handle Handle to the LCD device instance.
- @retval EFI_SUCCESS Plaform library initialized successfully.
+ @retval EFI_SUCCESS Platform library initialized successfully.
@retval !(EFI_SUCCESS) Other errors.
**/
EFI_STATUS
diff --git a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c index d01c910f6e..cea7ce2cc7 100644 --- a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c +++ b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c @@ -287,7 +287,7 @@ LcdInitialize ( return EFI_SUCCESS;
}
-/** Set ARM Mali DP in cofiguration mode.
+/** Set ARM Mali DP in configuration mode.
The ARM Mali DP must be in the configuration mode for
configuration of the H_INTERVALS, V_INTERVALS, SYNC_CONTROL
diff --git a/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.c b/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.c index ca48871993..8044730512 100644 --- a/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.c +++ b/ArmPlatformPkg/Library/LcdHwNullLib/LcdHwNullLib.c @@ -23,7 +23,7 @@ LcdIdentify ( VOID
)
{
- return EFI_SUCCESS;
+ return EFI_NOT_FOUND;
}
/**
diff --git a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c index 6ab3e99483..fb353cf2df 100644 --- a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c +++ b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c @@ -331,13 +331,13 @@ LibRtcInitialize ( EfiGcdMemoryTypeMemoryMappedIo,
mPL031RtcBase,
SIZE_4KB,
- EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME | EFI_MEMORY_XP
);
if (EFI_ERROR (Status)) {
return Status;
}
- Status = gDS->SetMemorySpaceAttributes (mPL031RtcBase, SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ Status = gDS->SetMemorySpaceAttributes (mPL031RtcBase, SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME | EFI_MEMORY_XP);
if (EFI_ERROR (Status)) {
return Status;
}
diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c index 07f9b0f6be..b0b0cd8a85 100644 --- a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -19,7 +19,7 @@ @retval EFI_SUCCESS Returns success if platform implements a
PL111 controller.
- @retval EFI_NOT_FOUND PL111 display controller not found the plaform.
+ @retval EFI_NOT_FOUND PL111 display controller not found the platform.
**/
EFI_STATUS
LcdIdentify (
@@ -71,9 +71,9 @@ LcdInitialize ( /** Set requested mode of the display.
- @param[in] ModeNumbe Display mode number.
+ @param[in] ModeNumber Display mode number.
- @retval EFI_SUCCESS Display mode set successfuly.
+ @retval EFI_SUCCESS Display mode set successfully.
@retval !(EFI_SUCCESS) Other errors.
**/
EFI_STATUS
diff --git a/ArmPlatformPkg/PeilessSec/AArch64/ArchPeilessSec.c b/ArmPlatformPkg/PeilessSec/AArch64/ArchPeilessSec.c new file mode 100644 index 0000000000..ccc9cde6d1 --- /dev/null +++ b/ArmPlatformPkg/PeilessSec/AArch64/ArchPeilessSec.c @@ -0,0 +1,37 @@ +/** @file
+
+ Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeilessSec.h"
+
+#include <AArch64/AArch64.h>
+
+/**
+ Architecture specific initialization routine.
+**/
+VOID
+ArchInitialize (
+ VOID
+ )
+{
+ // Enable Floating Point
+ if (FixedPcdGet32 (PcdVFPEnabled)) {
+ ArmEnableVFP ();
+ }
+
+ if (ArmReadCurrentEL () == AARCH64_EL2) {
+ // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2
+ ArmWriteHcr (ARM_HCR_TGE);
+
+ /* Enable Timer access for non-secure EL1 and EL0
+ The cnthctl_el2 register bits are architecturally
+ UNKNOWN on reset.
+ Disable event stream as it is not in use at this stage
+ */
+ ArmWriteCntHctl (CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN);
+ }
+}
diff --git a/ArmPlatformPkg/PeilessSec/AArch64/ModuleEntryPoint.S b/ArmPlatformPkg/PeilessSec/AArch64/ModuleEntryPoint.S new file mode 100644 index 0000000000..efb6c5ade9 --- /dev/null +++ b/ArmPlatformPkg/PeilessSec/AArch64/ModuleEntryPoint.S @@ -0,0 +1,89 @@ +//
+// Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+
+ASM_FUNC(_ModuleEntryPoint)
+ // Do early platform specific actions
+ bl ASM_PFX(ArmPlatformPeiBootAction)
+
+_SetSVCMode:
+// Check if we can install the stack at the top of the System Memory or if we need
+// to install the stacks at the bottom of the Firmware Device (case the FD is located
+// at the top of the DRAM)
+_SystemMemoryEndInit:
+ ldr x1, mSystemMemoryEnd
+
+_SetupStackPosition:
+ // r1 = SystemMemoryTop
+
+ // Calculate Top of the Firmware Device
+ MOV64 (x2, FixedPcdGet64(PcdFdBaseAddress))
+ MOV32 (x3, FixedPcdGet32(PcdFdSize) - 1)
+ sub x3, x3, #1
+ add x3, x3, x2 // x3 = FdTop = PcdFdBaseAddress + PcdFdSize
+
+ // UEFI Memory Size (stacks are allocated in this region)
+ MOV32 (x4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize))
+
+ //
+ // Reserve the memory for the UEFI region (contain stacks on its top)
+ //
+
+ // Calculate how much space there is between the top of the Firmware and the Top of the System Memory
+ subs x0, x1, x3 // x0 = SystemMemoryTop - FdTop
+ b.mi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when SEC is in XIP memory outside of the DRAM
+ cmp x0, x4
+ b.ge _SetupStack
+
+ // Case the top of stacks is the FdBaseAddress
+ mov x1, x2
+
+_SetupStack:
+ // x1 contains the top of the stack (and the UEFI Memory)
+
+ // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment
+ // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the
+ // top of the memory space)
+ adds x11, x1, #1
+ b.cs _SetupOverflowStack
+
+_SetupAlignedStack:
+ mov x1, x11
+ b _GetBaseUefiMemory
+
+_SetupOverflowStack:
+ // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE
+ // aligned (4KB)
+ and x1, x1, ~EFI_PAGE_MASK
+
+_GetBaseUefiMemory:
+ // Calculate the Base of the UEFI Memory
+ sub x0, x1, x4
+
+_GetStackBase:
+ // r1 = The top of the stack
+ mov sp, x1
+
+ // Stack for the primary core = PrimaryCoreStack
+ MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
+ sub x1, x1, x2
+
+ // Move sec startup address into a data register
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr x4, =ASM_PFX(CEntryPoint)
+
+ // Set the frame pointer to NULL so any backtraces terminate here
+ mov x29, xzr
+
+ // Jump to SEC C code
+ // x0 = UefiMemoryBase
+ // x1 = StacksBase
+ blr x4
+
+_NeverReturn:
+ b _NeverReturn
diff --git a/ArmPlatformPkg/PeilessSec/Arm/ArchPeilessSec.c b/ArmPlatformPkg/PeilessSec/Arm/ArchPeilessSec.c new file mode 100644 index 0000000000..3c3cef6925 --- /dev/null +++ b/ArmPlatformPkg/PeilessSec/Arm/ArchPeilessSec.c @@ -0,0 +1,25 @@ +/** @file
+
+ Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeilessSec.h"
+
+/**
+ Architecture specific initialization routine.
+**/
+VOID
+ArchInitialize (
+ VOID
+ )
+{
+ // Enable program flow prediction, if supported.
+ ArmEnableBranchPrediction ();
+
+ if (FixedPcdGet32 (PcdVFPEnabled)) {
+ ArmEnableVFP ();
+ }
+}
diff --git a/ArmPlatformPkg/PeilessSec/Arm/ModuleEntryPoint.S b/ArmPlatformPkg/PeilessSec/Arm/ModuleEntryPoint.S new file mode 100644 index 0000000000..ab5b023fa9 --- /dev/null +++ b/ArmPlatformPkg/PeilessSec/Arm/ModuleEntryPoint.S @@ -0,0 +1,96 @@ +//
+// Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLib.h>
+
+#include <Arm/AArch32.h>
+
+ASM_FUNC(_ModuleEntryPoint)
+ // Do early platform specific actions
+ bl ASM_PFX(ArmPlatformPeiBootAction)
+
+_SetSVCMode:
+ // Enter SVC mode, Disable FIQ and IRQ
+ mov r1, #(CPSR_MODE_SVC | CPSR_IRQ | CPSR_FIQ)
+ msr CPSR_c, r1
+
+// Check if we can install the stack at the top of the System Memory or if we need
+// to install the stacks at the bottom of the Firmware Device (case the FD is located
+// at the top of the DRAM)
+_SystemMemoryEndInit:
+ ADRL (r1, mSystemMemoryEnd)
+ ldrd r2, r3, [r1]
+ teq r3, #0
+ moveq r1, r2
+ mvnne r1, #0
+
+_SetupStackPosition:
+ // r1 = SystemMemoryTop
+
+ // Calculate Top of the Firmware Device
+ MOV32 (r2, FixedPcdGet32(PcdFdBaseAddress))
+ MOV32 (r3, FixedPcdGet32(PcdFdSize) - 1)
+ add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize
+
+ // UEFI Memory Size (stacks are allocated in this region)
+ MOV32 (r4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize))
+
+ //
+ // Reserve the memory for the UEFI region (contain stacks on its top)
+ //
+
+ // Calculate how much space there is between the top of the Firmware and the Top of the System Memory
+ subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop
+ bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when SEC is in XIP memory outside of the DRAM
+ cmp r0, r4
+ bge _SetupStack
+
+ // Case the top of stacks is the FdBaseAddress
+ mov r1, r2
+
+_SetupStack:
+ // r1 contains the top of the stack (and the UEFI Memory)
+
+ // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment
+ // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the
+ // top of the memory space)
+ adds r9, r1, #1
+ bcs _SetupOverflowStack
+
+_SetupAlignedStack:
+ mov r1, r9
+ b _GetBaseUefiMemory
+
+_SetupOverflowStack:
+ // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE
+ // aligned (4KB)
+ MOV32 (r9, ~EFI_PAGE_MASK & 0xFFFFFFFF)
+ and r1, r1, r9
+
+_GetBaseUefiMemory:
+ // Calculate the Base of the UEFI Memory
+ sub r0, r1, r4
+
+_GetStackBase:
+ // r1 = The top of the stack
+ mov sp, r1
+
+ // Stack for the primary core = PrimaryCoreStack
+ MOV32 (r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
+ sub r1, r1, r2
+
+ // Move sec startup address into a data register
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr r4, =ASM_PFX(CEntryPoint)
+
+ // Jump to SEC C code
+ // r0 = UefiMemoryBase
+ // r1 = StacksBase
+ blx r4
+
+_NeverReturn:
+ b _NeverReturn
diff --git a/ArmPlatformPkg/PeilessSec/PeilessSec.c b/ArmPlatformPkg/PeilessSec/PeilessSec.c new file mode 100644 index 0000000000..639c3744c9 --- /dev/null +++ b/ArmPlatformPkg/PeilessSec/PeilessSec.c @@ -0,0 +1,205 @@ +/** @file
+
+ Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeilessSec.h"
+
+#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) ||\
+ ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))
+
+UINT64 mSystemMemoryEnd = FixedPcdGet64 (PcdSystemMemoryBase) +
+ FixedPcdGet64 (PcdSystemMemorySize) - 1;
+
+/**
+ Obtain a PPI from the list of PPIs provided by the platform code.
+
+ @param[in] PpiGuid GUID of the PPI to obtain
+ @param[out] Ppi Address of GUID pointer to return the PPI
+
+ @return Whether the PPI was obtained successfully
+**/
+STATIC
+EFI_STATUS
+GetPlatformPpi (
+ IN EFI_GUID *PpiGuid,
+ OUT VOID **Ppi
+ )
+{
+ UINTN PpiListSize;
+ UINTN PpiListCount;
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ UINTN Index;
+
+ PpiListSize = 0;
+ ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
+ PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
+ for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
+ if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {
+ *Ppi = PpiList->Ppi;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ SEC main routine.
+
+ @param[in] UefiMemoryBase Start of the PI/UEFI memory region
+ @param[in] StackBase Start of the stack
+ @param[in] StartTimeStamp Timer value at start of execution
+**/
+STATIC
+VOID
+SecMain (
+ IN UINTN UefiMemoryBase,
+ IN UINTN StackBase,
+ IN UINT64 StartTimeStamp
+ )
+{
+ EFI_HOB_HANDOFF_INFO_TABLE *HobList;
+ ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
+ UINTN ArmCoreCount;
+ ARM_CORE_INFO *ArmCoreInfoTable;
+ EFI_STATUS Status;
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+ UINTN StacksSize;
+ FIRMWARE_SEC_PERFORMANCE Performance;
+
+ // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)
+ ASSERT (
+ IS_XIP () ||
+ ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&
+ ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd))
+ );
+
+ // Initialize the architecture specific bits
+ ArchInitialize ();
+
+ // Initialize the Serial Port
+ SerialPortInitialize ();
+ CharCount = AsciiSPrint (
+ Buffer,
+ sizeof (Buffer),
+ "UEFI firmware (version %s built at %a on %a)\n\r",
+ (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
+ __TIME__,
+ __DATE__
+ );
+ SerialPortWrite ((UINT8 *)Buffer, CharCount);
+
+ // Initialize the Debug Agent for Source Level Debugging
+ InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
+ SaveAndSetDebugTimerInterrupt (TRUE);
+
+ // Declare the PI/UEFI memory region
+ HobList = HobConstructor (
+ (VOID *)UefiMemoryBase,
+ FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
+ (VOID *)UefiMemoryBase,
+ (VOID *)StackBase // The top of the UEFI Memory is reserved for the stack
+ );
+ PrePeiSetHobList (HobList);
+
+ // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
+ Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
+ ASSERT_EFI_ERROR (Status);
+
+ // Create the Stacks HOB
+ StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
+ BuildStackHob (StackBase, StacksSize);
+
+ // TODO: Call CpuPei as a library
+ BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
+
+ if (ArmIsMpCore ()) {
+ // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
+ Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);
+
+ // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
+ ASSERT_EFI_ERROR (Status);
+
+ // Build the MP Core Info Table
+ ArmCoreCount = 0;
+ Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
+ if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {
+ // Build MPCore Info HOB
+ BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
+ }
+ }
+
+ // Store timer value logged at the beginning of firmware image execution
+ Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);
+
+ // Build SEC Performance Data Hob
+ BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));
+
+ // Set the Boot Mode
+ SetBootMode (ArmPlatformGetBootMode ());
+
+ // Initialize Platform HOBs (CpuHob and FvHob)
+ Status = PlatformPeim ();
+ ASSERT_EFI_ERROR (Status);
+
+ // Now, the HOB List has been initialized, we can register performance information
+ PERF_START (NULL, "PEI", NULL, StartTimeStamp);
+
+ // SEC phase needs to run library constructors by hand.
+ ProcessLibraryConstructorList ();
+
+ // Assume the FV that contains the SEC (our code) also contains a compressed FV.
+ Status = DecompressFirstFv ();
+ ASSERT_EFI_ERROR (Status);
+
+ // Load the DXE Core and transfer control to it
+ Status = LoadDxeCoreFromFv (NULL, 0);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ C entrypoint into the SEC driver.
+
+ @param[in] UefiMemoryBase Start of the PI/UEFI memory region
+ @param[in] StackBase Start of the stack
+**/
+VOID
+CEntryPoint (
+ IN UINTN UefiMemoryBase,
+ IN UINTN StackBase
+ )
+{
+ UINT64 StartTimeStamp;
+
+ // Initialize the platform specific controllers
+ ArmPlatformInitialize (ArmReadMpidr ());
+
+ if (PerformanceMeasurementEnabled ()) {
+ // We cannot call yet the PerformanceLib because the HOB List has not been initialized
+ StartTimeStamp = GetPerformanceCounter ();
+ } else {
+ StartTimeStamp = 0;
+ }
+
+ // Data Cache enabled on Primary core when MMU is enabled.
+ ArmDisableDataCache ();
+ // Invalidate instruction cache
+ ArmInvalidateInstructionCache ();
+ // Enable Instruction Caches on all cores.
+ ArmEnableInstructionCache ();
+
+ InvalidateDataCacheRange (
+ (VOID *)UefiMemoryBase,
+ FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
+ );
+
+ SecMain (UefiMemoryBase, StackBase, StartTimeStamp);
+
+ // DXE Core should always load and never return
+ ASSERT (FALSE);
+}
diff --git a/ArmPlatformPkg/PeilessSec/PeilessSec.h b/ArmPlatformPkg/PeilessSec/PeilessSec.h new file mode 100644 index 0000000000..70d78cafb0 --- /dev/null +++ b/ArmPlatformPkg/PeilessSec/PeilessSec.h @@ -0,0 +1,76 @@ +/** @file
+
+ Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PEILESSSEC_H_
+#define PEILESSSEC_H_
+
+#include <PiPei.h>
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PerformanceLib.h>
+#include <Library/PrePiHobListPointerLib.h>
+#include <Library/PrePiLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/TimerLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+#include <Ppi/GuidedSectionExtraction.h>
+#include <Ppi/SecPerformance.h>
+
+extern UINT64 mSystemMemoryEnd;
+
+/**
+ Entrypoint of the memory PEIM driver.
+
+ @param[in] UefiMemoryBase The base of the PI/UEFI memory region
+ @param[in[ UefiMemorySize The size of the PI/UEFI memory region
+
+ @return Whether the memory PEIM driver executed successfully
+**/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ );
+
+/**
+ Entrypoint of platform PEIM driver.
+
+ @return Whether the platform PEIM driver executed successfully
+**/
+EFI_STATUS
+EFIAPI
+PlatformPeim (
+ VOID
+ );
+
+/**
+ Populate and install the memory type information HOB.
+**/
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+/**
+ Architecture specific initialization routine.
+**/
+VOID
+ArchInitialize (
+ VOID
+ );
+
+#endif /* PEILESSSEC_H_ */
diff --git a/ArmPlatformPkg/PeilessSec/PeilessSec.inf b/ArmPlatformPkg/PeilessSec/PeilessSec.inf new file mode 100644 index 0000000000..7ceeb74f69 --- /dev/null +++ b/ArmPlatformPkg/PeilessSec/PeilessSec.inf @@ -0,0 +1,78 @@ +## @file
+# SEC driver for PEI-less ARM platforms.
+#
+# Copyright (C) 2015 Hewlett-Packard Development Company, L.P.<BR>
+# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 1.30
+ BASE_NAME = PeilessSec
+ FILE_GUID = d90b03a8-2df5-4174-9ec1-c6e5b12b334b
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+
+[Sources]
+ PeilessSec.h
+ PeilessSec.c
+
+[Sources.ARM]
+ Arm/ArchPeilessSec.c
+ Arm/ModuleEntryPoint.S
+
+[Sources.AArch64]
+ AArch64/ArchPeilessSec.c
+ AArch64/ModuleEntryPoint.S
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ ArmPlatformLib
+ BaseMemoryLib
+ CacheMaintenanceLib
+ DebugAgentLib
+ DebugLib
+ HobLib
+ MemoryInitPeiLib
+ PerformanceLib
+ PlatformPeiLib
+ PrePiHobListPointerLib
+ PrePiLib
+ PrintLib
+ SerialPortLib
+ TimerLib
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[Guids]
+ gArmMpCoreInfoGuid
+ gEfiFirmwarePerformanceGuid
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+ gArmTokenSpaceGuid.PcdFvSize
+ gArmTokenSpaceGuid.PcdVFPEnabled
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S b/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S index ffb643a56d..d0d6bc44f7 100644 --- a/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S +++ b/ArmPlatformPkg/PrePeiCore/AArch64/Exception.S @@ -5,7 +5,7 @@ #
#
-#include <Chipset/AArch64.h>
+#include <AArch64/AArch64.h>
#include <AsmMacroIoLibV8.h>
#include <Base.h>
#include <AutoGen.h>
diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S b/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S index 2a604b719b..9b81b96a49 100644 --- a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S +++ b/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S @@ -6,7 +6,7 @@ #=======================================================================================
#include <AsmMacroIoLibV8.h>
-#include <Chipset/AArch64.h>
+#include <AArch64/AArch64.h>
// Setup EL1 while in EL1
ASM_FUNC(SetupExceptionLevel1)
diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S b/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S index 8ecec234bf..1c1054304a 100644 --- a/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S +++ b/ArmPlatformPkg/PrePeiCore/AArch64/PrePeiCoreEntryPoint.S @@ -30,41 +30,23 @@ ASM_FUNC(_ModuleEntryPoint) b ASM_PFX(MainEntryPoint)
ASM_PFX(MainEntryPoint):
- // Identify CPU ID
- bl ASM_PFX(ArmReadMpidr)
- // Keep a copy of the MpId register value
- mov x5, x0
-
- // Is it the Primary Core ?
- bl ASM_PFX(ArmPlatformIsPrimaryCore)
-
// Get the top of the primary stacks (and the base of the secondary stacks)
MOV64 (x1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))
- // x0 is equal to 1 if I am the primary core
- cmp x0, #1
- b.eq _SetupPrimaryCoreStack
-
-_SetupSecondaryCoreStack:
- // x1 contains the base of the secondary stacks
-
- // Get the Core Position
- mov x6, x1 // Save base of the secondary stacks
- mov x0, x5
- bl ASM_PFX(ArmPlatformGetCorePosition)
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
- add x0, x0, #1
+ // Set up the stack pointer
+ mov sp, x1
- // StackOffset = CorePos * StackSize
- MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
- mul x0, x0, x2
- // SP = StackBase + StackOffset
- add sp, x6, x0
+ // Apply the init value to the entire stack
+ MOV64 (x8, FixedPcdGet64 (PcdCPUCoresStackBase))
+ MOV64 (x9, FixedPcdGet32 (PcdInitValueInTempStack) |\
+ FixedPcdGet32 (PcdInitValueInTempStack) << 32)
+0:stp x9, x9, [x8], #16
+ cmp x8, x1
+ b.lt 0b
-_PrepareArguments:
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
MOV64 (x2, FixedPcdGet64(PcdFvBaseAddress))
- ldr x1, [x2, #8]
+ ldr x0, [x2, #8]
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias)
@@ -74,17 +56,6 @@ _PrepareArguments: mov x29, xzr
// Jump to PrePeiCore C code
- // x0 = mp_id
- // x1 = pei_core_address
+ // x0 = pei_core_address
mov x0, x5
blr x3
-
-_SetupPrimaryCoreStack:
- mov sp, x1
- MOV64 (x8, FixedPcdGet64 (PcdCPUCoresStackBase))
- MOV64 (x9, FixedPcdGet32 (PcdInitValueInTempStack) |\
- FixedPcdGet32 (PcdInitValueInTempStack) << 32)
-0:stp x9, x9, [x8], #16
- cmp x8, x1
- b.lt 0b
- b _PrepareArguments
diff --git a/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.S b/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.S index 1c9d1b5193..b3c67234e9 100644 --- a/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.S +++ b/ArmPlatformPkg/PrePeiCore/Arm/PrePeiCoreEntryPoint.S @@ -11,63 +11,30 @@ ASM_FUNC(_ModuleEntryPoint) // Do early platform specific actions
bl ASM_PFX(ArmPlatformPeiBootAction)
- // Identify CPU ID
- bl ASM_PFX(ArmReadMpidr)
- // Keep a copy of the MpId register value
- mov r5, r0
-
- // Is it the Primary Core ?
- bl ASM_PFX(ArmPlatformIsPrimaryCore)
-
// Get the top of the primary stacks (and the base of the secondary stacks)
MOV32 (r1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))
- // r0 is equal to 1 if I am the primary core
- cmp r0, #1
- beq _SetupPrimaryCoreStack
-
-_SetupSecondaryCoreStack:
- // r1 contains the base of the secondary stacks
-
- // Get the Core Position
- mov r6, r1 // Save base of the secondary stacks
- mov r0, r5
- bl ASM_PFX(ArmPlatformGetCorePosition)
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
- add r0, r0, #1
+ // Set up the stack pointer
+ mov sp, r1
- // StackOffset = CorePos * StackSize
- MOV32 (r2, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
- mul r0, r0, r2
- // SP = StackBase + StackOffset
- add sp, r6, r0
+ // Apply the init value to the entire stack
+ MOV32 (r8, FixedPcdGet64 (PcdCPUCoresStackBase))
+ MOV32 (r9, FixedPcdGet32 (PcdInitValueInTempStack))
+ mov r10, r9
+ mov r11, r9
+ mov r12, r9
+0:stm r8!, {r9-r12}
+ cmp r8, r1
+ blt 0b
-_PrepareArguments:
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
MOV32 (r2, FixedPcdGet32(PcdFvBaseAddress))
- ldr r1, [r2, #4]
+ ldr r0, [r2, #4]
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias)
ldr r3, =ASM_PFX(CEntryPoint)
// Jump to PrePeiCore C code
- // r0 = mp_id
- // r1 = pei_core_address
- mov r0, r5
+ // r0 = pei_core_address
blx r3
-
-_SetupPrimaryCoreStack:
- mov sp, r1
- MOV32 (r8, FixedPcdGet64 (PcdCPUCoresStackBase))
- MOV32 (r9, FixedPcdGet32 (PcdInitValueInTempStack))
- mov r10, r9
- mov r11, r9
- mov r12, r9
-0:stm r8!, {r9-r12}
- cmp r8, r1
- blt 0b
- b _PrepareArguments
-
-_NeverReturn:
- b _NeverReturn
diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c deleted file mode 100644 index b5d0d3a644..0000000000 --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c +++ /dev/null @@ -1,153 +0,0 @@ -/** @file
-
- Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include <Library/ArmGicLib.h>
-
-#include <Ppi/ArmMpCoreInfo.h>
-
-#include "PrePeiCore.h"
-
-/*
- * This is the main function for secondary cores. They loop around until a non Null value is written to
- * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
- * Note:The secondary cores, while executing secondary_main, assumes that:
- * : SGI 0 is configured as Non-secure interrupt
- * : Priority Mask is configured to allow SGI 0
- * : Interrupt Distributor and CPU interfaces are enabled
- *
- */
-VOID
-EFIAPI
-SecondaryMain (
- IN UINTN MpId
- )
-{
- EFI_STATUS Status;
- UINTN PpiListSize;
- UINTN PpiListCount;
- EFI_PEI_PPI_DESCRIPTOR *PpiList;
- ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
- UINTN Index;
- UINTN ArmCoreCount;
- ARM_CORE_INFO *ArmCoreInfoTable;
- UINT32 ClusterId;
- UINT32 CoreId;
-
- VOID (*SecondaryStart)(
- VOID
- );
- UINTN SecondaryEntryAddr;
- UINTN AcknowledgeInterrupt;
- UINTN InterruptId;
-
- ClusterId = GET_CLUSTER_ID (MpId);
- CoreId = GET_CORE_ID (MpId);
-
- // Get the gArmMpCoreInfoPpiGuid
- PpiListSize = 0;
- ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
- PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
- for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
- if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
- break;
- }
- }
-
- // On MP Core Platform we must implement the ARM MP Core Info PPI
- ASSERT (Index != PpiListCount);
-
- ArmMpCoreInfoPpi = PpiList->Ppi;
- ArmCoreCount = 0;
- Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
- ASSERT_EFI_ERROR (Status);
-
- // Find the core in the ArmCoreTable
- for (Index = 0; Index < ArmCoreCount; Index++) {
- if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr) == ClusterId) &&
- (GET_MPIDR_AFF0 (ArmCoreInfoTable[Index].Mpidr) == CoreId))
- {
- break;
- }
- }
-
- // The ARM Core Info Table must define every core
- ASSERT (Index != ArmCoreCount);
-
- // Clear Secondary cores MailBox
- MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
-
- do {
- ArmCallWFI ();
-
- // Read the Mailbox
- SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
-
- // Acknowledge the interrupt and send End of Interrupt signal.
- AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);
- // Check if it is a valid interrupt ID
- if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {
- // Got a valid SGI number hence signal End of Interrupt
- ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
- }
- } while (SecondaryEntryAddr == 0);
-
- // Jump to secondary core entry point.
- SecondaryStart = (VOID (*)()) SecondaryEntryAddr;
- SecondaryStart ();
-
- // The secondaries shouldn't reach here
- ASSERT (FALSE);
-}
-
-VOID
-EFIAPI
-PrimaryMain (
- IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
- )
-{
- EFI_SEC_PEI_HAND_OFF SecCoreData;
- UINTN PpiListSize;
- EFI_PEI_PPI_DESCRIPTOR *PpiList;
- UINTN TemporaryRamBase;
- UINTN TemporaryRamSize;
-
- CreatePpiList (&PpiListSize, &PpiList);
-
- // Enable the GIC Distributor
- ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));
-
- // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
- if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
- // Sending SGI to all the Secondary CPU interfaces
- ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
- }
-
- // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
- // the base of the primary core stack
- PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);
- TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
- TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
-
- //
- // Bind this information into the SEC hand-off state
- // Note: this must be in sync with the stuff in the asm file
- // Note also: HOBs (pei temp ram) MUST be above stack
- //
- SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
- SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
- SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
- SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
- SecCoreData.TemporaryRamSize = TemporaryRamSize;
- SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
- SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
- SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
- SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
-
- // Jump to PEI core entry point
- PeiCoreEntryPoint (&SecCoreData, PpiList);
-}
diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c index 1c2580eb92..3d3c6caaa3 100644 --- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c @@ -10,15 +10,6 @@ VOID
EFIAPI
-SecondaryMain (
- IN UINTN MpId
- )
-{
- ASSERT (FALSE);
-}
-
-VOID
-EFIAPI
PrimaryMain (
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
)
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index 42a7ccc9c6..cbaccbbad9 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -81,7 +81,6 @@ PrintFirmwareVersion ( VOID
CEntryPoint (
- IN UINTN MpId,
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
)
{
@@ -117,26 +116,21 @@ CEntryPoint ( // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
- // If not primary Jump to Secondary Main
- if (ArmPlatformIsPrimaryCore (MpId)) {
- // Invoke "ProcessLibraryConstructorList" to have all library constructors
- // called.
- ProcessLibraryConstructorList ();
+ // Invoke "ProcessLibraryConstructorList" to have all library constructors
+ // called.
+ ProcessLibraryConstructorList ();
- PrintFirmwareVersion ();
+ PrintFirmwareVersion ();
- // Initialize the Debug Agent for Source Level Debugging
- InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
- SaveAndSetDebugTimerInterrupt (TRUE);
+ // Initialize the Debug Agent for Source Level Debugging
+ InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
+ SaveAndSetDebugTimerInterrupt (TRUE);
- // Initialize the platform specific controllers
- ArmPlatformInitialize (MpId);
+ // Initialize the platform specific controllers
+ ArmPlatformInitialize (ArmReadMpidr ());
- // Goto primary Main.
- PrimaryMain (PeiCoreEntryPoint);
- } else {
- SecondaryMain (MpId);
- }
+ // Goto primary Main.
+ PrimaryMain (PeiCoreEntryPoint);
// PEI Core should always load and never return
ASSERT (FALSE);
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h index fbf6207db8..966b0e7eee 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h @@ -52,21 +52,6 @@ PrimaryMain ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
);
-/*
- * This is the main function for secondary cores. They loop around until a non Null value is written to
- * SYS_FLAGS register.The SYS_FLAGS register is platform specific.
- * Note:The secondary cores, while executing secondary_main, assumes that:
- * : SGI 0 is configured as Non-secure interrupt
- * : Priority Mask is configured to allow SGI 0
- * : Interrupt Distributor and CPU interfaces are enabled
- *
- */
-VOID
-EFIAPI
-SecondaryMain (
- IN UINTN MpId
- );
-
VOID
PeiCommonExceptionEntry (
IN UINT32 Entry,
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf index 1d50b4d0b5..772bd14db0 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf @@ -55,9 +55,6 @@ [Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
-[FeaturePcd]
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
-
[FixedPcd]
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
@@ -65,6 +62,5 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize
gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack
diff --git a/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c b/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c index 296b029e08..27a85049fa 100644 --- a/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c +++ b/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c @@ -8,7 +8,7 @@ #include "PrePi.h"
-#include <Chipset/AArch64.h>
+#include <AArch64/AArch64.h>
VOID
ArchInitialize (
diff --git a/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S b/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S index e3aa546897..c45fc5f400 100644 --- a/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S +++ b/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S @@ -11,11 +11,6 @@ ASM_FUNC(_ModuleEntryPoint) // Do early platform specific actions
bl ASM_PFX(ArmPlatformPeiBootAction)
- // Get ID of this CPU in multi-core system
- bl ASM_PFX(ArmReadMpidr)
- // Keep a copy of the MpId register value
- mov x10, x0
-
_SetSVCMode:
// Check if we can install the stack at the top of the System Memory or if we need
// to install the stacks at the bottom of the Firmware Device (case the FD is located
@@ -71,31 +66,16 @@ _GetBaseUefiMemory: sub x11, x1, x4
_GetStackBase:
- // r1 = The top of the Mpcore Stacks
+ // r1 = The top of the stack
+ mov sp, x1
+
// Stack for the primary core = PrimaryCoreStack
MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
sub x12, x1, x2
- // Stack for the secondary core = Number of Cores - 1
- MOV32 (x1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
- sub x12, x12, x1
-
- // x12 = The base of the MpCore Stacks (primary stack & secondary stacks)
- mov x0, x12
- mov x1, x10
- //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)
- MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
- MOV32 (x3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
- bl ASM_PFX(ArmPlatformStackSet)
-
- // Is it the Primary Core ?
- mov x0, x10
- bl ASM_PFX(ArmPlatformIsPrimaryCore)
- cmp x0, #1
- bne _PrepareArguments
+ // Get ID of this CPU in multi-core system
+ bl ASM_PFX(ArmReadMpidr)
-_PrepareArguments:
- mov x0, x10
mov x1, x11
mov x2, x12
diff --git a/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.S b/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.S index 6709dad0b9..c87f94689c 100644 --- a/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.S +++ b/ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.S @@ -7,17 +7,12 @@ #include <AsmMacroIoLib.h>
-#include <Chipset/ArmV7.h>
+#include <Arm/AArch32.h>
ASM_FUNC(_ModuleEntryPoint)
// Do early platform specific actions
bl ASM_PFX(ArmPlatformPeiBootAction)
- // Get ID of this CPU in multi-core system
- bl ASM_PFX(ArmReadMpidr)
- // Keep a copy of the MpId register value
- mov r8, r0
-
_SetSVCMode:
// Enter SVC mode, Disable FIQ and IRQ
mov r1, #(CPSR_MODE_SVC | CPSR_IRQ | CPSR_FIQ)
@@ -81,34 +76,18 @@ _GetBaseUefiMemory: sub r9, r1, r4
_GetStackBase:
- // r1 = The top of the Mpcore Stacks
+ // r1 = The top of the stack
+ mov sp, r1
+
// Stack for the primary core = PrimaryCoreStack
MOV32 (r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
sub r10, r1, r2
- // Stack for the secondary core = Number of Cores - 1
- MOV32 (r1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
- sub r10, r10, r1
-
- // r10 = The base of the MpCore Stacks (primary stack & secondary stacks)
- mov r0, r10
- mov r1, r8
- //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)
- MOV32 (r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))
- MOV32 (r3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))
- bl ASM_PFX(ArmPlatformStackSet)
-
- // Is it the Primary Core ?
- mov r0, r8
- bl ASM_PFX(ArmPlatformIsPrimaryCore)
- cmp r0, #1
- bne _PrepareArguments
+ // Get ID of this CPU in multi-core system
+ bl ASM_PFX(ArmReadMpidr)
-_PrepareArguments:
- mov r0, r8
mov r1, r9
mov r2, r10
- mov r3, sp
// Move sec startup address into a data register
// Ensure we're jumping to FV version of the code (not boot remapped alias)
diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c b/ArmPlatformPkg/PrePi/MainMPCore.c deleted file mode 100644 index 68a7c13298..0000000000 --- a/ArmPlatformPkg/PrePi/MainMPCore.c +++ /dev/null @@ -1,104 +0,0 @@ -/** @file
-
- Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "PrePi.h"
-
-#include <Library/ArmGicLib.h>
-
-#include <Ppi/ArmMpCoreInfo.h>
-
-VOID
-PrimaryMain (
- IN UINTN UefiMemoryBase,
- IN UINTN StacksBase,
- IN UINT64 StartTimeStamp
- )
-{
- // Enable the GIC Distributor
- ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));
-
- // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization
- if (!FixedPcdGet32 (PcdSendSgiToBringUpSecondaryCores)) {
- // Sending SGI to all the Secondary CPU interfaces
- ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
- }
-
- PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
-
- // We must never return
- ASSERT (FALSE);
-}
-
-VOID
-SecondaryMain (
- IN UINTN MpId
- )
-{
- EFI_STATUS Status;
- ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
- UINTN Index;
- UINTN ArmCoreCount;
- ARM_CORE_INFO *ArmCoreInfoTable;
- UINT32 ClusterId;
- UINT32 CoreId;
-
- VOID (*SecondaryStart)(
- VOID
- );
- UINTN SecondaryEntryAddr;
- UINTN AcknowledgeInterrupt;
- UINTN InterruptId;
-
- ClusterId = GET_CLUSTER_ID (MpId);
- CoreId = GET_CORE_ID (MpId);
-
- // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
- Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);
- ASSERT_EFI_ERROR (Status);
-
- ArmCoreCount = 0;
- Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
- ASSERT_EFI_ERROR (Status);
-
- // Find the core in the ArmCoreTable
- for (Index = 0; Index < ArmCoreCount; Index++) {
- if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr) == ClusterId) &&
- (GET_MPIDR_AFF0 (ArmCoreInfoTable[Index].Mpidr) == CoreId))
- {
- break;
- }
- }
-
- // The ARM Core Info Table must define every core
- ASSERT (Index != ArmCoreCount);
-
- // Clear Secondary cores MailBox
- MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
-
- do {
- ArmCallWFI ();
-
- // Read the Mailbox
- SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
-
- // Acknowledge the interrupt and send End of Interrupt signal.
- AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);
- // Check if it is a valid interrupt ID
- if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {
- // Got a valid SGI number hence signal End of Interrupt
- ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
- }
- } while (SecondaryEntryAddr == 0);
-
- // Jump to secondary core entry point.
- SecondaryStart = (VOID (*)()) SecondaryEntryAddr;
- SecondaryStart ();
-
- // The secondaries shouldn't reach here
- ASSERT (FALSE);
-}
diff --git a/ArmPlatformPkg/PrePi/MainUniCore.c b/ArmPlatformPkg/PrePi/MainUniCore.c deleted file mode 100644 index 6162d1241f..0000000000 --- a/ArmPlatformPkg/PrePi/MainUniCore.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @file
-
- Copyright (c) 2011, ARM Limited. All rights reserved.
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "PrePi.h"
-
-VOID
-PrimaryMain (
- IN UINTN UefiMemoryBase,
- IN UINTN StacksBase,
- IN UINT64 StartTimeStamp
- )
-{
- PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
-
- // We must never return
- ASSERT (FALSE);
-}
-
-VOID
-SecondaryMain (
- IN UINTN MpId
- )
-{
- // We must never get into this function on UniCore system
- ASSERT (FALSE);
-}
diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiMPCore.inf deleted file mode 100644 index 0b13b72353..0000000000 --- a/ArmPlatformPkg/PrePi/PeiMPCore.inf +++ /dev/null @@ -1,106 +0,0 @@ -#/** @file
-#
-# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>
-# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-#**/
-
-[Defines]
- INF_VERSION = 1.30
- BASE_NAME = ArmPlatformPrePiMPCore
- FILE_GUID = d959e387-7b91-452c-90e0-a1dbac90ddb8
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
-
-[Sources]
- PrePi.h
- PrePi.c
- MainMPCore.c
-
-[Sources.ARM]
- Arm/ArchPrePi.c
- Arm/ModuleEntryPoint.S | GCC
-
-[Sources.AArch64]
- AArch64/ArchPrePi.c
- AArch64/ModuleEntryPoint.S
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-
-[LibraryClasses]
- BaseLib
- CacheMaintenanceLib
- DebugLib
- DebugAgentLib
- ArmLib
- ArmGicLib
- IoLib
- TimerLib
- SerialPortLib
- ExtractGuidedSectionLib
- LzmaDecompressLib
- DebugAgentLib
- PrePiLib
- ArmPlatformLib
- ArmPlatformStackLib
- MemoryAllocationLib
- HobLib
- PrePiHobListPointerLib
- PlatformPeiLib
- MemoryInitPeiLib
-
-[Ppis]
- gArmMpCoreInfoPpiGuid
-
-[Guids]
- gArmMpCoreInfoGuid
- gEfiFirmwarePerformanceGuid
-
-[FeaturePcd]
- gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
-
-[Pcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
-
-[FixedPcd]
- gArmTokenSpaceGuid.PcdVFPEnabled
-
- gArmTokenSpaceGuid.PcdFdBaseAddress
- gArmTokenSpaceGuid.PcdFdSize
-
- gArmTokenSpaceGuid.PcdFvBaseAddress
- gArmTokenSpaceGuid.PcdFvSize
-
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize
-
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gArmTokenSpaceGuid.PcdGicSgiIntId
-
- gArmTokenSpaceGuid.PcdSystemMemoryBase
- gArmTokenSpaceGuid.PcdSystemMemorySize
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
-
- gArmPlatformTokenSpaceGuid.PcdCoreCount
-
- gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
-
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
- gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
-
diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/PeiUniCore.inf index 2e237172d5..9aa97d0a30 100644 --- a/ArmPlatformPkg/PrePi/PeiUniCore.inf +++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf @@ -18,7 +18,6 @@ [Sources]
PrePi.h
PrePi.c
- MainUniCore.c
[Sources.ARM]
Arm/ArchPrePi.c
@@ -49,7 +48,6 @@ DebugAgentLib
PrePiLib
ArmPlatformLib
- ArmPlatformStackLib
MemoryAllocationLib
HobLib
PrePiHobListPointerLib
@@ -65,7 +63,6 @@ [FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
@@ -80,7 +77,6 @@ gArmTokenSpaceGuid.PcdFvSize
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
diff --git a/ArmPlatformPkg/PrePi/PrePi.c b/ArmPlatformPkg/PrePi/PrePi.c index 9b127b94a6..f98a0e56c1 100644 --- a/ArmPlatformPkg/PrePi/PrePi.c +++ b/ArmPlatformPkg/PrePi/PrePi.c @@ -28,6 +28,15 @@ UINT64 mSystemMemoryEnd = FixedPcdGet64 (PcdSystemMemoryBase) +
FixedPcdGet64 (PcdSystemMemorySize) - 1;
+/**
+ Obtain a PPI from the list of PPIs provided by the platform code.
+
+ @param[in] PpiGuid GUID of the PPI to obtain
+ @param[out] Ppi Address of GUID pointer to return the PPI
+
+ @return Whether the PPI was obtained successfully
+**/
+STATIC
EFI_STATUS
GetPlatformPpi (
IN EFI_GUID *PpiGuid,
@@ -52,6 +61,14 @@ GetPlatformPpi ( return EFI_NOT_FOUND;
}
+/**
+ SEC main routine.
+
+ @param[in] UefiMemoryBase Start of the PI/UEFI memory region
+ @param[in] StacksBase Start of the stack
+ @param[in] StartTimeStamp Timer value at start of execution
+**/
+STATIC
VOID
PrePiMain (
IN UINTN UefiMemoryBase,
@@ -108,14 +125,8 @@ PrePiMain ( Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
ASSERT_EFI_ERROR (Status);
- // Create the Stacks HOB (reserve the memory for all stacks)
- if (ArmIsMpCore ()) {
- StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +
- ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));
- } else {
- StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
- }
-
+ // Create the Stacks HOB
+ StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
BuildStackHob (StacksBase, StacksSize);
// TODO: Call CpuPei as a library
@@ -177,9 +188,7 @@ CEntryPoint ( // Initialize the platform specific controllers
ArmPlatformInitialize (MpId);
- if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {
- // Initialize the Timer Library to setup the Timer HW controller
- TimerConstructor ();
+ if (PerformanceMeasurementEnabled ()) {
// We cannot call yet the PerformanceLib because the HOB List has not been initialized
StartTimeStamp = GetPerformanceCounter ();
} else {
@@ -193,31 +202,12 @@ CEntryPoint ( // Enable Instruction Caches on all cores.
ArmEnableInstructionCache ();
- // Define the Global Variable region when we are not running in XIP
- if (!IS_XIP ()) {
- if (ArmPlatformIsPrimaryCore (MpId)) {
- if (ArmIsMpCore ()) {
- // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
- ArmCallSEV ();
- }
- } else {
- // Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)
- ArmCallWFE ();
- }
- }
-
- // If not primary Jump to Secondary Main
- if (ArmPlatformIsPrimaryCore (MpId)) {
- InvalidateDataCacheRange (
- (VOID *)UefiMemoryBase,
- FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
- );
+ InvalidateDataCacheRange (
+ (VOID *)UefiMemoryBase,
+ FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
+ );
- // Goto primary Main.
- PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);
- } else {
- SecondaryMain (MpId);
- }
+ PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
// DXE Core should always load and never return
ASSERT (FALSE);
diff --git a/ArmPlatformPkg/PrePi/PrePi.h b/ArmPlatformPkg/PrePi/PrePi.h index 1d47ba26be..9d3e7feaa0 100644 --- a/ArmPlatformPkg/PrePi/PrePi.h +++ b/ArmPlatformPkg/PrePi/PrePi.h @@ -23,19 +23,6 @@ extern UINT64 mSystemMemoryEnd;
-RETURN_STATUS
-EFIAPI
-TimerConstructor (
- VOID
- );
-
-VOID
-PrePiMain (
- IN UINTN UefiMemoryBase,
- IN UINTN StacksBase,
- IN UINT64 StartTimeStamp
- );
-
EFI_STATUS
EFIAPI
MemoryPeim (
@@ -49,30 +36,12 @@ PlatformPeim ( VOID
);
-VOID
-PrimaryMain (
- IN UINTN UefiMemoryBase,
- IN UINTN StacksBase,
- IN UINT64 StartTimeStamp
- );
-
-VOID
-SecondaryMain (
- IN UINTN MpId
- );
-
// Either implemented by PrePiLib or by MemoryInitPei
VOID
BuildMemoryTypeInformationHob (
VOID
);
-EFI_STATUS
-GetPlatformPpi (
- IN EFI_GUID *PpiGuid,
- OUT VOID **Ppi
- );
-
// Initialize the Architecture specific controllers
VOID
ArchInitialize (
diff --git a/ArmPlatformPkg/Sec/AArch64/ArchSec.c b/ArmPlatformPkg/Sec/AArch64/ArchSec.c new file mode 100644 index 0000000000..371f2b9e3c --- /dev/null +++ b/ArmPlatformPkg/Sec/AArch64/ArchSec.c @@ -0,0 +1,49 @@ +/** @file
+ Architecture specific handling of CPU exceptions taken while running in PEI.
+
+ Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Sec.h"
+
+/**
+ Minimal high level handling of exceptions occurring in PEI.
+
+ @param[in] Entry Type of exception
+ @param[in] LR Address of instruction where the exception was taken
+**/
+VOID
+PeiCommonExceptionEntry (
+ IN UINT32 Entry,
+ IN UINTN LR
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ switch (Entry) {
+ case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Synchronous Exception at 0x%X\n\r", LR);
+ break;
+ case EXCEPT_AARCH64_IRQ:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "IRQ Exception at 0x%X\n\r", LR);
+ break;
+ case EXCEPT_AARCH64_FIQ:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "FIQ Exception at 0x%X\n\r", LR);
+ break;
+ case EXCEPT_AARCH64_SERROR:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "SError/Abort Exception at 0x%X\n\r", LR);
+ break;
+ default:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Unknown Exception at 0x%X\n\r", LR);
+ break;
+ }
+
+ SerialPortWrite ((UINT8 *)Buffer, CharCount);
+
+ while (1) {
+ }
+}
diff --git a/ArmPlatformPkg/Sec/AArch64/Exception.S b/ArmPlatformPkg/Sec/AArch64/Exception.S new file mode 100644 index 0000000000..d0d6bc44f7 --- /dev/null +++ b/ArmPlatformPkg/Sec/AArch64/Exception.S @@ -0,0 +1,116 @@ +#
+# Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+#include <AArch64/AArch64.h>
+#include <AsmMacroIoLibV8.h>
+#include <Base.h>
+#include <AutoGen.h>
+
+.text
+
+//============================================================
+//Default Exception Handlers
+//============================================================
+
+#define TO_HANDLER \
+ EL1_OR_EL2(x1) \
+1: mrs x1, elr_el1 /* EL1 Exception Link Register */ ;\
+ b 3f ;\
+2: mrs x1, elr_el2 /* EL2 Exception Link Register */ ;\
+3: bl ASM_PFX(PeiCommonExceptionEntry) ;
+
+
+//
+// Default Exception handlers: There is no plan to return from any of these exceptions.
+// No context saving at all.
+//
+
+VECTOR_BASE(PeiVectorTable)
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)
+_DefaultSyncExceptHandler_t:
+ mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)
+_DefaultIrq_t:
+ mov x0, #EXCEPT_AARCH64_IRQ
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)
+_DefaultFiq_t:
+ mov x0, #EXCEPT_AARCH64_FIQ
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)
+_DefaultSError_t:
+ mov x0, #EXCEPT_AARCH64_SERROR
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SYNC)
+_DefaultSyncExceptHandler_h:
+ mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_IRQ)
+_DefaultIrq_h:
+ mov x0, #EXCEPT_AARCH64_IRQ
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_FIQ)
+_DefaultFiq_h:
+ mov x0, #EXCEPT_AARCH64_FIQ
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPX_SERR)
+_DefaultSError_h:
+ mov x0, #EXCEPT_AARCH64_SERROR
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC)
+_DefaultSyncExceptHandler_LowerA64:
+ mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ)
+_DefaultIrq_LowerA64:
+ mov x0, #EXCEPT_AARCH64_IRQ
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ)
+_DefaultFiq_LowerA64:
+ mov x0, #EXCEPT_AARCH64_FIQ
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR)
+_DefaultSError_LowerA64:
+ mov x0, #EXCEPT_AARCH64_SERROR
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC)
+_DefaultSyncExceptHandler_LowerA32:
+ mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ)
+_DefaultIrq_LowerA32:
+ mov x0, #EXCEPT_AARCH64_IRQ
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ)
+_DefaultFiq_LowerA32:
+ mov x0, #EXCEPT_AARCH64_FIQ
+ TO_HANDLER
+
+VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR)
+_DefaultSError_LowerA32:
+ mov x0, #EXCEPT_AARCH64_SERROR
+ TO_HANDLER
+
+VECTOR_END(PeiVectorTable)
+
+AARCH64_BTI_NOTE()
diff --git a/ArmPlatformPkg/Sec/AArch64/Helper.S b/ArmPlatformPkg/Sec/AArch64/Helper.S new file mode 100644 index 0000000000..9b81b96a49 --- /dev/null +++ b/ArmPlatformPkg/Sec/AArch64/Helper.S @@ -0,0 +1,42 @@ +#========================================================================================
+# Copyright (c) 2011-2017, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#=======================================================================================
+
+#include <AsmMacroIoLibV8.h>
+#include <AArch64/AArch64.h>
+
+// Setup EL1 while in EL1
+ASM_FUNC(SetupExceptionLevel1)
+ mov x5, x30 // Save LR
+
+ mov x0, #CPACR_CP_FULL_ACCESS
+ bl ASM_PFX(ArmWriteCpacr) // Disable copro traps to EL1
+
+ ret x5
+
+// Setup EL2 while in EL2
+ASM_FUNC(SetupExceptionLevel2)
+ msr sctlr_el2, xzr
+ mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
+
+ // Send all interrupts to their respective Exception levels for EL2
+ orr x0, x0, #(1 << 3) // Enable EL2 FIQ
+ orr x0, x0, #(1 << 4) // Enable EL2 IRQ
+ orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort
+ msr hcr_el2, x0 // Write back our settings
+
+ msr cptr_el2, xzr // Disable copro traps to EL2
+
+ // Enable Timer access for non-secure EL1 and EL0
+ // The cnthctl_el2 register bits are architecturally
+ // UNKNOWN on reset.
+ // Disable event stream as it is not in use at this stage
+ mov x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN)
+ msr cnthctl_el2, x0
+
+ ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPlatformPkg/Sec/AArch64/ModuleEntryPoint.S b/ArmPlatformPkg/Sec/AArch64/ModuleEntryPoint.S new file mode 100644 index 0000000000..7addae6cff --- /dev/null +++ b/ArmPlatformPkg/Sec/AArch64/ModuleEntryPoint.S @@ -0,0 +1,60 @@ +//
+// Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+
+ASM_FUNC(_ModuleEntryPoint)
+ // Do early platform specific actions
+ bl ASM_PFX(ArmPlatformPeiBootAction)
+
+// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
+// and configure the system accordingly. EL2 is default if possible.
+// If we started in EL3 we need to switch and run at EL2.
+// If we are running at EL2 stay in EL2
+// If we are starting at EL1 stay in EL1.
+
+// If started at EL3 Sec is run and switches to EL2 before jumping to PEI.
+// If started at EL1 or EL2 Sec jumps directly to PEI without making any
+// changes.
+
+// Which EL are we running at? Every EL needs some level of setup...
+// We should not run this code in EL3
+ EL1_OR_EL2(x0)
+1:bl ASM_PFX(SetupExceptionLevel1)
+ b ASM_PFX(MainEntryPoint)
+2:bl ASM_PFX(SetupExceptionLevel2)
+ b ASM_PFX(MainEntryPoint)
+
+ASM_PFX(MainEntryPoint):
+ // Get the top of the primary stacks (and the base of the secondary stacks)
+ MOV64 (x1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))
+
+ // Set up the stack pointer
+ mov sp, x1
+
+ // Apply the init value to the entire stack
+ MOV64 (x8, FixedPcdGet64 (PcdCPUCoresStackBase))
+ MOV64 (x9, FixedPcdGet32 (PcdInitValueInTempStack) |\
+ FixedPcdGet32 (PcdInitValueInTempStack) << 32)
+0:stp x9, x9, [x8], #16
+ cmp x8, x1
+ b.lt 0b
+
+ // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
+ MOV64 (x2, FixedPcdGet64(PcdFvBaseAddress))
+ ldr x0, [x2, #8]
+
+ // Move sec startup address into a data register
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr x3, =ASM_PFX(CEntryPoint)
+
+ // Set the frame pointer to NULL so any backtraces terminate here
+ mov x29, xzr
+
+ // Jump to PrePeiCore C code
+ // x0 = pei_core_address
+ blr x3
diff --git a/ArmPlatformPkg/Sec/AArch64/SwitchStack.S b/ArmPlatformPkg/Sec/AArch64/SwitchStack.S new file mode 100644 index 0000000000..308b8764fc --- /dev/null +++ b/ArmPlatformPkg/Sec/AArch64/SwitchStack.S @@ -0,0 +1,32 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroIoLibV8.h>
+
+#/**
+# This allows the caller to switch the stack and return
+#
+# @param StackDelta Signed amount by which to modify the stack pointer
+#
+# @return Nothing. Goes to the Entry Point passing in the new parameters
+#
+#**/
+#VOID
+#EFIAPI
+#SecSwitchStack (
+# VOID *StackDelta
+# )#
+#
+ASM_FUNC(SecSwitchStack)
+ mov x1, sp
+ add x1, x0, x1
+ mov sp, x1
+ ret
+
diff --git a/ArmPlatformPkg/Sec/Arm/ArchSec.c b/ArmPlatformPkg/Sec/Arm/ArchSec.c new file mode 100644 index 0000000000..0c1e4998d7 --- /dev/null +++ b/ArmPlatformPkg/Sec/Arm/ArchSec.c @@ -0,0 +1,60 @@ +/** @file
+ Architecture specific handling of CPU exceptions taken while running in PEI.
+
+ Copyright (c) 2012, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Sec.h"
+
+/**
+ Minimal high level handling of exceptions occurring in PEI.
+
+ @param[in] Entry Type of exception
+ @param[in] LR Address of instruction where the exception was taken
+**/
+VOID
+PeiCommonExceptionEntry (
+ IN UINT32 Entry,
+ IN UINTN LR
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ switch (Entry) {
+ case 0:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Reset Exception at 0x%X\n\r", LR);
+ break;
+ case 1:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Undefined Exception at 0x%X\n\r", LR);
+ break;
+ case 2:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "SWI Exception at 0x%X\n\r", LR);
+ break;
+ case 3:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "PrefetchAbort Exception at 0x%X\n\r", LR);
+ break;
+ case 4:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "DataAbort Exception at 0x%X\n\r", LR);
+ break;
+ case 5:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Reserved Exception at 0x%X\n\r", LR);
+ break;
+ case 6:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "IRQ Exception at 0x%X\n\r", LR);
+ break;
+ case 7:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "FIQ Exception at 0x%X\n\r", LR);
+ break;
+ default:
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Unknown Exception at 0x%X\n\r", LR);
+ break;
+ }
+
+ SerialPortWrite ((UINT8 *)Buffer, CharCount);
+ while (1) {
+ }
+}
diff --git a/ArmPlatformPkg/Sec/Arm/Exception.S b/ArmPlatformPkg/Sec/Arm/Exception.S new file mode 100644 index 0000000000..956ae84714 --- /dev/null +++ b/ArmPlatformPkg/Sec/Arm/Exception.S @@ -0,0 +1,96 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <AutoGen.h>
+
+#start of the code section
+.text
+.align 5
+
+# IMPORT
+GCC_ASM_IMPORT(PeiCommonExceptionEntry)
+
+# EXPORT
+GCC_ASM_EXPORT(PeiVectorTable)
+
+//============================================================
+//Default Exception Handlers
+//============================================================
+
+
+ASM_PFX(PeiVectorTable):
+ b _DefaultResetHandler
+ b _DefaultUndefined
+ b _DefaultSWI
+ b _DefaultPrefetchAbort
+ b _DefaultDataAbort
+ b _DefaultReserved
+ b _DefaultIrq
+ b _DefaultFiq
+
+//
+// Default Exception handlers: There is no plan to return from any of these exceptions.
+// No context saving at all.
+//
+_DefaultResetHandler:
+ mov r1, lr
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #0
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultUndefined:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #1
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultSWI:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #2
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultPrefetchAbort:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #3
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultDataAbort:
+ sub r1, LR, #8
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #4
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultReserved:
+ mov r1, lr
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #5
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultIrq:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #6
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
+_DefaultFiq:
+ sub r1, LR, #4
+ # Switch to SVC for common stack
+ cps #0x13
+ mov r0, #7
+ blx ASM_PFX(PeiCommonExceptionEntry)
+
diff --git a/ArmPlatformPkg/Sec/Arm/ModuleEntryPoint.S b/ArmPlatformPkg/Sec/Arm/ModuleEntryPoint.S new file mode 100644 index 0000000000..b3c67234e9 --- /dev/null +++ b/ArmPlatformPkg/Sec/Arm/ModuleEntryPoint.S @@ -0,0 +1,40 @@ +//
+// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+#include <AsmMacroIoLib.h>
+
+ASM_FUNC(_ModuleEntryPoint)
+ // Do early platform specific actions
+ bl ASM_PFX(ArmPlatformPeiBootAction)
+
+ // Get the top of the primary stacks (and the base of the secondary stacks)
+ MOV32 (r1, FixedPcdGet64(PcdCPUCoresStackBase) + FixedPcdGet32(PcdCPUCorePrimaryStackSize))
+
+ // Set up the stack pointer
+ mov sp, r1
+
+ // Apply the init value to the entire stack
+ MOV32 (r8, FixedPcdGet64 (PcdCPUCoresStackBase))
+ MOV32 (r9, FixedPcdGet32 (PcdInitValueInTempStack))
+ mov r10, r9
+ mov r11, r9
+ mov r12, r9
+0:stm r8!, {r9-r12}
+ cmp r8, r1
+ blt 0b
+
+ // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
+ MOV32 (r2, FixedPcdGet32(PcdFvBaseAddress))
+ ldr r0, [r2, #4]
+
+ // Move sec startup address into a data register
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr r3, =ASM_PFX(CEntryPoint)
+
+ // Jump to PrePeiCore C code
+ // r0 = pei_core_address
+ blx r3
diff --git a/ArmPlatformPkg/Sec/Arm/SwitchStack.S b/ArmPlatformPkg/Sec/Arm/SwitchStack.S new file mode 100644 index 0000000000..d64772b8ed --- /dev/null +++ b/ArmPlatformPkg/Sec/Arm/SwitchStack.S @@ -0,0 +1,32 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroIoLib.h>
+
+#/**
+# This allows the caller to switch the stack and return
+#
+# @param StackDelta Signed amount by which to modify the stack pointer
+#
+# @return Nothing. Goes to the Entry Point passing in the new parameters
+#
+#**/
+#VOID
+#EFIAPI
+#SecSwitchStack (
+# VOID *StackDelta
+# )#
+#
+ASM_FUNC(SecSwitchStack)
+ mov R1, R13
+ add R1, R0, R1
+ mov R13, R1
+ bx LR
+
+
+
diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c new file mode 100644 index 0000000000..482e68ad42 --- /dev/null +++ b/ArmPlatformPkg/Sec/Sec.c @@ -0,0 +1,245 @@ +/** @file
+ Generic SEC driver for ARM platforms
+
+ Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "Sec.h"
+
+/**
+ This service of the EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI that migrates temporary
+ RAM into permanent memory.
+
+ @param PeiServices Pointer to the PEI Services Table.
+ @param TemporaryMemoryBase Source Address in temporary memory from which
+ the SEC or PEIM will copy the Temporary RAM
+ contents.
+ @param PermanentMemoryBase Destination Address in permanent memory into
+ which the SEC or PEIM will copy the Temporary
+ RAM contents.
+ @param CopySize Amount of memory to migrate from temporary to
+ permanent memory.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize >
+ TemporaryMemoryBase when TemporaryMemoryBase >
+ PermanentMemoryBase.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SecTemporaryRamSupport (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ )
+{
+ VOID *OldHeap;
+ VOID *NewHeap;
+ VOID *OldStack;
+ VOID *NewStack;
+ UINTN HeapSize;
+
+ HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);
+
+ OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;
+ NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));
+
+ OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);
+ NewStack = (VOID *)(UINTN)PermanentMemoryBase;
+
+ //
+ // Migrate the temporary memory stack to permanent memory stack.
+ //
+ CopyMem (NewStack, OldStack, CopySize - HeapSize);
+
+ //
+ // Migrate the temporary memory heap to permanent memory heap.
+ //
+ CopyMem (NewHeap, OldHeap, HeapSize);
+
+ SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);
+
+ return EFI_SUCCESS;
+}
+
+STATIC CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
+ SecTemporaryRamSupport
+};
+
+STATIC CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiTemporaryRamSupportPpiGuid,
+ (VOID *)&mTemporaryRamSupportPpi
+ }
+};
+
+/**
+ Construct a PPI list from the PPIs provided in this file and the ones
+ provided by the platform code.
+
+ @param[out] PpiListSize Size of the PPI list in bytes
+ @param[out] PpiList Pointer to the constructed PPI list
+**/
+STATIC
+VOID
+CreatePpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;
+ UINTN PlatformPpiListSize;
+ UINTN ListBase;
+ EFI_PEI_PPI_DESCRIPTOR *LastPpi;
+
+ // Get the Platform PPIs
+ PlatformPpiListSize = 0;
+ ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);
+
+ // Copy the Common and Platform PPis in Temporary Memory
+ ListBase = PcdGet64 (PcdCPUCoresStackBase);
+ CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));
+ CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
+
+ // Set the Terminate flag on the last PPI entry
+ LastPpi = (EFI_PEI_PPI_DESCRIPTOR *)ListBase +
+ ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;
+ LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+
+ *PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;
+ *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;
+}
+
+/**
+
+ Prints firmware version and build time to serial console.
+
+**/
+STATIC
+VOID
+PrintFirmwareVersion (
+ VOID
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ CharCount = AsciiSPrint (
+ Buffer,
+ sizeof (Buffer),
+ "UEFI firmware (version %s built at %a on %a)\n\r",
+ (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
+ __TIME__,
+ __DATE__
+ );
+ SerialPortWrite ((UINT8 *)Buffer, CharCount);
+}
+
+/**
+ SEC main routine.
+
+ @param[in] PeiCoreEntryPoint Address in ram of the entrypoint of the PEI
+ core
+**/
+STATIC
+VOID
+EFIAPI
+SecMain (
+ IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
+ )
+{
+ EFI_SEC_PEI_HAND_OFF SecCoreData;
+ UINTN PpiListSize;
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ UINTN TemporaryRamBase;
+ UINTN TemporaryRamSize;
+
+ CreatePpiList (&PpiListSize, &PpiList);
+
+ // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
+ // the base of the primary core stack
+ PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);
+ TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
+ TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
+
+ //
+ // Bind this information into the SEC hand-off state
+ // Note: this must be in sync with the stuff in the asm file
+ // Note also: HOBs (pei temp ram) MUST be above stack
+ //
+ SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
+ SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
+ SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
+ SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
+ SecCoreData.TemporaryRamSize = TemporaryRamSize;
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
+ SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
+ SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
+ SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
+
+ // Jump to PEI core entry point
+ (PeiCoreEntryPoint)(&SecCoreData, PpiList);
+}
+
+/**
+ Module C entrypoint.
+
+ @param[in] PeiCoreEntryPoint Address in ram of the entrypoint of the PEI
+ core
+**/
+VOID
+CEntryPoint (
+ IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
+ )
+{
+ if (!ArmMmuEnabled ()) {
+ // Data Cache enabled on Primary core when MMU is enabled.
+ ArmDisableDataCache ();
+ // Invalidate instruction cache
+ ArmInvalidateInstructionCache ();
+ // Enable Instruction Caches on all cores.
+ ArmEnableInstructionCache ();
+
+ InvalidateDataCacheRange (
+ (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
+ PcdGet32 (PcdCPUCorePrimaryStackSize)
+ );
+ }
+
+ // Write VBAR - The Exception Vector table must be aligned to its requirement
+ // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
+ // 'Align=4K' is defined into your FDF for this module.
+ ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
+ ArmWriteVBar ((UINTN)PeiVectorTable);
+
+ // Enable Floating Point
+ if (FixedPcdGet32 (PcdVFPEnabled)) {
+ ArmEnableVFP ();
+ }
+
+ // Invoke "ProcessLibraryConstructorList" to have all library constructors
+ // called.
+ ProcessLibraryConstructorList ();
+
+ PrintFirmwareVersion ();
+
+ // Initialize the Debug Agent for Source Level Debugging
+ InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
+ SaveAndSetDebugTimerInterrupt (TRUE);
+
+ // Initialize the platform specific controllers
+ ArmPlatformInitialize (ArmReadMpidr ());
+
+ // Goto primary Main.
+ SecMain (PeiCoreEntryPoint);
+
+ // PEI Core should always load and never return
+ ASSERT (FALSE);
+}
diff --git a/ArmPlatformPkg/Sec/Sec.h b/ArmPlatformPkg/Sec/Sec.h new file mode 100644 index 0000000000..56d9f352bd --- /dev/null +++ b/ArmPlatformPkg/Sec/Sec.h @@ -0,0 +1,54 @@ +/** @file
+ Generic SEC driver for ARM platforms
+
+ Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SEC_H_
+#define SEC_H_
+
+#include <PiPei.h>
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <Ppi/TemporaryRamSupport.h>
+
+/**
+ Helper function to switch to a different stack. Implemented in assembler as
+ this cannot be done from C code.
+**/
+VOID
+SecSwitchStack (
+ INTN StackDelta
+ );
+
+/**
+ Vector Table for the PEI Phase. This is executable code but not a callable
+ function. Implemented in assembler.
+**/
+VOID
+PeiVectorTable (
+ VOID
+ );
+
+/**
+ Minimal high level handling of exceptions occurring in PEI.
+**/
+VOID
+PeiCommonExceptionEntry (
+ IN UINT32 Entry,
+ IN UINTN LR
+ );
+
+#endif
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/Sec/Sec.inf index c5cad7e37f..58a566f5f0 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf +++ b/ArmPlatformPkg/Sec/Sec.inf @@ -1,65 +1,59 @@ -#/** @file
-# Pre PeiCore - Hand-off to PEI Core in Normal World
+## @file
+# Generic SEC driver for ARM platforms
#
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-#**/
+##
[Defines]
INF_VERSION = 1.30
- BASE_NAME = ArmPlatformPrePeiCore
- FILE_GUID = b78d02bb-d0b5-4389-bc7f-b39ee846c784
+ BASE_NAME = Sec
+ FILE_GUID = 4c97830a-8e18-4aa6-9fd0-837b089910e2
MODULE_TYPE = SEC
VERSION_STRING = 1.0
[Sources.common]
- MainMPCore.c
- PrePeiCore.h
- PrePeiCore.c
+ Sec.h
+ Sec.c
[Sources.ARM]
- Arm/ArchPrePeiCore.c
- Arm/PrePeiCoreEntryPoint.S | GCC
- Arm/SwitchStack.S | GCC
- Arm/Exception.S | GCC
+ Arm/ArchSec.c
+ Arm/Exception.S
+ Arm/ModuleEntryPoint.S
+ Arm/SwitchStack.S
[Sources.AARCH64]
- AArch64/ArchPrePeiCore.c
- AArch64/PrePeiCoreEntryPoint.S
- AArch64/SwitchStack.S
+ AArch64/ArchSec.c
AArch64/Exception.S
AArch64/Helper.S
+ AArch64/ModuleEntryPoint.S
+ AArch64/SwitchStack.S
[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
[LibraryClasses]
ArmLib
ArmPlatformLib
- CacheMaintenanceLib
BaseLib
- DebugLib
+ BaseMemoryLib
+ CacheMaintenanceLib
DebugAgentLib
- IoLib
- ArmGicLib
+ DebugLib
PrintLib
SerialPortLib
[Ppis]
gEfiTemporaryRamSupportPpiGuid
- gArmMpCoreInfoPpiGuid
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
-[FeaturePcd]
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
-
[FixedPcd]
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
@@ -67,10 +61,5 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize
-
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gArmTokenSpaceGuid.PcdGicSgiIntId
gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack
|