diff options
Diffstat (limited to 'MdePkg/Include/IndustryStandard')
19 files changed, 534 insertions, 50 deletions
diff --git a/MdePkg/Include/IndustryStandard/Acpi51.h b/MdePkg/Include/IndustryStandard/Acpi51.h index 4241b8f198..cdf95386d2 100644 --- a/MdePkg/Include/IndustryStandard/Acpi51.h +++ b/MdePkg/Include/IndustryStandard/Acpi51.h @@ -1760,6 +1760,7 @@ typedef struct { #define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi60.h b/MdePkg/Include/IndustryStandard/Acpi60.h index 3757d3f827..d545de1ba2 100644 --- a/MdePkg/Include/IndustryStandard/Acpi60.h +++ b/MdePkg/Include/IndustryStandard/Acpi60.h @@ -1947,6 +1947,7 @@ typedef struct { #define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi61.h b/MdePkg/Include/IndustryStandard/Acpi61.h index c3facc6e37..5100d8b3b4 100644 --- a/MdePkg/Include/IndustryStandard/Acpi61.h +++ b/MdePkg/Include/IndustryStandard/Acpi61.h @@ -1979,6 +1979,8 @@ typedef struct { #define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_1_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi62.h b/MdePkg/Include/IndustryStandard/Acpi62.h index 4dd3e21c23..711b88b758 100644 --- a/MdePkg/Include/IndustryStandard/Acpi62.h +++ b/MdePkg/Include/IndustryStandard/Acpi62.h @@ -2292,6 +2292,8 @@ typedef struct { #define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_2_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi63.h b/MdePkg/Include/IndustryStandard/Acpi63.h index 7582dccf64..68798da725 100644 --- a/MdePkg/Include/IndustryStandard/Acpi63.h +++ b/MdePkg/Include/IndustryStandard/Acpi63.h @@ -2252,6 +2252,8 @@ typedef struct { #define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_3_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h b/MdePkg/Include/IndustryStandard/Acpi64.h index faf069a045..bbe6a3c9eb 100644 --- a/MdePkg/Include/IndustryStandard/Acpi64.h +++ b/MdePkg/Include/IndustryStandard/Acpi64.h @@ -2335,6 +2335,8 @@ typedef struct { #define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_4_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF
///
diff --git a/MdePkg/Include/IndustryStandard/Acpi65.h b/MdePkg/Include/IndustryStandard/Acpi65.h index b9616a3e29..1f2af6ad2a 100644 --- a/MdePkg/Include/IndustryStandard/Acpi65.h +++ b/MdePkg/Include/IndustryStandard/Acpi65.h @@ -2,7 +2,7 @@ ACPI 6.5 definitions from the ACPI Specification Revision 6.5 Aug, 2022.
Copyright (c) 2017 - 2022, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2019 - 2023, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2019 - 2024, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -1621,7 +1621,7 @@ typedef struct { #define EFI_ACPI_6_5_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
#define EFI_ACPI_6_5_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
-#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x6.5B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
#define EFI_ACPI_6_5_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
@@ -1949,7 +1949,7 @@ typedef struct { ///
/// HEST Version (as defined in ACPI 6.5 spec.)
///
-#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+#define EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x02
//
// Error Source structure types.
@@ -2419,7 +2419,7 @@ typedef struct { ///
/// EINJ Version (as defined in ACPI 6.5 spec.)
///
-#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_REVISION 0x01
+#define EFI_ACPI_6_5_ERROR_INJECTION_TABLE_REVISION 0x02
///
/// EINJ Error Injection Actions
@@ -2432,6 +2432,10 @@ typedef struct { #define EFI_ACPI_6_5_EINJ_EXECUTE_OPERATION 0x05
#define EFI_ACPI_6_5_EINJ_CHECK_BUSY_STATUS 0x06
#define EFI_ACPI_6_5_EINJ_GET_COMMAND_STATUS 0x07
+#define EFI_ACPI_6_5_EINJ_SET_ERROR_TYPE_WITH_ADDRESS 0x08
+#define EFI_ACPI_6_5_EINJ_GET_EXECUTE_OPERATION_TIMINGS 0x09
+#define EFI_ACPI_6_5_EINJ_EINJV2_SET_ERROR_TYPE 0x10
+#define EFI_ACPI_6_5_EINJ_EINJV2_GET_ERROR_TYPE 0x11
#define EFI_ACPI_6_5_EINJ_TRIGGER_ERROR 0xFF
///
@@ -3264,6 +3268,11 @@ typedef struct { ///
#define EFI_ACPI_6_5_XEN_PROJECT_TABLE_SIGNATURE SIGNATURE_32('X', 'E', 'N', 'V')
+///
+/// "MPAM" Memory System Resource Partitioning and Monitoring Table
+///
+#define EFI_ACPI_MEMORY_SYSTEM_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'A', 'M')
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/IoRemappingTable.h b/MdePkg/Include/IndustryStandard/IoRemappingTable.h index 544aa67a05..851ce00cb8 100644 --- a/MdePkg/Include/IndustryStandard/IoRemappingTable.h +++ b/MdePkg/Include/IndustryStandard/IoRemappingTable.h @@ -43,8 +43,9 @@ #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2
#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3
-#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
-#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CANWBS BIT2
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1
@@ -60,7 +61,8 @@ #define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1
#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0
-#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1 // HW update of Access Flag supported
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE_DS BIT2 // HW update of Access Flag + Dirty Flag supported
#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3
#define EFI_ACPI_IORT_SMMUv3_FLAG_DEVICEID_VALID BIT4
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h b/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h index b92958454f..93f625a32b 100644 --- a/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h +++ b/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h @@ -10,6 +10,7 @@ and Appendix H, Sub-function Assignments.
Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) Microsoft Corporation.
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -42,5 +43,50 @@ typedef struct { UINT8 OEMEvData3;
} IPMI_PLATFORM_EVENT_MESSAGE_DATA_REQUEST;
+//
+// Definitions for Set Sensor Thresholds command
+//
+#define IPMI_SENSOR_SET_SENSOR_THRESHOLDS 0x26
+
+typedef union {
+ struct _SENSOR_BITS {
+ UINT8 LowerNonCriticalThreshold : 1;
+ UINT8 LowerCriticalThreshold : 1;
+ UINT8 LowerNonRecoverableThreshold : 1;
+ UINT8 UpperNonCriticalThreshold : 1;
+ UINT8 UpperCriticalThreshold : 1;
+ UINT8 UpperNonRecoverableThreshold : 1;
+ UINT8 Reserved : 2;
+ } Bits;
+ UINT8 Uint8;
+} SENSOR_BITS;
+
+typedef struct _IPMI_SENSOR_SET_SENSOR_THRESHOLD_REQUEST_DATA {
+ UINT8 SensorNumber;
+ SENSOR_BITS SetBitEnable;
+ UINT8 LowerNonCriticalThreshold;
+ UINT8 LowerCriticalThreshold;
+ UINT8 LowerNonRecoverableThreshold;
+ UINT8 UpperNonCriticalThreshold;
+ UINT8 UpperCriticalThreshold;
+ UINT8 UpperNonRecoverableThreshold;
+} IPMI_SENSOR_SET_SENSOR_THRESHOLD_REQUEST_DATA;
+
+//
+// Definitions for Get Sensor Thresholds command
+//
+#define IPMI_SENSOR_GET_SENSOR_THRESHOLDS 0x27
+
+typedef struct _IPMI_SENSOR_GET_SENSOR_THRESHOLD_RESPONSE_DATA {
+ UINT8 CompletionCode;
+ SENSOR_BITS GetBitEnable;
+ UINT8 LowerNonCriticalThreshold;
+ UINT8 LowerCriticalThreshold;
+ UINT8 LowerNonRecoverableThreshold;
+ UINT8 UpperNonCriticalThreshold;
+ UINT8 UpperCriticalThreshold;
+ UINT8 UpperNonRecoverableThreshold;
+} IPMI_SENSOR_GET_SENSOR_THRESHOLD_RESPONSE_DATA;
+
#pragma pack()
#endif
diff --git a/MdePkg/Include/IndustryStandard/Mpam.h b/MdePkg/Include/IndustryStandard/Mpam.h new file mode 100644 index 0000000000..8358b35d81 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Mpam.h @@ -0,0 +1,246 @@ +/** @file
+ ACPI for Memory System Resource Partitioning and Monitoring 2.0 (MPAM) as
+ specified in ARM spec DEN0065
+
+ Copyright (c) 2024, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - [1] ACPI for Memory System Resource Partitioning and Monitoring 2.0
+ (https://developer.arm.com/documentation/den0065/latest)
+
+ @par Glossary:
+ - MPAM - Memory System Resource Partitioning And Monitoring
+ - MSC - Memory System Component
+ - PCC - Platform Communication Channel
+ - RIS - Resource Instance Selection
+ - SMMU - Arm System Memory Management Unit
+ **/
+
+#ifndef MPAM_H_
+#define MPAM_H_
+
+#include <IndustryStandard/Acpi.h>
+
+///
+/// MPAM Revision
+///
+#define EFI_ACPI_MEMORY_SYSTEM_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_REVISION (0x01)
+
+///
+/// MPAM Interrupt mode
+///
+#define EFI_ACPI_MPAM_INTERRUPT_LEVEL_TRIGGERED (0x0)
+#define EFI_ACPI_MPAM_INTERRUPT_EDGE_TRIGGERED (0x1)
+
+///
+/// MPAM Interrupt type
+///
+#define EFI_ACPI_MPAM_INTERRUPT_WIRED (0x0)
+
+///
+/// MPAM Interrupt affinity type
+///
+#define EFI_ACPI_MPAM_INTERRUPT_PROCESSOR_AFFINITY (0x0)
+#define EFI_ACPI_MPAM_INTERRUPT_PROCESSOR_CONTAINER_AFFINITY (0x1)
+
+///
+/// MPAM MSC affinity valid
+///
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_NOT_VALID (0x0)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_VALID (0x1)
+
+///
+/// MPAM Interrupt flag - bit positions
+///
+#define EFI_ACPI_MPAM_INTERRUPT_MODE_SHIFT (0)
+#define EFI_ACPI_MPAM_INTERRUPT_TYPE_SHIFT (1)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_TYPE_SHIFT (3)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_VALID_SHIFT (4)
+#define EFI_ACPI_MPAM_INTERRUPT_RESERVED_SHIFT (5)
+
+///
+/// MPAM Interrupt flag - bit masks
+///
+#define EFI_ACPI_MPAM_INTERRUPT_MODE_MASK (0x1)
+#define EFI_ACPI_MPAM_INTERRUPT_TYPE_MASK (0x3)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_TYPE_MASK (0x8)
+#define EFI_ACPI_MPAM_INTERRUPT_AFFINITY_VALID_MASK (0x10)
+#define EFI_ACPI_MPAM_INTERRUPT_RESERVED_MASK (0xFFFFFFE0)
+
+///
+/// MPAM Location types
+/// as described in document [1], table 11.
+///
+#define EFI_ACPI_MPAM_LOCATION_PROCESSOR_CACHE (0x0)
+#define EFI_ACPI_MPAM_LOCATION_MEMORY (0x1)
+#define EFI_ACPI_MPAM_LOCATION_SMMU (0x2)
+#define EFI_ACPI_MPAM_LOCATION_MEMORY_CACHE (0x3)
+#define EFI_ACPI_MPAM_LOCATION_ACPI_DEVICE (0x4)
+#define EFI_ACPI_MPAM_LOCATION_INTERCONNECT (0x5)
+#define EFI_ACPI_MPAM_LOCATION_UNKNOWN (0xFF)
+
+///
+/// MPAM Interface types
+/// as desscribed in document[1], table 4.
+///
+#define EFI_ACPI_MPAM_INTERFACE_MMIO (0x00)
+#define EFI_ACPI_MPAM_INTERFACE_PCC (0x0A)
+
+///
+/// MPAM Link types
+/// as described in document [1], table 19.
+///
+#define EFI_ACPI_MPAM_LINK_TYPE_NUMA (0x00)
+#define EFI_ACPI_MPAM_LINK_TYPE_PROC (0x01)
+
+#pragma pack(1)
+
+///
+/// MPAM MSC generic locator descriptor
+/// as described in document [1], table 12.
+///
+typedef struct {
+ UINT64 Descriptor1;
+ UINT32 Descriptor2;
+} EFI_ACPI_MPAM_GENERIC_LOCATOR;
+
+///
+/// MPAM processor cache locator descriptor
+/// as described in document [1], table 13.
+///
+typedef struct {
+ UINT64 CacheReference;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_CACHE_LOCATOR;
+
+///
+/// MPAM memory locator descriptor
+/// as described in document [1], table 14.
+///
+typedef struct {
+ UINT64 ProximityDomain;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_MEMORY_LOCATOR;
+
+///
+/// MPAM SMMU locator descriptor
+/// as described in document [1], table 15.
+///
+typedef struct {
+ UINT64 SmmuInterface;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_SMMU_LOCATOR;
+
+///
+/// MPAM memory-side cache locator descriptor
+/// as described in Document [1], table 16.
+///
+typedef struct {
+ UINT8 Reserved[7];
+ UINT8 Level;
+ UINT32 Reference;
+} EFI_ACPI_MPAM_MEMORY_CACHE_LOCATOR;
+
+///
+/// MPAM ACPI device locator descriptor
+/// as described in document [1], table 17.
+///
+typedef struct {
+ UINT64 AcpiHardwareId;
+ UINT32 AcpiUniqueId;
+} EFI_ACPI_MPAM_ACPI_LOCATOR;
+
+///
+/// MPAM interconnect locator descriptor
+/// as described in document [1], table 18.
+///
+typedef struct {
+ UINT64 InterconnectDescTblOff;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_INTERCONNECT_LOCATOR;
+
+///
+/// MPAM interconnect descriptor
+/// as described in document [1], table 19.
+///
+typedef struct {
+ UINT32 SourceId;
+ UINT32 DestinationId;
+ UINT8 LinkType;
+ UINT8 Reserved[3];
+} EFI_ACPI_MPAM_INTERCONNECT_DESCRIPTOR;
+
+///
+/// MPAM interconnect descriptor table
+/// as described in document [1], table 20.
+///
+typedef struct {
+ UINT8 Signature[16];
+ UINT32 NumDescriptors;
+} EFI_ACPI_MPAM_INTERCONNECT_DESCRIPTOR_TABLE;
+
+///
+/// MPAM resource locator
+///
+typedef union {
+ EFI_ACPI_MPAM_CACHE_LOCATOR CacheLocator;
+ EFI_ACPI_MPAM_MEMORY_LOCATOR MemoryLocator;
+ EFI_ACPI_MPAM_SMMU_LOCATOR SmmuLocator;
+ EFI_ACPI_MPAM_MEMORY_CACHE_LOCATOR MemCacheLocator;
+ EFI_ACPI_MPAM_ACPI_LOCATOR AcpiLocator;
+ EFI_ACPI_MPAM_INTERCONNECT_LOCATOR InterconnectIfcLocator;
+ EFI_ACPI_MPAM_GENERIC_LOCATOR GenericLocator;
+} EFI_ACPI_MPAM_LOCATOR;
+
+///
+/// MPAM MSC node body
+/// as described document [1], table 4.
+///
+typedef struct {
+ UINT16 Length;
+ UINT8 InterfaceType;
+ UINT8 Reserved;
+ UINT32 Identifier;
+ UINT64 BaseAddress;
+ UINT32 MmioSize;
+ UINT32 OverflowInterrupt;
+ UINT32 OverflowInterruptFlags;
+ UINT32 Reserved1;
+ UINT32 OverflowInterruptAffinity;
+ UINT32 ErrorInterrupt;
+ UINT32 ErrorInterruptFlags;
+ UINT32 Reserved2;
+ UINT32 ErrorInterruptAffinity;
+ UINT32 MaxNrdyUsec;
+ UINT64 HardwareIdLinkedDevice;
+ UINT32 InstanceIdLinkedDevice;
+ UINT32 NumResources;
+} EFI_ACPI_MPAM_MSC_NODE;
+
+///
+/// MPAM MSC resource
+/// as described in document [1], table 9.
+///
+typedef struct {
+ UINT32 Identifier;
+ UINT8 RisIndex;
+ UINT16 Reserved1;
+ UINT8 LocatorType;
+ EFI_ACPI_MPAM_LOCATOR Locator;
+ UINT32 NumFunctionalDependencies;
+} EFI_ACPI_MPAM_MSC_RESOURCE;
+
+///
+/// MPAM Function dependency descriptor
+/// as described in document [1], table 10.
+///
+typedef struct {
+ UINT32 Producer;
+ UINT32 Reserved;
+} EFI_ACPI_MPAM_FUNCTIONAL_DEPENDENCY_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Nvme.h b/MdePkg/Include/IndustryStandard/Nvme.h index c190d678e1..2a94e21203 100644 --- a/MdePkg/Include/IndustryStandard/Nvme.h +++ b/MdePkg/Include/IndustryStandard/Nvme.h @@ -54,16 +54,16 @@ typedef struct { UINT8 Cqr : 1; // Contiguous Queues Required
UINT8 Ams : 2; // Arbitration Mechanism Supported
UINT8 Rsvd1 : 5;
- UINT8 To; // Timeout
- UINT16 Dstrd : 4;
+ UINT8 To; // Timeout
+ UINT16 Dstrd : 4; // Doorbell Stride
UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS
UINT16 Css : 8; // Command Sets Supported - Bit 37
UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4
UINT16 Rsvd3 : 2;
- UINT8 Mpsmin : 4;
- UINT8 Mpsmax : 4;
- UINT8 Pmrs : 1;
- UINT8 Cmbs : 1;
+ UINT8 Mpsmin : 4; // Memory Page Size Minimum
+ UINT8 Mpsmax : 4; // Memory Page Size Maximum
+ UINT8 Pmrs : 1; // Persistent Memory Region Supported
+ UINT8 Cmbs : 1; // Controller Memory Buffer Supported
UINT8 Rsvd4 : 6;
} NVME_CAP;
diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/IndustryStandard/Pci.h index 42c00ac762..4220ad8a6f 100644 --- a/MdePkg/Include/IndustryStandard/Pci.h +++ b/MdePkg/Include/IndustryStandard/Pci.h @@ -9,7 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _PCI_H_
#define _PCI_H_
-#include <IndustryStandard/PciExpress50.h>
+#include <IndustryStandard/PciExpress60.h>
#include <IndustryStandard/PciCodeId.h>
#endif
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h index 341e3e5639..b437ca5c1e 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -40,7 +40,7 @@ typedef union { UINT16 SlotImplemented : 1;
UINT16 InterruptMessageNumber : 5;
UINT16 Undefined : 1;
- UINT16 Reserved : 1;
+ UINT16 FlitModeSupported : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_CAPABILITY;
@@ -64,11 +64,13 @@ typedef union { UINT32 EndpointL1AcceptableLatency : 3;
UINT32 Undefined : 3;
UINT32 RoleBasedErrorReporting : 1;
- UINT32 Reserved : 2;
+ UINT32 ErrCorSubclassCapable : 1;
+ UINT32 RxMpsFixed : 1;
UINT32 CapturedSlotPowerLimitValue : 8;
UINT32 CapturedSlotPowerLimitScale : 2;
UINT32 FunctionLevelReset : 1;
- UINT32 Reserved2 : 3;
+ UINT32 MixedMpsSupported : 1;
+ UINT32 Reserved2 : 2;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY;
@@ -111,13 +113,14 @@ typedef union { typedef union {
struct {
- UINT16 CorrectableError : 1;
- UINT16 NonFatalError : 1;
- UINT16 FatalError : 1;
- UINT16 UnsupportedRequest : 1;
- UINT16 AuxPower : 1;
- UINT16 TransactionsPending : 1;
- UINT16 Reserved : 10;
+ UINT16 CorrectableError : 1;
+ UINT16 NonFatalError : 1;
+ UINT16 FatalError : 1;
+ UINT16 UnsupportedRequest : 1;
+ UINT16 AuxPower : 1;
+ UINT16 TransactionsPending : 1;
+ UINT16 EmergencyPowerReductionDetected : 1;
+ UINT16 Reserved : 9;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_STATUS;
@@ -146,7 +149,7 @@ typedef union { typedef union {
struct {
UINT16 AspmControl : 2;
- UINT16 Reserved : 1;
+ UINT16 PtmPropagationDelayB : 1;
UINT16 ReadCompletionBoundary : 1;
UINT16 LinkDisable : 1;
UINT16 RetrainLink : 1;
@@ -156,6 +159,9 @@ typedef union { UINT16 HardwareAutonomousWidthDisable : 1;
UINT16 LinkBandwidthManagementInterrupt : 1;
UINT16 LinkAutonomousBandwidthInterrupt : 1;
+ UINT16 SrisClocking : 1;
+ UINT16 FlitModeDisable : 1;
+ UINT16 DrsSignalingControl : 2;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL;
@@ -205,7 +211,9 @@ typedef union { UINT16 PowerController : 1;
UINT16 ElectromechanicalInterlock : 1;
UINT16 DataLinkLayerStateChanged : 1;
- UINT16 Reserved : 3;
+ UINT16 AutoSlotPowerLimitDisable : 1;
+ UINT16 InbandPdDisable : 1;
+ UINT16 Reserved : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;
@@ -233,7 +241,8 @@ typedef union { UINT16 SystemErrorOnFatalError : 1;
UINT16 PmeInterrupt : 1;
UINT16 CrsSoftwareVisibility : 1;
- UINT16 Reserved : 11;
+ UINT16 NoNfmSubtree : 1;
+ UINT16 Reserved : 10;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CONTROL;
@@ -268,7 +277,7 @@ typedef union { UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
- UINT32 LnSystemCLS : 2;
+ UINT32 Reserved : 2;
UINT32 TenBitTagCompleterSupported : 1;
UINT32 TenBitTagRequesterSupported : 1;
UINT32 Obff : 2;
@@ -277,7 +286,9 @@ typedef union { UINT32 MaxEndEndTlpPrefixes : 2;
UINT32 EmergencyPowerReductionSupported : 2;
UINT32 EmergencyPowerReductionInitializationRequired : 1;
- UINT32 Reserved3 : 4;
+ UINT32 Reserved2 : 1;
+ UINT32 DmwrCompleter : 1;
+ UINT32 DmwrLengths : 2;
UINT32 FrsSupported : 1;
} Bits;
UINT32 Uint32;
@@ -330,10 +341,15 @@ typedef union { typedef union {
struct {
- UINT32 Reserved : 1;
- UINT32 LinkSpeedsVector : 7;
- UINT32 Crosslink : 1;
- UINT32 Reserved2 : 23;
+ UINT32 Reserved : 1;
+ UINT32 LinkSpeedsVector : 7;
+ UINT32 Crosslink : 1;
+ UINT32 LowerSkpOsGeneration : 7;
+ UINT32 LowerSkpOsReception : 7;
+ UINT32 RetimerPresenceDetect : 1;
+ UINT32 TwoRetimersPresenceDetect : 1;
+ UINT32 Reserved2 : 6;
+ UINT32 DrsSupported : 1;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY2;
@@ -360,11 +376,25 @@ typedef union { UINT16 EqualizationPhase2Successful : 1;
UINT16 EqualizationPhase3Successful : 1;
UINT16 LinkEqualizationRequest : 1;
- UINT16 Reserved : 10;
+ UINT16 RetimerPresence : 1;
+ UINT16 TwoRetimersPresence : 1;
+ UINT16 CrosslinkResolution : 2;
+ UINT16 FlitModeStatus : 1;
+ UINT16 Reserved : 1;
+ UINT16 DownstreamComponentPresence : 3;
+ UINT16 DRSMessageReceived : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS2;
+typedef union {
+ struct {
+ UINT32 InbandPdDisable : 1;
+ UINT32 Reserved : 30;
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_SLOT_CAPABILITY2;
+
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
PCI_REG_PCIE_CAPABILITY Capability;
@@ -386,7 +416,7 @@ typedef struct { PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
- UINT32 SlotCapability2;
+ PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2;
UINT16 SlotControl2;
UINT16 SlotStatus2;
} PCI_CAPABILITY_PCIEXP;
diff --git a/MdePkg/Include/IndustryStandard/PciExpress60.h b/MdePkg/Include/IndustryStandard/PciExpress60.h new file mode 100644 index 0000000000..5427ddde38 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/PciExpress60.h @@ -0,0 +1,121 @@ +/** @file
+Support for the PCI Express 6.0 standard.
+
+This header file may not define all structures. Please extend as required.
+
+Copyright (c) 2024, American Megatrends International LLC. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PCIEXPRESS60_H_
+#define PCIEXPRESS60_H_
+
+#include <IndustryStandard/PciExpress50.h>
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.7 of PCI Express Base Specification 6.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_ID 0x0031
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_VER1 0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES_OFFSET 0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL_OFFSET 0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS_OFFSET 0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x10
+
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_ID 0x002F
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_VER1 0x1
+
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_3_OFFSET 0x04
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_3_OFFSET 0x08
+#define EFI_PCIE_CAPABILITY_DEVICE_STATUS_3_OFFSET 0x0C
+
+#pragma pack(1)
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES;
+
+typedef union {
+ struct {
+ UINT32 Reserved : 32; // Reserved bit 0:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL;
+
+typedef union {
+ struct {
+ UINT32 EqualizationComplete : 1; // bit 0
+ UINT32 EqualizationPhase1Success : 1; // bit 1
+ UINT32 EqualizationPhase2Success : 1; // bit 2
+ UINT32 EqualizationPhase3Success : 1; // bit 3
+ UINT32 LinkEqualizationRequest : 1; // bit 4
+ UINT32 TransmitterPrecodingOn : 1; // bit 5
+ UINT32 TransmitterPrecodeRequest : 1; // bit 6
+ UINT32 NoEqualizationNeededRcvd : 1; // bit 7
+ UINT32 Reserved : 24; // Reserved bit 8:31
+ } Bits;
+ UINT32 Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS;
+
+typedef union {
+ struct {
+ UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
+ UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
+ } Bits;
+ UINT8 Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES Capablities;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL Control;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS Status;
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_64_0;
+///@}
+
+typedef union {
+ struct {
+ UINT32 DmwrRequestRouting : 1; // bit 0
+ UINT32 FourteenBitTagCompleter : 1; // bit 1
+ UINT32 FourteenBitTagRequester : 1; // bit 2
+ UINT32 ReceiverL0p : 1; // bit 3
+ UINT32 PortL0pExitLatencyLatency : 3; // bit 4..6
+ UINT32 RetimerL0pExit : 3; // bit 7..9
+ UINT32 Reserved : 22; // bit 10..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_CAPABILITY3;
+
+typedef union {
+ struct {
+ UINT32 DmwrRequesterEnable : 1; // bit 0
+ UINT32 DmwrEgressBlocking : 1; // bit 1
+ UINT32 FourteenBitTagRequesterEnable : 1; // bit 2
+ UINT32 L0pEnable : 1; // bit 3
+ UINT32 TargetLinkWidth : 3; // bit 4..6
+ UINT32 Reserved : 25; // bit 7..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_CONTROL3;
+
+typedef union {
+ struct {
+ UINT32 InitialLinkWidth : 3; // bit 0..2
+ UINT32 SegmentCaptured : 1; // bit 3
+ UINT32 RemoteL0pSupported : 1; // bit 4
+ UINT32 Reserved : 27; // bit 5..31
+ } Bits;
+ UINT32 Uint32;
+} PCI_REG_PCIE_DEVICE_STATUS3;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h index 020733b777..c07cfcb814 100644 --- a/MdePkg/Include/IndustryStandard/SmBios.h +++ b/MdePkg/Include/IndustryStandard/SmBios.h @@ -1524,7 +1524,7 @@ typedef struct { UINT8 AsyncSurpriseRemoval : 1;
UINT8 FlexbusSlotCxl10Capable : 1;
UINT8 FlexbusSlotCxl20Capable : 1;
- UINT8 Reserved : 1; ///< Set to 0.
+ UINT8 FlexbusSlotCxl30Capable : 1; /// SMBIOS spec 3.7.0 updated CXL 3.0 support
} MISC_SLOT_CHARACTERISTICS2;
///
@@ -2027,6 +2027,13 @@ typedef struct { //
UINT32 ExtendedSpeed;
UINT32 ExtendedConfiguredMemorySpeed;
+ //
+ // Add for smbios 3.7.0
+ //
+ UINT16 Pmic0ManufacturerID;
+ UINT16 Pmic0RevisionNumber;
+ UINT16 RcdManufacturerID;
+ UINT16 RcdRevisionNumber;
} SMBIOS_TABLE_TYPE17;
///
diff --git a/MdePkg/Include/IndustryStandard/Tdx.h b/MdePkg/Include/IndustryStandard/Tdx.h index 2662761883..17f1e8f414 100644 --- a/MdePkg/Include/IndustryStandard/Tdx.h +++ b/MdePkg/Include/IndustryStandard/Tdx.h @@ -113,8 +113,8 @@ typedef struct { typedef struct {
UINT64 Gpaw;
UINT64 Attributes;
- UINT32 MaxVcpus;
UINT32 NumVcpus;
+ UINT32 MaxVcpus;
UINT64 Resv[3];
} TDCALL_INFO_RETURN_DATA;
diff --git a/MdePkg/Include/IndustryStandard/Tpm20.h b/MdePkg/Include/IndustryStandard/Tpm20.h index 4440f3769f..9303f16278 100644 --- a/MdePkg/Include/IndustryStandard/Tpm20.h +++ b/MdePkg/Include/IndustryStandard/Tpm20.h @@ -203,15 +203,16 @@ typedef UINT16 TPM_ALG_ID; // Table 8 - TPM_ECC_CURVE Constants
typedef UINT16 TPM_ECC_CURVE;
-#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)
-#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
-#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
-#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
-#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
-#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
-#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)
-#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)
-#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)
+#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)
+#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)
+#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)
+#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)
+#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)
+#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)
+#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)
+#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)
+#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)
+#define TPM_ECC_BP_P512_R1 (TPM_ECC_CURVE)(0x0032)
// Table 11 - TPM_CC Constants (Numeric Order)
typedef UINT32 TPM_CC;
diff --git a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h index e7d14f9d2e..882e21dfe5 100644 --- a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h +++ b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h @@ -3,6 +3,7 @@ Copyright (c) 2013 - 2019, Intel Corporation. All rights reserved. <BR>
Copyright (c) 2021, Ampere Computing LLC. All rights reserved. <BR>
+Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. <BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -18,6 +19,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define EFI_TPM2_ACPI_TABLE_REVISION_4 4
#define EFI_TPM2_ACPI_TABLE_REVISION EFI_TPM2_ACPI_TABLE_REVISION_4
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE_REVISION_4 12
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE_REVISION_4
+
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
// Flags field is replaced in version 4 and above
diff --git a/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h b/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h index aaee5d6c88..1b7b2406e9 100644 --- a/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h +++ b/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h @@ -473,8 +473,6 @@ typedef struct tdTCG_Sp800_155_PlatformId_Event2 { // UINT8 PlatformModel[PlatformModelSize];
// UINT8 PlatformVersionSize;
// UINT8 PlatformVersion[PlatformVersionSize];
- // UINT8 PlatformModelSize;
- // UINT8 PlatformModel[PlatformModelSize];
// UINT8 FirmwareManufacturerStrSize;
// UINT8 FirmwareManufacturerStr[FirmwareManufacturerStrSize];
// UINT32 FirmwareManufacturerId;
@@ -499,8 +497,6 @@ typedef struct tdTCG_Sp800_155_PlatformId_Event3 { // UINT8 PlatformModel[PlatformModelSize];
// UINT8 PlatformVersionSize;
// UINT8 PlatformVersion[PlatformVersionSize];
- // UINT8 PlatformModelSize;
- // UINT8 PlatformModel[PlatformModelSize];
// UINT8 FirmwareManufacturerStrSize;
// UINT8 FirmwareManufacturerStr[FirmwareManufacturerStrSize];
// UINT32 FirmwareManufacturerId;
@@ -517,6 +513,18 @@ typedef struct tdTCG_Sp800_155_PlatformId_Event3 { // UINT8 PlatformCertLocator[PlatformCertLocatorLength];
} TCG_Sp800_155_PlatformId_Event3;
+/**
+ * TCG specifies a locator type with the following values
+ * 0 - Raw data in the locator itself.
+ * 1 - URI in rtf2396 format.
+ * 2 - local device path in EFI_DEVICE_PATH_PROTOCOL format.
+ * 3 - UEFI variable (16 byte EFI_GUID, then 00-terminated UCS2 string)
+**/
+#define TCG_LOCATOR_TYPE_RAW_DATA 0
+#define TCG_LOCATOR_TYPE_URI 1
+#define TCG_LOCATOR_TYPE_DEVICE_PATH 2
+#define TCG_LOCATOR_TYPE_UEFI_VARIABLE 3
+
#define TCG_EfiStartupLocalityEvent_SIGNATURE "StartupLocality"
//
|