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* UefiCpuPkg/PiSmmCpuDxeSmm: fix format stringGerd Hoffmann2023-04-011-1/+1
| | | | | | | | | | | | BufferPages is UINTN, so we need "%Lu" when printing it to avoid it being truncated. Also cast to UINT64 to make sure it works for 32bit builds too. Fixes: 4f441d024bee ("UefiCpuPkg/PiSmmCpuDxeSmm: fix error handling") Reported-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MtrrTest: Add test cases for TME-MK enable caseRay Ni2023-04-013-33/+107
| | | | | | | | | | | | | | | | When TME-MK is enabled, the MtrrLib should substract the TME-MK reserved bits from the max PA returned from CPUID instruction. The new test case guarantees such behavior in MtrrLib. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ahmad Anadani <ahmad.anadani@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: Substract TME-MK KEY_ID_BITS from CPU max PARay Ni2023-04-011-2/+22
| | | | | | | | | | | | | | | | | | CPUID enumeration of MAX_PA is unaffected by TME-MK activation and will continue to report the maximum physical address bits available for software to use, irrespective of the number of KeyID bits. So, we need to check if TME is enabled and adjust the PA size accordingly. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ahmad Anadani <ahmad.anadani@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuDxe: Refactor to use CPUID definitionsRay Ni2023-04-012-11/+10
| | | | | | | | | | | | | | | | | The patch does not change any code behavior but only refactors by: * replaces the hardcode 0x80000000 with CPUID_EXTENDED_FUNCTION * replaces the hardcode 0x80000008 with CPUID_VIR_PHY_ADDRESS_SIZE * replace "UINT32 Eax" with "CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize" Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ahmad Anadani <ahmad.anadani@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/MtrrLib: Substract TME-MK KEY_ID_BITS from CPU max PARay Ni2023-04-011-2/+22
| | | | | | | | | | | | | | | | | | CPUID enumeration of MAX_PA is unaffected by TME-MK activation and will continue to report the maximum physical address bits available for software to use, irrespective of the number of KeyID bits. So, we need to check if TME is enabled and adjust the PA size accordingly. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ahmad Anadani <ahmad.anadani@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/MtrrTest: Only claim CPUID max leaf as 1Ray Ni2023-04-011-1/+8
| | | | | | | | | | | | | | | MtrrLib code queries the CPUID leaf 7h result if support. Update Test code temporary to claim the CPUID only supports max leaf as 1 so MtrrLib skips to query CPUID leaf 7h. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ahmad Anadani <ahmad.anadani@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add TME-MK related CPUID and MSR definitionsRay Ni2023-04-012-3/+112
| | | | | | | | | | | | | | | TME (Total Memory Encryption) is the capability to encrypt the entirety of physical memory of a system. TME-MK (Total Memory Encryption-Multi-Key) builds on TME and adds support for multiple encryption keys. The patch adds some necessary CPUID/MSR definitions for TME-MK. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/Test: Disable random test casesRay Ni2023-03-311-10/+10
| | | | | | | | | | | | The random test cases just run for too long that may cause timeout in CI test. Disable them for now. Co-authored-by: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
* Maintainers.txt: BaseTools Bob Feng -> reviewer, Rebecca Cran -> maintainerRebecca Cran2023-03-311-1/+2
| | | | | | | | | | | | | | | Update Maintainers.txt for BaseTools: move Bob Feng from being a maintainer to reviewer, and add myself (Rebecca Cran) as a new maintainer. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdeModulePkg/Ahci: Skip retry for non-transient errorsAlbecki, Mateusz2023-03-312-5/+69
| | | | | | | | | | | | | | | | | | | | | | | bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=4011 Currently AHCI driver will try to retry all failed packets regardless of the failure cause. This is a problem in password unlock flow where number of password retries is tracked by the device. If user passes a wrong password Ahci driver will try to send the wrong password multiple times which will exhaust number of password retries and force the user to restart the machine. This commit introduces a logic to check for the cause of packet failure and only retry packets which failed due to transient conditions on the link. With this patch only packets for which CRC error is flagged are retried. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Hunter Chang <hunter.chang@intel.com> Cc: Baraneedharan Anbazhagan <anbazhagan@hp.com> Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Baraneedharan Anbazhagan <anbazhagan@hp.com>
* OvmfPkg/CI: Revert SMP modeMichael Kubacki2023-03-311-1/+0
| | | | | | | | | | | | | | | | | This is causing excessive boot times in the VS2019 IA32/X64 Full run to shell tasks (> 2 minutes) and blocking all edk2 CI. This patch removes the change so it can be root caused separately without blocking other patches unrelated to OVMF. Reverts f92a9dce10281c103b04d6b38283e0ff1d677b91 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
* .azurepipelines/templates: Increase run to shell timeoutMichael D Kinney2023-03-301-1/+1
| | | | | | | | | | | | | | | Increase the CI agent timeout to boot to UEFI Shell from 1 minute to 2 minutes. There have been a few cases where the boot to shell in QEMU has not quite completed in 1 minute and it is failing the CI check and preventing a PR from being merged. Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Kubacki <mikuback@linux.microsoft.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe: PcdRtcDefaultYear boundsMichael D Kinney2023-03-301-2/+4
| | | | | | | | | | | | | | | | | | Add bounds checks of PcdRtcDefaultYear to guarantee that the year is always between PcdMinimalValidYear and PcdMaximalValidYear. This is required to make the following commit a backwards compatible change and guarantee and invalid year is never set. https://github.com/tianocore/edk2/commit/d55d73152ebf5c793b645d6ec5bc517d219881cd This is required because use of an expression in the DEC file PCD default value is only used to determine the DEC default values. If an INF/DSC overrides PcdRtcDefaultYear, then the DEC expression for PcdMinimalValidYear is not applied again. Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* RedfishPkg/RedfishPlatformCredentialIpmiLib: IPMI implementationNickle Wang2023-03-306-0/+599
| | | | | | | | | | | | | This library follows Redfish Host Interface specification and use IPMI command to get bootstrap account credential(NetFn 2Ch, Command 02h) from BMC. RedfishHostInterfaceDxe will use this credential for the following communication between BIOS and BMC. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Igor Kulchytskyy <igork@ami.com>
* MdePkg: Update MemoryAttributesTable to v2.10Ard Biesheuvel2023-03-302-3/+7
| | | | | | | | | | | | | | | | UEFI v2.10 introduces a new flag to the memory attributes table to inform the OS whether or not runtime services code regions were emitted by the compiler with guard instructions for forward edge control flow integrity enforcement. So update our definition accordingly. Link: https://uefi.org/specs/UEFI/2.10/04_EFI_System_Table.html#efi-memory-attributes-table Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* ArmVirtPkg/ArmPlatformLibQemu: Make IdMap.S BTI compatibleArd Biesheuvel2023-03-301-0/+2
| | | | | | | | | The IdMap.S asm source file has not executable content, but its lack of a BTI annotation prevents the linker from marking any executables it emits as BTI compatible if this object is part of the build. So add the BTI note by hand. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg/PrePeiCore: Make vector table object BTI compatibleArd Biesheuvel2023-03-301-0/+2
| | | | | | | | | | | The object file containing the vector table does not contain any callable functions, so it will not be implicitly annotated as BTI compatible on BTI builds. So add the annotation by hand, and use the 'empty' type so we get the GNU ELF note but not the actual BTI opcode. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* ArmPkg, BaseTools AARCH64: Add BTI ELF note to .hii objectsArd Biesheuvel2023-03-302-2/+3
| | | | | | | | | | | | | | | | The ELF based toolchains use objcopy to create HII object files, which contain only a single .hii section. This means no GNU note is inserted that describes the object as compatible with BTI, even though the lack of executable code in such an object makes the distinction irrelevant. However, the linker will not add the note globally to the resulting ELF executable, and this breaks BTI compatibility. So let's insert a GNU BTI-compatible ELF note by hand when generating such object files. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* ArmPkg/GccLto AARCH64: Add BTI note to LTO helper libraryArd Biesheuvel2023-03-301-0/+0
| | | | | | | | | | | | | The GccLto helper library does not contain any code, as its only purpose is to pull in other libraries that implement intrinsics to which the linker's codegen pass may emit calls. So mark it as BTI compatible, so that the linker does not complain about unannotated objects. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* ArmPkg: Emit BTI opcodes when BTI codegen is enabledArd Biesheuvel2023-03-303-6/+6
| | | | | | | | | | | | | | | | When building with -mbranch-protection=bti, which affects the compiler codegen only, ensure that the assembler based codegen is aligned with this, by emitting the BTI C opcode at the start of each exported function. While most exported functions are not in fact ever called indirectly, whether or not this is the case is a property of the caller so annotating every exported function is a reasonable default. While at it, fix two occurrences in ArmPkg of exported functions that did not use the ASM_FUNC() macro. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseRngLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-302-2/+2
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseSynchronizationLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-301-0/+5
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseMemoryLibOptDxe AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-305-0/+9
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-308-0/+10
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseLib AARCH64: Make LongJump() BTI compatibleArd Biesheuvel2023-03-301-2/+1
| | | | | | | | | | | | | | | | | | Currently, the AArch64 implementation of LongJump() avoids using the RET instruction to perform the jump, even though the target address is held in the link register X30, as the nature of a long jump implies that the ordinary return address prediction machinery will not be able to make a correct prediction. However, LongJump() is rarely used, and the return stack will be out of sync in any case, so this optimization has little value in practice, and given that indirect calls other than function returns require a BTI landing pad at the call site, this optimization is not compatible with BTI. So let's just use RET instead. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseIoLibIntrinsic AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-301-0/+8
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/BaseCpuLib AARCH64: Make asm files BTI compatibleArd Biesheuvel2023-03-302-0/+2
| | | | | | | | | Add the BTI instructions and the associated note to make the AArch64 asm objects compatible with BTI enforcement. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* MdePkg/ProcessorBind AARCH64: Add asm macro to emit GNU BTI noteArd Biesheuvel2023-03-301-0/+34
| | | | | | | | | | Implement a CPP macro that can be called from .S files to emit the .note section carrying the annotation that informs the linker that the object file is compatible with BTI control flow integrity checks. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com>
* UefiPayloadPkg: Support more input parameterLinus Wu2023-03-301-1/+44
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4386 Add additional input parameter support --SpecRevision: user input spec version --Revision: user input revision --ProducerId: producer company name 1. UniversalPayloadBuild.py 2. Downgrade spec revision from 0.9 to 0.7 Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: Linus Wu <linusx.wu@intel.com>
* OvmfPkg/CI: Boot OVMF in SMP mode.Gerd Hoffmann2023-03-291-1/+1
| | | | | | Increase the chance that CI finds bugs in MP changes. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* ArmVirtPkg: Fix depex in kvmtool guest Rtc librarySami Mujawar2023-03-291-2/+2
| | | | | | | | | | | | | | | | The Rtc library for the kvmtool guest firmware configures the RTC controller address range as runtime memory by calling the gDS->SetMemorySpaceAttributes(). The SetMemorySpaceAttributes() function has a dependency on the CPU Arch Protocol. If the CPU Arch Protocol is not installed the call to set the memory attributes fails with error code EFI_NOT_AVAILABLE_YET. Therefore, set the library dependency on the CPU Arch protocol. Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmVirtPkg: Fix parsing of serial port nodeSami Mujawar2023-03-291-2/+2
| | | | | | | | | | | | | | | When scanning for the Serial Port in the device tree, the length and value parameters to ScanMem8() are not in the right order. This results in the serial port not being detected if the chosen node in the device tree has additional elements. Therefore, pass the parameters to ScanMem8() in the correct order to fix this issue. Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Fix parsing of serial port nodeSami Mujawar2023-03-291-2/+2
| | | | | | | | | | | | | | When scanning for the Serial Port in the device tree, the length and value parameters to ScanMem8() are not in the right order. This results in the serial port not being detected if the chosen node in the device tree has additional elements. Therefore, pass the parameters to ScanMem8() in the correct order to fix this issue. Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Reduce log output from TableHelperLibSami Mujawar2023-03-291-14/+14
| | | | | | | | | Reduce the log output from Configuration Manager Object Parser in TableHelperLib by enabling the logs only if DEBUG_INFO is enabled. Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
* OvmfPkg: Use Xcode5 version of CpuExceptionHandlerLib for CLANGDWARFRebecca Cran2023-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | | The CLANGDWARF toolchain has the same problem as XCODE5 linking CpuExceptionHandlerLib. So, use the Xcode5SecPeiCpuExceptionHandlerLib.inf when building with the CLANGDWARF toolchain. Since the difference is that the non-Xcode5 version uses `mov` while the Xcode5 version uses `lea`, they can be merged in future with the single version using `lea`. [ardb: the main difference is that the 'mov' instructions result in absolute symbol references, which are necessary because the code in question is copied in memory independently from the code that carries the symbols it refers to. The Xcode5 version has additional runtime handling to fix up the copied code with the correct absolute references.] Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg: Replace static struct initialization with ZeroMem callRebecca Cran2023-03-291-1/+3
| | | | | | | | | | | Replace the static struct initialization with a call to ZeroMem to avoid generating a call to memset in certain build configurations. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* RedfishPkg: fix config handler driver issuesNickle Wang2023-03-292-6/+8
| | | | | | | | | | | | | | | Bug fix: - function stack fault - config handler driver requires the dependency of Redfish Credential Protocol - incorrect caller id installation when failed to perform init() - fix typo Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* RedfishPkg: Redfish discover driver improvementNickle Wang2023-03-293-57/+120
| | | | | | | | | | | | | | | | | | | | | | | Bug fix: - function stack fault - properly handle "SubnetAddrInfoIPv6" when there is no IPv6 support - copy-n-paste error in RedfishGetHostInterfaceProtocolData() - fix typo Enhancement: - Redfish discover driver now can configure host IP address based on the information from SMBIOS type 42 record. This saves the effort of configuring host IP address in setup menu. - Performance improvement to driver binding process. Redfish discover driver will wait until all required drivers are ready and do driver binding start(). - Use CopyGuid() to copy GUID instead of intrinsic function. - Error handling when SMBIOS data is corrupted. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* RedfishPkg/JsonLib: address coverity issueNickle Wang2023-03-291-1/+2
| | | | | | | | | | Fix implicit conversion issue in JsonLib. Signed-off-by: Nickle Wang <nicklew@nvidia.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Igor Kulchytskyy <igork@ami.com> Cc: Nick Ramirez <nramirez@nvidia.com> Reviewed-by: Abner Chang <abner.chang@amd.com>
* ArmVirtPkg: can't find gUefiOvmfPkgTokenSpaceGuidJianyong Wu2023-03-281-0/+1
| | | | | | | | | | | commit f13264b34 introduces a bug for CloudHv as OvmfPkg/OvmfPkg.dec is missing in CloudHvHasAcpiDtDxe.inf which leads to gUefiOvmfPkgTokenSpaceGuid found nowhere when build. Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com>
* ArmPkg/SmbiosMiscDxe: Adjust the priority of getting firmware versionTinh Nguyen2023-03-281-24/+38
| | | | | | | | | | | | | | | | | | | The BIOS Firmware Version in the SMBIOS Type 0 can be fetched from the fixed PcdFirmwareVersionString or platform specific OemMiscLib. In fact, the support from OemMiscLib comes into play when the firmware version may be modified at boot time for extended information. Therefore, the priority of getting the version from OemMiscLib should be higher. In case there is no modification in the OemMiscLib, we have to keep HII string STR_MISC_BIOS_VERSION empty or 'Not Specified' to indicate that the firmware version should be fetched from the PcdFirmwareVersionString. Signed-off-by: Tinh Nguyen <tinhnguyen@os.amperecomputing.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Oliver Smith-Denny <osd@smith-denny.com> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* OvmfPkg/PlatformInitLib: simplify mtrr setupGerd Hoffmann2023-03-281-21/+15
| | | | | | | | | | | | With the new mmconfig location at 0xe0000000 above the 32-bit PCI MMIO window we don't have to special-case the mmconfig xbar any more. We'll just add a mtrr uncachable entry starting at MMIO window base and ending at 4GB. Update comments to match reality. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
* OvmfPkg/PlatformInitLib: move mmconfig to 0xe0000000Gerd Hoffmann2023-03-286-10/+10
| | | | | | | | | | | | | | | | | Also swap the ordering of 32bit PCI MMIO window on q35, i.e. use the room between end of low memory and the start of the mmconfig bar. With a typical configuration on modern qemu with gigabyte-aligned memory the MMIO window start at 0x8000000, sized 1532 MB. In case there is memory present above 0x80000000 the window will start at 0xc0000000 instead, with 512 MB size. This depends on qemu commit 4a4418369d6d ("q35: fix mmconfig and PCI0._CRS"), so it raises the bar for the lowest supported version to qemu 4.1 (released Aug 2019). Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
* OvmfPkg/PlatformInitLib: update address space layout commentGerd Hoffmann2023-03-281-13/+15
| | | | | | | | Move the commment up so it is placed just before the address space calculations start. Also add q35 memory layout. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
* OvmfPkg/RiscVVirt: Support multiple reserved memory rangesSunil V L2023-03-281-77/+149
| | | | | | | | | | | | | | | | | | | | | | M-mode firmware ranges should not be used by EDK2/OS. Currently, we search for mmode_resv0 node in FDT and mark it as the reserved memory in EFI memory map. However, if there are multiple M-mode firmware ranges, then this will miss those extra ranges allowing the OS to access the memory and hit a fault. This issue is exposed since recent opensbi started creating two ranges for text and data. Fix this by searching for all reserved memory nodes and marking them as reserved in the EFI memory map. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
* SecurityPkg/FvReportPei: Use FirmwareVolumeShadowPpiUmang Patel2023-03-273-7/+32
| | | | | | | | | | If FirmwareVolumeShadow PPI is available, then use it to shadow FVs to memory. Otherwise fallback to CopyMem(). Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Signed-off-by: Patel Umang <umang.patel@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/Include/Ppi: Add FirmwareVolumeShadowPpiUmang Patel2023-03-272-0/+64
| | | | | | | | | Add FirmwareVolumeShadow PPI to shadow an FV to memory. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Patel Umang <umang.patel@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* UefiCpuPkg/CpuPageTableLib: Reduce the number of random testsDun Tan2023-03-271-5/+5
| | | | | | | | | | | | | | Reduce the number of random tests. In previous patch, non-1:1 mapping is enbaled and it may need more than an hour and a half for the CI test, which may lead to CI timeout. Reduce the number of random test count to pass the CI. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE pagingDun Tan2023-03-273-6/+11
| | | | | | | | | | | Add RandomTest for PAE paging. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Enable PAE pagingDun Tan2023-03-273-11/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify CpuPageTableLib code to enable PAE paging. In PageTableMap() API: When creating new PAE page table, after creating page table, set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero fields are treated as RW and other attributes by the common map logic. So they might be set to 1. When updating exsiting PAE page table, the special steps are: 1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE. 2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. 4.After updating the page table, set the MustBeZero fields of 4 temp PDPTE to 0. 5.Copy the temp PDPTE to original PDPTE. In PageTableParse() API, also create 4 temp PDPTE in stack. Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally use the address of temp PDPTE as the page table address. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
generated by cgit (git 2.34.1) at 2025-02-23 19:35:45 +0000