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* pip: bump edk2-pytool-library from 0.21.8 to 0.21.9dependabot/pip/edk2-pytool-library-0.21.9dependabot[bot]2024-08-051-1/+1
| | | | | | | | | | | | | | Bumps [edk2-pytool-library](https://github.com/tianocore/edk2-pytool-library) from 0.21.8 to 0.21.9. - [Release notes](https://github.com/tianocore/edk2-pytool-library/releases) - [Commits](https://github.com/tianocore/edk2-pytool-library/compare/v0.21.8...v0.21.9) --- updated-dependencies: - dependency-name: edk2-pytool-library dependency-type: direct:production update-type: version-update:semver-patch ... Signed-off-by: dependabot[bot] <support@github.com>
* UefiCpuPkg: rename and simplify IsAddressValid functionDun Tan2024-08-053-34/+31
| | | | | | | | | | | | | | | In this commit, we rename IsAddressValid function to IsSmmProfilePFAddressAbove4GValid and remove unneeded code logic in it. Currently, IsAddressValid is only used in the function RestorePageTableAbove4G. It's used to identify if a SMM profile PF address above 4G is inside mProtectionMemRange or not. So we can remove the PcdCpuSmmProfileEnable FALSE condition related code logic in it. Also the function name is change to be more detailed and specific. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: remove unneeded code in SmmProfilePFHandlerDun Tan2024-08-051-8/+0
| | | | | | | | | | | | | | | | | | | | | | Remove unneeded calling of SmmProfileMapPFAddress () in SmmProfileMapPFAddress if SMM profile is not started. Previously, before SMM profile is started at ReadyToLock, SMM page table only covers [0, 4G]. The access to the range above 4G will cause PF. SmmProfileMapPFAddress is needed here to map the PF address before SMM profile is started. Now we always create full mapping SMM page table in the SmmInitPageTable(). When SMM profile is enabled, before SMM profile is started at ReadyToLock, SMM page table covers [0, MaxSupportedPhysicalAddress]. So the case that access to the range above 4G causes PF won't happen anymore. Then we can remove the calling of SmmProfileMapPFAddress before SMM profile is started. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: rename the SmiDefaultPFHandler functionDun Tan2024-08-057-166/+221
| | | | | | | | Rename SmiDefaultPFHandler to SmiProfileMapPFAddress and move the implementation to SmmProfileArch.c since it only will be used when SMM profile is enabled. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: Remove duplicate code in SmiPfHandlerDun Tan2024-08-052-12/+6
| | | | | | | | | | | | | | In this commit, we remove duplicate CpuDeadLoop in SmiPfHandler where mCpuSmmRestrictedMemoryAccess is TRUE. With last commit, we always call CpuDeadLoop if SMM profile is disabled. Then the CpuDeadLoop calling for the condition (mCpuSmmRestrictedMemoryAccess && IsSmmCommBufferForbiddenAddress (PFAddress)) is not needed anymore. We also modify the IA32 related code to be aligned with X64. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg:CpuDeadLoop in SmiPFHandler if SMM profile is disabledDun Tan2024-08-052-3/+4
| | | | | | | | | | | | | | | | | | | | Always call CpuDeadLoop() in SmiPFHandler if SMM profile is disabled. Previously, when PcdCpuSmmRestrictedMemoryAccess is FALSE, SMM page table only covers [0, 4g]. When code access to range above 4g happens, SmiPFHandler will map the accessed not-present range to present. After we always create full mapping page table, the dynamic page table creation logic is only needed when SMM profile is enabled. So we use CpuDeadLoop() in SmiPFHandler to cover the all the PF exception when SMM profile is disabled Considering that [0, 4g] is always mapped in SMM page table, we also modify the IA32 SmiPFHandler code to be aligned with X64 code. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: remove unnecessary manipulation for smm page tableDun Tan2024-08-051-17/+17
| | | | | | | | | | | | | | | | | | | In this commit, we only set some special bits in paging entry content when SMM profile is enabled. Previously, we set Pml4Entry sub-entries number and set the IA32_PG_PMNT bit for first 4 PdptEntry. It's to make sure that the paging structures cover [0, 4G] won't be reclaimed during dynamic page table creation. In last commit, we always create full mapping SMM page table regardless PcdCpuSmmRestrictedMemoryAccess. With this change, we only need to dynamic create SMM page table in smm PF handler when PcdCpuSmmProfileEnable is TRUE. So the sub-entries number and IA32_PG_PMNT bit in paging entry is only needed to set when PcdCpuSmmProfileEnable is TRUE. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: always create full mapping SMM page tableDun Tan2024-08-052-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this commit, we always create full mapping SMM page table in SmmInitPageTable regardless the value of the PcdCpuSmmRestrictedMemoryAccess. Previously, when PcdCpuSmmRestrictedMemoryAccess is false, only [0, 4G] is mapped in smm page table in SmmInitPageTable. If the range above 4G is accessed in SMM, SmiPFHandler will create new paging entry for the accessed range. To simplify the code logic, we also create full mapping SMM page table in SmmInitPageTable when PcdCpuSmmRestrictedMemoryAccess is false. Then we don't need to dynamic create paging entry for range above 4G except SMM profile is enabled. The comparison of SMM page table before and after the change under different configuration are listed here: 1.PcdCpuSmmRestrictedMemoryAccess is TRUE No change 2.PcdCpuSmmRestrictedMemoryAccess is FALSE and PcdCpuSmmProfileEnable is TRUE Before: the SMM page table when ReadyToLock covers 1. SMRAM range 2.SMM profile range 3. MMIO range below 4G After: the SMM page table when ReadyToLock covers 1. SMRAM range 2.SMM profile range 3. MMIO range below 4G and above 4G 3.PcdCpuSmmRestrictedMemoryAccess is FALSE and PcdCpuSmmProfileEnable is FALSE Before: the SMM page table when ReadyToLock covers [0, 4G] After: the SMM page table when ReadyToLock covers [0, MaxSupportPhysicalAddress] Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: Revert "UefiCpuPkg/PiSmmCpuDxeSmm: Fix system..."Dun Tan2024-08-051-30/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bef0d333dc "UefiCpuPkg/PiSmmCpuDxeSmm: Fix system hang when SmmProfile enable". The commit bef0d333dc was added to modify the code logic in InitPaging() to fix a code assert issue. Previously, the root cause of this issue is that we try to only set NX attribute for not-present MMIO range above 4G when SMM profile feature is enabled, which is not allowed by CpuPageTableLib. But after we always create full mapping initial SMM page table in the next commit, this code assert issue won't happen anymore since MMIO range above 4g will also be present in SMM page table before InitPaging(). Meanwhile another issue was introduced by commit bef0d333dc: In the entrypoint of PiSmmCpuDxe driver, we will set some pages in stack range as not-present in SMM page table if PcdCpuSmmStackGuard or PcdControlFlowEnforcementPropertyMask is TRUE. But in commit bef0d333dc, all SMRAM range are set to present in InitPaging() if SMM profile is enabled. Then the stack guard and shadow stack features do not work anymore. So let's revert the commit "UefiCpuPkg/PiSmmCpuDxeSmm: Fix system hang when SmmProfile enable" Signed-off-by: Dun Tan <dun.tan@intel.com>
* BaseTools/Capsule: Support Different Hash Algorithm for Payload DigestJason1 Lin2024-08-051-14/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4821 - The capsule payload digest got hardcoded inside the GenerateCapsule script as "sha256". - It would be hard for the caller to change the supported hash algorithm which supported on OpenSSL or Windows signtool program and platform. - Capsule payload digest signed data is followed by the PKCS#7 standard, in EDK-II CryptoPkg "Pkcs7Verify ()" is supported to validate with several hash algorithms naturally. (md5, sha1, sha256, sha384, and sha512) - Deliver below changes within this patch, (1) Introduce an optional argument "--hash-algorithm" to assign the caller expected one and leave the default value "sha256" to support the backward compatibility. (2) Add the double quotes to put the string of certificate's subject name inside it. (3) Set "Open" argument of "SignToolSubjectName" into "False". (4) Set "Convert" argument of "SignToolSubjectName: into "str". (5) Correct the actual name of the "--subject-name" flag. (6) Add back correct number of arguments for PayloadDescriptor class object initializing. Note: - Platform needs to support the correspond hash algorithm to validate the digital signature or the failure would be observed. - Set the md5 and sha1 algorithm as EOL based on the CryptoPkg supported table and reject the capsule creation. Signed-off-by: Jason1 Lin <jason1.lin@intel.com>
* MdePkg /IoRemappingTable: Define additional IORT SMMUv3 node flags.joe2024-08-041-1/+2
| | | | | | | | | | | | | | | | | | | | | The flag for HTTU override in an SMMUv3 node in the IORT table is defined in MdePkg/Include/IndustryStandard/IoRemappingTable.h as a single bit. BIT0 or BIT1. The implementation of this field is actually two bits, with the following mapings: 0b0000: Hardware update of the Access flag and dirty state are not supported. 0b0001: Support for hardware update of the Access flag for Block and Page descriptors. 0b0010: As 0b0001, and adds support for hardware update of the Access flag for Block and Page descriptors. Hardware update of dirty state is supported. Referenced in Arm® System Memory Management Unit Architecture Specification SMMU architecture version 3: https://documentation-service.arm.com/static/63d7a2d5e4378a55c5e045b9 Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
* BaseTools/WinRcPath: Improve Performance.Joey Vagedes2024-08-041-10/+26
| | | | | | | | | | | | | | | | WinRcPath generally takes about 2 seconds to run, due to calling multiple .bat files behind the scenes. This change reduces this time to ~0 seconds due to the following changes: 1. It will attempt to load the path from the cache, which is located a $(WORKSPACE)/Conf/.rc_path. If the loading is a success and the rc_path still exists, it will use it. 2. If the cache did not exist, or the path provided by the cache does not exist, it will find the rc path via the .bat files. If that succeeds, it will write the path to the cache. Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
* OvmfPkg: Pass correct virtio-scsi request sizeSami Mujawar2024-08-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch at "1fc55a3933b0 OvmfPkg: Use heap memory for virtio-scsi request" modified the virtio-scsi request header memory to be allocated from the heap. In doing so the request structure header which was a local variable on the stack was converted to be a pointer. This required adjusting the size computation for the request header to reflect that the structure was changed to a pointer. Unfortunately, this was missed out in the call to VirtioAppendDesc() for enqueuing the request due to which only 8 bytes were being shared with the host instead of the size of the VIRTIO_SCSI_REQ structure which is 51 bytes. This resulted in the following error message to be printed by qemu: "qemu-system-<arch>: wrong size for virtio-scsi headers" and the virtio-scsi functionality degraded. Therefore, pass the correct size of the virtio-scsi request header when enqueuing the request. Reported-by: Aithal Srikanth <sraithal@amd.com> Tested-by: Aithal Srikanth <sraithal@amd.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Avoid use global variable in InitSmmS3Cr3Jiaxin Wu2024-08-026-20/+29
| | | | | | | This patch is to avoid use global variable in InitSmmS3Cr3. No function impact. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clean redundant SmmS3Cr3 InitJiaxin Wu2024-08-023-8/+3
| | | | | | | | The SmmS3Cr3 is only used by S3Resume PEIM to switch CPU from 32bit to 64bit, it should be the CR3 for Non-SMM environment and init by InitSmmS3Cr3 function. No need set to SMM CR3. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: clean unused PCD for S3Jiaxin Wu2024-08-021-1/+0
| | | | | | | This patch is to clean the PcdCpuFeaturesInitOnS3Resume since it's unused after commit 077760fe Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* DynamicTablesPkg/DynamicTableManagerDxe: Adds X64 GetAcpiTablePresenceInfoAbdul Lateef Attar2024-08-022-9/+7
| | | | | | | | | Adds X64 specific GetAcpiTablePresenceInfo() function, which checks for mandatory ACPI tables. Cc: Sami Mujawar <Sami.Mujawar@arm.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
* DynamicTablesPkg/AcpiFadtLib: Adds FADT X64 generatorAbdul Lateef Attar2024-08-027-50/+662
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4781 Updates FADT X64 generator to collect below configuration information and update the table accordingly. - SCI interrupt - SCI command - PM Block - GPE Block - PM Block 64-bit - GPE Block 64-bit - Sleep block - Reset block - Miscellaneous legacy information Cc: Sami Mujawar <Sami.Mujawar@arm.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
* DynamicTablesPkg: Adds X64 namespace objectAbdul Lateef Attar2024-08-024-0/+72
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4781 Adds empty X64 namespace object for future use. Cc: Sami Mujawar <Sami.Mujawar@arm.com> Cc: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Iterate page table to find proper entryJiaxin Wu2024-08-021-16/+29
| | | | | | | | | | | Iterate through the page table to find the appropriate page table entry for page creation if one of the following cases is met: 1) StartBit > EndBit: The PageSize of current entry is bigger than the platform-specified PageSize granularity. 2) IA32_PG_P bit is 0 & IA32_PG_PS bit is not 0: The current entry is present and it's a non-leaf entry. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove assert check for PDE entry not existJiaxin Wu2024-08-021-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If 2MB-page is selected, PDE entry might exist, it's incorrect to assert it's not exist. Detailed see blow case analysis (it's similar case if address exceeds 4G): Assume the Default Page table has covered below 6M size range: [0000000000001000, 0000000000601000) Then, with PageTableMap API, below Page table entry will be created if 1G-page or 2M-page mode is selected: [0000000000001000, 0000000000002000) --> 4K [0000000000002000, 0000000000003000) --> 4K ... [00000000001FF000, 0000000000200000) --> 4k [0000000000200000, 0000000000400000) --> 2M [0000000000400000, 0000000000600000) --> 2M [0000000000600000, 0000000000601000) --> 4K Above will cover 2M aligned address (0000000000600000) in page table. If Page Fault happen by accessing 0000000000602000, need create the page entry: [0000000000602000, 0000000000603000) --> 4K But PDE entry has been created/existed in page table with 0 PS bit. So, this patch removes the assert check. The page table entry created will be the platform-specified PageSize granularity. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Check PDE entry exist or not before useJiaxin Wu2024-08-023-5/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Before the commit 701b5797 & 4ceefd6d, 2MB-page will be created to cover [0: 4G] by default if SmmProfile enabled, and it will be go through to change 2MB-page into 4KB-page during page table update (InitPaging). If so, there was no problem to assert PDE entry exist in the RestorePageTableBelow4G. But after above commits, PageTableMap API is used to create/update the page table, 1G-page will be the default page table mode, and only covers the limited address range. Those not covered ranges will be marked as non-present in 1g-page level address. If so, 2M-page address might not exist, it's incorrect to assert PDE entry exist in the RestorePageTableBelow4G. The correct behavior should check PDE entry exist or not, if not, PDE should be allocated and assigned to PDPTE. Note: RestorePageTableBelow4G () does not use 1G page size entries for the creation of new pages, maintaining consistency with the behavior of the original code. The purpose of this patch is to ensure that a Page Directory Entry (PDE) exists prior to its usage. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Enable single step after SmmProfile startJiaxin Wu2024-08-022-5/+11
| | | | | | | | | | | | | There is a bug in the existing code: the single step is always enabled once the Page Fault (#PF) occurs, but it is only disabled when the SMM Profile feature actually starts (see DebugExceptionHandler). If the SMM Profile feature has not been started, this will result in the single-step mode remaining enabled if a Page Fault occurs. This patch is to enable the single-step debugging mode by setting the Trap Flag only after SmmProfile feature starts. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* DynamicTablesPkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-012-2/+2
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in DynamicTablesPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* EmbeddedPkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-014-4/+4
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in EmbeddedPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* UefiPayloadPkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-015-7/+7
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in UefiPayloadPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* RedfishPkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-013-6/+6
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in RedfishPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* MdePkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-015-32/+32
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in MdePkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* ArmVirtPkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-012-15/+15
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in ArmVirtPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* ArmPlatformPkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-013-5/+5
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in ArmPlatformPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* .pytool: Sort the list of words in cspell.base.yamlRebecca Cran2024-08-011-234/+234
| | | | | | | Sort the list of words to add to cspell's dictionary by running the list through `sort`. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* .pytool: Add "MPIDR" to the list of known words in cspell.base.yamlRebecca Cran2024-08-011-1/+2
| | | | | | | | "MPIDR" is the Multiprocessor Affinity Register on Arm systems. Add it the list of known words so that cspell doesn't flag it as a misspelling. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* ShellPkg/AcpiView: Add MPAM ParserRohit Mathew2024-08-015-2/+1267
| | | | | | | | | | | | | | | Add a parser for the MPAM (Memory system resource partitioning and monitoring) ACPI table. This parser would parse all MPAM related structures embedded as part of the ACPI table. Necessary validations are also performed where and when required. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Cc: James Morse <james.Morse@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Cc: Yeo Reum Yun <YeoReum.Yun@arm.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* ShellPkg: acpiview: Add routines to print reserved fieldsRohit Mathew2024-08-012-0/+164
| | | | | | | | | | | | | Most of the ACPI tables have fields that are marked reserved. Implement functions "DumpReserved" and "DumpReservedBits" aligning with the print-formatter prototype to print out reserved fields. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Cc: James Morse <james.Morse@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ShellPkg: acpiview: Add routine to print 16 charsRohit Mathew2024-08-012-0/+57
| | | | | | | | | | | | | | | Certain ACPI tables like MPAM has fields which are 16 bytes long. Routines similar to Dump12Chars but for 16 characters are required to print such fields. Add Dump16Chars routine to satisfy this requirement. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Cc: James Morse <james.Morse@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ShellPkg/AcpiView: Update print-formatter prototypeRohit Mathew2024-08-0112-36/+98
| | | | | | | | | | | | | | | | | As of now, the print-formatter implemented by the FNPTR_PRINT_FORMATTER function pointer takes two parameters, the format string and the pointer to the field. For cases where the print-formatter has to have access to the length of the field, there is no clean way to currently do it. In order to resolve this, update the print-formatter's prototype to take the length of the field as a third parameter. This change should improve the overall robustness and flexibility of AcpiView. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Cc: James Morse <james.Morse@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ShellPkg/AcpiView: Update field-validator prototypeRohit Mathew2024-08-0119-137/+266
| | | | | | | | | | | | | | | | | | | | | As of now, the field-validator implemented by FNPTR_FIELD_VALIDATOR function pointer takes two parameters, the pointer to the field and a context pointer. For cases where the validator has to have access to the length of the field, there is no clean way to currently do it. In order to resolve this, this commit updates the field-validator's prototype to take the length of the field as an additional parameter. This enhancement allows field validators to perform more comprehensive validation, especially when the length of the field is critical to the validation logic. This change should improve the overall robustness and flexibility of AcpiView. Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Cc: James Morse <james.Morse@arm.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/IndustryStandard: Add definitions for MPAM ACPI specificationRohit Mathew2024-08-012-1/+252
| | | | | | | | | | | | | | | | Add definitions, macros and types for elements associated with MPAM ACPI 2.0 specification. Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Cc: James Morse <james.Morse@arm.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Thomas Abraham <thomas.abraham@arm.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* IntelFsp2WrapperPkg/FspmWrapperPeim: Fix FspT/M address for measurementZhihao Li2024-08-012-8/+33
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4716 Tcg module should use permanent address of FSP-T/M for measurement. TCG notification checks MigatedFvInfoHob and transmits DRAM address for measurement. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Chen Gang C <gang.c.chen@intel.com> Signed-off-by: Zhihao Li <zhihao.li@intel.com>
* ArmVirtPkg: Switch all PrePeiCore users to new Sec.infArd Biesheuvel2024-08-014-4/+4
| | | | | | | | Switch to the new SEC driver based on PrePeiCore, but with a sane name. The old one will be retired once all users have migrated, including many in edk2-platforms. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg: Clone PrePeiUniCore into SecArd Biesheuvel2024-08-0113-0/+892
| | | | | | | | | | | | PrePeiUniCore was already named rather awkwardly, but now that the UniCore bit has become redundant too, let's rename it in a way that conveys its purpose a bit better: Sec. This also matches what other architectures and platforms tend to provide. A straight rename would break all out-of-tree users, so clone it into a new module with a fresh GUID, giving users some time to update. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg: Clone PrePiUniCore into PeilessSecArd Biesheuvel2024-08-018-0/+607
| | | | | | | | | | | PrePiUniCore was already spectacularly mis-named but now that the UniCore bit has become redundant too, let's rename it in a way that conveys its purpose a bit better: PeilessSec. A straight rename would break all out-of-tree users, so clone it into a new module with a fresh GUID, giving users some time to update. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg/PrePi: Make some functions STATICArd Biesheuvel2024-08-012-6/+17
| | | | | | | Make some functions STATIC that are only called locally, and add some function headers to placate the tools. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/ArmArchTimerLib: Drop pointless constructorArd Biesheuvel2024-08-012-25/+2
| | | | | | | | | | | | Drop the pointless constructor in ArmArchTimerLib, which does nothing useful, especially because AArch64 mandates the presence of the generic timer, and 32-bit ARM is mostly obsolete these days. To preserve the existing behavior in DEBUG builds when actually using the timer, move the ASSERT () on a non-zero frequency to the associated accessor helper function. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg/PrePi: Drop call to TimerConstructor()Ard Biesheuvel2024-08-012-8/+0
| | | | | | | Drop the call to the TimerConstructor, which should not be called explicitly, and does nothing useful to begin with. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmVirtPkg/PrePi: Drop call to TimerConstructor()Ard Biesheuvel2024-08-012-8/+0
| | | | | | | Drop the call to the TimerConstructor, which should not be called explicitly, and does nothing useful to begin with. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg/PrePi: Drop secondary stack handlingArd Biesheuvel2024-08-014-54/+10
| | | | | | | | | | This SEC driver is single CPU only now, so all of the secondary stack handling is dead code, and can be removed. This removes the last remaining user of the associated PCD, so drop that as well. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg/PrePeiCore: Drop secondary stack handlingArd Biesheuvel2024-08-014-89/+25
| | | | | | | This SEC driver is single CPU only now, so all of the secondary stack handling is dead code, and can be removed. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg/PrePeiCore: Drop MPCore variantArd Biesheuvel2024-08-017-272/+11
| | | | | | | | The PrePeiCore SEC driver can be built in unicore and MPcore versions from [mostly] the same source. The latter is obsolete, so remove it and simplify the remaining code accordingly. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPlatformPkg/PrePi: Drop MPCore variantArd Biesheuvel2024-08-017-295/+8
| | | | | | | | The PrePi SEC driver can be built in unicore and MPcore versions from [mostly] the same source. The latter is obsolete, so remove it and simplyify the remaining code accordingly. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
generated by cgit (git 2.34.1) at 2025-02-22 22:33:21 +0000