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* IntelFsp2(Wrapper)Pkg: Revert from e8208100 to 737f812bChasel, Chiu2018-09-289-76/+51
| | | | | | | | | | | | Commit formats had issues so reverted 9 commits from IntelFsp2Pkg and IntelFsp2WrapperPkg. Will re-submit them with correct formats. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* ShellPkg/TftpDynamicCommand: Fix the potentially uninitialized local ↵Jiaxin Wu2018-09-281-1/+2
| | | | | | | | | | | | | | | | | variable used. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1217 Local variable 'Mtftp4Token' might be uninitialized when error happen. This patch is to resolve the issue. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Carsey Jaben <jaben.carsey@intel.com> Cc: Zeng Star <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* EmulatorPkg/EmulatorPkg.dsc: override PCD default to avoid boot failureJian J Wang2018-09-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1215 This issue is caused by commit 5267926134d17e86672b84fd57b438f05ffa68e1. The reason is this commit changed the condition of building page table in DxeIpl. The code before it will only build page table for the sake of PcdSetNxForStack. This commit added PcdImageProtectionPolicy and PcdDxeNxMemoryProtectionPolicy into the logic. But the default value of PcdImageProtectionPolicy is 02, which means the DxeIpl should build page table. Due to the fact that EmulatorPkg doesn't support page table at all, this will cause exception on Windows OS. This patch solves this issue by setting PcdImageProtectionPolicy to 0 explicitly in EmulatorPkg.dsc. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* Nt32Pkg/Nt32Pkg.dsc: override PCD default to avoid boot failureJian J Wang2018-09-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1215 This issue is caused by commit 5267926134d17e86672b84fd57b438f05ffa68e1. The reason is this commit changed the condition of building page table in DxeIpl. The code before it will only build page table for the sake of PcdSetNxForStack. This commit added PcdImageProtectionPolicy and PcdDxeNxMemoryProtectionPolicy into the logic. But the default value of PcdImageProtectionPolicy is 02, which means the DxeIpl should build page table. Due to the fact that Nt32Pkg doesn't support page table at all, this will cause exception on Windows OS. This patch solves this issue by setting PcdImageProtectionPolicy to 0 explicitly in Nt32Pkg.dsc. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* GenCfgOpt.py: remove tailing space from output fileChasel, Chiu2018-09-281-2/+9
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212 UPD header files generated by GenCfgOpt.py may have tailing white space from some of the UPD description in DSC, especially when python script automatically switching lines for long description string. This patch will always remove tailing white space for UPD header files. Test: Verified the patch can remove tailing space in output header files when UPD DSC contains intentional tailing white space. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignmentChasel, Chiu2018-09-281-2/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211 For reducing maintenance effort, the UPD offset can be automatic assigned by GenCfgOpt.py following by alignment requirements. The usage model as below: . If UPD offset in DSC file are all '*', GenCfgOpt.py will assign offset for all UPD automatically. In this case no need to manually hardcode offset to all UPD in DSC. . If UPD offset in DSC file are all not '*', GenCfgOpt.py will use hardcoded offset directly (original usage model) . Tool does not support mixing scenario so UPD offset in DSC should be all '*' or all hardcoded but not mixed. In auto mode UPD offset will be assigned following natural alignment (size aligned) rule and the whole structure size will align to either 32bits or 64bits depends on maximal UPD size in the structure. Test: Verified by both UPD offset hardcoded or '*' in DSC and generated UPD header files are correct. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCDChasel, Chiu2018-09-281-3/+3
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210 FixedAtBuild PCD is suggested to be used instead of FeatureFlag PCD so extend this tool to support. Also skipped PCDs which commented out by '#'. Test: Verified with FixedAtBuild PCD for including or excluding lines in generated UPD header files successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 06/16] IntelFsp2WrapperPkg/BaseFspWrapperPlatformLibSample:Chasel, Chiu2018-09-271-3/+0
| | | | | | | | | | | | | | | Remove PCDs The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 05/16] IntelFsp2WrapperPkg/FspWrapperNotifyDxe: Remove anChasel, Chiu2018-09-271-1/+0
| | | | | | | | | | | | | | unused PCD The PCD below is unused, so it has been removed from inf. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 04/16] IntelFsp2Pkg/BaseFspSwitchStackLib: Remove unusedChasel, Chiu2018-09-271-4/+0
| | | | | | | | | | | | | | | PCDs The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 03/16] IntelFsp2Pkg/BaseFspPlatformLib: Remove unused PCDsChasel, Chiu2018-09-271-9/+0
| | | | | | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 02/16] IntelFsp2Pkg/BaseFspCommonLib: Remove unused PCDsChasel, Chiu2018-09-271-5/+0
| | | | | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 01/16] IntelFsp2Pkg/FspSecCore: Remove unused PCDsChasel, Chiu2018-09-273-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Use new EfiLocateFirstAcpiTable()Star Zeng2018-09-273-85/+6
| | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=967 Request to add a library function for GetAcpiTable() in order to get ACPI table using signature as input. After evaluation, we found there are many duplicated code to find ACPI table by signature in different modules. This patch updates PiSmmCpuDxeSmm to use new EfiLocateFirstAcpiTable() and remove the duplicated code. Cc: Younas khan <pmdyounaskhan786@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ShellPkg DpDynamicCommand: Use new EfiLocateFirstAcpiTable()Star Zeng2018-09-275-139/+3
| | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=967 Request to add a library function for GetAcpiTable() in order to get ACPI table using signature as input. After evaluation, we found there are many duplicated code to find ACPI table by signature in different modules. This patch updates DpDynamicCommand to use new EfiLocateFirstAcpiTable() and remove the duplicated code. Cc: Younas khan <pmdyounaskhan786@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* PcAtChipsetPkg PcRtc: Use new EfiLocateFirstAcpiTable()Star Zeng2018-09-271-77/+3
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=967 Request to add a library function for GetAcpiTable() in order to get ACPI table using signature as input. After evaluation, we found there are many duplicated code to find ACPI table by signature in different modules. This patch updates PcatRealTimeClockRuntimeDxe to use new EfiLocateFirstAcpiTable() and remove the duplicated code. Cc: Younas khan <pmdyounaskhan786@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* MdeModulePkg S3SaveStateDxe: Use new EfiLocateFirstAcpiTable()Star Zeng2018-09-272-206/+5
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=967 Request to add a library function for GetAcpiTable() in order to get ACPI table using signature as input. After evaluation, we found there are many duplicated code to find ACPI table by signature in different modules. This patch updates S3SaveStateDxe to use new EfiLocateFirstAcpiTable() and remove the duplicated code. Cc: Younas khan <pmdyounaskhan786@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelSiliconPkg IntelVTdDxe: Use new EfiLocateFirstAcpiTable()Star Zeng2018-09-271-133/+3
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=967 Request to add a library function for GetAcpiTable() in order to get ACPI table using signature as input. After evaluation, we found there are many duplicated code to find ACPI table by signature in different modules. This patch updates IntelVTdDxe to use new EfiLocateFirstAcpiTable() and remove the duplicated code. Cc: Younas khan <pmdyounaskhan786@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFrameworkPkg FrameworkUefiLib: Add new EfiLocateXXXAcpiTable APIsStar Zeng2018-09-272-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=967 Request to add a library function for GetAcpiTable() in order to get ACPI table using signature as input. After evaluation, we found there are many duplicated code to find ACPI table by signature in different modules. This patch adds new EfiLocateXXXAcpiTable() APIs in UefiLib for the request and also the following patch to remove the duplicated code. V2: ASSERT(FALSE) and return NULL instead of real implementation for the new APIs as the IntelFrameworkPkg is a to-be-deprecated packages. Cc: Younas khan <pmdyounaskhan786@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg UefiLib: Add new EfiLocateXXXAcpiTable() APIsStar Zeng2018-09-273-0/+499
| | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=967 Request to add a library function for GetAcpiTable() in order to get ACPI table using signature as input. After evaluation, we found there are many duplicated code to find ACPI table by signature in different modules. This patch adds new EfiLocateXXXAcpiTable() APIs in UefiLib for the request and also the following patch to remove the duplicated code. Cc: Younas khan <pmdyounaskhan786@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* NetworkPkg/UefiPxeBcDxe: Add the clarification compared to UefiPxeBcDxe in ↵Jiaxin Wu2018-09-271-2/+7
| | | | | | | | | | | | | | | | MdeModulePkg. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205 This patch is to add the driver usage/difference clarification compared to UefiPxeBcDxe in MdeModulePkg. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* NetworkPkg/IScsiDxe: Add the clarification compared to IScsiDxe in MdeModulePkg.Jiaxin Wu2018-09-271-1/+11
| | | | | | | | | | | | | | Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205 This patch is to add the driver usage/difference clarification compared to IScsiDxe in MdeModulePkg. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* NetworkPkg/TcpDxe: Add the clarification compared to Tcp4Dxe in MdeModulePkg.Jiaxin Wu2018-09-271-2/+7
| | | | | | | | | | | | | | Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205 This patch is to add the driver usage/difference clarification compared to Tcp4Dxe in MdeModulePkg. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/UefiPxeBcDxe: Add the clarification compared to UefiPxeBcDxe in ↵Jiaxin Wu2018-09-271-1/+10
| | | | | | | | | | | | | | | | NetworkPkg. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205 This patch is to add the driver usage/difference clarification compared to UefiPxeBcDxe in NetworkPkg. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/IScsiDxe: Add the clarification compared to IScsiDxe in NetworkPkg.Jiaxin Wu2018-09-271-1/+11
| | | | | | | | | | | | | | Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205 This patch is to add the driver usage/difference clarification compared to IScsiDxe in NetworkPkg. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/Tcp4Dxe: Add the clarification compared to TcpDxe in NetworkPkg.Jiaxin Wu2018-09-271-1/+11
| | | | | | | | | | | | | | Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205 This patch is to add the driver usage/difference clarification compared to TcpDxe in NetworkPkg. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* NetworkPkg/UefiPxeBcDxe: Use the specified MTFTP windowsize.Jiaxin Wu2018-09-274-35/+121
| | | | | | | | | | | | | | | | | | | | | *v2: Since the new PCD (PcdPxeTftpWindowSize) was renamed/defined in NetworkPkg instead of MdeModulePkg, this new version is to update the consuming PXE driver. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=886 This patch is to use the specified MTFTP windowsize to benefit the PXE download performance. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Shao Ming <ming.shao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com>
* NetworkPkg: Define one PCD for PXE to specify MTFTP windowsize.Jiaxin Wu2018-09-272-0/+12
| | | | | | | | | | | | | | | | | | | *v2: Rename and redefine the PCD in NetworkPkg instead of MdeModulePkg. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=886 This patch is to define one new PCD for PXE driver to specify MTFTP windowsize so as to improve the PXE download performance. The default value is set to 4. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Shao Ming <ming.shao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ShellPkg/TftpDynamicCommand: Add one option for tftp command to specify ↵Jiaxin Wu2018-09-272-12/+59
| | | | | | | | | | | | | | | | | | | | | | | windowsize. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=886 This patch is to define one new option for TFTP shell command to specify the windowsize option as defined in RFC 7440. Valid range is between 1 and 64, default value is 1. Note that: RFC 7440 does not mention max window size value, but for the stability reason, the value is limited to 64. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Carsey Jaben <jaben.carsey@intel.com> Cc: Shao Ming <ming.shao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com>
* NetworkPkg/Mtftp6Dxe: Support windowsize in read request operation.Jiaxin Wu2018-09-276-24/+90
| | | | | | | | | | | | | | | | | | | | | Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=886 This patch is to support the TFTP windowsize option described in RFC 7440. The feature allows the client and server to negotiate a window size of consecutive blocks to send as an alternative for replacing the single-block lockstep schema. Currently, the windowsize for write request operation is not supported since there is no real use cases. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Shao Ming <ming.shao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com>
* MdeModulePke/Mtftp4Dxe: Support windowsize in read request operation.Jiaxin Wu2018-09-278-37/+89
| | | | | | | | | | | | | | | | | | | | | Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=886 This patch is to support the TFTP windowsize option described in RFC 7440. The feature allows the client and server to negotiate a window size of consecutive blocks to send as an alternative for replacing the single-block lockstep schema. Currently, the windowsize for write request operation is not supported since there is no real use cases. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Shao Ming <ming.shao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com>
* BaseTool: Support different PCDs that refers to the same EFI variable.bob.c.feng@intel.com2018-09-264-18/+60
| | | | | | | | | | | If Structure PCD and Normal Pcd refer to the same EFI variable, do EFI variable merge, otherwise, do EFI variable combination. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTool: Replace dict with OrderedDict.BobCF2018-09-263-20/+30
| | | | | | | | | | Replace dict with OrderedDict for PCD so that the pcd list has same order. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* BaseTools: Fix the wrong reference _GetSkuIds() in AutoGen codeLiming Gao2018-09-261-1/+1
| | | | | | | | | | | DscBuildData has been updated to define SkuIds instead of _GetSkuIds(). The consumer code should refer to SkuIds. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
* MdePkg/BaseSynchronizationLib: fix XADD operands in GCC IA32/X64 assemblyLaszlo Ersek2018-09-262-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, "gcc-4.8.5-28.el7_5.1.x86_64" generates the following code for me, from the XADD inline assembly added to "X64/GccInline.c" in commit 17634d026f96: > 0000000000004383 <InternalSyncIncrement>: > UINT32 > EFIAPI > InternalSyncIncrement ( > IN volatile UINT32 *Value > ) > { > 4383: 55 push %rbp > 4384: 48 89 e5 mov %rsp,%rbp > 4387: 48 83 ec 10 sub $0x10,%rsp > 438b: 48 89 4d 10 mov %rcx,0x10(%rbp) > UINT32 Result; > > __asm__ __volatile__ ( > 438f: 48 8b 55 10 mov 0x10(%rbp),%rdx > 4393: 48 8b 45 10 mov 0x10(%rbp),%rax > 4397: b8 01 00 00 00 mov $0x1,%eax > 439c: f0 0f c1 00 lock xadd %eax,(%rax) > 43a0: ff c0 inc %eax > 43a2: 89 45 fc mov %eax,-0x4(%rbp) > : "m" (*Value) // %2 > : "memory", > "cc" > ); > > return Result; > 43a5: 8b 45 fc mov -0x4(%rbp),%eax > } > 43a8: c9 leaveq > 43a9: c3 retq > The MOV $0X1,%EAX instruction corrupts the address of Value in %RAX before we reach the XADD instruction. In fact, it makes no sense for XADD to use %EAX as source operand and (%RAX) as destination operand at the same time. The XADD instruction's destination operand is a read-write operand. The GCC documentation states: > The ordinary output operands must be write-only; GCC will assume that > the values in these operands before the instruction are dead and need > not be generated. Extended asm supports input-output or read-write > operands. Use the constraint character `+' to indicate such an operand > and list it with the output operands. You should only use read-write > operands when the constraints for the operand (or the operand in which > only some of the bits are to be changed) allow a register. (The above is intentionally quoted from the oldest GCC release that edk2 supports, namely gcc-4.4: <https://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/Extended-Asm.html>.) Fix the operand list accordingly. With the patch applied, I get: > 0000000000004383 <InternalSyncIncrement>: > UINT32 > EFIAPI > InternalSyncIncrement ( > IN volatile UINT32 *Value > ) > { > 4383: 55 push %rbp > 4384: 48 89 e5 mov %rsp,%rbp > 4387: 48 83 ec 10 sub $0x10,%rsp > 438b: 48 89 4d 10 mov %rcx,0x10(%rbp) > UINT32 Result; > > __asm__ __volatile__ ( > 438f: 48 8b 55 10 mov 0x10(%rbp),%rdx > 4393: 48 8b 45 10 mov 0x10(%rbp),%rax > 4397: b8 01 00 00 00 mov $0x1,%eax > 439c: f0 0f c1 02 lock xadd %eax,(%rdx) > 43a0: ff c0 inc %eax > 43a2: 89 45 fc mov %eax,-0x4(%rbp) > : // no inputs that aren't also outputs > : "memory", > "cc" > ); > > return Result; > 43a5: 8b 45 fc mov -0x4(%rbp),%eax > } > 43a8: c9 leaveq > 43a9: c3 retq Note that some other bugs remain in "BaseSynchronizationLib/*/GccInline.c"; those should be addressed later, under <https://bugzilla.tianocore.org/show_bug.cgi?id=1208>. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1207 Fixes: 17634d026f968c404b039a8d8431b6389dd396ea Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition.Eric Dong2018-09-261-9/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V3 changes include: 1. Keep the ReservedX not change if bit info not changed for this field. V2 changes include: 1. Use X in ReservedX fields from totally new value if MSR structure definition changed. For example, if in current structure, the max reserved variable is Reserved2, in new definition, reserved variable is begin with Reserved3. V1 Changes: Changes includes: 1. Update MSR structure definition, change some reserved fields to useful fields: 1. MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER 2. MSR_XEON_PHI_SMM_MCA_CAP_REGISTER 2. For MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER structure, it expand the field range. Old definition like below: typedef union { /// /// Individual bit fields /// struct { /// /// [Bits 15:0] LVL_2 Base Address (R/W). /// UINT32 Lvl2Base:16; /// /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the /// maximum C-State code name to be included when IO read to MWAIT /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 /// is the max C-State to include 110b - C6 is the max C-State to include. /// UINT32 CStateRange:3; UINT32 Reserved1:13; UINT32 Reserved2:32; } Bits; /// /// All bit fields as a 32-bit value /// UINT32 Uint32; /// /// All bit fields as a 64-bit value /// UINT64 Uint64; } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER; This patch make below changes for this data structure, it expand "CStateRange" field width. old one: UINT32 CStateRange:3; UINT32 Reserved1:13; new one: UINT32 CStateRange:7; UINT32 Reserved1:9; Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.Eric Dong2018-09-261-2/+12
| | | | | | | | | | | | | | | | | | | | | V3 changes include: 1. Keep ReservedX not change if bit info not changed for this field. V2 changes include: 1. Use X in ReservedX fields from totally new value if MSR structure definition changed. For example, if in current structure, the max reserved variable is Reserved2, in new definition, reserved variable is begin with Reserved3. V1 Changes includes: 1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and keep old ↵Eric Dong2018-09-261-10/+24
| | | | | | | | | | | | | | | | | | | | one. Changes includes: 1. Change MSR name: 1. MSR_GOLDMONT_SGXOWNER0 => MSR_GOLDMONT_SGXOWNEREPOCH0 2. MSR_GOLDMONT_SGXOWNER1 => MSR_GOLDMONT_SGXOWNEREPOCH1 2. Keep old MSR definition (MSR_GOLDMONT_SGXOWNER0/1) for compatibility. 1. Define old MSR like below style: #define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one.Eric Dong2018-09-261-13/+27
| | | | | | | | | | | | | | | | | | Changes includes: 1. Change MSR name: 1. MSR_SKYLAKE_SGXOWNER0 => MSR_SKYLAKE_SGXOWNEREPOCH0 2. MSR_SKYLAKE_SGXOWNER1 => MSR_SKYLAKE_SGXOWNEREPOCH1 2. Keep old MSR definition(MSR_SKYLAKE_SGXOWNER0/1) for compatibility 1. Use below coding style to define old MSR #define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR.Eric Dong2018-09-261-48/+0
| | | | | | | | | | | | | | Changes includes: 1. Remove old MSR which not existed in 2018-05 version spec: 1. MSR_CORE_ROB_CR_BKUPTMPDR6 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR.Eric Dong2018-09-261-48/+0
| | | | | | | | | | | | | Changes includes: 1. Remove MSR which not existed in 2018-05 version spec: MSR_P6_ROB_CR_BKUPTMPDR6. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR.Eric Dong2018-09-261-60/+0
| | | | | | | | | | | | | | Changes includes: 1. Remove old MSR which not existed in 2018-05 version spec: 1. MSR_CORE2_BBL_CR_CTL3 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.Eric Dong2018-09-261-0/+64
| | | | | | | | | | | | | Changes includes: 1. Add new MSRs: MSR_IA32_L2_QOS_CFG/MSR_IA32_CSTAR. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.Eric Dong2018-09-261-1/+1546
| | | | | | | | | | | | | | Changes includes: 1. Add new MSR definitions. 2. Add support platform info. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.Eric Dong2018-09-261-3/+246
| | | | | | | | | | | | | | | | | | Changes includes: 1. Add new MSR definition: 1. MSR_XEON_PHI_PPIN_CTL 2. MSR_XEON_PHI_PPIN 3. MSR_XEON_PHI_MISC_FEATURE_ENABLES 4. MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 2. Add DisplayModule == 0x85 supports. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.Eric Dong2018-09-263-2/+164
| | | | | | | | | | | | | Changes includes: 1. Add new MSR: MSR_*_MSRUNCORE_RATIO_LIMIT Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.Eric Dong2018-09-261-0/+48
| | | | | | | | | | | | | Changes includes: 1. Add new MSR: MSR_SILVERMONT_PLATFORM_INFO Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for ↵Eric Dong2018-09-262-3/+276
| | | | | | | | | | | | | | | goldmont plus microarchitecture. Changes includes: 1. Add new MSR file which used for goldmont plus microarchitecture. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr: Update reference spec info.Eric Dong2018-09-2621-372/+359
| | | | | | | | | | | | | | | | | | Latest SDM has moved MSR related content from volume 3 chapter 35 to volume 4 chapter 2. Current MSR's comments need to be updated to reference the new chapter info. Changes includes: 1. Update referenced chapter info from some MSRs. 2. Update referenced SDM version info. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MtrrLib: Revert "Skip MSR access when the pair is invalid"Ruiyu Ni2018-09-261-16/+13
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1187 The patch reverts 9c8c4478cfcacaf5fd60b75ff78d26732d93a5b8 "UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid". Microsoft Windows will report an error in event manager if MTRR usage is different across hibernate even when the difference is in an non valid MTRR pair. This seems like a bug in Windows but for compatibility and servicing reasons we think a change in UEFI would wise. A Windows change has already been submitted for the next iteration (2019 time frame). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com>
generated by cgit (git 2.34.1) at 2025-02-24 19:32:09 +0000