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* MdePkg: Move StackCheckLibStaticInit to StackCheckLibOliver Smith-Denny2025-02-072-0/+2
| | | | | | | | | | | | | | | This commit oves StackCheckLib from a NULL lib to an instance of StackCheckLib. This requires every entry point to add a library dependency on StackCheckLib. It also requires every SEC module to have a dependency on StackCheckLib because there is no standard SEC entry point. It allows for greater flexibility for a platform to apply stack cookies and simplifies DSC logic. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
* UefiCpuPkg LocalApicLib: Correct typo LINT0 to LINT1Star Zeng2025-01-242-2/+2
| | | | | | In ProgramVirtualWireMode(), correct typo LINT0 to LINT1. Signed-off-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/CpuMpPei: Add LoongArch64 supportChao Li2025-01-222-3/+90
| | | | | | | | | | | | Added LoongArch64 CPU multiple processor PPI support. Cc: Ray Ni <ray.ni@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* UefiCpuPkg/CpuMpPei: Split CpuMpPei.c to two filesChao Li2025-01-225-393/+406
| | | | | | | | | | | | | | | CpuMpPei.c contains two parts: EFI_PEI_MP_SERVICES_PPI instance and CpuMpPpi list installer. Move the EFI_PEI_MP_SERVICES_PPI instance in a new file called CpuMp.c, keep the specific logic and entry point in CpuMpPei.c, and rename the CpuMp2Pei.c to CpuMp2.c Cc: Ray Ni <ray.ni@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* UefiCpuPkg/PiSmmCpuDxeSmm: SmmWaitForApArrival first sync checkKhor Swee Aun2025-01-221-8/+5
| | | | | | | | | | | | | Restructured the SmmWaitForApArrival first CPU synchronization conditional checks and added new IsCpuSyncAlwaysNeeded check to determine whether the sync should be executed unconditionally when a SMI occurs. The first CPU synchronization shall executed unconditionally if the new IsCpuSyncAlwaysNeeded check return TRUE. Otherwise, first CPU synchronization is not executed unconditionally, and the decision to synchronize should be based on the system configuration and status. Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
* UefiCpuPkg: Add NULL TdxMeasurementLib instanceCeping Sun2025-01-133-0/+119
| | | | | | | | | | | Add NULL instance of TdxMeasurementLib. Cc: Ray Ni <ray.ni@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
* UefiCpuPkg: Add TdxMeasurementLib.hCeping Sun2025-01-132-0/+88
| | | | | | | | | | | | | | Add below APIs to UefiCpuPkg. - TdxMeasurementMapPcrToMrIndex - TdxMeasurementHashAndExtendToRtmr - TdxMeasurementBuildGuidHob Cc: Ray Ni <ray.ni@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
* UefiCpuPkg: Update return status to follow specCrystal Lee2025-01-131-1/+0
| | | | | | | | | | | | | | SplitPage may return OUT_OF_RESOURCES if no memory resource to split page entry. ConvertMemoryPageAttributes should also return OUT_OF_RESOURCES instead of override the status to UNSUPPORTED. Then EfiSetMemoryAttributes and EfiClearMemoryAttributes can return correct status of OUT_OF_RESOURCES when requested attributes cannot be applied due to lack of system resource. Cc: Felix Polyudov <felixp@ami.com> Cc: David Hsieh <davidhsieh@ami.com> Cc: James Wang <jameswang@ami.com> Signed-off-by: Crystal Lee <crystallee@ami.com>
* UefiCpuPkg: Produce EFI memory attributes protocolCrystal Lee2025-01-134-0/+313
| | | | | | | | | | Produce the protocol introduced in UEFI v2.10 that permits the caller to manage mapping permissions in the page tables. Cc: Felix Polyudov <felixp@ami.com> Cc: David Hsieh <davidhsieh@ami.com> Cc: James Wang <jameswang@ami.com> Signed-off-by: Crystal Lee <crystallee@ami.com>
* Add SmmCpuPlatformHookLib IsCpuSyncAlwaysNeeded interfaceKhor Swee Aun2025-01-102-0/+43
| | | | | | | | | | | | | | | | This patch adds the IsCpuSyncAlwaysNeeded interface to the SmmCpuPlatformHookLib. This interface will determine whether the first CPU Synchronization should be executed unconditionally when a SMI occurs. If the function returns true, it indicates that there is no need to check the system configuration and status, and the first CPU Synchronization should be executed unconditionally. If the function returns false, it indicates that the first CPU Synchronization is not executed unconditionally, and the decision to synchronize should be based on the system configuration and status. Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
* UefiCpuPkg: Add dump interrupt type on LoongArch64Chao Li2024-12-233-0/+61
| | | | | | | | | | | | | | If the exception type is INT, we need to know which interrupt could not be handled, so we added a method to dump them. Cc: Ray Ni <ray.ni@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* UefiCpuPkg: Adjust the exception handler logic on LoongArch64Chao Li2024-12-233-16/+8
| | | | | | | | | | | | | | | There is a problem with LoongArch64 exception handler, it returns a unhandled value when we get an exception type, the correct value should be right shifted 16 bits, so fix it. Cc: Ray Ni <ray.ni@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* UefiPkg/PiSmmCpuDxeSmm: Set SmmProfile Variable only for DXE SMMZhao,Yanxin2024-12-201-6/+9
| | | | | | | | | | | | Some platforms plan to move the Standalone MM CPU driver into the FSP. However, there is no variable service support in FSP. Therefore, the SetVariable logic for the Standalone MM CPU will be removed. With this change, users can dump the SmmProfile data from the Memory Allocation HOB: gMmProfileDataHobGuid. This change does not impact the DXE SMM, which will still retrieve the SmmProfile data from the variable service. Signed-off-by: Yanxin Zhao <yanxin.zhao@intel.com>
* UefiCpuPkg: x86 CpuDxe: Allocate AP Exception Stack Below 4GBOliver Smith-Denny2024-12-171-3/+25
| | | | | | | | | | | | | | | | | | | | | When setting up the APs' exception stacks, the x86 CpuDxe allocates any range and then copies over the existing GDT and IDT and adds the appropriate new entries for this AP, then installs them. This can cause an issue if the allocated buffer is over 4GB because the next time the AP is started, it goes through an INIT-SIPI-SIPI, stepping through real mode -> protected mode -> long mode and when it is in protected mode it needs a 32 code segment descriptor or else it will fault when trying to execute. If the GDT lives above 4GB, it cannot be accessed by the protected mode code and the triple fault is seen. This patch updates CpuDxe's MP management code to allocate the exception stacks for all APs below 4GB explicitly to avoid this problem, such as it does with the BSP's GDT that first gets populated to the APs. Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
* UefiCpuPkg: Remove macro MAX_LOONGARCH_EXCEPTIONChao Li2024-12-123-21/+0
| | | | | | | | | | | | | | | Since the UEFI 2.11 has been released, the macro MAX_LOONGARCH_EXCEPTION has been added in MdePkg, so it is deleted in LoongArch folder header file. Cc: Ray Ni <ray.ni@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* UefiCpuPkg/CpuMmuLib: Adjust default memory attributes on LoongArchChao Li2024-12-021-0/+1
| | | | | | | | When updating memory attributes, if only access attributes are changed, the default memory cache attribute is NULL and a CACHE_CC is added by default. Signed-off-by: Chao Li <lichao@loongson.cn>
* UefiCpuPkg/PiSmmCpuDxeSmm:Check resource HOB range before mappingDun Tan2024-11-251-0/+10
| | | | | | | | | | | | This commit is to check if the resource HOB range does not exceed the max supported physical address. The function BuildMemoryMapFromResDescHobs is to build Memory Region from resource HOBs. Then the memory maps will be used during creating or modifying SMM page table. If the resource HOB range exceeds the max supported physical address, then subsequent calling of PageTableMap() will fail. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: Fix unchecked returns and potential integer overflowskenlautner2024-11-1519-73/+423
| | | | | | | | | | | Resolves several issues in UefiCpuPkg related to: 1. Unchecked returns leading to potential NULL or uninitialized access. 2. Potential unchecked integer overflows. 3. Incorrect comparison between integers of different sizes. Co-authored-by: kenlautner <85201046+kenlautner@users.noreply.github.com> Signed-off-by: Chris Fernald <chfernal@microsoft.com>
* MdePkg: MdeLibs.dsc.inc: Apply StackCheckLibNull to All Module TypesOliver Smith-Denny2024-11-131-8/+2
| | | | | | | | | | | | | | | Now that the ResetVectors are USER_DEFINED modules, they will not be linked against StackCheckLibNull, which were the only modules causing issues. So, we can now remove the kludge we had before and the requirement for every DSC to include StackCheckLibNull for SEC modules and just apply StackCheckLibNull globally. This also changes every DSC to drop the SEC definition of StackCheckLibNull. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* UefiCpuPkg: Make the ResetVector USER_DEFINEDOliver Smith-Denny2024-11-132-2/+2
| | | | | | | | | | | | | | | | | | | | | | | The x86 reset vector is the initial FW code to run on an AP. It should not link to any libraries and is implemented entirely in assembly. This module is currently labled as SEC, because it runs during the SEC phase, but by having it SEC, it will be linked to all NULL libraries linked globally. This causes issue with StackCheckLib (though any NULL library being applied globally has the same issue) because BaseTools will attempt to link the library and add an extern to _ModuleEntryPoint, which does not exist for this module. Moving this module to USER_DEFINED instructs BaseTools to not link any NULL libraries to it, which is the desired behavior, and leads to a much cleaner global NULL library implementation, in this case for StackCheckLib. This change was tested on OVMF IA32/X64 and proved to work as before. Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* UefiCpuPkg: SmmProfile: Use public Architectural MSRs from MdePkgVivian Nowka-Keane2024-11-122-24/+35
| | | | | | Replaced local Msr defines with inclusion of Register/Amd/Msr.h. Signed-off-by: Vivian Nowka-Keane <vnowkakeane@linux.microsoft.com>
* UefiCpuPkg: Use public Architectural MSRs from MdePkgVivian Nowka-Keane2024-11-125-24/+31
| | | | | | | Replaced local Msr defines with inclusion of Register/Amd/Msr.h in Amd libraries. Signed-off-by: Vivian Nowka-Keane <vnowkakeane@linux.microsoft.com>
* UefiCpuPkg/MtrrLib: Fix unit test read overflowMichael D Kinney2024-11-111-1/+1
| | | | | | | Change conditional check to check the array index before reading the array member to prevent read past end of buffer. Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/SecCore: Consume PcdMaxMappingAddressBeforeTempRamExitJiaxin Wu2024-11-073-81/+126
| | | | | | | | | | | Consume PcdMaxMappingAddressBeforeTempRamExit for page table creation in permanent memory before Temp Ram Exit. This patch will create the full page table in two steps: Step 1: Create the max address in page table before the Temporary RAM exit. Step 2: Create the full range page table after the Temporary RAM exit. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/UefiCpuPkg.dec: Add PcdMaxMappingAddressBeforeTempRamExitJiaxin Wu2024-11-071-0/+8
| | | | | | | | | | | | | | | This change is made for boot performance considerations. Before the Temporary RAM is disabled, the permanent memory is in UC state, causing the creation of the page table in permanent memory to take more time with larger page table sizes. Therefore, this patch adds the PcdMaxMappingAddressBeforeTempRamExit to provide the platform with the capability to control the max mapping address in page table before Temp Ram Exit. The value of 0xFFFFFFFFFFFFFFFF, then firmware will map entire physical address space. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg: Remove AMD 32-bit SMRAM save state mapPhil Noh2024-11-013-157/+101
| | | | | | | | | | Per AMD64 Architecture Programmer's Manual Volume 2: System Programming - 10.2.3 SMRAM State-Save Area (Rev 24593), the AMD64 architecture does not use the legacy SMM state-save area format (Table 10-2) for 32-bit SMRAM save state map. Clean up codes for the invalid save state map. Signed-off-by: Phil Noh <Phil.Noh@amd.com>
* UefiCpuPkg/MmUnblockMemoryLib: Check if buffer range is validDun Tan2024-10-301-0/+90
| | | | | | | | | | | Check if input buffer range unblockable: 1.The input buffer range to block should be totally covered by one or multi memory allocation HOB 2.All the memory allocation HOB that overlap with the input buffer range should be EfiRuntimeServicesData, EfiACPIMemoryNVS or EfiReservedMemoryType. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix extraneous parenthesesMike Beaton2024-10-291-1/+1
| | | | | | | | | | | Without this change, when building OvmfPkg with -D SMM_REQUIRE using the XCODE5 toolchain we get: error: equality comparison with extraneous parentheses which stops the build. Signed-off-by: Mike Beaton <mjsbeaton@gmail.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Save and restore CR2 only if SmiProfile enableJiaxin Wu2024-10-161-2/+18
| | | | | | | | A page fault (#PF) that triggers an update to the page table only occurs if SmiProfile is enabled. Therefore, it is necessary to save and restore the CR2 register if SmiProfile is configured to be enabled. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Consume SmmCpuPlatformHookBeforeMmiHandler funcJiaxin Wu2024-10-121-8/+23
| | | | | | | | | | | | | This patch is for PiSmmCpuDxeSmm driver to add one round wait/release sync for BSP and AP to perform the SMM CPU Platform Hook before executing MMI Handler: SmmCpuPlatformHookBeforeMmiHandler (). With the function, SMM CPU driver can perform the platform specific items after one round BSP and AP sync (to make sure all APs in SMI) and before the MMI handlers. After the change, steps #1 and #2 are additional requirements if the MmCpuSyncModeTradition mode is selected. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg: Add SmmCpuPlatformHookBeforeMmiHandlerJiaxin Wu2024-10-122-2/+35
| | | | | | | | | | | | | This patch is to add SmmCpuPlatformHookBeforeMmiHandler interface in SmmCpuPlatformHookLib. The new API can be used to perform the platform specific items before executing MMI Handler. For example, Intel can leverage this API to clear the pending SMI bit after all CPUs finish the sync and before the MMI handlers. If so, the the redundant SMI can be avoided after CPU exit from current SMI. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clarification for BSP & APs Sync FlowJiaxin Wu2024-10-121-22/+22
| | | | | | | | | | | | | | | | | | | | This patch does not impact functionality. It aims to clarify the synchronization flow between the BSP and APs to enhance code readability and understanding: Steps #6 and #11 are the basic synchronization requirements for all cases. Steps #1 is additional requirements if the MmCpuSyncModeTradition mode is selected. Steps #1, #2, #3, #4, #5, #7, #8, #9, and #10 are additional requirements if the system needs to configure the MTRR. Steps #9 and #10 are additional requirements if the system needs to support the mSmmDebugAgentSupport. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/MpLib: Remove NotifyOnS3SmmInitDonePpiZhiguang Liu2024-10-102-65/+0
| | | | | | | | | | | | | Previously, the SMM S3 resume code required taking control of APs to perform SMM rebase, which would overwrite the context set by MpLib. As a result, MpLib needed to wake up APs using InitSipiSipi to restore the context after SMM S3 resume. With the recent change where SMM rebase occurs in the early PEI phase, the SMM S3 resume code no longer modifies AP context. Therefore, the forced use of InitSipiSipi after SMM S3 resume is no longer necessary. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/S3: Skip CR3 modification in S3Resume for 64-bit PEIZhiguang Liu2024-10-101-3/+5
| | | | | | | | | | | | | | | | Previously, when PEI was 32-bit and DXE was 64-bit, S3 resume code had to set or change the CR3 register before executing 64-bit code. However, with both PEI and DXE now may being 64-bit, this modification is unnecessary as PEI already utilizes sufficiently large page tables. Additionally, there is a bug in the current implementation where the changed CR3 during S3 resume could map only below 4G MMIO, which could lead to issues if end of PEI notify attempts to access above 4G. Overall, skipping the CR3 modification in S3Resume when PEI is 64-bit can fix the bug and also avoid unnecessary logic. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: RiscV64: initialize FPUHeinrich Schuchardt2024-10-048-0/+80
| | | | | | | | | | | | The OpenSSL library uses floating point registers. The is no guarantee that a prior firmware stage has enabled the FPU. Provide a library BaseRiscVFpuLib to * Enable the FPU and set it to state 'dirty'. * Clear the fcsr CSR. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* UefiCpuPkg/MtrrLib: MtrrLibIsMtrrSupported always return FALSE in TD-GuestMin M Xu2024-09-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | Currently, TDX exposes MTRR CPUID bit to TDX VM. So based on the CPUID, the guest software components (OVMF/TDVF and guest kernel) will access MTRR MSRs. One problem for guest to use of MTRR is the change of MTRR setting needs to set CR0.CD=1, which will case #VE for TDX. For Linux kernel, there is a mechanism called SW defined MTRR introduced by the patch https://lore.kernel.org/all/20230502120931. 20719-4-jgross@suse.com/. If this is integrated for TDX guest, then Linux kernel will not access any MTRR MSRs. So we update MtrrLibIsMtrrSupported() to always return false for TD-Guest, then TDVF will not access MTRR MSRs at all. Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Binbin Wu <binbin.wu@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* UefiCpuPkg/AmdSmmCpuFeaturesLib: Skip SMBASE configurationPhil Noh2024-09-172-5/+28
| | | | | | | | | This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Signed-off-by: Phil Noh <Phil.Noh@amd.com>
* UefiCpuPkg: Add StackCheckLibOliver Smith-Denny2024-09-131-2/+8
| | | | | | | SecCore and SecCoreNative require StackCheckLib and so the NULL instance is linked against them here. Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove RestrictedMemoryAccess check for MM CPUJiaxin Wu2024-09-066-31/+46
| | | | | | | | | | | | | | The PcdCpuSmmRestrictedMemoryAccess is declared as either a dynamic or fixed PCD. It is not recommended for use in the MM CPU driver. Furthermore, IsRestrictedMemoryAccess() is only needed for SMM. Therefor, there is no need for MM to consume the PcdCpuSmmRestrictedMemoryAccess. So, this patch is to add the SMM specific file for its own functions, with the change, the dependency of the MM CPU driver on PcdCpuSmmRestrictedMemoryAccess can be removed. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clean mCpuSmmRestrictedMemoryAccessJiaxin Wu2024-09-061-7/+4
| | | | | | | | | | Currently, mCpuSmmRestrictedMemoryAccess is only used by the IsRestrictedMemoryAccess(). And IsRestrictedMemoryAccess() can consume the PcdCpuSmmRestrictedMemoryAccess directly. Therefore, mCpuSmmRestrictedMemoryAccess can be cleaned to simply the code logic. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Update IfReadOnlyPageTableNeededJiaxin Wu2024-09-061-18/+1
| | | | | | | | | | After the 9f29fbd3, full mapping SMM page table is always created regardless the value of the PcdCpuSmmRestrictedMemoryAccess. If so, SMM PageTable Attributes can be set to ready-only since there is no need to update it. So, this patch is to remove restricted memory access check when setting the SMM PageTable attributes. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Correct SetPageTableAttributes func usageJiaxin Wu2024-09-062-12/+8
| | | | | | | | | | | SetPageTableAttributes() will use the IfReadOnlyPageTableNeeded() to determine whether it is necessary to set the page table itself to read-only. And IfReadOnlyPageTableNeeded() has already token into account the status of IsRestrictedMemoryAccess(). Therefore, there is no need for an additional call to IsRestrictedMemoryAccess() before calling the SetPageTableAttributes(). Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Deadloop if PFAddr is not supported by systemJiaxin Wu2024-09-061-1/+1
| | | | | | | Deadloop if PFAddr is not supported by system, no need check SMM CPU RestrictedMemory access enable or not. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Always save and restore CR2Jiaxin Wu2024-09-061-14/+4
| | | | | | | | | | | | | | | | | Following the commit 9f29fbd3, full mapping SMM page table is always created regardless the value of the PcdCpuSmmRestrictedMemoryAccess. Consequently, a page fault (#PF) that triggers an update to the page table occurs only when SmiProfile is enabled. Therefore, it is necessary to save and restore the CR2 register when SmiProfile is configured to be enabled. And the operation of saving and restoring CR2 is considered to be not heavy operation compared to the saving and restoring of CR3. As a result, the condition check for SmiProfile has been removed, and CR2 is now saved and restored unconditionally, without the need for additional condition checks. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix IsSmmCommBufferForbiddenAddress checkJiaxin Wu2024-09-062-1/+5
| | | | | | | | | | | | | | | | SmiPFHandler depends on the IsSmmCommBufferForbiddenAddress() to do the forbidden address check: For SMM, verifying whether an address is forbidden is necessary only when RestrictedMemoryAccess is enabled. For MM, all accessible address is recorded in the ResourceDescriptor HOB, so no need check the RestrictedMemoryAccess is enabled or not. This patch is to move RestrictedMemoryAccess check into SMM IsSmmCommBufferForbiddenAddress to align with above behavior. With the change, SmiPFHandler doesn't need to check the RestrictedMemoryAccess enable or not. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Avoid to access MCA_CAP if CPU does not supportJiaxin Wu2024-09-061-5/+3
| | | | | | Do not access MCA_CAP MSR unless the CPU supports the SmmRegFeatureControl Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/UefiCpuPkg.ci.yaml: Add PrEval CI configJoey Vagedes2024-09-021-0/+3
| | | | | | | | | | | Adds an entry to the package's CI configuration file that enable policy 5 for stuart_pr_eval. With this Policy, all INFs used by the package are extracted from the provided DSC file and compared against the list of changed *.inf (INF) files in the PR. If there is a match, stuart_pr_eval will specify that this package is affected by the PR and needs to be tested. Signed-off-by: Joey Vagedes <joey.vagedes@gmail.com>
* UefiCpuPkg: Using the new name of LoongArch CSR 0x20 registerChao Li2024-08-302-2/+2
| | | | | | | | | | | Since the LoongArch SPEC has adjusted the CSR 0x20 register name and the MdePkg also added the new name, so enable it in UefiCpuPkg. Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* UefiCpuPkg/MpInitLib: Skip X2APIC enabling when BSP in X2APIC alreadyRay Ni2024-08-281-1/+3
| | | | | | | | | | | The BSP's APIC mode is synced to all APs in CollectProcessorCount(). So, it's safe to skip the X2 APIC enabling in AutoEnableX2Apic() which runs later when BSP's APIC mode is X2 APIC already. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Sync BSP's APIC mode to APs in InitConfig pathRay Ni2024-08-282-5/+28
| | | | | | | | | | | | The change saves the BSP's initial APIC mode and syncs to all APs in first time wakeup. It allows certain platforms to switch to X2 APIC as early as possible and also independent on CpuFeaturePei/Dxe. The platform should switch BSP to X2 APIC mode first before the CpuMpPeim runs. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
generated by cgit (git 2.34.1) at 2025-02-23 12:46:51 +0000