From 1b70dcd375765d293f57fe546710b98525e6a46d Mon Sep 17 00:00:00 2001
From: Sienski Piotr <piotr.sienski@intel.com>
Date: Mon, 14 Oct 2024 12:24:14 +0200
Subject: MdePkg/Include/Guid: Add missing CXL definitions to Cper.h

[Issue Description]
In MdePkg/Include/Guid/Cper.h there are missing multiple definitions
regarding CXL that can be found in UEFI 2.10 spec
chapters N.2.13 and N.2.14

[Resolution]
Add these definitions to MdePkg/Include/Guid/Cper.h

Signed-off-by: Sienski Piotr <piotr.sienski@intel.com>
---
 MdePkg/Include/Guid/Cper.h | 98 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 98 insertions(+)

diff --git a/MdePkg/Include/Guid/Cper.h b/MdePkg/Include/Guid/Cper.h
index deb96d4af9..15a4a3f603 100644
--- a/MdePkg/Include/Guid/Cper.h
+++ b/MdePkg/Include/Guid/Cper.h
@@ -1208,6 +1208,104 @@ typedef struct {
   UINT64    PteL1;
 } EFI_IOMMU_DMAR_ERROR_DATA;
 
+///
+/// CXL Cachemem Event Log Valid bits
+///@{
+#define CXL_CACHMEM_AGENT_TYPE      BIT0  // CXL Agent Type field is valid
+#define CXL_CACHMEM_AGENT_ADDRESS   BIT1  // CXL Agent Address field is valid
+#define CXL_CACHMEM_DEVICE_ID       BIT2  // Device ID field is valid
+#define CXL_CACHMEM_DEVICE_SER_NUM  BIT3  // Device Serial Number field is valid
+#define CXL_CACHMEM_CAP_STRUCT      BIT4  // Capability structure field is valid
+#define CXL_CACHMEM_DVSEC           BIT5  // CXL DVSET field is valid
+#define CXL_CACHMEM_ERROR_LOG       BIT6  // CXL Error Log field is valid
+///@}
+
+//
+// CXL Agent Types
+///@{
+#define CXL_AGENT_CXL11_DEV          0    // CXL 1.1 Device
+#define CXL_AGENT_CXL11_DSP          1    // CXL 1.1 Downstream Port
+#define CXL_AGENT_CXL20_DEV          2    // CXL 2.0 Device
+#define CXL_AGENT_CXL20_LOGICAL_DEV  3    // CXL 2.0 Logical Device
+#define CXL_AGENT_CXL20_FMLD         4    // CXL 2.0 Fabric Manager managed Logical device
+#define CXL_AGENT_CXL20_RP           5    // CXL 2.0 Root Port
+#define CXL_AGENT_CXL20_DSP          6    // CXL 2.0 Downstream Switch Port
+#define CXL_AGENT_CXL20_USP          7    // CXL 2.0 Upstream Switch Port
+///@}
+
+//
+// CXL Mem Event Log Valid bits
+///@{
+#define CXL_MEM_DEVICE_ID       BIT0  // Device ID field is valid
+#define CXL_MEM_DEVICE_SER_NUM  BIT1  // Device Serial Number field is valid
+#define CXL_MEM_COMP_ERROR_LOG  BIT2  // CXL Component Error Log field is valid
+///@}
+
+//
+// CXL Agent Address
+//
+typedef union {
+  struct {
+    UINT64    Function : 8;
+    UINT64    Device   : 8;
+    UINT64    Bus      : 8;
+    UINT64    Segment  : 16;
+    UINT64    Rsvd     : 24;
+  } Bits;
+  struct {
+    UINT32    Low;
+    UINT32    High;
+  } RcrbBase;
+} CXL_AGENT_ADDRESS;
+
+//
+// CXL Device ID
+//
+typedef struct _CXL_AGENT_DEVICE_ID {
+  UINT16    VendorId;
+  UINT16    DeviceId;
+  UINT16    Svid;
+  UINT16    Sid;
+  UINT16    ClassCode;
+  struct {
+    UINT16    Rsvd : 3;
+    UINT16    Num  : 13;
+  } Slot;
+  UINT32    Rsvd;
+} CXL_AGENT_DEVICE_ID;
+
+//
+// CXL Device Serial Number
+//
+typedef struct _CXL_DEVICE_SERIAL_NUM {
+  UINT32    Lower;
+  UINT32    Upper;
+} CXL_DEVICE_SERIAL_NUM;
+
+//
+// PCIe device identifiers of CXL Component
+//
+typedef struct {
+  UINT16                        VendorId;
+  UINT16                        DeviceId;
+  UINT8                         Function;
+  UINT8                         Device;
+  UINT8                         Bus;
+  UINT16                        Segment;
+  EFI_GENERIC_ERROR_PCI_SLOT    Slot;
+  UINT8                         Resvd;
+} CXL_ERROR_PCIE_DEV_ID;
+
+//
+// CXL Component Events Section
+//
+typedef struct _CXL_COMPONENT_EVENT_LOG {
+  UINT32                   Length;
+  UINT64                   ValidFields;
+  CXL_ERROR_PCIE_DEV_ID    CxlDeviceId;
+  UINT64                   DeviceSerialNo;
+} CXL_COMPONENT_EVENT_LOG;
+
 #pragma pack()
 
 extern EFI_GUID  gEfiEventNotificationTypeCmcGuid;
-- 
cgit