From b294633c68d4f4ed8c784501e8da321127121877 Mon Sep 17 00:00:00 2001 From: Yu Pu Date: Tue, 29 Mar 2022 11:28:32 +0800 Subject: MdePkg: Move API and implementation from UefiCpuLib to CpuLib There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib. This patch merges UefiCpuPkg/UefiCpuLib to MdePkg/CpuLib. Change-Id: Ic26f4c2614ed6bd9840f817d50e47ac1de4bd013 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Yu Pu Reviewed-by: Liming Gao Signed-off-by: Zhiguang Liu --- MdePkg/Include/Library/CpuLib.h | 48 +++++++++++++ MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 ++ MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm | 68 ++++++++++++++++++ MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm | 51 ++++++++++++++ MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c | 81 ++++++++++++++++++++++ UefiCpuPkg/Include/Library/UefiCpuLib.h | 49 ------------- UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 81 ---------------------- .../Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 8 +-- .../Library/BaseUefiCpuLib/BaseUefiCpuLibNull.c | 18 +++++ .../Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm | 68 ------------------ .../Library/BaseUefiCpuLib/X64/InitializeFpu.nasm | 51 -------------- 11 files changed, 273 insertions(+), 256 deletions(-) create mode 100644 MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm create mode 100644 MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm create mode 100644 MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c delete mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLibNull.c delete mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm delete mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm diff --git a/MdePkg/Include/Library/CpuLib.h b/MdePkg/Include/Library/CpuLib.h index 25f6d9478c..3f29937dc7 100644 --- a/MdePkg/Include/Library/CpuLib.h +++ b/MdePkg/Include/Library/CpuLib.h @@ -41,4 +41,52 @@ CpuFlushTlb ( VOID ); +#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) + +/** + Initializes floating point units for requirement of UEFI specification. + This function initializes floating-point control word to 0x027F (all exceptions + masked,double-precision, round-to-nearest) and multimedia-extensions control word + (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero + for masked underflow). +**/ +VOID +EFIAPI +InitializeFloatingPointUnits ( + VOID + ); + +/** + Determine if the standard CPU signature is "AuthenticAMD". + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ); + +/** + Return the 32bit CPU family and model value. + @return CPUID[01h].EAX with Processor Type and Stepping ID cleared. +**/ +UINT32 +EFIAPI +GetCpuFamilyModel ( + VOID + ); + +/** + Return the CPU stepping ID. + @return CPU stepping ID value in CPUID[01h].EAX. +**/ +UINT8 +EFIAPI +GetCpuSteppingId ( + VOID + ); + +#endif + #endif diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf index 5b18343c59..9a162afe6d 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -29,16 +29,22 @@ # VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64 # +[Sources.IA32, Sources.X64] + X86BaseCpuLib.c + [Sources.IA32] Ia32/CpuSleep.c | MSFT Ia32/CpuSleep.nasm| INTEL Ia32/CpuSleepGcc.c | GCC X86CpuFlushTlb.c + Ia32/InitializeFpu.nasm + [Sources.X64] X86CpuFlushTlb.c X64/CpuSleep.nasm + X64/InitializeFpu.nasm [Sources.EBC] Ebc/CpuSleepFlushTlb.c diff --git a/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm b/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm new file mode 100644 index 0000000000..5e27cc3250 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/Ia32/InitializeFpu.nasm @@ -0,0 +1,68 @@ +;------------------------------------------------------------------------------ +;* +;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;------------------------------------------------------------------------------ + + SECTION .rodata + +; +; Float control word initial value: +; all exceptions masked, double-precision, round-to-nearest +; +mFpuControlWord: DW 0x27F +; +; Multimedia-extensions control word: +; all exceptions masked, round-to-nearest, flush to zero for masked underflow +; +mMmxControlWord: DD 0x1F80 + + SECTION .text + +; +; Initializes floating point units for requirement of UEFI specification. +; +; This function initializes floating-point control word to 0x027F (all exceptions +; masked,double-precision, round-to-nearest) and multimedia-extensions control word +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero +; for masked underflow). +; +global ASM_PFX(InitializeFloatingPointUnits) +ASM_PFX(InitializeFloatingPointUnits): + + push ebx + + ; + ; Initialize floating point units + ; + finit + fldcw [mFpuControlWord] + + ; + ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test + ; whether the processor supports SSE instruction. + ; + mov eax, 1 + cpuid + bt edx, 25 + jnc Done + + ; + ; Set OSFXSR bit 9 in CR4 + ; + mov eax, cr4 + or eax, BIT9 + mov cr4, eax + + ; + ; The processor should support SSE instruction and we can use + ; ldmxcsr instruction + ; + ldmxcsr [mMmxControlWord] +Done: + pop ebx + + ret + diff --git a/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm b/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm new file mode 100644 index 0000000000..8485b47135 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/X64/InitializeFpu.nasm @@ -0,0 +1,51 @@ +;------------------------------------------------------------------------------ +;* +;* Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;------------------------------------------------------------------------------ + + SECTION .rodata +; +; Float control word initial value: +; all exceptions masked, double-extended-precision, round-to-nearest +; +mFpuControlWord: DW 0x37F +; +; Multimedia-extensions control word: +; all exceptions masked, round-to-nearest, flush to zero for masked underflow +; +mMmxControlWord: DD 0x1F80 + +DEFAULT REL +SECTION .text + +; +; Initializes floating point units for requirement of UEFI specification. +; +; This function initializes floating-point control word to 0x027F (all exceptions +; masked,double-precision, round-to-nearest) and multimedia-extensions control word +; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero +; for masked underflow). +; +global ASM_PFX(InitializeFloatingPointUnits) +ASM_PFX(InitializeFloatingPointUnits): + + ; + ; Initialize floating point units + ; + finit + fldcw [mFpuControlWord] + + ; + ; Set OSFXSR bit 9 in CR4 + ; + mov rax, cr4 + or rax, BIT9 + mov cr4, rax + + ldmxcsr [mMmxControlWord] + + ret + diff --git a/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c b/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c new file mode 100644 index 0000000000..1cad32a4be --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/X86BaseCpuLib.c @@ -0,0 +1,81 @@ +/** @file + This library defines some routines that are generic for IA32 family CPU. + + The library routines are UEFI specification compliant. + + Copyright (c) 2020, AMD Inc. All rights reserved.
+ Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +#include +#include + +/** + Determine if the standard CPU signature is "AuthenticAMD". + + @retval TRUE The CPU signature matches. + @retval FALSE The CPU signature does not match. + +**/ +BOOLEAN +EFIAPI +StandardSignatureIsAuthenticAMD ( + VOID + ) +{ + UINT32 RegEbx; + UINT32 RegEcx; + UINT32 RegEdx; + + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); +} + +/** + Return the 32bit CPU family and model value. + + @return CPUID[01h].EAX with Processor Type and Stepping ID cleared. +**/ +UINT32 +EFIAPI +GetCpuFamilyModel ( + VOID + ) +{ + CPUID_VERSION_INFO_EAX Eax; + + AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); + + // + // Mask other fields than Family and Model. + // + Eax.Bits.SteppingId = 0; + Eax.Bits.ProcessorType = 0; + Eax.Bits.Reserved1 = 0; + Eax.Bits.Reserved2 = 0; + return Eax.Uint32; +} + +/** + Return the CPU stepping ID. + @return CPU stepping ID value in CPUID[01h].EAX. +**/ +UINT8 +EFIAPI +GetCpuSteppingId ( + VOID + ) +{ + CPUID_VERSION_INFO_EAX Eax; + + AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); + + return (UINT8)Eax.Bits.SteppingId; +} diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/Library/UefiCpuLib.h index 0ff4a35774..ab6982db6e 100644 --- a/UefiCpuPkg/Include/Library/UefiCpuLib.h +++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h @@ -13,53 +13,4 @@ #ifndef __UEFI_CPU_LIB_H__ #define __UEFI_CPU_LIB_H__ -/** - Initializes floating point units for requirement of UEFI specification. - - This function initializes floating-point control word to 0x027F (all exceptions - masked,double-precision, round-to-nearest) and multimedia-extensions control word - (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero - for masked underflow). - -**/ -VOID -EFIAPI -InitializeFloatingPointUnits ( - VOID - ); - -/** - Determine if the standard CPU signature is "AuthenticAMD". - - @retval TRUE The CPU signature matches. - @retval FALSE The CPU signature does not match. - -**/ -BOOLEAN -EFIAPI -StandardSignatureIsAuthenticAMD ( - VOID - ); - -/** - Return the 32bit CPU family and model value. - - @return CPUID[01h].EAX with Processor Type and Stepping ID cleared. -**/ -UINT32 -EFIAPI -GetCpuFamilyModel ( - VOID - ); - -/** - Return the CPU stepping ID. - @return CPU stepping ID value in CPUID[01h].EAX. -**/ -UINT8 -EFIAPI -GetCpuSteppingId ( - VOID - ); - #endif diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c deleted file mode 100644 index 5d925bc273..0000000000 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c +++ /dev/null @@ -1,81 +0,0 @@ -/** @file - This library defines some routines that are generic for IA32 family CPU. - - The library routines are UEFI specification compliant. - - Copyright (c) 2020, AMD Inc. All rights reserved.
- Copyright (c) 2021, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include - -#include -#include - -/** - Determine if the standard CPU signature is "AuthenticAMD". - - @retval TRUE The CPU signature matches. - @retval FALSE The CPU signature does not match. - -**/ -BOOLEAN -EFIAPI -StandardSignatureIsAuthenticAMD ( - VOID - ) -{ - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - - AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); - return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && - RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && - RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); -} - -/** - Return the 32bit CPU family and model value. - - @return CPUID[01h].EAX with Processor Type and Stepping ID cleared. -**/ -UINT32 -EFIAPI -GetCpuFamilyModel ( - VOID - ) -{ - CPUID_VERSION_INFO_EAX Eax; - - AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); - - // - // Mask other fields than Family and Model. - // - Eax.Bits.SteppingId = 0; - Eax.Bits.ProcessorType = 0; - Eax.Bits.Reserved1 = 0; - Eax.Bits.Reserved2 = 0; - return Eax.Uint32; -} - -/** - Return the CPU stepping ID. - @return CPU stepping ID value in CPUID[01h].EAX. -**/ -UINT8 -EFIAPI -GetCpuSteppingId ( - VOID - ) -{ - CPUID_VERSION_INFO_EAX Eax; - - AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); - - return (UINT8)Eax.Bits.SteppingId; -} diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf index 34d3a7bb43..9f8b62d87a 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf @@ -24,14 +24,8 @@ # VALID_ARCHITECTURES = IA32 X64 # -[Sources.IA32] - Ia32/InitializeFpu.nasm - -[Sources.X64] - X64/InitializeFpu.nasm - [Sources] - BaseUefiCpuLib.c + BaseUefiCpuLibNull.c [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLibNull.c b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLibNull.c new file mode 100644 index 0000000000..e29d2e892c --- /dev/null +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLibNull.c @@ -0,0 +1,18 @@ +/** @file +This library contains a dummy function to pass build. + +Copyright (c) 2022, Intel Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include + +/** + Dummy function. +**/ +VOID +Dummy ( + VOID + ) +{ +} diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm deleted file mode 100644 index 5e27cc3250..0000000000 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm +++ /dev/null @@ -1,68 +0,0 @@ -;------------------------------------------------------------------------------ -;* -;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
-;* SPDX-License-Identifier: BSD-2-Clause-Patent -;* -;* -;------------------------------------------------------------------------------ - - SECTION .rodata - -; -; Float control word initial value: -; all exceptions masked, double-precision, round-to-nearest -; -mFpuControlWord: DW 0x27F -; -; Multimedia-extensions control word: -; all exceptions masked, round-to-nearest, flush to zero for masked underflow -; -mMmxControlWord: DD 0x1F80 - - SECTION .text - -; -; Initializes floating point units for requirement of UEFI specification. -; -; This function initializes floating-point control word to 0x027F (all exceptions -; masked,double-precision, round-to-nearest) and multimedia-extensions control word -; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero -; for masked underflow). -; -global ASM_PFX(InitializeFloatingPointUnits) -ASM_PFX(InitializeFloatingPointUnits): - - push ebx - - ; - ; Initialize floating point units - ; - finit - fldcw [mFpuControlWord] - - ; - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test - ; whether the processor supports SSE instruction. - ; - mov eax, 1 - cpuid - bt edx, 25 - jnc Done - - ; - ; Set OSFXSR bit 9 in CR4 - ; - mov eax, cr4 - or eax, BIT9 - mov cr4, eax - - ; - ; The processor should support SSE instruction and we can use - ; ldmxcsr instruction - ; - ldmxcsr [mMmxControlWord] -Done: - pop ebx - - ret - diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm b/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm deleted file mode 100644 index 8485b47135..0000000000 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm +++ /dev/null @@ -1,51 +0,0 @@ -;------------------------------------------------------------------------------ -;* -;* Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
-;* SPDX-License-Identifier: BSD-2-Clause-Patent -;* -;* -;------------------------------------------------------------------------------ - - SECTION .rodata -; -; Float control word initial value: -; all exceptions masked, double-extended-precision, round-to-nearest -; -mFpuControlWord: DW 0x37F -; -; Multimedia-extensions control word: -; all exceptions masked, round-to-nearest, flush to zero for masked underflow -; -mMmxControlWord: DD 0x1F80 - -DEFAULT REL -SECTION .text - -; -; Initializes floating point units for requirement of UEFI specification. -; -; This function initializes floating-point control word to 0x027F (all exceptions -; masked,double-precision, round-to-nearest) and multimedia-extensions control word -; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero -; for masked underflow). -; -global ASM_PFX(InitializeFloatingPointUnits) -ASM_PFX(InitializeFloatingPointUnits): - - ; - ; Initialize floating point units - ; - finit - fldcw [mFpuControlWord] - - ; - ; Set OSFXSR bit 9 in CR4 - ; - mov rax, cr4 - or rax, BIT9 - mov cr4, rax - - ldmxcsr [mMmxControlWord] - - ret - -- cgit