From c1eb477e0629e3a444cab43c66a02fb8daf12ce9 Mon Sep 17 00:00:00 2001 From: Ceping Sun Date: Thu, 12 Dec 2024 20:09:48 -0500 Subject: OvmfPkg/TdxDxe: Clear GPR Mask for RBX Refer to intel-tdx-module-api spec section 5.5.21, GPR mask (TDVMCALL_EXPOSE_REGS_MASK) is a bitmap that controls which part of the guest TD GPR and XMM state is passed as-is to the VMM and back. - A bit value of 0 indicates that the corresponding register is saved by the Intel TDX module and not passed as-is to Host VMM. - A bit value of 1 indicates that the corresponding register is passed as-is to the host VMM. Currently, RBX is used as the mailbox address in ApRunLoop.nasm, the corresponding bit value of RBX in MASK(Bit 3) is set as 1 which means the value is passed to Host VMM as-is and it can be changed by Host VMM. So the bitmask shall be set as 0 to avoid this situation. Reference: [TDX-API]: intel-tdx-module-abi-spec https://cdrdv2.intel.com/v1/dl/getContent/733579 Cc: Erdem Aktas Cc: Jiewen Yao Cc: Min Xu Cc: Gerd Hoffmann Cc: Hunter Adrian Signed-off-by: Ceping Sun --- OvmfPkg/TdxDxe/X64/ApRunLoop.nasm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm b/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm index 57560015f4..538ae71831 100644 --- a/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm +++ b/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm @@ -20,7 +20,7 @@ SECTION .text BITS 64 -%define TDVMCALL_EXPOSE_REGS_MASK 0xffcc +%define TDVMCALL_EXPOSE_REGS_MASK 0xffc4 %define TDVMCALL 0x0 %define EXIT_REASON_CPUID 0xa -- cgit