From ea55bd8f66eeca5f4e80c3679bcf1b1007286b8a Mon Sep 17 00:00:00 2001
From: Tuan Phan <tphan@ventanamicro.com>
Date: Wed, 7 Jun 2023 10:30:21 -0700
Subject: UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit

The timer compare register is 64-bit so simplifying the delay
function.

Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
 MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'MdePkg')

diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
index ee5c2ba603..6997de6cc0 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -20,6 +20,5 @@
   Name:
 
 #define ASM_FUNC(Name)  _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
-#define RISCV_TIMER_COMPARE_BITS  32
 
 #endif
-- 
cgit