diff options
| author | Michael Brown <mcb30@ipxe.org> | 2013-04-30 13:36:04 +0100 |
|---|---|---|
| committer | Michael Brown <mcb30@ipxe.org> | 2013-04-30 13:42:12 +0100 |
| commit | 592755eccf51c87ca727c2044eee7ffc3266e290 (patch) | |
| tree | e3be3ae927c223dc0d734ee0c4bb7c2217cc9db2 /src/drivers/net/realtek.c | |
| parent | e411b37eb1f1fdeca6e80db3ab2f74fd6373887d (diff) | |
| download | ipxe-592755eccf51c87ca727c2044eee7ffc3266e290.tar.gz | |
[realtek] Allow reaction time between writing RTL_CAPR and reading RTL_CR
Some older RTL8139 chips seem to not immediately update the
RTL_CR.BUFE bit in response to a write to RTL_CAPR. This results in
iPXE seeing a spurious zero-length received packet, and thereafter
being out of sync with the hardware's RX ring offset.
Fix by inserting an extra PCI read cycle after writing to RTL_CAPR, to
give the chip time to react before we next read RTL_CR.
Reported-by: Gelip <mrgelip@gmail.com>
Tested-by: Gelip <mrgelip@gmail.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/drivers/net/realtek.c')
| -rw-r--r-- | src/drivers/net/realtek.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/drivers/net/realtek.c b/src/drivers/net/realtek.c index d7c4d29d4..70c0ac1c6 100644 --- a/src/drivers/net/realtek.c +++ b/src/drivers/net/realtek.c @@ -861,6 +861,9 @@ static void realtek_legacy_poll_rx ( struct net_device *netdev ) { rtl->rx_offset = ( ( rtl->rx_offset + 3 ) & ~3 ); rtl->rx_offset = ( rtl->rx_offset % RTL_RXBUF_LEN ); writew ( ( rtl->rx_offset - 16 ), rtl->regs + RTL_CAPR ); + + /* Give chip time to react before rechecking RTL_CR */ + readw ( rtl->regs + RTL_CAPR ); } } |