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authorLadi Prosek <lprosek@redhat.com>2016-04-11 11:26:58 +0200
committerMichael Brown <mcb30@ipxe.org>2016-04-15 17:41:26 +0100
commit8a055a2a707f8cb92e7b62512391e03b4e25cae2 (patch)
tree368a64a84a3fdd8a3519d650f638df0bc6e4543e /src/include/ipxe/virtio-pci.h
parent7b499f849edc79f30b27dfe8143c04e90e3154c9 (diff)
downloadipxe-8a055a2a707f8cb92e7b62512391e03b4e25cae2.tar.gz
[virtio] Add virtio 1.0 PCI support
This commit adds support for driving virtio 1.0 PCI devices. In addition to various helpers, a number of vpm_ functions are introduced to be used instead of their legacy vp_ counterparts when accessing virtio 1.0 (aka modern) devices. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Modified-by: Michael Brown <mcb30@ipxe.org> Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/include/ipxe/virtio-pci.h')
-rw-r--r--src/include/ipxe/virtio-pci.h147
1 files changed, 147 insertions, 0 deletions
diff --git a/src/include/ipxe/virtio-pci.h b/src/include/ipxe/virtio-pci.h
index 8076f20c8..c7452c82f 100644
--- a/src/include/ipxe/virtio-pci.h
+++ b/src/include/ipxe/virtio-pci.h
@@ -97,6 +97,44 @@ struct virtio_pci_common_cfg {
__le32 queue_used_hi; /* read-write */
};
+/* Virtio 1.0 PCI region descriptor. We support memory mapped I/O, port I/O,
+ * and PCI config space access via the cfg PCI capability as a fallback. */
+struct virtio_pci_region {
+ void *base;
+ size_t length;
+ u8 bar;
+
+/* How to interpret the base field */
+#define VIRTIO_PCI_REGION_TYPE_MASK 0x00000003
+/* The base field is a memory address */
+#define VIRTIO_PCI_REGION_MEMORY 0x00000000
+/* The base field is a port address */
+#define VIRTIO_PCI_REGION_PORT 0x00000001
+/* The base field is an offset within the PCI bar */
+#define VIRTIO_PCI_REGION_PCI_CONFIG 0x00000002
+ unsigned flags;
+};
+
+/* Virtio 1.0 device state */
+struct virtio_pci_modern_device {
+ struct pci_device *pci;
+
+ /* VIRTIO_PCI_CAP_PCI_CFG position */
+ int cfg_cap_pos;
+
+ /* VIRTIO_PCI_CAP_COMMON_CFG data */
+ struct virtio_pci_region common;
+
+ /* VIRTIO_PCI_CAP_DEVICE_CFG data */
+ struct virtio_pci_region device;
+
+ /* VIRTIO_PCI_CAP_ISR_CFG data */
+ struct virtio_pci_region isr;
+
+ /* VIRTIO_PCI_CAP_NOTIFY_CFG data */
+ int notify_cap_pos;
+};
+
static inline u32 vp_get_features(unsigned int ioaddr)
{
return inl(ioaddr + VIRTIO_PCI_HOST_FEATURES);
@@ -156,6 +194,115 @@ static inline void vp_del_vq(unsigned int ioaddr, int queue_index)
outl(0, ioaddr + VIRTIO_PCI_QUEUE_PFN);
}
+struct vring_virtqueue;
+
int vp_find_vq(unsigned int ioaddr, int queue_index,
struct vring_virtqueue *vq);
+
+/* Virtio 1.0 I/O routines abstract away the three possible HW access
+ * mechanisms - memory, port I/O, and PCI cfg space access. Also built-in
+ * are endianness conversions - to LE on write and from LE on read. */
+
+void vpm_iowrite8(struct virtio_pci_modern_device *vdev,
+ struct virtio_pci_region *region, u8 data, size_t offset);
+
+void vpm_iowrite16(struct virtio_pci_modern_device *vdev,
+ struct virtio_pci_region *region, u16 data, size_t offset);
+
+void vpm_iowrite32(struct virtio_pci_modern_device *vdev,
+ struct virtio_pci_region *region, u32 data, size_t offset);
+
+static inline void vpm_iowrite64(struct virtio_pci_modern_device *vdev,
+ struct virtio_pci_region *region,
+ u64 data, size_t offset_lo, size_t offset_hi)
+{
+ vpm_iowrite32(vdev, region, (u32)data, offset_lo);
+ vpm_iowrite32(vdev, region, data >> 32, offset_hi);
+}
+
+u8 vpm_ioread8(struct virtio_pci_modern_device *vdev,
+ struct virtio_pci_region *region, size_t offset);
+
+u16 vpm_ioread16(struct virtio_pci_modern_device *vdev,
+ struct virtio_pci_region *region, size_t offset);
+
+u32 vpm_ioread32(struct virtio_pci_modern_device *vdev,
+ struct virtio_pci_region *region, size_t offset);
+
+/* Virtio 1.0 device manipulation routines */
+
+#define COMMON_OFFSET(field) offsetof(struct virtio_pci_common_cfg, field)
+
+static inline void vpm_reset(struct virtio_pci_modern_device *vdev)
+{
+ vpm_iowrite8(vdev, &vdev->common, 0, COMMON_OFFSET(device_status));
+ while (vpm_ioread8(vdev, &vdev->common, COMMON_OFFSET(device_status)))
+ mdelay(1);
+}
+
+static inline u8 vpm_get_status(struct virtio_pci_modern_device *vdev)
+{
+ return vpm_ioread8(vdev, &vdev->common, COMMON_OFFSET(device_status));
+}
+
+static inline void vpm_add_status(struct virtio_pci_modern_device *vdev,
+ u8 status)
+{
+ u8 curr_status = vpm_ioread8(vdev, &vdev->common, COMMON_OFFSET(device_status));
+ vpm_iowrite8(vdev, &vdev->common,
+ curr_status | status, COMMON_OFFSET(device_status));
+}
+
+static inline u64 vpm_get_features(struct virtio_pci_modern_device *vdev)
+{
+ u32 features_lo, features_hi;
+
+ vpm_iowrite32(vdev, &vdev->common, 0, COMMON_OFFSET(device_feature_select));
+ features_lo = vpm_ioread32(vdev, &vdev->common, COMMON_OFFSET(device_feature));
+ vpm_iowrite32(vdev, &vdev->common, 1, COMMON_OFFSET(device_feature_select));
+ features_hi = vpm_ioread32(vdev, &vdev->common, COMMON_OFFSET(device_feature));
+
+ return ((u64)features_hi << 32) | features_lo;
+}
+
+static inline void vpm_set_features(struct virtio_pci_modern_device *vdev,
+ u64 features)
+{
+ u32 features_lo = (u32)features;
+ u32 features_hi = features >> 32;
+
+ vpm_iowrite32(vdev, &vdev->common, 0, COMMON_OFFSET(guest_feature_select));
+ vpm_iowrite32(vdev, &vdev->common, features_lo, COMMON_OFFSET(guest_feature));
+ vpm_iowrite32(vdev, &vdev->common, 1, COMMON_OFFSET(guest_feature_select));
+ vpm_iowrite32(vdev, &vdev->common, features_hi, COMMON_OFFSET(guest_feature));
+}
+
+static inline void vpm_get(struct virtio_pci_modern_device *vdev,
+ unsigned offset, void *buf, unsigned len)
+{
+ u8 *ptr = buf;
+ unsigned i;
+
+ for (i = 0; i < len; i++)
+ ptr[i] = vpm_ioread8(vdev, &vdev->device, offset + i);
+}
+
+static inline u8 vpm_get_isr(struct virtio_pci_modern_device *vdev)
+{
+ return vpm_ioread8(vdev, &vdev->isr, 0);
+}
+
+void vpm_notify(struct virtio_pci_modern_device *vdev,
+ struct vring_virtqueue *vq);
+
+int vpm_find_vqs(struct virtio_pci_modern_device *vdev,
+ unsigned nvqs, struct vring_virtqueue *vqs);
+
+int virtio_pci_find_capability(struct pci_device *pci, uint8_t cfg_type);
+
+int virtio_pci_map_capability(struct pci_device *pci, int cap, size_t minlen,
+ u32 align, u32 start, u32 size,
+ struct virtio_pci_region *region);
+
+void virtio_pci_unmap_capability(struct virtio_pci_region *region);
#endif /* _VIRTIO_PCI_H_ */