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authorAlif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com>2025-02-18 16:35:06 +0800
committerTom Rini <trini@konsulko.com>2025-02-25 10:54:02 -0600
commit1c37e59bfbbae14dcc15894c8367339d16dda95a (patch)
tree1d84bc06893718e60b0a154c364f49740113a0af
parentb005eca0c91ce1b0136f4ac088fb98b7d93bbb51 (diff)
downloadu-boot-1c37e59bfbbae14dcc15894c8367339d16dda95a.tar.gz
arm: armv8: Improve SPL data save and restore implementation
Introduce a new symbol in the beginning of .data section in the common ARMv8 linker script and use that as a reference for data save and restore. Previously, the code would rely on calculating the start of the .data section address via data size, however, we observed that the data size does not really reflect the SPL mapped addresses. In our case, the binman_sym section size was not included in the data size, which will result in a wrong address for the .data start section, which prevents us from properly saving and restoring SPL data. This approach skips the calculation for the starting address of the .data section, and instead just defines the beginning address of the .data section and calling the symbol as needed, in which we think as a simpler and much more robust method. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
-rw-r--r--arch/arm/cpu/armv8/spl_data.c13
-rw-r--r--arch/arm/cpu/armv8/u-boot-spl.lds1
-rw-r--r--arch/arm/mach-socfpga/spl_agilex5.c21
-rw-r--r--configs/socfpga_agilex5_defconfig1
4 files changed, 32 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c
index 259b49ff364..492353c93df 100644
--- a/arch/arm/cpu/armv8/spl_data.c
+++ b/arch/arm/cpu/armv8/spl_data.c
@@ -5,23 +5,28 @@
#include <spl.h>
+char __data_start[0] __section(".__data_start");
char __data_save_start[0] __section(".__data_save_start");
char __data_save_end[0] __section(".__data_save_end");
u32 cold_reboot_flag = 1;
+u32 __weak reset_flag(void)
+{
+ return 1;
+}
+
void spl_save_restore_data(void)
{
u32 data_size = __data_save_end - __data_save_start;
+ cold_reboot_flag = reset_flag();
if (cold_reboot_flag == 1) {
/* Save data section to data_save section */
- memcpy(__data_save_start, __data_save_start - data_size,
- data_size);
+ memcpy(__data_save_start, __data_start, data_size);
} else {
/* Restore the data_save section to data section */
- memcpy(__data_save_start - data_size, __data_save_start,
- data_size);
+ memcpy(__data_start, __data_save_start, data_size);
}
cold_reboot_flag++;
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
index fed69644b55..c4f83ec9cfc 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -37,6 +37,7 @@ SECTIONS
.data : {
. = ALIGN(8);
+ *(.__data_start)
*(.data*)
} >.sram
diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c
index c87e9ed1641..3451611082d 100644
--- a/arch/arm/mach-socfpga/spl_agilex5.c
+++ b/arch/arm/mach-socfpga/spl_agilex5.c
@@ -21,11 +21,32 @@
DECLARE_GLOBAL_DATA_PTR;
+u32 reset_flag(void)
+{
+ /* Check rstmgr.stat for warm reset status */
+ u32 status = readl(SOCFPGA_RSTMGR_ADDRESS);
+
+ /* Check whether any L4 watchdogs or SDM had triggered warm reset */
+ u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK;
+
+ if (status & warm_reset_mask)
+ return 0;
+
+ return 1;
+}
+
void board_init_f(ulong dummy)
{
int ret;
struct udevice *dev;
+ /* Enable Async */
+ asm volatile("msr daifclr, #4");
+
+#ifdef CONFIG_SPL_BUILD
+ spl_save_restore_data();
+#endif
+
ret = spl_early_init();
if (ret)
hang();
diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index 10686a0a7b3..61ce065a2bf 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -97,3 +97,4 @@ CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_BLOBLIST_ADDR=0x7e000
CONFIG_HANDOFF=y
+CONFIG_SPL_RECOVER_DATA_SECTION=y