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author | Vignesh Raghavendra <vigneshr@ti.com> | 2022-03-07 14:55:51 +0530 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2022-04-11 11:39:19 -0400 |
commit | 7262ff7e564c8b7d81f940af242c20f832ee7511 (patch) | |
tree | 1f9c0de78eee845b61608d18aa74ccc7b9e34b80 | |
parent | 1583c87b1b813a04c95732ae8075d79b14a26eea (diff) | |
download | u-boot-7262ff7e564c8b7d81f940af242c20f832ee7511.tar.gz |
ARM: dts: k3-j721s2: Correct timer frequency
MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears
incorrect.
Without this delays in R5 SPL are 10x off.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
-rw-r--r-- | arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi index 749bc717f39..a17e61eccf2 100644 --- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi @@ -40,7 +40,7 @@ compatible = "ti,omap5430-timer"; reg = <0x0 0x40400000 0x0 0x80>; ti,timer-alwon; - clock-frequency = <25000000>; + clock-frequency = <250000000>; u-boot,dm-spl; }; |