Merge patch series "Add QOS support for J722S and AM62P"

Jayesh Choudhary <j-choudhary@ti.com> says:

Add QOS support for DSS in TI K3 SoC to route the DSS traffic through
RT queue by setting orderID as 15:
- J722S
- AM62P

Link: https://lore.kernel.org/r/20241126070614.47136-1-j-choudhary@ti.com

10 files changed, 216 insertions, 0 deletions

diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c
index 34ed01cd78c..2d35a7ce77e 100644
--- a/arch/arm/mach-k3/am62px/am62p5_init.c
+++ b/arch/arm/mach-k3/am62px/am62p5_init.c
@@ -159,6 +159,8 @@ void board_init_f(ulong dummy)
 	}
 
 	spl_enable_cache();
+
+	setup_qos();
 	debug("am62px_init: %s done\n", __func__);
 }
 
diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c
index 01b00681f68..0313e1148bc 100644
--- a/arch/arm/mach-k3/j722s/j722s_init.c
+++ b/arch/arm/mach-k3/j722s/j722s_init.c
@@ -165,6 +165,7 @@ void board_init_f(ulong dummy)
 {
 	k3_spl_init();
 	k3_mem_init();
+	setup_qos();
 }
 
 static u32 __get_backup_bootmedia(u32 devstat)
diff --git a/arch/arm/mach-k3/r5/am62px/Makefile b/arch/arm/mach-k3/r5/am62px/Makefile
index 091d4fa5b45..066c3cef8d1 100644
--- a/arch/arm/mach-k3/r5/am62px/Makefile
+++ b/arch/arm/mach-k3/r5/am62px/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += am62p_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/am62px/am62p_qos.h b/arch/arm/mach-k3/r5/am62px/am62p_qos.h
new file mode 100644
index 00000000000..99e2ee48562
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/am62p_qos.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST	0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST	0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST	0x45D14800
+#define PULSAR_UL_MAIN_0_CPU0_RMST	0x45D15000
+#define PULSAR_UL_MAIN_0_CPU0_WMST	0x45D15400
+#define PULSAR_UL_MAIN_0_CPU0_PMST	0x45D15800
+#define PULSAR_ULS_MCU_0_CPU0_RMST	0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST	0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST	0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R	0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W	0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW	0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR	0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM	0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM	0x45D22400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD	0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR	0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR	0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD	0x45D23C00
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA	0x45D25400
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC	0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC	0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC	0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC	0x45D27400
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC	0x45D29800
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC	0x45D2A000
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA	0x45D30000
+#define K3_DSS_UL_MAIN_1_VBUSM_DMA	0x45D30400
+#define USB2SS_16FFC_MAIN_0_MSTR0	0x45D34000
+#define USB2SS_16FFC_MAIN_0_MSTW0	0x45D34400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR	0x45D34800
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD	0x45D34C00
+#define USB2SS_16FFC_MAIN_1_MSTR0	0x45D35000
+#define USB2SS_16FFC_MAIN_1_MSTW0	0x45D35400
diff --git a/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c b/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
new file mode 100644
index 00000000000..d25512a038f
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/am62p_qos_uboot.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am62p Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/k3-qos.h>
+#include "am62p_qos.h"
+
+struct k3_qos_data qos_data[] = {
+	/* modules_qosConfig0 - 1 endpoints, 4 channels */
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 3),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+
+	/* modules_qosConfig1 - 1 endpoints, 4 channels */
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 0),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 1),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 2),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 3),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+
+	/* Following registers set 1:1 mapping for orderID MAP1/MAP2
+	 * remap registers. orderID x is remapped to orderID x again
+	 * This is to ensure orderID from MAP register is unchanged
+	 */
+
+	/* K3_DSS_UL_MAIN_0_VBUSM_DMA - 0 groups */
+
+	/* K3_DSS_UL_MAIN_1_VBUSM_DMA - 0 groups */
+};
+
+u32 qos_count = ARRAY_SIZE(qos_data);
diff --git a/arch/arm/mach-k3/r5/j722s/Makefile b/arch/arm/mach-k3/r5/j722s/Makefile
index 2a0dbf5f5a8..2f0b35a41e8 100644
--- a/arch/arm/mach-k3/r5/j722s/Makefile
+++ b/arch/arm/mach-k3/r5/j722s/Makefile
@@ -4,3 +4,4 @@
 
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j722s_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j722s/j722s_qos.h b/arch/arm/mach-k3/r5/j722s/j722s_qos.h
new file mode 100644
index 00000000000..88fa208322f
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/j722s_qos.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST	0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST	0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST	0x45D14800
+#define PULSAR_UL_MAIN_0_CPU0_RMST	0x45D15000
+#define PULSAR_UL_MAIN_0_CPU0_WMST	0x45D15400
+#define PULSAR_UL_MAIN_0_CPU0_PMST	0x45D15800
+#define PULSAR_ULS_MCU_0_CPU0_RMST	0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST	0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST	0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R	0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W	0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW	0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR	0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM	0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM	0x45D22400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD	0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR	0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR	0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD	0x45D23C00
+#define USB3P0SS64_16FFC_MAIN_0_MSTR0	0x45D24800
+#define USB3P0SS64_16FFC_MAIN_0_MSTW0	0x45D24C00
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA	0x45D25400
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W	0x45D25800
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R	0x45D25C00
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC	0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC	0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC	0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC	0x45D27400
+#define SAM67_C7XV_WRAP_MAIN_0_C7XV_SOC	0x45D27800
+#define SAM67_VPAC_WRAP_MAIN_0_LDC0_M_MST	0x45D28000
+#define PCIE_G2X1_64_MAIN_0_PCIE_MST_RD	0x45D29000
+#define PCIE_G2X1_64_MAIN_0_PCIE_MST_WR	0x45D29400
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC	0x45D29800
+#define SAM67_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC	0x45D2A000
+#define SAM67_C7XV_WRAP_MAIN_1_C7XV_SOC	0x45D2C000
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA	0x45D30000
+#define K3_DSS_UL_MAIN_1_VBUSM_DMA	0x45D30400
+#define USB2SS_16FFC_MAIN_0_MSTR0	0x45D34000
+#define USB2SS_16FFC_MAIN_0_MSTW0	0x45D34400
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR	0x45D34800
+#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD	0x45D34C00
+#define USB2SS_16FFC_MAIN_1_MSTR0	0x45D35000
+#define USB2SS_16FFC_MAIN_1_MSTW0	0x45D35400
diff --git a/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c b/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
new file mode 100644
index 00000000000..1d59f49252e
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j722s/j722s_qos_uboot.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * j722s Quality of Service (QoS) Configuration Data
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/k3-qos.h>
+#include "j722s_qos.h"
+
+struct k3_qos_data qos_data[] = {
+	/* modules_qosConfig0 - 1 endpoints, 4 channels */
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 0),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 1),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 2),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_0_VBUSM_DMA, 3),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+
+	/* modules_qosConfig1 - 1 endpoints, 4 channels */
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 0),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 1),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 2),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+	{
+		.reg = K3_QOS_REG(K3_DSS_UL_MAIN_1_VBUSM_DMA, 3),
+		.val = K3_QOS_VAL(0, 15, 0, 0, 0, 0),
+	},
+
+	/* Following registers set 1:1 mapping for orderID MAP1/MAP2
+	 * remap registers. orderID x is remapped to orderID x again
+	 * This is to ensure orderID from MAP register is unchanged
+	 */
+
+	/* K3_DSS_UL_MAIN_0_VBUSM_DMA - 0 groups */
+
+	/* K3_DSS_UL_MAIN_1_VBUSM_DMA - 0 groups */
+};
+
+u32 qos_count = ARRAY_SIZE(qos_data);
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index a93c33c1d9c..a0eaa128f47 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -89,6 +89,7 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
+CONFIG_K3_QOS=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_MMC_SDHCI=y
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index a3c13fedef3..0f7cd4bf37a 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -89,6 +89,7 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
+CONFIG_K3_QOS=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_MMC_SDHCI=y