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| author | Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | 2022-05-11 10:39:07 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-05-23 09:33:10 -0400 |
| commit | 2d25f63cc02e42f3e4a798bd5385e9cd73e51fd4 (patch) | |
| tree | 3c79ab6cb733d4833ef431b3e9067a0085724475 | |
| parent | 012afa83ae8b47ce4019d5d9c85ed308c61645fc (diff) | |
| download | u-boot-2d25f63cc02e42f3e4a798bd5385e9cd73e51fd4.tar.gz | |
arm: gic_v2: Skip gic_init_secure when cpu is not in el3
This would prevent configuring non-secure regs in case gic security
extensions are not emulated in Qemu.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
| -rw-r--r-- | arch/arm/lib/gic_64.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index 155212a419b..86cd882fc75 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -40,6 +40,8 @@ ENTRY(gic_init_secure) sub w10, w10, #0x1 cbnz w10, 0b #elif defined(CONFIG_GICV2) + switch_el x1, 2f, 1f, 1f +2: mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */ str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */ ldr w9, [x0, GICD_TYPER] @@ -141,6 +143,8 @@ ENTRY(gic_init_secure_percpu) * x0: Distributor Base * x1: Cpu Interface Base */ + switch_el x2, 4f, 5f, 5f +4: mov w9, #~0 /* Config SGIs and PPIs as Grp1 */ str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */ mov w9, #0x1 /* Enable SGI 0 */ @@ -155,6 +159,7 @@ ENTRY(gic_init_secure_percpu) mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */ str w9, [x1, GICC_PMR] #endif +5: ret ENDPROC(gic_init_secure_percpu) |