diff options
| author | Saeed Nowshadi <saeed.nowshadi@amd.com> | 2023-09-11 16:10:48 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-09-21 13:20:11 +0200 |
| commit | 0ec0c1e957aab80aa9c7e5119e5092d19315baab (patch) | |
| tree | cf5138028b91c4134c4b8c6137ca97f2cfaec72f | |
| parent | d282c1d9e744dea4c7b3a8de63c1c77c16bf3a7c (diff) | |
| download | u-boot-0ec0c1e957aab80aa9c7e5119e5092d19315baab.tar.gz | |
arm64: zynqmp: Fix i2c address for si570_user1 clock
Correct the i2c address for si570 oscillator that generates the si570_user1
clock. i2c address was changed by commit b6a8c603d680 ("arm64: zynqmp: Fix
i2c addresses for vck190 SC") because address in node name wasn't aligned
with reg property. But actual 0x5f address is correct which is quite rare
because all other si570s are at 0x5d.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6f31881b0e2dd657f0d4ff0869c009c2e1224f22.1694441445.git.michal.simek@amd.com
| -rw-r--r-- | arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index bf6ffb778b6..bf7569c6dda 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -2,7 +2,8 @@ /* * dts file for Xilinx Versal a2197 RevA System Controller * - * (C) Copyright 2019 - 2021, Xilinx, Inc. + * (C) Copyright 2019 - 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -460,10 +461,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <6>; - si570_user1: clock-generator@5d { /* u205 */ + si570_user1: clock-generator@5f { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; - reg = <0x5d>; + reg = <0x5f>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; |