diff options
| author | Tom Rini <trini@konsulko.com> | 2019-12-09 10:32:08 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-12-09 10:32:08 -0500 |
| commit | 2f02845817bec0dd0f89eb0d829b17b40d005afc (patch) | |
| tree | 516685ba58b11ddabeed03f3be7b43286ebdce24 | |
| parent | b38c3a641fc01fcd4eda5fa107ae3c247baa0196 (diff) | |
| parent | 6a4b07e08605ad171823021aa158b6b9bebfc6e6 (diff) | |
| download | u-boot-2f02845817bec0dd0f89eb0d829b17b40d005afc.tar.gz | |
Merge tag 'u-boot-imx-20191209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Fixes for 2020.01
-----------------
- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support
24 files changed, 1455 insertions, 1071 deletions
diff --git a/arch/arm/dts/imx6sx-softing-vining-2000.dts b/arch/arm/dts/imx6sx-softing-vining-2000.dts index 371890ff608..78dd5755a37 100644 --- a/arch/arm/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/dts/imx6sx-softing-vining-2000.dts @@ -270,6 +270,17 @@ status = "okay"; }; +®_pcie { + regulator-always-on; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpios>; @@ -360,6 +371,12 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0 + >; + }; + pinctrl_pwm1: pwm1grp-1 { fsl,pins = < /* blue LED */ diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts index e56b7226e6f..08a682f3144 100644 --- a/arch/arm/dts/imx7ulp-evk.dts +++ b/arch/arm/dts/imx7ulp-evk.dts @@ -15,7 +15,7 @@ compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; chosen { - bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200"; + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200"; stdout-path = &lpuart4; }; @@ -66,7 +66,7 @@ compatible = "regulator-fixed"; reg = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; regulator-name = "usb_otg1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -84,22 +84,6 @@ enable-active-high; }; - reg_vsd_3v3b: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "VSD_3V3B"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_extcon_usb1>; }; pf1550-rpmsg { @@ -166,134 +150,135 @@ imx7ulp-evk { pinctrl_hog_1: hoggrp-1 { fsl,pins = < - ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */ - ULP1_PAD_PTC1__PTC1 0x20100 - ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */ - ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */ - ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */ - ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */ + IMX7ULP_PAD_PTC1__PTC1 0x20000 >; }; pinctrl_backlight: backlight_grp { fsl,pins = < - ULP1_PAD_PTF2__PTF2 0x20100 + IMX7ULP_PAD_PTF2__PTF2 0x20100 >; }; pinctrl_lpi2c5: lpi2c5grp { fsl,pins = < - ULP1_PAD_PTC4__LPI2C5_SCL 0x527 - ULP1_PAD_PTC5__LPI2C5_SDA 0x527 + IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27 + IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27 >; }; pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { fsl,pins = < - ULP1_PAD_PTC19__PTC19 0x20103 + IMX7ULP_PAD_PTC19__PTC19 0x20003 >; }; pinctrl_lpuart4: lpuart4grp { fsl,pins = < - ULP1_PAD_PTC3__LPUART4_RX 0x400 - ULP1_PAD_PTC2__LPUART4_TX 0x400 + IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 >; }; pinctrl_lpuart6: lpuart6grp { fsl,pins = < - ULP1_PAD_PTE10__LPUART6_TX 0x400 - ULP1_PAD_PTE11__LPUART6_RX 0x400 - ULP1_PAD_PTE9__LPUART6_RTS_B 0x400 - ULP1_PAD_PTE8__LPUART6_CTS_B 0x400 - ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */ + IMX7ULP_PAD_PTE10__LPUART6_TX 0x3 + IMX7ULP_PAD_PTE11__LPUART6_RX 0x3 + IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3 + IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3 + IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */ >; }; pinctrl_lpuart7: lpuart7grp { fsl,pins = < - ULP1_PAD_PTF14__LPUART7_TX 0x400 - ULP1_PAD_PTF15__LPUART7_RX 0x400 - ULP1_PAD_PTF13__LPUART7_RTS_B 0x400 - ULP1_PAD_PTF12__LPUART7_CTS_B 0x400 + IMX7ULP_PAD_PTF14__LPUART7_TX 0x3 + IMX7ULP_PAD_PTF15__LPUART7_RX 0x3 + IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3 + IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3 >; }; pinctrl_usdhc0: usdhc0grp { fsl,pins = < - ULP1_PAD_PTD1__SDHC0_CMD 0x843 - ULP1_PAD_PTD2__SDHC0_CLK 0x10843 - ULP1_PAD_PTD7__SDHC0_D3 0x843 - ULP1_PAD_PTD8__SDHC0_D2 0x843 - ULP1_PAD_PTD9__SDHC0_D1 0x843 - ULP1_PAD_PTD10__SDHC0_D0 0x843 + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */ + IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */ >; }; pinctrl_usdhc0_8bit: usdhc0grp_8bit { fsl,pins = < - ULP1_PAD_PTD1__SDHC0_CMD 0x843 - ULP1_PAD_PTD2__SDHC0_CLK 0x843 - ULP1_PAD_PTD3__SDHC0_D7 0x843 - ULP1_PAD_PTD4__SDHC0_D6 0x843 - ULP1_PAD_PTD5__SDHC0_D5 0x843 - ULP1_PAD_PTD6__SDHC0_D4 0x843 - ULP1_PAD_PTD7__SDHC0_D3 0x843 - ULP1_PAD_PTD8__SDHC0_D2 0x843 - ULP1_PAD_PTD9__SDHC0_D1 0x843 - ULP1_PAD_PTD10__SDHC0_D0 0x843 + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 + IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 + IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 + IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 + IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 >; }; pinctrl_lpi2c7: lpi2c7grp { fsl,pins = < - ULP1_PAD_PTF12__LPI2C7_SCL 0x527 - ULP1_PAD_PTF13__LPI2C7_SDA 0x527 + IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27 + IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27 >; }; pinctrl_lpspi3: lpspi3grp { fsl,pins = < - ULP1_PAD_PTF16__LPSPI3_SIN 0x300 - ULP1_PAD_PTF17__LPSPI3_SOUT 0x300 - ULP1_PAD_PTF18__LPSPI3_SCK 0x300 - ULP1_PAD_PTF19__LPSPI3_PCS0 0x300 + IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0 + IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0 + IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0 + IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0 >; }; - pinctrl_usb_otg1: usbotg1grp { + pinctrl_usbotg1_vbus: otg1vbusgrp { fsl,pins = < - ULP1_PAD_PTC0__PTC0 0x30100 + IMX7ULP_PAD_PTC0__PTC0 0x20000 >; }; - pinctrl_extcon_usb1: extcon1grp { + pinctrl_usbotg1_id: otg1idgrp { fsl,pins = < - ULP1_PAD_PTC8__PTC8 0x30103 + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - ULP1_PAD_PTE3__SDHC1_CMD 0x843 - ULP1_PAD_PTE2__SDHC1_CLK 0x843 - ULP1_PAD_PTE1__SDHC1_D0 0x843 - ULP1_PAD_PTE0__SDHC1_D1 0x843 - ULP1_PAD_PTE5__SDHC1_D2 0x843 - ULP1_PAD_PTE4__SDHC1_D3 0x843 + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43 + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042 + IMX7ULP_PAD_PTE1__SDHC1_D0 0x43 + IMX7ULP_PAD_PTE0__SDHC1_D1 0x43 + IMX7ULP_PAD_PTE5__SDHC1_D2 0x43 + IMX7ULP_PAD_PTE4__SDHC1_D3 0x43 >; }; pinctrl_usdhc1_rst: usdhc1grp_rst { fsl,pins = < - ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */ + IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */ + IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */ + IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */ + IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */ >; }; - pinctrl_wifi: wifigrp { + pinctrl_dsi_hdmi: dsi_hdmi_grp { fsl,pins = < - ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */ + IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */ >; }; }; @@ -304,7 +289,7 @@ disp-dev = "mipi_dsi_northwest"; display = <&display0>; - display0: display { + display0: display@0 { bits-per-pixel = <16>; bus-width = <24>; @@ -343,21 +328,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpi2c5>; status = "okay"; - - fxas2100x@20 { - compatible = "fsl,fxas2100x"; - reg = <0x20>; - }; - - fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x1e>; - }; - - mpl3115@60 { - compatible = "fsl,mpl3115"; - reg = <0x60>; - }; }; &lpspi3 { @@ -406,13 +376,18 @@ &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; - extcon = <0>, <&extcon_usb1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; srp-disable; hnp-disable; adp-disable; status = "okay"; }; +&usbphy1 { + fsl,tx-d-cal = <88>; +}; + &usdhc0 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; diff --git a/arch/arm/dts/imx7ulp-pinfunc.h b/arch/arm/dts/imx7ulp-pinfunc.h index b1b6a71f2cd..777d7f09475 100644 --- a/arch/arm/dts/imx7ulp-pinfunc.h +++ b/arch/arm/dts/imx7ulp-pinfunc.h @@ -1,5 +1,6 @@ /* - * Copyright 2014 - 2015 Freescale Semiconductor, Inc. + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 - 2018 NXP * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -7,876 +8,885 @@ * */ -#ifndef __DTS_ULP1_PINFUNC_H -#define __DTS_ULP1_PINFUNC_H +#ifndef __DTS_IMX7ULP_PINFUNC_H +#define __DTS_IMX7ULP_PINFUNC_H /* * The pin function ID is a tuple of - * <mux_conf_reg mux2_reg mux_mode mux2_val> - * - * !!! IMPORTANT NOTE !!! - * - * There's common mux_reg & conf_reg register for each pad on ULP1 device, so the first - * two values are defined as same value. Extra non-zero mux2_reg value within the tuple - * means that there's additional mux2 control register that must be configured to - * mux2_val accordingly to fetch desired pin functionality on ULP1 device. - * + * <mux_conf_reg input_reg mux_mode input_val> */ +#define IMX7ULP_PAD_PTA0__CMP0_IN1_3V 0x0000 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA0__PTA0 0x0000 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA0__LPSPI0_PCS1 0x0000 0x0104 0x3 0x2 +#define IMX7ULP_PAD_PTA0__LPUART0_CTS_B 0x0000 0x01F8 0x4 0x2 +#define IMX7ULP_PAD_PTA0__LPI2C0_SCL 0x0000 0x017C 0x5 0x2 +#define IMX7ULP_PAD_PTA0__TPM0_CLKIN 0x0000 0x01A8 0x6 0x2 +#define IMX7ULP_PAD_PTA0__I2S0_RX_BCLK 0x0000 0x01B8 0x7 0x2 +#define IMX7ULP_PAD_PTA0__LLWU0_P0 0x0000 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA1__CMP0_IN2_3V 0x0004 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA1__LPSPI0_PCS2 0x0004 0x0108 0x3 0x1 +#define IMX7ULP_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA1__LPI2C0_SDA 0x0004 0x0180 0x5 0x1 +#define IMX7ULP_PAD_PTA1__TPM0_CH0 0x0004 0x0138 0x6 0x1 +#define IMX7ULP_PAD_PTA1__I2S0_RX_FS 0x0004 0x01BC 0x7 0x1 +#define IMX7ULP_PAD_PTA2__CMP1_IN2_3V 0x0008 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA2__LPSPI0_PCS3 0x0008 0x010C 0x3 0x1 +#define IMX7ULP_PAD_PTA2__LPUART0_TX 0x0008 0x0200 0x4 0x1 +#define IMX7ULP_PAD_PTA2__LPI2C0_HREQ 0x0008 0x0178 0x5 0x1 +#define IMX7ULP_PAD_PTA2__TPM0_CH1 0x0008 0x013C 0x6 0x1 +#define IMX7ULP_PAD_PTA2__I2S0_RXD0 0x0008 0x01DC 0x7 0x1 +#define IMX7ULP_PAD_PTA3__CMP1_IN4_3V 0x000C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA3__PTA3 0x000C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA3__LPSPI0_PCS0 0x000C 0x0100 0x3 0x1 +#define IMX7ULP_PAD_PTA3__LPUART0_RX 0x000C 0x01FC 0x4 0x1 +#define IMX7ULP_PAD_PTA3__TPM0_CH2 0x000C 0x0140 0x6 0x1 +#define IMX7ULP_PAD_PTA3__I2S0_RXD1 0x000C 0x01E0 0x7 0x1 +#define IMX7ULP_PAD_PTA3__CMP0_OUT 0x000C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA3__LLWU0_P1 0x000C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA4__ADC1_CH3A 0x0010 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA4__LPSPI0_SIN 0x0010 0x0114 0x3 0x1 +#define IMX7ULP_PAD_PTA4__LPUART1_CTS_B 0x0010 0x0204 0x4 0x1 +#define IMX7ULP_PAD_PTA4__LPI2C1_SCL 0x0010 0x0188 0x5 0x1 +#define IMX7ULP_PAD_PTA4__TPM0_CH3 0x0010 0x0144 0x6 0x1 +#define IMX7ULP_PAD_PTA4__I2S0_MCLK 0x0010 0x01B4 0x7 0x1 +#define IMX7ULP_PAD_PTA5__ADC1_CH3B 0x0014 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA5__LPSPI0_SOUT 0x0014 0x0118 0x3 0x1 +#define IMX7ULP_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA5__LPI2C1_SDA 0x0014 0x018C 0x5 0x1 +#define IMX7ULP_PAD_PTA5__TPM0_CH4 0x0014 0x0148 0x6 0x1 +#define IMX7ULP_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01C0 0x7 0x1 +#define IMX7ULP_PAD_PTA6__ADC1_CH4A 0x0018 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA6__LPSPI0_SCK 0x0018 0x0110 0x3 0x1 +#define IMX7ULP_PAD_PTA6__LPUART1_TX 0x0018 0x020C 0x4 0x1 +#define IMX7ULP_PAD_PTA6__LPI2C1_HREQ 0x0018 0x0184 0x5 0x1 +#define IMX7ULP_PAD_PTA6__TPM0_CH5 0x0018 0x014C 0x6 0x1 +#define IMX7ULP_PAD_PTA6__I2S0_TX_FS 0x0018 0x01C4 0x7 0x1 +#define IMX7ULP_PAD_PTA7__ADC1_CH4B 0x001C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA7__PTA7 0x001C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA7__LPUART1_RX 0x001C 0x0208 0x4 0x1 +#define IMX7ULP_PAD_PTA7__TPM1_CH1 0x001C 0x0154 0x6 0x1 +#define IMX7ULP_PAD_PTA7__I2S0_TXD0 0x001C 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA8__ADC1_CH5A 0x0020 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA8__LPSPI1_PCS1 0x0020 0x0120 0x3 0x1 +#define IMX7ULP_PAD_PTA8__LPUART2_CTS_B 0x0020 0x0210 0x4 0x1 +#define IMX7ULP_PAD_PTA8__LPI2C2_SCL 0x0020 0x0194 0x5 0x1 +#define IMX7ULP_PAD_PTA8__TPM1_CLKIN 0x0020 0x01AC 0x6 0x1 +#define IMX7ULP_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA9__ADC1_CH5B 0x0024 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA9__LPSPI1_PCS2 0x0024 0x0124 0x3 0x1 +#define IMX7ULP_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA9__LPI2C2_SDA 0x0024 0x0198 0x5 0x1 +#define IMX7ULP_PAD_PTA9__TPM1_CH0 0x0024 0x0150 0x6 0x1 +#define IMX7ULP_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA10__LPSPI1_PCS3 0x0028 0x0128 0x3 0x1 +#define IMX7ULP_PAD_PTA10__LPUART2_TX 0x0028 0x0218 0x4 0x1 +#define IMX7ULP_PAD_PTA10__LPI2C2_HREQ 0x0028 0x0190 0x5 0x1 +#define IMX7ULP_PAD_PTA10__TPM2_CLKIN 0x0028 0x01F4 0x6 0x1 +#define IMX7ULP_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01B8 0x7 0x1 +#define IMX7ULP_PAD_PTA11__ADC1_CH6B 0x002C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA11__PTA11 0x002C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA11__LPUART2_RX 0x002C 0x0214 0x4 0x1 +#define IMX7ULP_PAD_PTA11__TPM2_CH0 0x002C 0x0158 0x6 0x1 +#define IMX7ULP_PAD_PTA11__I2S0_RX_FS 0x002C 0x01BC 0x7 0x2 +#define IMX7ULP_PAD_PTA12__ADC1_CH7A 0x0030 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA12__LPSPI1_SIN 0x0030 0x0130 0x3 0x1 +#define IMX7ULP_PAD_PTA12__LPUART3_CTS_B 0x0030 0x021C 0x4 0x1 +#define IMX7ULP_PAD_PTA12__LPI2C3_SCL 0x0030 0x01A0 0x5 0x1 +#define IMX7ULP_PAD_PTA12__TPM2_CH1 0x0030 0x015C 0x6 0x1 +#define IMX7ULP_PAD_PTA12__I2S0_RXD0 0x0030 0x01DC 0x7 0x2 +#define IMX7ULP_PAD_PTA13__ADC1_CH7B 0x0034 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA13__PTA13 0x0034 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA13__LPSPI1_SOUT 0x0034 0x0134 0x3 0x2 +#define IMX7ULP_PAD_PTA13__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA13__LPI2C3_SDA 0x0034 0x01A4 0x5 0x2 +#define IMX7ULP_PAD_PTA13__TPM3_CLKIN 0x0034 0x01B0 0x6 0x1 +#define IMX7ULP_PAD_PTA13__I2S0_RXD1 0x0034 0x01E0 0x7 0x2 +#define IMX7ULP_PAD_PTA13__CMP0_OUT 0x0034 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA13__LLWU0_P2 0x0034 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA14__ADC1_CH8A 0x0038 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA14__PTA14 0x0038 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA14__LPSPI1_SCK 0x0038 0x012C 0x3 0x2 +#define IMX7ULP_PAD_PTA14__LPUART3_TX 0x0038 0x0224 0x4 0x2 +#define IMX7ULP_PAD_PTA14__LPI2C3_HREQ 0x0038 0x019C 0x5 0x2 +#define IMX7ULP_PAD_PTA14__TPM3_CH0 0x0038 0x0160 0x6 0x1 +#define IMX7ULP_PAD_PTA14__I2S0_MCLK 0x0038 0x01B4 0x7 0x2 +#define IMX7ULP_PAD_PTA14__LLWU0_P3 0x0038 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA15__ADC1_CH8B 0x003C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA15__PTA15 0x003C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA15__LPSPI1_PCS0 0x003C 0x011C 0x3 0x1 +#define IMX7ULP_PAD_PTA15__LPUART3_RX 0x003C 0x0220 0x4 0x1 +#define IMX7ULP_PAD_PTA15__TPM3_CH1 0x003C 0x0164 0x6 0x1 +#define IMX7ULP_PAD_PTA15__I2S0_TX_BCLK 0x003C 0x01C0 0x7 0x2 +#define IMX7ULP_PAD_PTA16__CMP1_IN5_3V 0x0040 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA16__LPSPI0_SOUT 0x0040 0x0118 0x3 0x2 +#define IMX7ULP_PAD_PTA16__LPUART0_CTS_B 0x0040 0x01F8 0x4 0x1 +#define IMX7ULP_PAD_PTA16__LPI2C0_SCL 0x0040 0x017C 0x5 0x1 +#define IMX7ULP_PAD_PTA16__TPM3_CH2 0x0040 0x0168 0x6 0x1 +#define IMX7ULP_PAD_PTA16__I2S0_TX_FS 0x0040 0x01C4 0x7 0x2 +#define IMX7ULP_PAD_PTA17__CMP1_IN6_3V 0x0044 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA17__LPSPI0_SCK 0x0044 0x0110 0x3 0x2 +#define IMX7ULP_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA17__LPI2C0_SDA 0x0044 0x0180 0x5 0x2 +#define IMX7ULP_PAD_PTA17__TPM3_CH3 0x0044 0x016C 0x6 0x1 +#define IMX7ULP_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA18__CMP1_IN1_3V 0x0048 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA18__PTA18 0x0048 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA18__FXIO0_D2 0x0048 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA18__LPSPI0_PCS0 0x0048 0x0100 0x3 0x2 +#define IMX7ULP_PAD_PTA18__LPUART0_TX 0x0048 0x0200 0x4 0x2 +#define IMX7ULP_PAD_PTA18__LPI2C0_HREQ 0x0048 0x0178 0x5 0x2 +#define IMX7ULP_PAD_PTA18__TPM3_CH4 0x0048 0x0170 0x6 0x1 +#define IMX7ULP_PAD_PTA18__I2S0_TXD1 0x0048 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA18__LLWU0_P4 0x0048 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA19__CMP1_IN3_3V 0x004C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA19__PTA19 0x004C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA19__FXIO0_D3 0x004C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA19__LPUART0_RX 0x004C 0x01FC 0x4 0x2 +#define IMX7ULP_PAD_PTA19__TPM3_CH5 0x004C 0x0174 0x6 0x1 +#define IMX7ULP_PAD_PTA19__I2S1_RX_BCLK 0x004C 0x01CC 0x7 0x1 +#define IMX7ULP_PAD_PTA19__LPTMR0_ALT3 0x004C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA19__LLWU0_P5 0x004C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA20__ADC0_CH10A 0x0050 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA20__LPSPI0_SIN 0x0050 0x0114 0x3 0x2 +#define IMX7ULP_PAD_PTA20__LPUART1_CTS_B 0x0050 0x0204 0x4 0x2 +#define IMX7ULP_PAD_PTA20__LPI2C1_SCL 0x0050 0x0188 0x5 0x2 +#define IMX7ULP_PAD_PTA20__TPM0_CLKIN 0x0050 0x01A8 0x6 0x1 +#define IMX7ULP_PAD_PTA20__I2S1_RX_FS 0x0050 0x01D0 0x7 0x1 +#define IMX7ULP_PAD_PTA21__ADC0_CH10B 0x0054 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA21__LPSPI0_PCS1 0x0054 0x0104 0x3 0x1 +#define IMX7ULP_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA21__LPI2C1_SDA 0x0054 0x018C 0x5 0x2 +#define IMX7ULP_PAD_PTA21__TPM0_CH0 0x0054 0x0138 0x6 0x2 +#define IMX7ULP_PAD_PTA21__I2S1_RXD0 0x0054 0x01E4 0x7 0x1 +#define IMX7ULP_PAD_PTA22__ADC0_CH9A 0x0058 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA22__LPSPI0_PCS2 0x0058 0x0108 0x3 0x2 +#define IMX7ULP_PAD_PTA22__LPUART1_TX 0x0058 0x020C 0x4 0x2 +#define IMX7ULP_PAD_PTA22__LPI2C1_HREQ 0x0058 0x0184 0x5 0x2 +#define IMX7ULP_PAD_PTA22__TPM0_CH1 0x0058 0x013C 0x6 0x2 +#define IMX7ULP_PAD_PTA22__I2S1_RXD1 0x0058 0x01E8 0x7 0x1 +#define IMX7ULP_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTA23__ADC0_CH9B 0x005C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA23__PTA23 0x005C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA23__FXIO0_D7 0x005C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA23__LPSPI0_PCS3 0x005C 0x010C 0x3 0x2 +#define IMX7ULP_PAD_PTA23__LPUART1_RX 0x005C 0x0208 0x4 0x2 +#define IMX7ULP_PAD_PTA23__TPM0_CH2 0x005C 0x0140 0x6 0x2 +#define IMX7ULP_PAD_PTA23__I2S1_MCLK 0x005C 0x01C8 0x7 0x1 +#define IMX7ULP_PAD_PTA23__LLWU0_P6 0x005C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTA24__ADC0_CH8A 0x0060 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA24__LPSPI1_PCS1 0x0060 0x0120 0x3 0x2 +#define IMX7ULP_PAD_PTA24__LPUART2_CTS_B 0x0060 0x0210 0x4 0x2 +#define IMX7ULP_PAD_PTA24__LPI2C2_SCL 0x0060 0x0194 0x5 0x2 +#define IMX7ULP_PAD_PTA24__TPM0_CH3 0x0060 0x0144 0x6 0x2 +#define IMX7ULP_PAD_PTA24__I2S1_TX_BCLK 0x0060 0x01D4 0x7 0x1 +#define IMX7ULP_PAD_PTA25__ADC0_CH8B 0x0064 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA25__LPSPI1_PCS2 0x0064 0x0124 0x3 0x2 +#define IMX7ULP_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA25__LPI2C2_SDA 0x0064 0x0198 0x5 0x2 +#define IMX7ULP_PAD_PTA25__TPM0_CH4 0x0064 0x0148 0x6 0x2 +#define IMX7ULP_PAD_PTA25__I2S1_TX_FS 0x0064 0x01D8 0x7 0x1 +#define IMX7ULP_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA26__LPSPI1_PCS3 0x0068 0x0128 0x3 0x2 +#define IMX7ULP_PAD_PTA26__LPUART2_TX 0x0068 0x0218 0x4 0x2 +#define IMX7ULP_PAD_PTA26__LPI2C2_HREQ 0x0068 0x0190 0x5 0x2 +#define IMX7ULP_PAD_PTA26__TPM0_CH5 0x0068 0x014C 0x6 0x2 +#define IMX7ULP_PAD_PTA26__I2S1_RXD2 0x0068 0x01EC 0x7 0x1 +#define IMX7ULP_PAD_PTA27__PTA27 0x006C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA27__JTAG_TDO 0x006C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA27__FXIO0_D11 0x006C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA27__LPUART2_RX 0x006C 0x0214 0x4 0x2 +#define IMX7ULP_PAD_PTA27__TPM1_CH1 0x006C 0x0154 0x6 0x2 +#define IMX7ULP_PAD_PTA27__I2S1_RXD3 0x006C 0x01F0 0x7 0x1 +#define IMX7ULP_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA28__LPSPI1_SIN 0x0070 0x0130 0x3 0x2 +#define IMX7ULP_PAD_PTA28__LPUART3_CTS_B 0x0070 0x021C 0x4 0x2 +#define IMX7ULP_PAD_PTA28__LPI2C3_SCL 0x0070 0x01A0 0x5 0x2 +#define IMX7ULP_PAD_PTA28__TPM1_CLKIN 0x0070 0x01AC 0x6 0x2 +#define IMX7ULP_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA29__LPSPI1_SOUT 0x0074 0x0134 0x3 0x1 +#define IMX7ULP_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTA29__LPI2C3_SDA 0x0074 0x01A4 0x5 0x1 +#define IMX7ULP_PAD_PTA29__TPM1_CH0 0x0074 0x0150 0x6 0x2 +#define IMX7ULP_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA30__ADC0_CH1A 0x0078 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA30__LPSPI1_SCK 0x0078 0x012C 0x3 0x1 +#define IMX7ULP_PAD_PTA30__LPUART3_TX 0x0078 0x0224 0x4 0x1 +#define IMX7ULP_PAD_PTA30__LPI2C3_HREQ 0x0078 0x019C 0x5 0x1 +#define IMX7ULP_PAD_PTA30__TPM2_CLKIN 0x0078 0x01F4 0x6 0x2 +#define IMX7ULP_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTA31__ADC0_CH1B 0x007C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTA31__PTA31 0x007C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTA31__FXIO0_D15 0x007C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTA31__LPSPI1_PCS0 0x007C 0x011C 0x3 0x2 +#define IMX7ULP_PAD_PTA31__LPUART3_RX 0x007C 0x0220 0x4 0x2 +#define IMX7ULP_PAD_PTA31__TPM2_CH0 0x007C 0x0158 0x6 0x2 +#define IMX7ULP_PAD_PTA31__I2S1_TXD1 0x007C 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTA31__LPTMR0_ALT1 0x007C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTA31__EWM_IN 0x007C 0x0228 0xc 0x1 +#define IMX7ULP_PAD_PTA31__LLWU0_P7 0x007C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB0__LPSPI0_SIN 0x0080 0x0114 0x3 0x3 +#define IMX7ULP_PAD_PTB0__LPUART0_TX 0x0080 0x0200 0x4 0x3 +#define IMX7ULP_PAD_PTB0__TPM2_CH1 0x0080 0x015C 0x6 0x2 +#define IMX7ULP_PAD_PTB0__CLKOUT0 0x0080 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTB1__ADC0_CH0B 0x0084 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB1__PTB1 0x0084 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB1__FXIO0_D17 0x0084 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB1__LPSPI0_SOUT 0x0084 0x0118 0x3 0x3 +#define IMX7ULP_PAD_PTB1__LPUART0_RX 0x0084 0x01FC 0x4 0x3 +#define IMX7ULP_PAD_PTB1__TPM3_CLKIN 0x0084 0x01B0 0x6 0x3 +#define IMX7ULP_PAD_PTB1__I2S1_TX_BCLK 0x0084 0x01D4 0x7 0x2 +#define IMX7ULP_PAD_PTB1__RTC_CLKOUT 0x0084 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB1__EWM_IN 0x0084 0x0228 0xc 0x2 +#define IMX7ULP_PAD_PTB1__LLWU0_P8 0x0084 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB2__ADC0_CH6A 0x0088 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB2__LPSPI0_SCK 0x0088 0x0110 0x3 0x3 +#define IMX7ULP_PAD_PTB2__LPUART1_TX 0x0088 0x020C 0x4 0x3 +#define IMX7ULP_PAD_PTB2__TPM3_CH0 0x0088 0x0160 0x6 0x2 +#define IMX7ULP_PAD_PTB2__I2S1_TX_FS 0x0088 0x01D8 0x7 0x2 +#define IMX7ULP_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB3__ADC0_CH6B 0x008C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB3__PTB3 0x008C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB3__FXIO0_D19 0x008C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB3__LPSPI0_PCS0 0x008C 0x0100 0x3 0x3 +#define IMX7ULP_PAD_PTB3__LPUART1_RX 0x008C 0x0208 0x4 0x3 +#define IMX7ULP_PAD_PTB3__TPM3_CH1 0x008C 0x0164 0x6 0x2 +#define IMX7ULP_PAD_PTB3__I2S1_TXD0 0x008C 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTB3__TRACE_D0 0x008C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB3__LPTMR1_ALT2 0x008C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB3__LLWU0_P9 0x008C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB4__LPSPI0_PCS1 0x0090 0x0104 0x3 0x3 +#define IMX7ULP_PAD_PTB4__LPUART2_TX 0x0090 0x0218 0x4 0x3 +#define IMX7ULP_PAD_PTB4__LPI2C0_HREQ 0x0090 0x0178 0x5 0x3 +#define IMX7ULP_PAD_PTB4__TPM3_CH2 0x0090 0x0168 0x6 0x2 +#define IMX7ULP_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTB4__QSPIA_DATA7 0x0090 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB4__SEC_VIO_B 0x0090 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB5__LPSPI0_PCS2 0x0094 0x0108 0x3 0x3 +#define IMX7ULP_PAD_PTB5__LPUART2_RX 0x0094 0x0214 0x4 0x3 +#define IMX7ULP_PAD_PTB5__LPI2C1_HREQ 0x0094 0x0184 0x5 0x3 +#define IMX7ULP_PAD_PTB5__TPM3_CH3 0x0094 0x016C 0x6 0x2 +#define IMX7ULP_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTB5__QSPIA_DATA6 0x0094 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB5__RTC_CLKOUT 0x0094 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB6__ADC1_CH1A 0x0098 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB6__PTB6 0x0098 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB6__FXIO0_D22 0x0098 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB6__LPSPI0_PCS3 0x0098 0x010C 0x3 0x3 +#define IMX7ULP_PAD_PTB6__LPUART3_TX 0x0098 0x0224 0x4 0x3 +#define IMX7ULP_PAD_PTB6__LPI2C0_SCL 0x0098 0x017C 0x5 0x3 +#define IMX7ULP_PAD_PTB6__TPM3_CH4 0x0098 0x0170 0x6 0x2 +#define IMX7ULP_PAD_PTB6__I2S1_TXD3 0x0098 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTB6__QSPIA_DATA5 0x0098 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB6__TRACE_D3 0x0098 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB6__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB6__LLWU0_P10 0x0098 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB7__ADC1_CH1B 0x009C 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB7__PTB7 0x009C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB7__FXIO0_D23 0x009C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB7__LPSPI1_SIN 0x009C 0x0130 0x3 0x3 +#define IMX7ULP_PAD_PTB7__LPUART3_RX 0x009C 0x0220 0x4 0x3 +#define IMX7ULP_PAD_PTB7__LPI2C0_SDA 0x009C 0x0180 0x5 0x3 +#define IMX7ULP_PAD_PTB7__TPM3_CH5 0x009C 0x0174 0x6 0x2 +#define IMX7ULP_PAD_PTB7__I2S1_MCLK 0x009C 0x01C8 0x7 0x2 +#define IMX7ULP_PAD_PTB7__QSPIA_SS1_B 0x009C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB7__CMP1_OUT 0x009C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB7__LLWU0_P11 0x009C 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 0x00A0 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB8__PTB8 0x00A0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB8__FXIO0_D24 0x00A0 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB8__LPSPI1_SOUT 0x00A0 0x0134 0x3 0x3 +#define IMX7ULP_PAD_PTB8__LPI2C1_SCL 0x00A0 0x0188 0x5 0x3 +#define IMX7ULP_PAD_PTB8__TPM0_CLKIN 0x00A0 0x01A8 0x6 0x3 +#define IMX7ULP_PAD_PTB8__I2S1_RX_BCLK 0x00A0 0x01CC 0x7 0x2 +#define IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x00A0 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB8__RTC_CLKOUT 0x00A0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 0x00A4 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB9__PTB9 0x00A4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB9__FXIO0_D25 0x00A4 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB9__LPSPI1_SCK 0x00A4 0x012C 0x3 0x3 +#define IMX7ULP_PAD_PTB9__LPI2C1_SDA 0x00A4 0x018C 0x5 0x3 +#define IMX7ULP_PAD_PTB9__TPM0_CH0 0x00A4 0x0138 0x6 0x3 +#define IMX7ULP_PAD_PTB9__I2S1_RX_FS 0x00A4 0x01D0 0x7 0x2 +#define IMX7ULP_PAD_PTB9__QSPIA_DQS 0x00A4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB9__LLWU0_P12 0x00A4 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB10__CMP0_IN1 0x00A8 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB10__PTB10 0x00A8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB10__FXIO0_D26 0x00A8 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB10__LPSPI1_PCS0 0x00A8 0x011C 0x3 0x3 +#define IMX7ULP_PAD_PTB10__LPI2C2_SCL 0x00A8 0x0194 0x5 0x3 +#define IMX7ULP_PAD_PTB10__TPM0_CH1 0x00A8 0x013C 0x6 0x3 +#define IMX7ULP_PAD_PTB10__I2S1_RXD0 0x00A8 0x01E4 0x7 0x2 +#define IMX7ULP_PAD_PTB10__TRACE_D4 0x00A8 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB11__CMP0_IN3 0x00AC 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB11__PTB11 0x00AC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB11__FXIO0_D27 0x00AC 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB11__LPSPI1_PCS1 0x00AC 0x0120 0x3 0x3 +#define IMX7ULP_PAD_PTB11__LPI2C2_SDA 0x00AC 0x0198 0x5 0x3 +#define IMX7ULP_PAD_PTB11__TPM1_CLKIN 0x00AC 0x01AC 0x6 0x3 +#define IMX7ULP_PAD_PTB11__I2S1_RXD1 0x00AC 0x01E8 0x7 0x2 +#define IMX7ULP_PAD_PTB11__TRACE_D5 0x00AC 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 0x00B0 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB12__PTB12 0x00B0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB12__FXIO0_D28 0x00B0 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB12__LPSPI1_PCS2 0x00B0 0x0124 0x3 0x3 +#define IMX7ULP_PAD_PTB12__LPUART2_TX 0x00B0 0x0218 0x4 0x4 +#define IMX7ULP_PAD_PTB12__LPI2C3_SCL 0x00B0 0x01A0 0x5 0x3 +#define IMX7ULP_PAD_PTB12__TPM1_CH0 0x00B0 0x0150 0x6 0x3 +#define IMX7ULP_PAD_PTB12__I2S1_RXD2 0x00B0 0x01EC 0x7 0x2 +#define IMX7ULP_PAD_PTB12__TRACE_D6 0x00B0 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 0x00B4 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB13__PTB13 0x00B4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB13__FXIO0_D29 0x00B4 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB13__LPSPI1_PCS3 0x00B4 0x0128 0x3 0x3 +#define IMX7ULP_PAD_PTB13__LPUART2_RX 0x00B4 0x0214 0x4 0x4 +#define IMX7ULP_PAD_PTB13__LPI2C3_SDA 0x00B4 0x01A4 0x5 0x3 +#define IMX7ULP_PAD_PTB13__TPM1_CH1 0x00B4 0x0154 0x6 0x3 +#define IMX7ULP_PAD_PTB13__I2S1_RXD3 0x00B4 0x01F0 0x7 0x2 +#define IMX7ULP_PAD_PTB13__QSPIA_DATA4 0x00B4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB13__TRACE_D7 0x00B4 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTB14__ADC1_CH2A 0x00B8 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB14__PTB14 0x00B8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB14__FXIO0_D30 0x00B8 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB14__LPI2C2_HREQ 0x00B8 0x0190 0x5 0x3 +#define IMX7ULP_PAD_PTB14__TPM2_CLKIN 0x00B8 0x01F4 0x6 0x3 +#define IMX7ULP_PAD_PTB14__QSPIA_SS1_B 0x00B8 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB14__QSPIA_SCLK_B 0x00B8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTB14__RTC_CLKOUT 0x00B8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTB14__LLWU0_P13 0x00B8 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB15__ADC1_CH2B 0x00BC 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB15__PTB15 0x00BC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB15__FXIO0_D31 0x00BC 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTB15__LPI2C3_HREQ 0x00BC 0x019C 0x5 0x3 +#define IMX7ULP_PAD_PTB15__TPM2_CH0 0x00BC 0x0158 0x6 0x3 +#define IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x00BC 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB16__ADC0_CH4A 0x00C0 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB16__PTB16 0x00C0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB16__TPM2_CH1 0x00C0 0x015C 0x6 0x3 +#define IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x00C0 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB16__LLWU0_P14 0x00C0 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTB17__ADC0_CH4B 0x00C4 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB17__PTB17 0x00C4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB17__TPM3_CLKIN 0x00C4 0x01B0 0x6 0x2 +#define IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x00C4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB18__ADC0_CH5A 0x00C8 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB18__PTB18 0x00C8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB18__TPM3_CH0 0x00C8 0x0160 0x6 0x3 +#define IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x00C8 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB19__ADC0_CH5B 0x00CC 0x0000 0x0 0x0 +#define IMX7ULP_PAD_PTB19__PTB19 0x00CC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTB19__TPM3_CH1 0x00CC 0x0164 0x6 0x3 +#define IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x00CC 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTB19__USB0_ID 0x00CC 0x0338 0xa 0x0 +#define IMX7ULP_PAD_PTB19__LLWU0_P15 0x00CC 0x0000 0xd 0x0 +#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 +#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 +#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 +#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027C 0x5 0x1 +#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 +#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024C 0x4 0x1 +#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 +#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 +#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC3__PTC3 0x000C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000C 0x0248 0x4 0x1 +#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000C 0x0288 0x6 0x1 +#define IMX7ULP_PAD_PTC3__FB_AD3 0x000C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 +#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02A0 0x3 0x1 +#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 +#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02BC 0x5 0x1 +#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028C 0x6 0x1 +#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 +#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02A4 0x3 0x1 +#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02C0 0x5 0x1 +#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 +#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020C 0x2 0x1 +#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02A8 0x3 0x1 +#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 +#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02B8 0x5 0x1 +#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 +#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC7__PTC7 0x001C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001C 0x0210 0x2 0x1 +#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001C 0x0254 0x4 0x1 +#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001C 0x02C8 0x6 0x1 +#define IMX7ULP_PAD_PTC7__FB_AD7 0x001C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 +#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02B0 0x3 0x1 +#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025C 0x4 0x1 +#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02FC 0x5 0x1 +#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02CC 0x6 0x1 +#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 +#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02B4 0x3 0x1 +#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 +#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02C4 0x6 0x1 +#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021C 0x2 0x1 +#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02AC 0x3 0x1 +#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 +#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02F8 0x5 0x1 +#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02E8 0x6 0x1 +#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC11__PTC11 0x002C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002C 0x0220 0x2 0x1 +#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002C 0x029C 0x3 0x1 +#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002C 0x0260 0x4 0x1 +#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002C 0x02EC 0x6 0x1 +#define IMX7ULP_PAD_PTC11__FB_AD11 0x002C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 +#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 +#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 +#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 +#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02F0 0x6 0x1 +#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 +#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 +#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030C 0x5 0x1 +#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02F4 0x6 0x1 +#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1 +#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022C 0x2 0x1 +#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031C 0x3 0x1 +#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 +#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 +#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02DC 0x6 0x1 +#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC15__PTC15 0x003C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003C 0x0230 0x2 0x1 +#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003C 0x026C 0x4 0x1 +#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003C 0x02E0 0x6 0x1 +#define IMX7ULP_PAD_PTC15__FB_AD15 0x003C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 +#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 +#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02E4 0x6 0x1 +#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1 +#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 +#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 +#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02D8 0x6 0x1 +#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023C 0x2 0x1 +#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 +#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02D0 0x6 0x1 +#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2 +#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033C 0xc 0x1 +#define IMX7ULP_PAD_PTC19__PTC19 0x004C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004C 0x0240 0x2 0x1 +#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004C 0x0310 0x3 0x1 +#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004C 0x02D4 0x6 0x1 +#define IMX7ULP_PAD_PTC19__FB_A16 0x004C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC19__USB0_ID 0x004C 0x0338 0xa 0x3 +#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTC19__VIU_DE 0x004C 0x033C 0xc 0x3 +#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD3__PTD3 0x008C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD7__PTD7 0x009C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD8__PTD8 0x00A0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00A0 0x0298 0x6 0x2 +#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00A0 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD9__PTD9 0x00A4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00A4 0x0280 0x6 0x2 +#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00A4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD10__PTD10 0x00A8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00A8 0x0284 0x6 0x2 +#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00A8 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD11__PTD11 0x00AC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00AC 0x0288 0x6 0x2 +#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00AC 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02A0 0x3 0x2 +#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 +#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 +#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02A4 0x3 0x2 +#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027C 0x5 0x2 +#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02A8 0x3 0x2 +#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024C 0x4 0x2 +#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 +#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE3__PTE3 0x010C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010C 0x0248 0x4 0x2 +#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010C 0x02C8 0x6 0x2 +#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02B0 0x3 0x2 +#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 +#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02BC 0x5 0x2 +#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02CC 0x6 0x2 +#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02B4 0x3 0x2 +#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02C0 0x5 0x2 +#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02C4 0x6 0x2 +#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033C 0xc 0x2 +#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02AC 0x3 0x2 +#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 +#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02B8 0x5 0x2 +#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02E8 0x6 0x2 +#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1 +#define IMX7ULP_PAD_PTE7__PTE7 0x011C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011C 0x029C 0x3 0x2 +#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011C 0x0254 0x4 0x2 +#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011C 0x02EC 0x6 0x2 +#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE7__FB_A18 0x011C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE7__VIU_FID 0x011C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 +#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025C 0x4 0x2 +#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02FC 0x5 0x2 +#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02F0 0x6 0x2 +#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 +#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 +#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 +#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02F4 0x6 0x2 +#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032C 0x7 0x1 +#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031C 0x3 0x2 +#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 +#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02F8 0x5 0x2 +#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02DC 0x6 0x2 +#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 +#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE11__PTE11 0x012C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE11__VIU_D19 0x012C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012C 0x0260 0x4 0x2 +#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012C 0x02E0 0x6 0x2 +#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE11__FB_A20 0x012C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 +#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 +#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 +#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02E4 0x6 0x2 +#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 +#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 +#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 +#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030C 0x5 0x2 +#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02D8 0x6 0x2 +#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032C 0x8 0x2 +#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 +#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 +#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 +#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02D0 0x6 0x2 +#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 +#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE15__PTE15 0x013C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013C 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013C 0x0310 0x3 0x2 +#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013C 0x026C 0x4 0x2 +#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013C 0x02D4 0x6 0x2 +#define IMX7ULP_PAD_PTE15__FB_A24 0x013C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013C 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE15__VIU_D23 0x013C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 +#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 +#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 +#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033C 0xc 0x0 +#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027C 0x5 0x3 +#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 +#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024C 0x4 0x3 +#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 +#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 +#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF3__PTF3 0x018C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018C 0x0248 0x4 0x3 +#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018C 0x0288 0x6 0x3 +#define IMX7ULP_PAD_PTF3__FB_AD16 0x018C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 +#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02A0 0x3 0x3 +#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 +#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02BC 0x5 0x3 +#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028C 0x6 0x2 +#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 +#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02A4 0x3 0x3 +#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02C0 0x5 0x3 +#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 +#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020C 0x2 0x2 +#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02A8 0x3 0x3 +#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 +#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02B8 0x5 0x3 +#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 +#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF7__PTF7 0x019C 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019C 0x0210 0x2 0x2 +#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019C 0x0254 0x4 0x3 +#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019C 0x02C8 0x6 0x3 +#define IMX7ULP_PAD_PTF7__FB_AD20 0x019C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF7__VIU_D3 0x019C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF8__PTF8 0x01A0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01A0 0x0214 0x2 0x2 +#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01A0 0x02B0 0x3 0x3 +#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01A0 0x025C 0x4 0x3 +#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01A0 0x02FC 0x5 0x3 +#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01A0 0x02CC 0x6 0x3 +#define IMX7ULP_PAD_PTF8__FB_AD21 0x01A0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF8__USB1_CLK 0x01A0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF8__VIU_D4 0x01A0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF9__PTF9 0x01A4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01A4 0x0218 0x2 0x2 +#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01A4 0x02B4 0x3 0x3 +#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01A4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01A4 0x0300 0x5 0x3 +#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01A4 0x02C4 0x6 0x3 +#define IMX7ULP_PAD_PTF9__FB_AD22 0x01A4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF9__USB1_NXT 0x01A4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF9__VIU_D5 0x01A4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF10__PTF10 0x01A8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01A8 0x021C 0x2 0x2 +#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01A8 0x02AC 0x3 0x3 +#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01A8 0x0264 0x4 0x3 +#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01A8 0x02F8 0x5 0x3 +#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01A8 0x02E8 0x6 0x3 +#define IMX7ULP_PAD_PTF10__FB_AD23 0x01A8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF10__USB1_STP 0x01A8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF10__VIU_D6 0x01A8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF11__PTF11 0x01AC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01AC 0x0220 0x2 0x2 +#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01AC 0x029C 0x3 0x3 +#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01AC 0x0260 0x4 0x3 +#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01AC 0x02EC 0x6 0x3 +#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01AC 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF11__USB1_DIR 0x01AC 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF11__VIU_D7 0x01AC 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF12__PTF12 0x01B0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01B0 0x0224 0x2 0x2 +#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01B0 0x0314 0x3 0x3 +#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01B0 0x0268 0x4 0x3 +#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01B0 0x0308 0x5 0x3 +#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01B0 0x02F0 0x6 0x3 +#define IMX7ULP_PAD_PTF12__FB_AD24 0x01B0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF12__USB1_DATA0 0x01B0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF12__VIU_D8 0x01B0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF13__PTF13 0x01B4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01B4 0x0228 0x2 0x2 +#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01B4 0x0318 0x3 0x3 +#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01B4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01B4 0x030C 0x5 0x3 +#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01B4 0x02F4 0x6 0x3 +#define IMX7ULP_PAD_PTF13__FB_AD25 0x01B4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF13__USB1_DATA1 0x01B4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF13__VIU_D9 0x01B4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF14__PTF14 0x01B8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01B8 0x022C 0x2 0x2 +#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01B8 0x031C 0x3 0x3 +#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01B8 0x0270 0x4 0x3 +#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01B8 0x0304 0x5 0x3 +#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01B8 0x02DC 0x6 0x3 +#define IMX7ULP_PAD_PTF14__FB_AD26 0x01B8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF14__USB1_DATA2 0x01B8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF14__VIU_D10 0x01B8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF15__PTF15 0x01BC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01BC 0x0230 0x2 0x2 +#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01BC 0x026C 0x4 0x3 +#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01BC 0x02E0 0x6 0x3 +#define IMX7ULP_PAD_PTF15__FB_AD27 0x01BC 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF15__USB1_DATA3 0x01BC 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF15__VIU_D11 0x01BC 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF16__PTF16 0x01C0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF16__USB1_DATA4 0x01C0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF16__VIU_D12 0x01C0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01C0 0x0234 0x2 0x2 +#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01C0 0x0324 0x3 0x3 +#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01C0 0x02E4 0x6 0x3 +#define IMX7ULP_PAD_PTF16__FB_AD28 0x01C0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF17__PTF17 0x01C4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF17__USB1_DATA5 0x01C4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF17__VIU_D13 0x01C4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01C4 0x0238 0x2 0x2 +#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01C4 0x0328 0x3 0x3 +#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01C4 0x02D8 0x6 0x3 +#define IMX7ULP_PAD_PTF17__FB_AD29 0x01C4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF18__PTF18 0x01C8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF18__USB1_DATA6 0x01C8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF18__VIU_D14 0x01C8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01C8 0x023C 0x2 0x2 +#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01C8 0x0320 0x3 0x3 +#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01C8 0x02D0 0x6 0x3 +#define IMX7ULP_PAD_PTF18__FB_AD30 0x01C8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF19__PTF19 0x01CC 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF19__USB1_DATA7 0x01CC 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF19__VIU_D15 0x01CC 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01CC 0x0240 0x2 0x2 +#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01CC 0x0310 0x3 0x3 +#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01CC 0x02D4 0x6 0x3 +#define IMX7ULP_PAD_PTF19__FB_AD31 0x01CC 0x0000 0x9 0x0 -#define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0 -#define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0 -#define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0 -#define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2 -#define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2 -#define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2 -#define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2 -#define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2 -#define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0 -#define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 -#define ULP1_PAD_PTA1__LPSPI0_PCS2 0x0004 0xd108 0x3 0x1 -#define ULP1_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0 -#define ULP1_PAD_PTA1__LPI2C0_SDA 0x0004 0xd180 0x5 0x1 -#define ULP1_PAD_PTA1__TPM0_CH0 0x0004 0xd138 0x6 0x1 -#define ULP1_PAD_PTA1__I2S0_RX_FS 0x0004 0x01bc 0x7 0x1 -#define ULP1_PAD_PTA2__CMP1_IN2A 0x0008 0x0000 0x0 0x0 -#define ULP1_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0 -#define ULP1_PAD_PTA2__LPSPI0_PCS3 0x0008 0xd10c 0x3 0x1 -#define ULP1_PAD_PTA2__LPUART0_TX 0x0008 0xd200 0x4 0x1 -#define ULP1_PAD_PTA2__LPI2C0_HREQ 0x0008 0xd178 0x5 0x1 -#define ULP1_PAD_PTA2__TPM0_CH1 0x0008 0xd13c 0x6 0x1 -#define ULP1_PAD_PTA2__I2S0_RXD0 0x0008 0x01dc 0x7 0x1 -#define ULP1_PAD_PTA3_LLWU0_P1__CMP1_IN2B 0x000c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA3_LLWU0_P1__PTA3 0x000c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA3_LLWU0_P1__CMP0_OUT 0x000c 0x0000 0xb 0x0 -#define ULP1_PAD_PTA3_LLWU0_P1__LLWU0_P1 0x000c 0x0000 0xd 0x0 -#define ULP1_PAD_PTA3_LLWU0_P1__LPUART0_RX 0x000c 0xd1fc 0x4 0x1 -#define ULP1_PAD_PTA3_LLWU0_P1__TPM0_CH2 0x000c 0xd140 0x6 0x1 -#define ULP1_PAD_PTA3_LLWU0_P1__I2S0_RXD1 0x000c 0x01e0 0x7 0x1 -#define ULP1_PAD_PTA4__ADC1_CH2A 0x0010 0x0000 0x0 0x0 -#define ULP1_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0 -#define ULP1_PAD_PTA4__LPSPI0_SIN 0x0010 0xd114 0x3 0x1 -#define ULP1_PAD_PTA4__LPUART1_CTS_B 0x0010 0xd204 0x4 0x1 -#define ULP1_PAD_PTA4__LPI2C1_SCL 0x0010 0xd188 0x5 0x1 -#define ULP1_PAD_PTA4__TPM0_CH3 0x0010 0xd144 0x6 0x1 -#define ULP1_PAD_PTA4__I2S0_MCLK 0x0010 0x01b4 0x7 0x1 -#define ULP1_PAD_PTA5__ADC1_CH2B 0x0014 0x0000 0x0 0x0 -#define ULP1_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0 -#define ULP1_PAD_PTA5__LPSPI0_SOUT 0x0014 0xd118 0x3 0x1 -#define ULP1_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0 -#define ULP1_PAD_PTA5__LPI2C1_SDA 0x0014 0xd18c 0x5 0x1 -#define ULP1_PAD_PTA5__TPM0_CH4 0x0014 0xd148 0x6 0x1 -#define ULP1_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01c0 0x7 0x1 -#define ULP1_PAD_PTA6__ADC1_CH3A 0x0018 0x0000 0x0 0x0 -#define ULP1_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0 -#define ULP1_PAD_PTA6__LPSPI0_SCK 0x0018 0xd110 0x3 0x1 -#define ULP1_PAD_PTA6__LPUART1_TX 0x0018 0xd20c 0x4 0x1 -#define ULP1_PAD_PTA6__LPI2C1_HREQ 0x0018 0xd184 0x5 0x1 -#define ULP1_PAD_PTA6__TPM0_CH5 0x0018 0xd14c 0x6 0x1 -#define ULP1_PAD_PTA6__I2S0_TX_FS 0x0018 0x01c4 0x7 0x1 -#define ULP1_PAD_PTA7__ADC1_CH3B 0x001c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA7__PTA7 0x001c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA7__LPSPI0_PCS0 0x001c 0xd100 0x3 0x1 -#define ULP1_PAD_PTA7__LPUART1_RX 0x001c 0xd208 0x4 0x1 -#define ULP1_PAD_PTA7__TPM1_CH1 0x001c 0xd154 0x6 0x1 -#define ULP1_PAD_PTA7__I2S0_TXD0 0x001c 0x0000 0x7 0x0 -#define ULP1_PAD_PTA8__ADC1_CH7A 0x0020 0x0000 0x0 0x0 -#define ULP1_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0 -#define ULP1_PAD_PTA8__LPSPI1_PCS1 0x0020 0xd120 0x3 0x1 -#define ULP1_PAD_PTA8__LPUART2_CTS_B 0x0020 0xd210 0x4 0x1 -#define ULP1_PAD_PTA8__LPI2C2_SCL 0x0020 0xd194 0x5 0x1 -#define ULP1_PAD_PTA8__TPM1_CLKIN 0x0020 0xd1ac 0x6 0x1 -#define ULP1_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0 -#define ULP1_PAD_PTA9__ADC1_CH7B 0x0024 0x0000 0x0 0x0 -#define ULP1_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0 -#define ULP1_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0 -#define ULP1_PAD_PTA9__LPSPI1_PCS2 0x0024 0xd124 0x3 0x1 -#define ULP1_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0 -#define ULP1_PAD_PTA9__LPI2C2_SDA 0x0024 0xd198 0x5 0x1 -#define ULP1_PAD_PTA9__TPM1_CH0 0x0024 0xd150 0x6 0x1 -#define ULP1_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0 -#define ULP1_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0 -#define ULP1_PAD_PTA10__LPSPI1_PCS3 0x0028 0xd128 0x3 0x1 -#define ULP1_PAD_PTA10__LPUART2_TX 0x0028 0xd218 0x4 0x1 -#define ULP1_PAD_PTA10__LPI2C2_HREQ 0x0028 0xd190 0x5 0x1 -#define ULP1_PAD_PTA10__TPM2_CLKIN 0x0028 0xd1f4 0x6 0x1 -#define ULP1_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01b8 0x7 0x1 -#define ULP1_PAD_PTA11__ADC1_CH6B 0x002c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA11__PTA11 0x002c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA11__LPUART2_RX 0x002c 0xd214 0x4 0x1 -#define ULP1_PAD_PTA11__TPM2_CH0 0x002c 0xd158 0x6 0x1 -#define ULP1_PAD_PTA11__I2S0_RX_FS 0x002c 0x01bc 0x7 0x2 -#define ULP1_PAD_PTA12__ADC1_CH5A 0x0030 0x0000 0x0 0x0 -#define ULP1_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0 -#define ULP1_PAD_PTA12__LPSPI1_SIN 0x0030 0xd130 0x3 0x1 -#define ULP1_PAD_PTA12__LPUART3_CTS_B 0x0030 0xd21c 0x4 0x1 -#define ULP1_PAD_PTA12__LPI2C3_SCL 0x0030 0xd1a0 0x5 0x1 -#define ULP1_PAD_PTA12__TPM2_CH1 0x0030 0xd15c 0x6 0x1 -#define ULP1_PAD_PTA12__I2S0_RXD0 0x0030 0x01dc 0x7 0x2 -#define ULP1_PAD_PTA13_LLWU0_P2__ADC1_CH5B 0x0034 0x0000 0x0 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__PTA13 0x0034 0x0000 0x1 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__CMP0_OUT 0x0034 0x0000 0xb 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__LLWU0_P2 0x0034 0x0000 0xd 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__LPSPI1_SOUT 0x0034 0xd134 0x3 0x2 -#define ULP1_PAD_PTA13_LLWU0_P2__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0 -#define ULP1_PAD_PTA13_LLWU0_P2__LPI2C3_SDA 0x0034 0xd1a4 0x5 0x2 -#define ULP1_PAD_PTA13_LLWU0_P2__TPM3_CLKIN 0x0034 0xd1b0 0x6 0x1 -#define ULP1_PAD_PTA13_LLWU0_P2__I2S0_RXD1 0x0034 0x01e0 0x7 0x2 -#define ULP1_PAD_PTA14_LLWU0_P3__ADC1_CH4A 0x0038 0x0000 0x0 0x0 -#define ULP1_PAD_PTA14_LLWU0_P3__PTA14 0x0038 0x0000 0x1 0x0 -#define ULP1_PAD_PTA14_LLWU0_P3__LLWU0_P3 0x0038 0x0000 0xd 0x0 -#define ULP1_PAD_PTA14_LLWU0_P3__LPSPI1_SCK 0x0038 0xd12c 0x3 0x2 -#define ULP1_PAD_PTA14_LLWU0_P3__LPUART3_TX 0x0038 0xd224 0x4 0x2 -#define ULP1_PAD_PTA14_LLWU0_P3__LPI2C3_HREQ 0x0038 0xd19c 0x5 0x2 -#define ULP1_PAD_PTA14_LLWU0_P3__TPM3_CH0 0x0038 0xd160 0x6 0x1 -#define ULP1_PAD_PTA14_LLWU0_P3__I2S0_MCLK 0x0038 0x01b4 0x7 0x2 -#define ULP1_PAD_PTA15__ADC1_CH4B 0x003c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA15__PTA15 0x003c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA15__LPSPI1_PCS0 0x003c 0xd11c 0x3 0x1 -#define ULP1_PAD_PTA15__LPUART3_RX 0x003c 0xd220 0x4 0x1 -#define ULP1_PAD_PTA15__TPM3_CH1 0x003c 0xd164 0x6 0x1 -#define ULP1_PAD_PTA15__I2S0_TX_BCLK 0x003c 0x01c0 0x7 0x2 -#define ULP1_PAD_PTA16__CMP1_IN0A 0x0040 0x0000 0x0 0x0 -#define ULP1_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0 -#define ULP1_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0 -#define ULP1_PAD_PTA16__LPSPI0_PCS1 0x0040 0xd104 0x3 0x1 -#define ULP1_PAD_PTA16__LPUART0_CTS_B 0x0040 0xd1f8 0x4 0x1 -#define ULP1_PAD_PTA16__LPI2C0_SCL 0x0040 0xd17c 0x5 0x1 -#define ULP1_PAD_PTA16__TPM3_CH2 0x0040 0xd168 0x6 0x1 -#define ULP1_PAD_PTA16__I2S0_TX_FS 0x0040 0x01c4 0x7 0x2 -#define ULP1_PAD_PTA17__CMP1_IN0B 0x0044 0x0000 0x0 0x0 -#define ULP1_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0 -#define ULP1_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0 -#define ULP1_PAD_PTA17__LPSPI0_PCS2 0x0044 0xd108 0x3 0x2 -#define ULP1_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0 -#define ULP1_PAD_PTA17__LPI2C0_SDA 0x0044 0xd180 0x5 0x2 -#define ULP1_PAD_PTA17__TPM3_CH3 0x0044 0xd16c 0x6 0x1 -#define ULP1_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__CMP1_IN1A 0x0048 0x0000 0x0 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__PTA18 0x0048 0x0000 0x1 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__NMI1_B 0x0048 0x0000 0xb 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__LLWU0_P4 0x0048 0x0000 0xd 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__FXIO0_D2 0x0048 0x0000 0x2 0x0 -#define ULP1_PAD_PTA18_LLWU0_P4__LPSPI0_PCS3 0x0048 0xd10c 0x3 0x2 -#define ULP1_PAD_PTA18_LLWU0_P4__LPUART0_TX 0x0048 0xd200 0x4 0x2 -#define ULP1_PAD_PTA18_LLWU0_P4__LPI2C0_HREQ 0x0048 0xd178 0x5 0x2 -#define ULP1_PAD_PTA18_LLWU0_P4__TPM3_CH4 0x0048 0xd170 0x6 0x1 -#define ULP1_PAD_PTA18_LLWU0_P4__I2S0_TXD1 0x0048 0x0000 0x7 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__CMP1_IN1B 0x004c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__PTA19 0x004c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__LPTMR0_ALT3 0x004c 0x0000 0xb 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__LLWU0_P5 0x004c 0x0000 0xd 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__FXIO0_D3 0x004c 0x0000 0x2 0x0 -#define ULP1_PAD_PTA19_LLWU0_P5__LPUART0_RX 0x004c 0xd1fc 0x4 0x2 -#define ULP1_PAD_PTA19_LLWU0_P5__TPM3_CH5 0x004c 0xd174 0x6 0x1 -#define ULP1_PAD_PTA19_LLWU0_P5__I2S1_RX_BCLK 0x004c 0xd1cc 0x7 0x1 -#define ULP1_PAD_PTA20__ADC0_CH7A 0x0050 0x0000 0x0 0x0 -#define ULP1_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0 -#define ULP1_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0 -#define ULP1_PAD_PTA20__LPSPI0_SIN 0x0050 0xd114 0x3 0x2 -#define ULP1_PAD_PTA20__LPUART1_CTS_B 0x0050 0xd204 0x4 0x2 -#define ULP1_PAD_PTA20__LPI2C1_SCL 0x0050 0xd188 0x5 0x2 -#define ULP1_PAD_PTA20__TPM0_CLKIN 0x0050 0xd1a8 0x6 0x1 -#define ULP1_PAD_PTA20__I2S1_RX_FS 0x0050 0xd1d0 0x7 0x1 -#define ULP1_PAD_PTA21__ADC0_CH7B 0x0054 0x0000 0x0 0x0 -#define ULP1_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0 -#define ULP1_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0 -#define ULP1_PAD_PTA21__LPSPI0_SOUT 0x0054 0xd118 0x3 0x2 -#define ULP1_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0 -#define ULP1_PAD_PTA21__LPI2C1_SDA 0x0054 0xd18c 0x5 0x2 -#define ULP1_PAD_PTA21__TPM0_CH0 0x0054 0xd138 0x6 0x2 -#define ULP1_PAD_PTA21__I2S1_RXD0 0x0054 0xd1e4 0x7 0x1 -#define ULP1_PAD_PTA22__ADC0_CH6A 0x0058 0x0000 0x0 0x0 -#define ULP1_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0 -#define ULP1_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0 -#define ULP1_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0 -#define ULP1_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0 -#define ULP1_PAD_PTA22__LPSPI0_SCK 0x0058 0xd110 0x3 0x2 -#define ULP1_PAD_PTA22__LPUART1_TX 0x0058 0xd20c 0x4 0x2 -#define ULP1_PAD_PTA22__LPI2C1_HREQ 0x0058 0xd184 0x5 0x2 -#define ULP1_PAD_PTA22__TPM0_CH1 0x0058 0xd13c 0x6 0x2 -#define ULP1_PAD_PTA22__I2S1_RXD1 0x0058 0xd1e8 0x7 0x1 -#define ULP1_PAD_PTA23_LLWU0_P6__ADC0_CH6B 0x005c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA23_LLWU0_P6__PTA23 0x005c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA23_LLWU0_P6__LLWU0_P6 0x005c 0x0000 0xd 0x0 -#define ULP1_PAD_PTA23_LLWU0_P6__FXIO0_D7 0x005c 0x0000 0x2 0x0 -#define ULP1_PAD_PTA23_LLWU0_P6__LPSPI0_PCS0 0x005c 0xd100 0x3 0x2 -#define ULP1_PAD_PTA23_LLWU0_P6__LPUART1_RX 0x005c 0xd208 0x4 0x2 -#define ULP1_PAD_PTA23_LLWU0_P6__TPM0_CH2 0x005c 0xd140 0x6 0x2 -#define ULP1_PAD_PTA23_LLWU0_P6__I2S1_MCLK 0x005c 0xd1c8 0x7 0x1 -#define ULP1_PAD_PTA24__ADC0_CH5A 0x0060 0x0000 0x0 0x0 -#define ULP1_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0 -#define ULP1_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0 -#define ULP1_PAD_PTA24__LPSPI1_PCS1 0x0060 0xd120 0x3 0x2 -#define ULP1_PAD_PTA24__LPUART2_CTS_B 0x0060 0xd210 0x4 0x2 -#define ULP1_PAD_PTA24__LPI2C2_SCL 0x0060 0xd194 0x5 0x2 -#define ULP1_PAD_PTA24__TPM0_CH3 0x0060 0xd144 0x6 0x2 -#define ULP1_PAD_PTA24__I2S1_TX_BCLK 0x0060 0xd1d4 0x7 0x1 -#define ULP1_PAD_PTA25__ADC0_CH5B 0x0064 0x0000 0x0 0x0 -#define ULP1_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0 -#define ULP1_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0 -#define ULP1_PAD_PTA25__LPSPI1_PCS2 0x0064 0xd124 0x3 0x2 -#define ULP1_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0 -#define ULP1_PAD_PTA25__LPI2C2_SDA 0x0064 0xd198 0x5 0x2 -#define ULP1_PAD_PTA25__TPM0_CH4 0x0064 0xd148 0x6 0x2 -#define ULP1_PAD_PTA25__I2S1_TX_FS 0x0064 0xd1d8 0x7 0x1 -#define ULP1_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0 -#define ULP1_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0 -#define ULP1_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0 -#define ULP1_PAD_PTA26__LPSPI1_PCS3 0x0068 0xd128 0x3 0x2 -#define ULP1_PAD_PTA26__LPUART2_TX 0x0068 0xd218 0x4 0x2 -#define ULP1_PAD_PTA26__LPI2C2_HREQ 0x0068 0xd190 0x5 0x2 -#define ULP1_PAD_PTA26__TPM0_CH5 0x0068 0xd14c 0x6 0x2 -#define ULP1_PAD_PTA26__I2S1_RXD2 0x0068 0xd1ec 0x7 0x1 -#define ULP1_PAD_PTA27__PTA27 0x006c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA27__JTAG_TDO 0x006c 0x0000 0xa 0x0 -#define ULP1_PAD_PTA27__FXIO0_D11 0x006c 0x0000 0x2 0x0 -#define ULP1_PAD_PTA27__LPUART2_RX 0x006c 0xd214 0x4 0x2 -#define ULP1_PAD_PTA27__TPM1_CH1 0x006c 0xd154 0x6 0x2 -#define ULP1_PAD_PTA27__I2S1_RXD3 0x006c 0xd1f0 0x7 0x1 -#define ULP1_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0 -#define ULP1_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0 -#define ULP1_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0 -#define ULP1_PAD_PTA28__LPSPI1_SIN 0x0070 0xd130 0x3 0x2 -#define ULP1_PAD_PTA28__LPUART3_CTS_B 0x0070 0xd21c 0x4 0x2 -#define ULP1_PAD_PTA28__LPI2C3_SCL 0x0070 0xd1a0 0x5 0x2 -#define ULP1_PAD_PTA28__TPM1_CLKIN 0x0070 0xd1ac 0x6 0x2 -#define ULP1_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0 -#define ULP1_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0 -#define ULP1_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0 -#define ULP1_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0 -#define ULP1_PAD_PTA29__LPSPI1_SOUT 0x0074 0xd134 0x3 0x1 -#define ULP1_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0 -#define ULP1_PAD_PTA29__LPI2C3_SDA 0x0074 0xd1a4 0x5 0x1 -#define ULP1_PAD_PTA29__TPM1_CH0 0x0074 0xd150 0x6 0x2 -#define ULP1_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0 -#define ULP1_PAD_PTA30__ADC0_CH4A 0x0078 0x0000 0x0 0x0 -#define ULP1_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0 -#define ULP1_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0 -#define ULP1_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0 -#define ULP1_PAD_PTA30__LPSPI1_SCK 0x0078 0xd12c 0x3 0x1 -#define ULP1_PAD_PTA30__LPUART3_TX 0x0078 0xd224 0x4 0x1 -#define ULP1_PAD_PTA30__LPI2C3_HREQ 0x0078 0xd19c 0x5 0x1 -#define ULP1_PAD_PTA30__TPM2_CLKIN 0x0078 0xd1f4 0x6 0x2 -#define ULP1_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__ADC0_CH4B 0x007c 0x0000 0x0 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__PTA31 0x007c 0x0000 0x1 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__LPTMR0_ALT1 0x007c 0x0000 0xb 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__EWM_IN 0x007c 0xd228 0xc 0x1 -#define ULP1_PAD_PTA31_LLWU0_P7__LLWU0_P7 0x007c 0x0000 0xd 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__FXIO0_D15 0x007c 0x0000 0x2 0x0 -#define ULP1_PAD_PTA31_LLWU0_P7__LPSPI1_PCS0 0x007c 0xd11c 0x3 0x2 -#define ULP1_PAD_PTA31_LLWU0_P7__LPUART3_RX 0x007c 0xd220 0x4 0x2 -#define ULP1_PAD_PTA31_LLWU0_P7__TPM2_CH0 0x007c 0xd158 0x6 0x2 -#define ULP1_PAD_PTA31_LLWU0_P7__I2S1_TXD1 0x007c 0x0000 0x7 0x0 -#define ULP1_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0 -#define ULP1_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0 -#define ULP1_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0 -#define ULP1_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0 -#define ULP1_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0 -#define ULP1_PAD_PTB0__LPSPI0_SIN 0x0080 0xd114 0x3 0x3 -#define ULP1_PAD_PTB0__LPUART0_TX 0x0080 0xd200 0x4 0x3 -#define ULP1_PAD_PTB0__TPM2_CH1 0x0080 0xd15c 0x6 0x2 -#define ULP1_PAD_PTB0__CLKOUT 0x0080 0x0000 0x9 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__ADC0_CH0B 0x0084 0x0000 0x0 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__PTB1 0x0084 0x0000 0x1 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__RTC_CLKOUT 0x0084 0x0000 0xb 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__EWM_IN 0x0084 0xd228 0xc 0x2 -#define ULP1_PAD_PTB1_LLWU0_P8__LLWU0_P8 0x0084 0x0000 0xd 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__FXIO0_D17 0x0084 0x0000 0x2 0x0 -#define ULP1_PAD_PTB1_LLWU0_P8__LPSPI0_SOUT 0x0084 0xd118 0x3 0x3 -#define ULP1_PAD_PTB1_LLWU0_P8__LPUART0_RX 0x0084 0xd1fc 0x4 0x3 -#define ULP1_PAD_PTB1_LLWU0_P8__TPM3_CLKIN 0x0084 0xd1b0 0x6 0x3 -#define ULP1_PAD_PTB1_LLWU0_P8__I2S1_TX_BCLK 0x0084 0xd1d4 0x7 0x2 -#define ULP1_PAD_PTB2__ADC0_CH1A 0x0088 0x0000 0x0 0x0 -#define ULP1_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0 -#define ULP1_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0 -#define ULP1_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0 -#define ULP1_PAD_PTB2__LPSPI0_SCK 0x0088 0xd110 0x3 0x3 -#define ULP1_PAD_PTB2__LPUART1_TX 0x0088 0xd20c 0x4 0x3 -#define ULP1_PAD_PTB2__TPM3_CH0 0x0088 0xd160 0x6 0x2 -#define ULP1_PAD_PTB2__I2S1_TX_FS 0x0088 0xd1d8 0x7 0x2 -#define ULP1_PAD_PTB3_LLWU0_P9__ADC0_CH1B 0x008c 0x0000 0x0 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__PTB3 0x008c 0x0000 0x1 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__TRACE_D0 0x008c 0x0000 0xa 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__LPTMR1_ALT2 0x008c 0x0000 0xb 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__LLWU0_P9 0x008c 0x0000 0xd 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__FXIO0_D19 0x008c 0x0000 0x2 0x0 -#define ULP1_PAD_PTB3_LLWU0_P9__LPSPI0_PCS0 0x008c 0xd100 0x3 0x3 -#define ULP1_PAD_PTB3_LLWU0_P9__LPUART1_RX 0x008c 0xd208 0x4 0x3 -#define ULP1_PAD_PTB3_LLWU0_P9__TPM3_CH1 0x008c 0xd164 0x6 0x2 -#define ULP1_PAD_PTB3_LLWU0_P9__I2S1_TXD0 0x008c 0x0000 0x7 0x0 -#define ULP1_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0 -#define ULP1_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0 -#define ULP1_PAD_PTB4__BOOTCFG0 0x0090 0x0000 0xd 0x0 -#define ULP1_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0 -#define ULP1_PAD_PTB4__LPSPI0_PCS1 0x0090 0xd104 0x3 0x3 -#define ULP1_PAD_PTB4__LPUART2_TX 0x0090 0xd218 0x4 0x3 -#define ULP1_PAD_PTB4__LPI2C0_HREQ 0x0090 0xd178 0x5 0x3 -#define ULP1_PAD_PTB4__TPM3_CH2 0x0090 0xd168 0x6 0x2 -#define ULP1_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0 -#define ULP1_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0 -#define ULP1_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0 -#define ULP1_PAD_PTB5__BOOTCFG1 0x0094 0x0000 0xd 0x0 -#define ULP1_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0 -#define ULP1_PAD_PTB5__LPSPI0_PCS2 0x0094 0xd108 0x3 0x3 -#define ULP1_PAD_PTB5__LPUART2_RX 0x0094 0xd214 0x4 0x3 -#define ULP1_PAD_PTB5__LPI2C1_HREQ 0x0094 0xd184 0x5 0x3 -#define ULP1_PAD_PTB5__TPM3_CH3 0x0094 0xd16c 0x6 0x2 -#define ULP1_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__PTB6 0x0098 0x0000 0x1 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__TRACE_D3 0x0098 0x0000 0xa 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__LLWU0_P10 0x0098 0x0000 0xd 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__FXIO0_D22 0x0098 0x0000 0x2 0x0 -#define ULP1_PAD_PTB6_LLWU0_P10__LPSPI0_PCS3 0x0098 0xd10c 0x3 0x3 -#define ULP1_PAD_PTB6_LLWU0_P10__LPUART3_TX 0x0098 0xd224 0x4 0x3 -#define ULP1_PAD_PTB6_LLWU0_P10__LPI2C0_SCL 0x0098 0xd17c 0x5 0x3 -#define ULP1_PAD_PTB6_LLWU0_P10__TPM3_CH4 0x0098 0xd170 0x6 0x2 -#define ULP1_PAD_PTB6_LLWU0_P10__I2S1_TXD3 0x0098 0x0000 0x7 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__PTB7 0x009c 0x0000 0x1 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__CMP1_OUT 0x009c 0x0000 0xb 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__LLWU0_P11 0x009c 0x0000 0xd 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__FXIO0_D23 0x009c 0x0000 0x2 0x0 -#define ULP1_PAD_PTB7_LLWU0_P11__LPSPI1_SIN 0x009c 0xd130 0x3 0x3 -#define ULP1_PAD_PTB7_LLWU0_P11__LPUART3_RX 0x009c 0xd220 0x4 0x3 -#define ULP1_PAD_PTB7_LLWU0_P11__LPI2C0_SDA 0x009c 0xd180 0x5 0x3 -#define ULP1_PAD_PTB7_LLWU0_P11__TPM3_CH5 0x009c 0xd174 0x6 0x2 -#define ULP1_PAD_PTB7_LLWU0_P11__I2S1_MCLK 0x009c 0xd1c8 0x7 0x2 -#define ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x009c 0x0000 0x8 0x0 -#define ULP1_PAD_PTB8__CMP0_IN0A 0x00a0 0x0000 0x0 0x0 -#define ULP1_PAD_PTB8__PTB8 0x00a0 0x0000 0x1 0x0 -#define ULP1_PAD_PTB8__RTC_CLKOUT 0x00a0 0x0000 0xb 0x0 -#define ULP1_PAD_PTB8__FXIO0_D24 0x00a0 0x0000 0x2 0x0 -#define ULP1_PAD_PTB8__LPSPI1_SOUT 0x00a0 0xd134 0x3 0x3 -#define ULP1_PAD_PTB8__LPI2C1_SCL 0x00a0 0xd188 0x5 0x3 -#define ULP1_PAD_PTB8__TPM0_CLKIN 0x00a0 0xd1a8 0x6 0x3 -#define ULP1_PAD_PTB8__I2S1_RX_BCLK 0x00a0 0xd1cc 0x7 0x2 -#define ULP1_PAD_PTB8__QSPIA_SS0_B 0x00a0 0x0000 0x8 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__CMP0_IN0B 0x00a4 0x0000 0x0 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__PTB9 0x00a4 0x0000 0x1 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__LLWU0_P12 0x00a4 0x0000 0xd 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__FXIO0_D25 0x00a4 0x0000 0x2 0x0 -#define ULP1_PAD_PTB9_LLWU0_P12__LPSPI1_SCK 0x00a4 0xd12c 0x3 0x3 -#define ULP1_PAD_PTB9_LLWU0_P12__LPI2C1_SDA 0x00a4 0xd18c 0x5 0x3 -#define ULP1_PAD_PTB9_LLWU0_P12__TPM0_CH0 0x00a4 0xd138 0x6 0x3 -#define ULP1_PAD_PTB9_LLWU0_P12__I2S1_RX_FS 0x00a4 0xd1d0 0x7 0x2 -#define ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x00a4 0x0000 0x8 0x0 -#define ULP1_PAD_PTB10__CMP0_IN1A 0x00a8 0x0000 0x0 0x0 -#define ULP1_PAD_PTB10__PTB10 0x00a8 0x0000 0x1 0x0 -#define ULP1_PAD_PTB10__TRACE_D4 0x00a8 0x0000 0xa 0x0 -#define ULP1_PAD_PTB10__FXIO0_D26 0x00a8 0x0000 0x2 0x0 -#define ULP1_PAD_PTB10__LPSPI1_PCS0 0x00a8 0xd11c 0x3 0x3 -#define ULP1_PAD_PTB10__LPI2C2_SCL 0x00a8 0xd194 0x5 0x3 -#define ULP1_PAD_PTB10__TPM0_CH1 0x00a8 0xd13c 0x6 0x3 -#define ULP1_PAD_PTB10__I2S1_RXD0 0x00a8 0xd1e4 0x7 0x2 -#define ULP1_PAD_PTB10__QSPIA_DATA7 0x00a8 0x0000 0x8 0x0 -#define ULP1_PAD_PTB11__CMP0_IN1B 0x00ac 0x0000 0x0 0x0 -#define ULP1_PAD_PTB11__PTB11 0x00ac 0x0000 0x1 0x0 -#define ULP1_PAD_PTB11__TRACE_D5 0x00ac 0x0000 0xa 0x0 -#define ULP1_PAD_PTB11__FXIO0_D27 0x00ac 0x0000 0x2 0x0 -#define ULP1_PAD_PTB11__LPSPI1_PCS1 0x00ac 0xd120 0x3 0x3 -#define ULP1_PAD_PTB11__LPI2C2_SDA 0x00ac 0xd198 0x5 0x3 -#define ULP1_PAD_PTB11__TPM1_CLKIN 0x00ac 0xd1ac 0x6 0x3 -#define ULP1_PAD_PTB11__I2S1_RXD1 0x00ac 0xd1e8 0x7 0x2 -#define ULP1_PAD_PTB11__QSPIA_DATA6 0x00ac 0x0000 0x8 0x0 -#define ULP1_PAD_PTB12__ADC1_CH0A 0x00b0 0x0000 0x0 0x0 -#define ULP1_PAD_PTB12__PTB12 0x00b0 0x0000 0x1 0x0 -#define ULP1_PAD_PTB12__TRACE_D6 0x00b0 0x0000 0xa 0x0 -#define ULP1_PAD_PTB12__FXIO0_D28 0x00b0 0x0000 0x2 0x0 -#define ULP1_PAD_PTB12__LPSPI1_PCS2 0x00b0 0xd124 0x3 0x3 -#define ULP1_PAD_PTB12__LPI2C3_SCL 0x00b0 0xd1a0 0x5 0x3 -#define ULP1_PAD_PTB12__TPM1_CH0 0x00b0 0xd150 0x6 0x3 -#define ULP1_PAD_PTB12__I2S1_RXD2 0x00b0 0xd1ec 0x7 0x2 -#define ULP1_PAD_PTB12__QSPIA_DATA5 0x00b0 0x0000 0x8 0x0 -#define ULP1_PAD_PTB13__ADC1_CH0B 0x00b4 0x0000 0x0 0x0 -#define ULP1_PAD_PTB13__PTB13 0x00b4 0x0000 0x1 0x0 -#define ULP1_PAD_PTB13__TRACE_D7 0x00b4 0x0000 0xa 0x0 -#define ULP1_PAD_PTB13__FXIO0_D29 0x00b4 0x0000 0x2 0x0 -#define ULP1_PAD_PTB13__LPSPI1_PCS3 0x00b4 0xd128 0x3 0x3 -#define ULP1_PAD_PTB13__LPI2C3_SDA 0x00b4 0xd1a4 0x5 0x3 -#define ULP1_PAD_PTB13__TPM1_CH1 0x00b4 0xd154 0x6 0x3 -#define ULP1_PAD_PTB13__I2S1_RXD3 0x00b4 0xd1f0 0x7 0x2 -#define ULP1_PAD_PTB13__QSPIA_DATA4 0x00b4 0x0000 0x8 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__ADC1_CH1A 0x00b8 0x0000 0x0 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__PTB14 0x00b8 0x0000 0x1 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__LLWU0_P13 0x00b8 0x0000 0xd 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__FXIO0_D30 0x00b8 0x0000 0x2 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__LPI2C2_HREQ 0x00b8 0xd190 0x5 0x3 -#define ULP1_PAD_PTB14_LLWU0_P13__TPM2_CLKIN 0x00b8 0xd1f4 0x6 0x3 -#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SS0_B 0x00b8 0x0000 0x8 0x0 -#define ULP1_PAD_PTB14_LLWU0_P13__QSPIA_SCLK_B 0x00b8 0x0000 0x9 0x0 -#define ULP1_PAD_PTB15__ADC1_CH1B 0x00bc 0x0000 0x0 0x0 -#define ULP1_PAD_PTB15__PTB15 0x00bc 0x0000 0x1 0x0 -#define ULP1_PAD_PTB15__FXIO0_D31 0x00bc 0x0000 0x2 0x0 -#define ULP1_PAD_PTB15__LPI2C3_HREQ 0x00bc 0xd19c 0x5 0x3 -#define ULP1_PAD_PTB15__TPM2_CH0 0x00bc 0xd158 0x6 0x3 -#define ULP1_PAD_PTB15__QSPIA_SCLK 0x00bc 0x0000 0x8 0x0 -#define ULP1_PAD_PTB16_LLWU0_P14__ADC0_CH2A 0x00c0 0x0000 0x0 0x0 -#define ULP1_PAD_PTB16_LLWU0_P14__PTB16 0x00c0 0x0000 0x1 0x0 -#define ULP1_PAD_PTB16_LLWU0_P14__LLWU0_P14 0x00c0 0x0000 0xd 0x0 -#define ULP1_PAD_PTB16_LLWU0_P14__TPM2_CH1 0x00c0 0xd15c 0x6 0x3 -#define ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x00c0 0x0000 0x8 0x0 -#define ULP1_PAD_PTB17__ADC0_CH2B 0x00c4 0x0000 0x0 0x0 -#define ULP1_PAD_PTB17__PTB17 0x00c4 0x0000 0x1 0x0 -#define ULP1_PAD_PTB17__TPM3_CLKIN 0x00c4 0xd1b0 0x6 0x2 -#define ULP1_PAD_PTB17__QSPIA_DATA2 0x00c4 0x0000 0x8 0x0 -#define ULP1_PAD_PTB18__ADC0_CH3A 0x00c8 0x0000 0x0 0x0 -#define ULP1_PAD_PTB18__PTB18 0x00c8 0x0000 0x1 0x0 -#define ULP1_PAD_PTB18__TPM3_CH0 0x00c8 0xd160 0x6 0x3 -#define ULP1_PAD_PTB18__QSPIA_DATA1 0x00c8 0x0000 0x8 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__ADC0_CH3B 0x00cc 0x0000 0x0 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__PTB19 0x00cc 0x0000 0x1 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__USB0_ID 0x00cc 0x0000 0xa 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__LLWU0_P15 0x00cc 0x0000 0xd 0x0 -#define ULP1_PAD_PTB19_LLWU0_P15__TPM3_CH1 0x00cc 0xd164 0x6 0x3 -#define ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x00cc 0x0000 0x8 0x0 -#define ULP1_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 -#define ULP1_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 -#define ULP1_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 -#define ULP1_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 -#define ULP1_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 -#define ULP1_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 -#define ULP1_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 -#define ULP1_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 -#define ULP1_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 -#define ULP1_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 -#define ULP1_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 -#define ULP1_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 -#define ULP1_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 -#define ULP1_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 -#define ULP1_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 -#define ULP1_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 -#define ULP1_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 -#define ULP1_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 -#define ULP1_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 -#define ULP1_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 -#define ULP1_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 -#define ULP1_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 -#define ULP1_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 -#define ULP1_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 -#define ULP1_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 -#define ULP1_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 -#define ULP1_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 -#define ULP1_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 -#define ULP1_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 -#define ULP1_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 -#define ULP1_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 -#define ULP1_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 -#define ULP1_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 -#define ULP1_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 -#define ULP1_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 -#define ULP1_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 -#define ULP1_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 -#define ULP1_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 -#define ULP1_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 -#define ULP1_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 -#define ULP1_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 -#define ULP1_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 -#define ULP1_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 -#define ULP1_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 -#define ULP1_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 -#define ULP1_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 -#define ULP1_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 -#define ULP1_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 -#define ULP1_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 -#define ULP1_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 -#define ULP1_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 -#define ULP1_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 -#define ULP1_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 -#define ULP1_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 -#define ULP1_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 -#define ULP1_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 -#define ULP1_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 -#define ULP1_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 -#define ULP1_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 -#define ULP1_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 -#define ULP1_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 -#define ULP1_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 -#define ULP1_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 -#define ULP1_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 -#define ULP1_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 -#define ULP1_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 -#define ULP1_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 -#define ULP1_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 -#define ULP1_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 -#define ULP1_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 -#define ULP1_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 -#define ULP1_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 -#define ULP1_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 -#define ULP1_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 -#define ULP1_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 -#define ULP1_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 -#define ULP1_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 -#define ULP1_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 -#define ULP1_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 -#define ULP1_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 -#define ULP1_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 -#define ULP1_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 -#define ULP1_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 -#define ULP1_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 -#define ULP1_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 -#define ULP1_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 -#define ULP1_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 -#define ULP1_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 -#define ULP1_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 -#define ULP1_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 -#define ULP1_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 -#define ULP1_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 -#define ULP1_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 -#define ULP1_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 -#define ULP1_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 -#define ULP1_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 -#define ULP1_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 -#define ULP1_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 -#define ULP1_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 -#define ULP1_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 -#define ULP1_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 -#define ULP1_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 -#define ULP1_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 -#define ULP1_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 -#define ULP1_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 -#define ULP1_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 -#define ULP1_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 -#define ULP1_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 -#define ULP1_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 -#define ULP1_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 -#define ULP1_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 -#define ULP1_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 -#define ULP1_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 -#define ULP1_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 -#define ULP1_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 -#define ULP1_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 -#define ULP1_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 -#define ULP1_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 -#define ULP1_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 -#define ULP1_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 -#define ULP1_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 -#define ULP1_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 -#define ULP1_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 -#define ULP1_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 -#define ULP1_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 -#define ULP1_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 -#define ULP1_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 -#define ULP1_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 -#define ULP1_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 -#define ULP1_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 -#define ULP1_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 -#define ULP1_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 -#define ULP1_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 -#define ULP1_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 -#define ULP1_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 -#define ULP1_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 -#define ULP1_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 -#define ULP1_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 -#define ULP1_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 -#define ULP1_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 -#define ULP1_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 -#define ULP1_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 -#define ULP1_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 -#define ULP1_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 -#define ULP1_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 -#define ULP1_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 -#define ULP1_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 -#define ULP1_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 -#define ULP1_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 -#define ULP1_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 -#define ULP1_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 -#define ULP1_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 -#define ULP1_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 -#define ULP1_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 -#define ULP1_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 -#define ULP1_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 -#define ULP1_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 -#define ULP1_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 -#define ULP1_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 -#define ULP1_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 -#define ULP1_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 -#define ULP1_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 -#define ULP1_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 -#define ULP1_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 -#define ULP1_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 -#define ULP1_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 -#define ULP1_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 -#define ULP1_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 -#define ULP1_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 -#define ULP1_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 -#define ULP1_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 -#define ULP1_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 -#define ULP1_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 -#define ULP1_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 -#define ULP1_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 -#define ULP1_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 -#define ULP1_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 -#define ULP1_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 -#define ULP1_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 -#define ULP1_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 -#define ULP1_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 -#define ULP1_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 -#define ULP1_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 -#define ULP1_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 -#define ULP1_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 -#define ULP1_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 -#define ULP1_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 -#define ULP1_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 -#define ULP1_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 -#define ULP1_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 -#define ULP1_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 -#define ULP1_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 -#define ULP1_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 -#define ULP1_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 -#define ULP1_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 -#define ULP1_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 -#define ULP1_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 -#define ULP1_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 -#define ULP1_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 -#define ULP1_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 -#define ULP1_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 -#define ULP1_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 -#define ULP1_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 -#define ULP1_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 -#define ULP1_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 -#define ULP1_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 -#define ULP1_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 -#define ULP1_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 -#define ULP1_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 -#define ULP1_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 -#define ULP1_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 -#define ULP1_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 -#define ULP1_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 -#define ULP1_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 -#define ULP1_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 -#define ULP1_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 -#define ULP1_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 -#define ULP1_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 -#define ULP1_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 -#define ULP1_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 -#define ULP1_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 -#define ULP1_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 -#define ULP1_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 -#define ULP1_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 -#define ULP1_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 -#define ULP1_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 -#define ULP1_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0 -#define ULP1_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0 -#define ULP1_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0 -#define ULP1_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0 -#define ULP1_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 -#define ULP1_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 -#define ULP1_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 -#define ULP1_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 -#define ULP1_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 -#define ULP1_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 -#define ULP1_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 -#define ULP1_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 -#define ULP1_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 -#define ULP1_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 -#define ULP1_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 -#define ULP1_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 -#define ULP1_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 -#define ULP1_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 -#define ULP1_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 -#define ULP1_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 -#define ULP1_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 -#define ULP1_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 -#define ULP1_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 -#define ULP1_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 -#define ULP1_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 -#define ULP1_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 -#define ULP1_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 -#define ULP1_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 -#define ULP1_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 -#define ULP1_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 -#define ULP1_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 -#define ULP1_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 -#define ULP1_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 -#define ULP1_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 -#define ULP1_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 -#define ULP1_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 -#define ULP1_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 -#define ULP1_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 -#define ULP1_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 -#define ULP1_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 -#define ULP1_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 -#define ULP1_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 -#define ULP1_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 -#define ULP1_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 -#define ULP1_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 -#define ULP1_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 -#define ULP1_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 -#define ULP1_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 -#define ULP1_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 -#define ULP1_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 -#define ULP1_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 -#define ULP1_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 -#define ULP1_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 -#define ULP1_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 -#define ULP1_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 -#define ULP1_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 -#define ULP1_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 -#define ULP1_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 -#define ULP1_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 -#define ULP1_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 -#define ULP1_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 -#define ULP1_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 -#define ULP1_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 -#define ULP1_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 -#define ULP1_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 -#define ULP1_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 -#define ULP1_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 -#define ULP1_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 -#define ULP1_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 -#define ULP1_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0 -#define ULP1_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 -#define ULP1_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 -#define ULP1_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 -#define ULP1_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 -#define ULP1_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 -#define ULP1_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 -#define ULP1_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 -#define ULP1_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 -#define ULP1_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 -#define ULP1_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 -#define ULP1_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 -#define ULP1_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 -#define ULP1_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 -#define ULP1_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 -#define ULP1_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 -#define ULP1_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 -#define ULP1_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 -#define ULP1_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 -#define ULP1_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 -#define ULP1_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 -#define ULP1_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 -#define ULP1_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 -#define ULP1_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 -#define ULP1_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 -#define ULP1_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 -#define ULP1_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 -#define ULP1_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 -#define ULP1_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 -#define ULP1_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 -#define ULP1_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 -#define ULP1_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 -#define ULP1_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 -#define ULP1_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 -#define ULP1_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 -#define ULP1_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 -#define ULP1_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 -#define ULP1_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 -#define ULP1_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 -#define ULP1_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 -#define ULP1_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 -#define ULP1_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 -#define ULP1_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 -#define ULP1_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 -#define ULP1_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 -#define ULP1_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 -#define ULP1_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 -#define ULP1_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 -#define ULP1_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 -#define ULP1_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 -#define ULP1_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 -#define ULP1_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 -#define ULP1_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 -#define ULP1_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 -#define ULP1_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 -#define ULP1_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 -#define ULP1_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 -#define ULP1_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 -#define ULP1_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 -#define ULP1_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 -#define ULP1_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 -#define ULP1_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 -#define ULP1_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 -#define ULP1_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 -#define ULP1_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 -#define ULP1_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 -#define ULP1_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 -#define ULP1_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 -#define ULP1_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 -#define ULP1_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 -#define ULP1_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 -#define ULP1_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 -#define ULP1_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 -#define ULP1_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 -#define ULP1_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 -#define ULP1_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 -#define ULP1_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 -#define ULP1_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 -#define ULP1_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 -#define ULP1_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 -#define ULP1_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 -#define ULP1_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 -#define ULP1_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 -#define ULP1_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 -#define ULP1_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 -#define ULP1_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 -#define ULP1_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 -#define ULP1_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 -#define ULP1_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 -#define ULP1_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 -#define ULP1_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 -#define ULP1_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 -#define ULP1_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 -#define ULP1_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 -#define ULP1_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 -#define ULP1_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 -#define ULP1_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 -#define ULP1_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 -#define ULP1_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 -#define ULP1_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 -#define ULP1_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 -#define ULP1_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 -#define ULP1_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 -#define ULP1_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 -#define ULP1_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 -#define ULP1_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 -#define ULP1_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 -#define ULP1_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 -#define ULP1_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 -#define ULP1_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 -#define ULP1_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 -#define ULP1_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 -#define ULP1_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 -#define ULP1_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 -#define ULP1_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 -#define ULP1_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 -#define ULP1_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 -#define ULP1_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 -#define ULP1_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 -#define ULP1_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 -#define ULP1_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 -#define ULP1_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 -#define ULP1_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 -#define ULP1_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 -#define ULP1_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 -#define ULP1_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 -#define ULP1_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 -#define ULP1_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 -#define ULP1_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 -#define ULP1_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 -#define ULP1_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 -#define ULP1_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 -#define ULP1_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 -#define ULP1_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 -#define ULP1_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 -#define ULP1_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 -#define ULP1_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 -#define ULP1_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 -#define ULP1_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 -#define ULP1_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 -#define ULP1_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 -#define ULP1_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 -#define ULP1_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 -#define ULP1_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 -#define ULP1_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 -#define ULP1_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 -#define ULP1_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 -#define ULP1_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 -#define ULP1_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0 - -#endif /* __DTS_ULP1_PINFUNC_H */ +#endif /* __DTS_IMX7ULP_PINFUNC_H */ diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi index a8458f89d5f..7bcd2cc3469 100644 --- a/arch/arm/dts/imx7ulp.dtsi +++ b/arch/arm/dts/imx7ulp.dtsi @@ -16,10 +16,12 @@ interrupt-parent = <&intc>; aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; + gpio0 = &gpio4; + gpio1 = &gpio5; + gpio2 = &gpio0; + gpio3 = &gpio1; + gpio4 = &gpio2; + gpio5 = &gpio3; mmc0 = &usdhc0; mmc1 = &usdhc1; serial0 = &lpuart4; @@ -27,10 +29,12 @@ serial2 = &lpuart6; serial3 = &lpuart7; usbphy0 = &usbphy1; + usb0 = &usbotg1; i2c4 = &lpi2c4; i2c5 = &lpi2c5; i2c6 = &lpi2c6; i2c7 = &lpi2c7; + spi0 = &qspi1; }; cpus { @@ -503,6 +507,22 @@ fsl,mux_mask = <0xf00>; }; + gpio4: gpio@4103f000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x4103f000 0x1000 0x4100F000 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&iomuxc 0 0 32>; + }; + + gpio5: gpio@41040000 { + compatible = "fsl,imx7ulp-gpio"; + reg = <0x41040000 0x1000 0x4100F040 0x40>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&iomuxc 0 32 32>; + }; + gpio0: gpio@40ae0000 { compatible = "fsl,imx7ulp-gpio"; reg = <0x40ae0000 0x1000 0x400F0000 0x40>; diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 4bf7dff8b4d..1e5fa1a75eb 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -20,6 +20,14 @@ int imx6_pcie_toggle_power(void); int imx6_pcie_toggle_reset(void); +enum ldo_reg { + LDO_ARM, + LDO_SOC, + LDO_PU, +}; + +int set_ldo_voltage(enum ldo_reg ldo, u32 mv); + /** * iomuxc_set_rgmii_io_voltage - set voltage level of RGMII/USB pins * diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h index 531d8f3a950..b79bde338f4 100644 --- a/arch/arm/include/asm/arch-mx7ulp/scg.h +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -331,7 +331,6 @@ u32 decode_pll(enum pll_clocks pll); void scg_a7_rccr_init(void); void scg_a7_spll_init(void); void scg_a7_ddrclk_init(void); -void scg_a7_apll_init(void); void scg_a7_firc_init(void); void scg_a7_nicclk_init(void); void scg_a7_sys_clk_sel(enum scg_sys_src clk); diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 52c83ba9e4c..c9b509e6a79 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -153,6 +153,8 @@ void init_src(void); void init_snvs(void); void imx_wdog_disable_powerdown(void); +int arch_auxiliary_core_check_up(u32 core_id); + int board_mmc_get_env_dev(int devno); int nxp_board_rev(void); diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 181c715be33..5ce5a180e80 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -217,6 +217,7 @@ u32 get_cpu_rev(void) readl((void __iomem *)ROM_VERSION_A0); if (rom_version != CHIP_REV_1_0) { rom_version = readl((void __iomem *)ROM_VERSION_B0); + rom_version &= 0xff; if (rom_version == CHIP_REV_2_0) reg = CHIP_REV_2_0; } diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 607210520fd..ef816a24ffa 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -558,6 +558,7 @@ config TARGET_SOFTING_VINING_2000 select DM select DM_THERMAL select MX6SX + select SUPPORT_SPL imply CMD_DM config TARGET_WANDBOARD diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 926718b49c0..b8aaf3ef015 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -24,12 +24,6 @@ #include <imx_thermal.h> #include <mmc.h> -enum ldo_reg { - LDO_ARM, - LDO_SOC, - LDO_PU, -}; - struct scu_regs { u32 ctrl; u32 config; @@ -255,7 +249,7 @@ static void clear_ldo_ramp(void) * Possible values are from 0.725V to 1.450V in steps of * 0.025V (25mV). */ -static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) +int set_ldo_voltage(enum ldo_reg ldo, u32 mv) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 val, step, old, reg = readl(&anatop->reg_core); @@ -375,6 +369,37 @@ static void init_bandgap(void) } } +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) +static void noc_setup(void) +{ + enable_ipu_clock(); + + writel(0x80000201, 0xbb0608); + /* Bypass IPU1 QoS generator */ + writel(0x00000002, 0x00bb048c); + /* Bypass IPU2 QoS generator */ + writel(0x00000002, 0x00bb050c); + /* Bandwidth THR for of PRE0 */ + writel(0x00000200, 0x00bb0690); + /* Bandwidth THR for of PRE1 */ + writel(0x00000200, 0x00bb0710); + /* Bandwidth THR for of PRE2 */ + writel(0x00000200, 0x00bb0790); + /* Bandwidth THR for of PRE3 */ + writel(0x00000200, 0x00bb0810); + /* Saturation THR for of PRE0 */ + writel(0x00000010, 0x00bb0694); + /* Saturation THR for of PRE1 */ + writel(0x00000010, 0x00bb0714); + /* Saturation THR for of PRE2 */ + writel(0x00000010, 0x00bb0794); + /* Saturation THR for of PRE */ + writel(0x00000010, 0x00bb0814); + + disable_ipu_clock(); +} +#endif + int arch_cpu_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -452,6 +477,10 @@ int arch_cpu_init(void) init_src(); +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) + if (is_mx6dqp()) + noc_setup(); +#endif return 0; } diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index ed5f0aeb2d5..138c58363f5 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -3,6 +3,11 @@ if ARCH_MX7ULP config SYS_SOC default "mx7ulp" +config LDO_ENABLED_MODE + bool "i.MX7ULP LDO Enabled Mode" + help + Select this option to enable the PMC1 LDO. + config MX7ULP bool diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 819c90af6ce..c7bb7a1c667 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -949,67 +949,6 @@ void scg_a7_ddrclk_init(void) /* Clock source is System OSC <<0 */ #define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT) -/* - * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz, - * system PLL is sourced from APLL, - * APLL clock source is system OSC (24MHz) - */ -#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \ - SCG1_APLL_CFG_POSTDIV1_NUM | \ - (22 << SCG_PLL_CFG_MULT_SHIFT) | \ - SCG1_APLL_CFG_PFDSEL_NUM | \ - SCG1_APLL_CFG_PREDIV_NUM | \ - SCG1_APLL_CFG_BYPASS_NUM | \ - SCG1_APLL_CFG_PLLSEL_NUM | \ - SCG1_APLL_CFG_CLKSRC_NUM) - -/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */ -#define SCG1_APLL_PFD0_FRAC_NUM (27) - - -void scg_a7_apll_init(void) -{ - u32 val = 0; - - /* Disable A7 Auxiliary PLL */ - val = readl(&scg1_regs->apllcsr); - val &= ~SCG_APLL_CSR_APLLEN_MASK; - writel(val, &scg1_regs->apllcsr); - - /* Gate off A7 APLL PFD0 ~ PDF4 */ - val = readl(&scg1_regs->apllpfd); - val |= 0x80808080; - writel(val, &scg1_regs->apllpfd); - - /* ================ A7 APLL Configuration Start ============== */ - /* Configure A7 Auxiliary PLL */ - writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg); - - /* Enable A7 Auxiliary PLL */ - val = readl(&scg1_regs->apllcsr); - val |= SCG_APLL_CSR_APLLEN_MASK; - writel(val, &scg1_regs->apllcsr); - - /* Wait for A7 APLL clock ready */ - while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK)) - ; - - /* Configure A7 APLL PFD0 */ - val = readl(&scg1_regs->apllpfd); - val &= ~SCG_PLL_PFD0_FRAC_MASK; - val |= SCG1_APLL_PFD0_FRAC_NUM; - writel(val, &scg1_regs->apllpfd); - - /* Un-gate A7 APLL PFD0 */ - val = readl(&scg1_regs->apllpfd); - val &= ~SCG_PLL_PFD0_GATE_MASK; - writel(val, &scg1_regs->apllpfd); - - /* Wait for A7 APLL PFD0 clock being valid */ - while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK)) - ; -} - /* SCG1(A7) FIRC DIV configurations */ /* Disable FIRC DIV3 */ #define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT) diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 4b6014e7241..8345b01398b 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -10,6 +10,22 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/hab.h> +#define PMC0_BASE_ADDR 0x410a1000 +#define PMC0_CTRL 0x28 +#define PMC0_CTRL_LDOEN BIT(31) +#define PMC0_CTRL_LDOOKDIS BIT(30) +#define PMC0_CTRL_PMC1ON BIT(24) +#define PMC1_BASE_ADDR 0x40400000 +#define PMC1_RUN 0x8 +#define PMC1_STOP 0x10 +#define PMC1_VLPS 0x14 +#define PMC1_LDOVL_SHIFT 16 +#define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT) +#define PMC1_LDOVL_900 0x1e +#define PMC1_LDOVL_950 0x23 +#define PMC1_STATUS 0x20 +#define PMC1_STATUS_LDOVLF BIT(8) + static char *get_reset_cause(char *); #if defined(CONFIG_IMX_HAB) @@ -101,6 +117,44 @@ void init_wdog(void) disable_wdog(WDG2_RBASE); } +#if defined(CONFIG_LDO_ENABLED_MODE) +static void init_ldo_mode(void) +{ + unsigned int reg; + + /* Set LDOOKDIS */ + setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS); + + /* Set LDOVL to 0.95V in PMC1_RUN */ + reg = readl(PMC1_BASE_ADDR + PMC1_RUN); + reg &= ~PMC1_LDOVL_MASK; + reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT); + writel(PMC1_BASE_ADDR + PMC1_RUN, reg); + + /* Wait for LDOVLF to be cleared */ + reg = readl(PMC1_BASE_ADDR + PMC1_STATUS); + while (reg & PMC1_STATUS_LDOVLF) + ; + + /* Set LDOVL to 0.95V in PMC1_STOP */ + reg = readl(PMC1_BASE_ADDR + PMC1_STOP); + reg &= ~PMC1_LDOVL_MASK; + reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT); + writel(PMC1_BASE_ADDR + PMC1_STOP, reg); + + /* Set LDOVL to 0.90V in PMC1_VLPS */ + reg = readl(PMC1_BASE_ADDR + PMC1_VLPS); + reg &= ~PMC1_LDOVL_MASK; + reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT); + writel(PMC1_BASE_ADDR + PMC1_VLPS, reg); + + /* Set LDOEN bit */ + setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN); + + /* Set the PMC1ON bit */ + setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON); +} +#endif void s_init(void) { @@ -114,6 +168,10 @@ void s_init(void) /* enable dumb pmic */ writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR); } + +#if defined(CONFIG_LDO_ENABLED_MODE) + init_ldo_mode(); +#endif return; } @@ -132,6 +190,21 @@ const char *get_imx_type(u32 imxtype) return "7ULP"; } +#define PMC0_BASE_ADDR 0x410a1000 +#define PMC0_CTRL 0x28 +#define PMC0_CTRL_LDOEN BIT(31) + +static bool ldo_mode_is_enabled(void) +{ + unsigned int reg; + + reg = readl(PMC0_BASE_ADDR + PMC0_CTRL); + if (reg & PMC0_CTRL_LDOEN) + return true; + else + return false; +} + int print_cpuinfo(void) { u32 cpurev; @@ -160,6 +233,11 @@ int print_cpuinfo(void) break; } + if (ldo_mode_is_enabled()) + printf("PMC1: LDO enabled mode\n"); + else + printf("PMC1: LDO bypass mode\n"); + return 0; } #endif diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index 78692e92408..ef914b13a1a 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -72,42 +72,23 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) | - MUX_MODE_SION, - /* LAN8720 PHY Reset */ - MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static iomux_v3_cfg_t const pwm_led_pads[] = { MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */ MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */ MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */ }; -#define PHY_RESET IMX_GPIO_NR(5, 9) - -int board_eth_init(bd_t *bis) +static int board_net_init(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret; unsigned char eth1addr[6]; + int ret; - /* just to get secound mac address */ + /* just to get second mac address */ imx_get_mac_from_fuse(1, eth1addr); if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) eth_env_set_enetaddr("eth1addr", eth1addr); - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - /* * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by @@ -123,15 +104,7 @@ int board_eth_init(bd_t *bis) if (ret) goto eth_fail; - /* reset phy */ - gpio_request(PHY_RESET, "PHY-reset"); - gpio_direction_output(PHY_RESET, 0); - mdelay(16); - gpio_set_value(PHY_RESET, 1); - mdelay(1); - - ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR, - IMX_FEC_BASE); + ret = enable_fec_anatop_clock(1, ENET_50MHZ); if (ret) goto eth_fail; @@ -139,7 +112,6 @@ int board_eth_init(bd_t *bis) eth_fail: printf("FEC MXC: %s:failed (%i)\n", __func__, ret); - gpio_set_value(PHY_RESET, 0); return ret; } @@ -254,6 +226,9 @@ int power_init_board(void) if (ret < 0) return ret; + set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */ + set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ + return 0; } @@ -424,7 +399,7 @@ int board_init(void) setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif - return 0; + return board_net_init(); } int checkboard(void) @@ -433,3 +408,218 @@ int checkboard(void) return 0; } + +#define PCIE_PHY_PUP_REQ BIT(7) + +void board_preboot_os(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; + + /* Bring the PCI power domain up, so that old vendorkernel works. */ + setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); + setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); +} + +#ifdef CONFIG_SPL_BUILD +#include <linux/libfdt.h> +#include <spl.h> +#include <asm/arch/mx6-ddr.h> + +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR }; + +static iomux_v3_cfg_t const pcie_pads[] = { + MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static void vining2000_spl_setup_iomux_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); +} + +static void vining2000_spl_setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); +} + +int board_mmc_init(bd_t *bis) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000028, + .dram_cas = 0x00000028, + .dram_odt0 = 0x00000028, + .dram_odt1 = 0x00000028, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000028, +}; + +const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000028, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, + .grp_ctlds = 0x00000028, + .grp_ddr_type = 0x000c0000, + .grp_ddrmode = 0x00020000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x0022001C, + .p0_mpwldectrl1 = 0x001F001A, + .p0_mpdgctrl0 = 0x01380134, + .p0_mpdgctrl1 = 0x0124011C, + .p0_mprddlctl = 0x42404444, + .p0_mpwrdlctl = 0x36383C38, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1391, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */ + writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */ + writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */ + writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */ + writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */ + writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */ + writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */ +} + +static void vining2000_spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + .dsize = mem_ddr.width / 32, + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, /* RTT_wr = RZQ/4 */ + .rtt_nom = 1, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + + mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); + + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_write_level_calibration(&sysinfo); + mmdc_do_dqs_calibration(&sysinfo); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux setup */ + vining2000_spl_setup_iomux_pcie(); + vining2000_spl_setup_iomux_uart(); + + /* setup GP timer */ + timer_init(); + + /* reset the PCIe device */ + gpio_set_value(IMX_GPIO_NR(4, 6), 1); + udelay(50); + gpio_set_value(IMX_GPIO_NR(4, 6), 0); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + vining2000_spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/solidrun/mx6cuboxi/MAINTAINERS b/board/solidrun/mx6cuboxi/MAINTAINERS index 81f82bc9b5e..bd098b479f2 100644 --- a/board/solidrun/mx6cuboxi/MAINTAINERS +++ b/board/solidrun/mx6cuboxi/MAINTAINERS @@ -1,4 +1,5 @@ MX6CUBOXI BOARD +M: Baruch Siach <baruch@tkos.co.il> M: Fabio Estevam <fabio.estevam@nxp.com> S: Maintained F: board/solidrun/mx6cuboxi/ diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index c001316591a..b0914a9ead5 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -333,6 +333,43 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, bd_t *bd) { +#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY) + int up; + + up = arch_auxiliary_core_check_up(0); + if (up) { + int ret; + int areas = 1; + u64 start[2], size[2]; + + /* + * Reserve 1MB of memory for M4 (1MiB is also the minimum + * alignment for Linux due to MMU section size restrictions). + */ + start[0] = gd->bd->bi_dram[0].start; + size[0] = SZ_256M - SZ_1M; + + /* If needed, create a second entry for memory beyond 256M */ + if (gd->bd->bi_dram[0].size > SZ_256M) { + start[1] = gd->bd->bi_dram[0].start + SZ_256M; + size[1] = gd->bd->bi_dram[0].size - SZ_256M; + areas = 2; + } + + ret = fdt_set_usable_memory(blob, start, size, areas); + if (ret) { + eprintf("Cannot set usable memory\n"); + return ret; + } + } else { + int off; + + off = fdt_node_offset_by_compatible(blob, -1, + "fsl,imx7d-rpmsg"); + if (off > 0) + fdt_status_disabled(blob, off); + } +#endif #if defined(CONFIG_FDT_FIXUP_PARTITIONS) static const struct node_info nodes[] = { { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ diff --git a/common/fdt_support.c b/common/fdt_support.c index 68343990395..02cf5c6241b 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -467,6 +467,41 @@ int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) } return 0; } + +int fdt_set_usable_memory(void *blob, u64 start[], u64 size[], int areas) +{ + int err, nodeoffset; + int len; + u8 tmp[8 * 16]; /* Up to 64-bit address + 64-bit size */ + + if (areas > 8) { + printf("%s: num areas %d exceeds hardcoded limit %d\n", + __func__, areas, 8); + return -1; + } + + err = fdt_check_header(blob); + if (err < 0) { + printf("%s: %s\n", __func__, fdt_strerror(err)); + return err; + } + + /* find or create "/memory" node. */ + nodeoffset = fdt_find_or_add_subnode(blob, 0, "memory"); + if (nodeoffset < 0) + return nodeoffset; + + len = fdt_pack_reg(blob, tmp, start, size, areas); + + err = fdt_setprop(blob, nodeoffset, "linux,usable-memory", tmp, len); + if (err < 0) { + printf("WARNING: could not set %s %s.\n", + "reg", fdt_strerror(err)); + return err; + } + + return 0; +} #endif int fdt_fixup_memory(void *blob, u64 start, u64 size) diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 1ff5acb7305..c1542fe5d36 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -1,18 +1,32 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_MX6_DDRCAL=y CONFIG_TARGET_SOFTING_VINING_2000=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg" CONFIG_BOOTDELAY=0 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y @@ -46,13 +60,15 @@ CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_PWM_IMX=y -CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index eb58077e5d9..d31ca28fffd 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_WARP7=y CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x80000 +CONFIG_ENV_OFFSET=0xC0000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 091b092bbb3..a05dac7c7a1 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -74,7 +74,7 @@ static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; -static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", +static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", }; static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index cb39bcdebf5..81ac4b52f3b 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -196,4 +196,9 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define FEC_QUIRK_ENET_MAC +/* Misc configuration */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + #endif /* __IMX8QXP_MEK_H */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 54c8c2f62ef..0c0baf27385 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -58,8 +58,6 @@ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ -#define CONFIG_FEC_MXC - #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x0 @@ -91,4 +89,8 @@ #define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */ #endif +#ifdef CONFIG_SPL_BUILD +#define CONFIG_MXC_UART_BASE UART1_BASE +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 9a82581c5f3..da894ec0ca0 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -125,6 +125,19 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +/* + * Environment starts at CONFIG_ENV_OFFSET= 0xC0000 = 768k = 768*1024 = 786432 + * + * Detect overlap between U-Boot image and environment area in build-time + * + * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset + * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 + * + * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so + * write the direct value here + */ +#define CONFIG_BOARD_SIZE_LIMIT 785408 + /* I2C configs */ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/fdt_support.h b/include/fdt_support.h index cefb2b2cce2..2286ea77939 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -94,6 +94,7 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size); */ #ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks); +int fdt_set_usable_memory(void *blob, u64 start[], u64 size[], int banks); #else static inline int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) |