diff options
author | Johan Jonker <jbx6244@gmail.com> | 2022-04-15 23:21:39 +0200 |
---|---|---|
committer | Kever Yang <kever.yang@rock-chips.com> | 2022-04-18 11:25:13 +0800 |
commit | 52a0c68994596544bfdbb3f8d0a034a5d2b13c1e (patch) | |
tree | 8ff7656efd7a36eeabe4df3074e5f9f96c046890 /arch/arm/dts/rk3288-u-boot.dtsi | |
parent | 334d519a13e4636dd454738510fc840467109b0e (diff) | |
download | u-boot-52a0c68994596544bfdbb3f8d0a034a5d2b13c1e.tar.gz |
arm: dts: rockchip: move all rk3288 u-boot specific properties in separate dtsi files
In order to sync rk3288.dtsi from Linux it needed to
move all u-boot specific properties in separate dtsi files.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/dts/rk3288-u-boot.dtsi')
-rw-r--r-- | arch/arm/dts/rk3288-u-boot.dtsi | 80 |
1 files changed, 69 insertions, 11 deletions
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index e3c6c10f130..9eb696b1411 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -7,10 +7,53 @@ #include "rockchip-optee.dtsi" / { + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + gpio8 = &gpio8; + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio0; + mmc3 = &sdio1; + }; + chosen { u-boot,spl-boot-order = \ "same-as-spl", &emmc, &sdmmc; }; + + dmc: dmc@ff610000 { + compatible = "rockchip,rk3288-dmc", "syscon"; + reg = <0xff610000 0x3fc + 0xff620000 0x294 + 0xff630000 0x3fc + 0xff640000 0x294>; + clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, + <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, + <&cru ARMCLK>; + clock-names = "pclk_ddrupctl0", "pclk_publ0", + "pclk_ddrupctl1", "pclk_publ1", + "arm_clk"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,noc = <&noc>; + rockchip,pmu = <&pmu>; + rockchip,sgrf = <&sgrf>; + rockchip,sram = <&ddr_sram>; + u-boot,dm-pre-reloc; + }; + + noc: syscon@ffac0000 { + compatible = "rockchip,rk3288-noc", "syscon"; + reg = <0xffac0000 0x2000>; + u-boot,dm-pre-reloc; + }; }; #ifdef CONFIG_ROCKCHIP_SPI_IMAGE @@ -37,38 +80,53 @@ }; #endif -&dmc { - u-boot,dm-pre-reloc; +&bus_intmem { + ddr_sram: ddr-sram@1000 { + compatible = "rockchip,rk3288-ddr-sram"; + reg = <0x1000 0x4000>; + }; }; -&pmu { +&cru { u-boot,dm-pre-reloc; }; -&sgrf { +&gpio7 { u-boot,dm-pre-reloc; }; -&cru { +&grf { u-boot,dm-pre-reloc; }; -&grf { +&pmu { u-boot,dm-pre-reloc; }; -&vopb { +&sgrf { u-boot,dm-pre-reloc; }; -&vopl { - u-boot,dm-pre-reloc; +&uart0 { + clock-frequency = <24000000>; +}; + +&uart1 { + clock-frequency = <24000000>; }; -&noc { +&uart2 { + clock-frequency = <24000000>; +}; + +&uart3 { + clock-frequency = <24000000>; +}; + +&vopb { u-boot,dm-pre-reloc; }; -&gpio7 { +&vopl { u-boot,dm-pre-reloc; }; |