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authorMichal Simek <michal.simek@xilinx.com>2022-05-11 11:52:54 +0200
committerMichal Simek <michal.simek@amd.com>2022-05-18 13:17:54 +0200
commit11ed38f5dc12afb581e0fdb2e617c6e25fa81af8 (patch)
tree0e5f6af5e346738fe09dcdeba20f44e57efbfac3 /arch/arm/dts/zynqmp-zcu102-revA.dts
parentd5b9b22f7b070a422b630421fdcefade5bf577a5 (diff)
downloadu-boot-11ed38f5dc12afb581e0fdb2e617c6e25fa81af8.tar.gz
arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106
Origin DT binding just specify driver but wasn't aligned with DT binding which came later. Extend description for zcu102 and zcu106 to cover latest binding. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/db66a4bb501183ffbd033da4dd263afdb214f8ec.1652262769.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm/dts/zynqmp-zcu102-revA.dts')
-rw-r--r--arch/arm/dts/zynqmp-zcu102-revA.dts21
1 files changed, 20 insertions, 1 deletions
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index aac798d6e74..c13b52a6aea 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -604,7 +604,26 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- /* SI5328 - u20 */
+ si5328: clock-generator@69 {/* SI5328 - u20 */
+ compatible = "silabs,si5328";
+ reg = <0x69>;
+ /*
+ * Chip has interrupt present connected to PL
+ * interrupt-parent = <&>;
+ * interrupts = <>;
+ */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ clocks = <&refhdmi>;
+ clock-names = "xtal";
+ clock-output-names = "si5328";
+
+ si5328_clk: clk0@0 {
+ reg = <0>;
+ clock-frequency = <27000000>;
+ };
+ };
};
/* 5 - 7 unconnected */
};