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| author | Tom Rini <trini@konsulko.com> | 2021-03-15 12:15:38 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-03-15 12:15:38 -0400 |
| commit | 22fc991dafee0142fc6bf621e7bd558bd58020b4 (patch) | |
| tree | e5da8826fd735de968519f432864dc1545d96017 /arch/arm/mach-omap2 | |
| parent | 1876b390f31afca15de334e499aa071b0bf64a44 (diff) | |
| parent | 4103e13534141c31e4e9bf40848ab3a61dabce81 (diff) | |
| download | u-boot-22fc991dafee0142fc6bf621e7bd558bd58020b4.tar.gz | |
Merge tag 'v2021.04-rc4' into next
Prepare v2021.04-rc4
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/omap3/board.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap3/lowlevel_init.S | 6 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index 4da8df47cc6..029bd545957 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -179,6 +179,8 @@ void early_system_init(void) hw_data_init(); } +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) /****************************************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. @@ -207,6 +209,7 @@ void s_init(void) ehci_clocks_enable(); #endif } +#endif #ifdef CONFIG_SPL_BUILD void board_init_f(ulong dummy) diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S index 2a05b5e5212..4fa89418a11 100644 --- a/arch/arm/mach-omap2/omap3/lowlevel_init.S +++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S @@ -45,7 +45,7 @@ ENDPROC(do_omap3_emu_romcode_call) ENTRY(cpy_clk_code) /* Copy DPLL code into SRAM */ adr r0, go_to_speed /* copy from start of go_to_speed... */ - adr r2, lowlevel_init /* ... up to start of low_level_init */ + adr r2, go_to_speed_end /* ... up to start of go_to_speed_end */ next2: ldmia r0!, {r3 - r10} /* copy from source address [r0] */ stmia r1!, {r3 - r10} /* copy to target address [r1] */ @@ -167,8 +167,11 @@ pll_div_add5: pll_div_val5: .word CLSEL1_EMU_VAL +go_to_speed_end: #endif +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ + !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) ENTRY(lowlevel_init) ldr sp, SRAM_STACK str ip, [sp] /* stash ip register */ @@ -187,6 +190,7 @@ ENTRY(lowlevel_init) b s_init ENDPROC(lowlevel_init) +#endif /* the literal pools origin */ .ltorg |