diff options
| author | Tom Rini <trini@konsulko.com> | 2024-10-29 12:12:09 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-10-29 16:17:47 -0600 |
| commit | e28e70e392306626b750bedb4225bee24db40466 (patch) | |
| tree | 0e748d6db5297ff0a02f3da9fd0b4a74b9535efb /arch/arm | |
| parent | 2d42f7d9018a9c7bf7e65780d6505280a46c0cda (diff) | |
| parent | 4d5510774d4905f1966388098cf918ca27118197 (diff) | |
| download | u-boot-e28e70e392306626b750bedb4225bee24db40466.tar.gz | |
Merge patch series "Support Aspeed SGPIO controller"
Billy Tsai <billy_tsai@aspeedtech.com> says:
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
Link: https://lore.kernel.org/r/20241016085955.314236-1-billy_tsai@aspeedtech.com
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/ast2500-evb.dts | 5 | ||||
| -rw-r--r-- | arch/arm/dts/ast2500.dtsi | 20 | ||||
| -rw-r--r-- | arch/arm/dts/ast2600-evb.dts | 10 | ||||
| -rw-r--r-- | arch/arm/dts/ast2600.dtsi | 40 |
4 files changed, 75 insertions, 0 deletions
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index d481eadfeb0..9a5037deca2 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -129,3 +129,8 @@ reg = <0x4d>; }; }; + +&sgpio { + status = "okay"; + ngpios = <80>; +}; diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index 320d2e5340a..d677705fe85 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -255,6 +255,21 @@ interrupt-controller; }; + sgpio: sgpio@1e780200 { + compatible = "aspeed,ast2500-sgpio"; + reg = <0x1e780200 0x100>; + interrupts = <40>; + clocks = <&scu ASPEED_CLK_APB>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + bus-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm_default>; + status = "disabled"; + }; + timer: timer@1e782000 { /* This timer is a Faraday FTTMR010 derivative */ compatible = "aspeed,ast2400-timer"; @@ -1445,4 +1460,9 @@ function = "WDTRST2"; groups = "WDTRST2"; }; + + pinctrl_sgpm_default: sgpm_default { + function = "SGPM"; + groups = "SGPM"; + }; }; diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index 9aac0e26f28..570ba61965a 100644 --- a/arch/arm/dts/ast2600-evb.dts +++ b/arch/arm/dts/ast2600-evb.dts @@ -266,3 +266,13 @@ bootph-all; status = "okay"; }; + +&sgpiom0 { + status = "okay"; + ngpios = <128>; +}; + +&sgpiom1 { + status = "okay"; + ngpios = <80>; +}; diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index 43db80edfe5..cb8ce8b6b6f 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -501,6 +501,36 @@ ngpios = <208>; }; + sgpiom0: sgpiom@1e780500 { + compatible = "aspeed,ast2600-sgpiom"; + reg = <0x1e780500 0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scu ASPEED_CLK_APB2>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + bus-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm1_default>; + status = "disabled"; + }; + + sgpiom1: sgpiom@1e780600 { + compatible = "aspeed,ast2600-sgpiom"; + reg = <0x1e780600 0x100>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scu ASPEED_CLK_APB2>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + bus-frequency = <12000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm2_default>; + status = "disabled"; + }; + gpio1: gpio@1e780800 { compatible = "aspeed,ast2600-gpio"; reg = <0x1e780800 0x800>; @@ -2167,4 +2197,14 @@ function = "PCIE1RC"; groups = "PCIE1RC"; }; + + pinctrl_sgpm1_default: sgpm1_default { + function = "SGPM1"; + groups = "SGPM1"; + }; + + pinctrl_sgpm2_default: sgpm2_default { + function = "SGPM2"; + groups = "SGPM2"; + }; }; |