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| author | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2024-10-11 17:31:48 +0200 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2024-10-16 20:18:56 +0200 |
| commit | 5cb33c70b2c57248eb552e57fba8af305fa3b2c8 (patch) | |
| tree | d4e7e9c12ad258ba0952532f702595a8674da7fb /arch/arm | |
| parent | 5fccc2891e280ea1f1beff1821d5c9762591bde2 (diff) | |
| download | u-boot-5cb33c70b2c57248eb552e57fba8af305fa3b2c8.tar.gz | |
stm32mp: compute ram_top based on the optee base address only for STM32MP1
Reserved memory for OP-TEE is located at end of DDR for STM32MP1 SoC only
(STM32MP13 and STM32MP15) and the OP-TEE reserved memory is located at the
beginning of DDR for STM32MP25 SoC, before CONFIG_TEXT_BASE and
with reserved memory for companion coprocessor. So the ram_top is limited
by OP-TEE reserved memory only for STM32MP1 SoC.
This patch solves an issue for ram_top value on STM32MP25 SoC because the
generic reserved memory management, based on LMB, is no more used before
relocation.
Fixes: 8242f14a3e6f ("stm32mp: compute ram_top based on the optee base address")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-stm32mp/dram_init.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 3698fc49bf1..a2ad6d1aaac 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -62,7 +62,6 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { - int ret; phys_size_t size; phys_addr_t reg; u32 optee_start, optee_size; @@ -75,10 +74,17 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) * if the effective available memory is bigger */ gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); + + /* add 8M for U-Boot reserved memory: display, fdt, gd,... */ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); - ret = optee_get_reserved_memory(&optee_start, &optee_size); - reg = (!ret ? optee_start : gd->ram_top) - size; + reg = gd->ram_top - size; + + /* Reserved memory for OP-TEE at END of DDR for STM32MP1 SoC */ + if (IS_ENABLED(CONFIG_STM32MP13X) || IS_ENABLED(CONFIG_STM32MP15X)) { + if (!optee_get_reserved_memory(&optee_start, &optee_size)) + reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); + } /* before relocation, mark the U-Boot memory as cacheable by default */ if (!(gd->flags & GD_FLG_RELOC)) |