diff options
| author | Simon Glass <sjg@chromium.org> | 2020-05-10 11:40:13 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-18 21:19:23 -0400 |
| commit | cd93d625fd751d55c729c78b10f82109d56a5f1d (patch) | |
| tree | 158fd30f3d06142f6a99cbae6ed8ccb0f3be567b /arch/mips/mach-mscc | |
| parent | f09f1ecbe77863ecefe586ccd6000064b49105a3 (diff) | |
| download | u-boot-cd93d625fd751d55c729c78b10f82109d56a5f1d.tar.gz | |
common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/mips/mach-mscc')
19 files changed, 22 insertions, 0 deletions
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 8273a0f5aa8..b4ffd44ea44 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -5,6 +5,7 @@ #include <common.h> #include <init.h> +#include <linux/bitops.h> #include <asm/io.h> #include <asm/types.h> diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c index 5e3a53372d9..d6b4c5d7684 100644 --- a/arch/mips/mach-mscc/gpio.c +++ b/arch/mips/mach-mscc/gpio.c @@ -5,6 +5,7 @@ #include <common.h> #include <asm/io.h> +#include <linux/bitops.h> void mscc_gpio_set_alternate(int gpio, int mode) { diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index bf75e52ec3c..d52eabbd2b1 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -9,6 +9,7 @@ #include <asm/cacheops.h> #include <asm/io.h> #include <asm/reboot.h> +#include <linux/bitops.h> #include <mach/common.h> #define MIPS_VCOREIII_MEMORY_DDR3 diff --git a/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h index 4a1228d29f3..8d1d21b9b10 100644 --- a/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h @@ -6,6 +6,8 @@ #ifndef _MSCC_JR2_DEVCPU_GCB_H_ #define _MSCC_JR2_DEVCPU_GCB_H_ +#include <linux/bitops.h> + #define PERF_GPR 0x4 #define PERF_SOFT_RST 0x8 diff --git a/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h index 3c84edc18ab..e11ad8788fb 100644 --- a/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h @@ -6,6 +6,8 @@ #ifndef _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_ #define _MSCC_JR2_DEVCPU_GCB_MIIM_REGS_H_ +#include <linux/bitops.h> + #define MIIM_MII_STATUS(gi) (0xc8 + (gi * 36)) #define MIIM_MII_CMD(gi) (0xd0 + (gi * 36)) #define MIIM_MII_DATA(gi) (0xd4 + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h index 6e0bbe2746a..151bb3e6d48 100644 --- a/arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h @@ -6,6 +6,8 @@ #ifndef _MSCC_JR2_ICPU_CFG_H_ #define _MSCC_JR2_ICPU_CFG_H_ +#include <linux/bitops.h> + #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x4 diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h index a74a68593d2..750a8013d16 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_DEVCPU_GCB_H_ #define _MSCC_OCELOT_DEVCPU_GCB_H_ +#include <linux/bitops.h> #define PERF_SOFT_RST 0x90 #define PERF_SOFT_RST_SOFT_SWC_RST BIT(1) diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h index 2303734894c..07c4f9aeb61 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb_miim_regs.h @@ -8,6 +8,7 @@ #ifndef _MSCC_LUTON_MIIM_REGS_H_ #define _MSCC_LUTON_MIIM_REGS_H_ +#include <linux/bitops.h> #define MIIM_MII_STATUS(gi) (0xa0 + (gi * 36)) #define MIIM_MII_CMD(gi) (0xa8 + (gi * 36)) #define MIIM_MII_DATA(gi) (0xac + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h index 9233f037bb8..ded7c5fa77a 100644 --- a/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_ICPU_CFG_H_ #define _MSCC_OCELOT_ICPU_CFG_H_ +#include <linux/bitops.h> #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x4 diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h index b2a4203644a..5715ec164c8 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_DEVCPU_GCB_H_ #define _MSCC_OCELOT_DEVCPU_GCB_H_ +#include <linux/bitops.h> #define PERF_SOFT_RST 0x8 #define PERF_SOFT_RST_SOFT_NON_CFG_RST BIT(2) diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h index 4ad92214a3b..50cf073eab6 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb_miim_regs.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ #define _MSCC_OCELOT_DEVCPU_GCB_MIIM_REGS_H_ +#include <linux/bitops.h> #define MIIM_MII_STATUS(gi) (0x9c + (gi * 36)) #define MIIM_MII_CMD(gi) (0xa4 + (gi * 36)) #define MIIM_MII_DATA(gi) (0xa8 + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h index 04cf70bec34..fb10bf2c26e 100644 --- a/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h @@ -6,6 +6,7 @@ #ifndef _MSCC_OCELOT_ICPU_CFG_H_ #define _MSCC_OCELOT_ICPU_CFG_H_ +#include <linux/bitops.h> #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x4 diff --git a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h index 9b80fdb574b..43d40be7165 100644 --- a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVAL_DEVCPU_GCB_H_ #define _MSCC_SERVAL_DEVCPU_GCB_H_ +#include <linux/bitops.h> #define CHIP_ID 0x0 #define PERF_GPR 0x4 diff --git a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h index a3abbc40156..e8cb1dcf9a0 100644 --- a/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/serval/serval_devcpu_gcb_miim_regs.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_ #define _MSCC_SERVAL_DEVCPU_GCB_MIIM_REGS_H_ +#include <linux/bitops.h> #define MIIM_MII_STATUS(gi) (0x5c + (gi * 36)) #define MIIM_MII_CMD(gi) (0x64 + (gi * 36)) #define MIIM_MII_DATA(gi) (0x68 + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h index b8c9d5ca49e..4d4151b3d55 100644 --- a/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/serval/serval_icpu_cfg.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVAL_ICPU_CFG_H_ #define _MSCC_SERVAL_ICPU_CFG_H_ +#include <linux/bitops.h> #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x8 diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h index 493eaad1df7..7d6c64f316b 100644 --- a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h +++ b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVALT_DEVCPU_GCB_H_ #define _MSCC_SERVALT_DEVCPU_GCB_H_ +#include <linux/bitops.h> #define PERF_GPR 0x4 #define PERF_SOFT_RST 0x8 diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h index 8c67190ecb4..72d7c4d08de 100644 --- a/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h +++ b/arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_ #define _MSCC_SERVALT_DEVCPU_GCB_MIIM_REGS_H_ +#include <linux/bitops.h> #define MIIM_MII_STATUS(gi) (0xc4 + (gi * 36)) #define MIIM_MII_CMD(gi) (0xcc + (gi * 36)) #define MIIM_MII_DATA(gi) (0xd0 + (gi * 36)) diff --git a/arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h b/arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h index 491ead169fe..13967f66b06 100644 --- a/arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h +++ b/arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h @@ -6,6 +6,7 @@ #ifndef _MSCC_SERVALT_ICPU_CFG_H_ #define _MSCC_SERVALT_ICPU_CFG_H_ +#include <linux/bitops.h> #define ICPU_GPR(x) (0x4 * (x)) #define ICPU_GPR_RSZ 0x8 diff --git a/arch/mips/mach-mscc/include/mach/tlb.h b/arch/mips/mach-mscc/include/mach/tlb.h index fdb554f5518..ebd8ad0dc1a 100644 --- a/arch/mips/mach-mscc/include/mach/tlb.h +++ b/arch/mips/mach-mscc/include/mach/tlb.h @@ -7,6 +7,7 @@ #define __ASM_MACH_TLB_H #include <asm/mipsregs.h> +#include <linux/bitops.h> #include <mach/common.h> #include <linux/sizes.h> |