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| author | Zong Li <zong.li@sifive.com> | 2021-06-30 23:23:50 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-07-06 20:24:26 +0800 |
| commit | 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829 (patch) | |
| tree | 62d2ac2c805629f26ab5f0709d7d4775020587ea /configs/sifive_unmatched_defconfig | |
| parent | ffe9a394df0cf4ec14331ce425938409289e5780 (diff) | |
| download | u-boot-4b4159d0f31ca3e0174ccfdce9a24a1fe3671829.tar.gz | |
board: sifive: support spl multi-dtb on unmatched board
There are two revisions of unmatched board with different DDR timing,
we'd like to support multi-dtb mechanism in SPL, then it selects the
right DTB at runtime according to PCB revision in I2C EEPROM.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'configs/sifive_unmatched_defconfig')
| -rw-r--r-- | configs/sifive_unmatched_defconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 44edfd29743..3a456702803 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -41,3 +41,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_SPL_OF_LIST="hifive-unmatched-a00 hifive-unmatched-a00-rev1" +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 |