Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2020.10

Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default

ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform

Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board

mmc:
- minor GD pointer removal

net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver

spi:
- Cleanup global macros for xilinx spi drivers

firmware:
- Add support for pmufw reloading

fpga:
- Improve error status reporting

common:
- Remove 4kB addition space for FDT allocation

1 files changed, 3 insertions, 4 deletions

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 13f7275d170..f922fecd6b5 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev)
 		 * Fixup for the AR8035 which only has two bits. The two
 		 * remaining bits map to the same frequencies.
 		 */
-		if (phydev->drv->uid == AR8035_PHY_ID) {
-			u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
 
-			priv->clk_25m_mask &= ~clear;
-			priv->clk_25m_reg &= ~clear;
+		if (phydev->drv->uid == AR8035_PHY_ID) {
+			priv->clk_25m_reg &= AR8035_CLK_25M_MASK;
+			priv->clk_25m_mask &= AR8035_CLK_25M_MASK;
 		}
 	}