diff options
| author | T Karthik Reddy <t.karthik.reddy@xilinx.com> | 2022-05-12 04:05:34 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-06-29 16:00:31 +0200 |
| commit | 248fe9f302df5f20d75a7d88b793db017262d750 (patch) | |
| tree | 642dc7f671ce7af7deca3a61857a43c5c60e38f5 /drivers/spi/cadence_qspi_apb.c | |
| parent | bf8dae5fcf400a593d56d5847d8ee62bc4c27855 (diff) | |
| download | u-boot-248fe9f302df5f20d75a7d88b793db017262d750.tar.gz | |
spi: cadence_qspi: Enable apb linear mode for apb read & write operations
On versal platform, enable apb linear mode for apb read and write
execute operations amd disable it when using dma reads. This is done by
xilinx_pm_request() secure calls when CONFIG_ZYNQMP_FIRMWARE is enabled,
else we use direct raw reads and writes in case of mini U-Boot.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-5-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers/spi/cadence_qspi_apb.c')
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index b11bd2d2c61..c00755050e1 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -38,6 +38,11 @@ #include <malloc.h> #include "cadence_qspi.h" +__weak void cadence_qspi_apb_enable_linear_mode(bool enable) +{ + return; +} + void cadence_qspi_apb_controller_enable(void *reg_base) { unsigned int reg; @@ -730,6 +735,9 @@ int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat, void *buf = op->data.buf.in; size_t len = op->data.nbytes; + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) + cadence_qspi_apb_enable_linear_mode(true); + if (plat->use_dac_mode && (from + len < plat->ahbsize)) { if (len < 256 || dma_memcpy(buf, plat->ahbbase + from, len) < 0) { @@ -897,6 +905,9 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat, const void *buf = op->data.buf.out; size_t len = op->data.nbytes; + if (CONFIG_IS_ENABLED(ARCH_VERSAL)) + cadence_qspi_apb_enable_linear_mode(true); + /* * Some flashes like the Cypress Semper flash expect a dummy 4-byte * address (all 0s) with the read status register command in DTR mode. |