diff options
| author | Gaurav Jain <gaurav.jain@nxp.com> | 2022-05-11 14:23:19 +0530 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-05-20 12:36:47 +0200 |
| commit | 1919f58a8f371c19c340127b6a76859867e90247 (patch) | |
| tree | 89e5bcd5d90161358f045365061b548a6b6199dd /drivers | |
| parent | cad77280c31f6736e93bf18060080fee50cc9ee3 (diff) | |
| download | u-boot-1919f58a8f371c19c340127b6a76859867e90247.tar.gz | |
crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish
HW accelerated hash operations are giving incorrect hash output.
so add flush and invalidate for input/output hash buffers.
Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using hardware acceleration.)
Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/crypto/fsl/fsl_hash.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index a52c4ac957e..9e6829b7ad4 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -149,12 +149,20 @@ static int caam_hash_finish(void *hash_ctx, void *dest_buf, driver_hash[caam_algo].digestsize, 1); + flush_dcache_range((ulong)ctx->sg_tbl, (ulong)(ctx->sg_tbl) + len); + flush_dcache_range((ulong)ctx->sha_desc, + (ulong)(ctx->sha_desc) + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE)); + flush_dcache_range((ulong)ctx->hash, + (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize); + ret = run_descriptor_jr(ctx->sha_desc); if (ret) { debug("Error %x\n", ret); return ret; } else { + invalidate_dcache_range((ulong)ctx->hash, + (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize); memcpy(dest_buf, ctx->hash, sizeof(ctx->hash)); } free(ctx); |