diff options
| author | Mario Six <mario.six@gdsys.cc> | 2019-01-21 09:18:01 +0100 |
|---|---|---|
| committer | Mario Six <mario.six@gdsys.cc> | 2019-05-21 07:52:33 +0200 |
| commit | a8f975391f2452bc7a51eeafd030c85c32e1aca5 (patch) | |
| tree | 8b5bc02ac3891c277a8cae70dcf951f86c705f65 /include/configs/kmcoge5ne.h | |
| parent | 87ee51048eae94eb5c075b6c900d4da5e9531cf4 (diff) | |
| download | u-boot-a8f975391f2452bc7a51eeafd030c85c32e1aca5.tar.gz | |
mpc83xx: Simplify BR,OR lines
Re-format all BR,OR #define lines into single lines. This makes them
harder to read, but accessible to semi-automatic replacement.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/kmcoge5ne.h')
| -rw-r--r-- | include/configs/kmcoge5ne.h | 55 |
1 files changed, 13 insertions, 42 deletions
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 370e6b496ae..5027073d6e9 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -108,15 +108,9 @@ */ #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | /* 16 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xF0000000 | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_5 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -125,15 +119,10 @@ /* * PRIO1/PIGGY on the local bus CS1 */ -/* Window base at flash base */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - BR_PS_8 | /* 8 bit port size */ \ - BR_MS_GPCM | /* MSEL = GPCM */ \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | OR_GPCM_EAD) + +/* KMBEC_FPGA */ +#define CONFIG_SYS_BR1_PRELIM (0xE8000000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -347,18 +336,9 @@ #define CONFIG_SYS_PAXE_BASE 0xA0000000 #define CONFIG_SYS_PAXE_SIZE 256 -#define CONFIG_SYS_BR3_PRELIM (\ - CONFIG_SYS_PAXE_BASE | \ - BR_PS_8 | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (\ - OR_AM_256MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | \ - OR_GPCM_EAD) +/* PAXE */ +#define CONFIG_SYS_BR3_PRELIM (0xA0000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM (OR_AM_256MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * BFTIC3 on the local bus CS4 @@ -366,18 +346,9 @@ #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 #define CONFIG_SYS_BFTIC3_SIZE 256 -#define CONFIG_SYS_BR4_PRELIM (\ - CONFIG_SYS_BFTIC3_BASE |\ - BR_PS_8 | \ - BR_V) - -#define CONFIG_SYS_OR4_PRELIM (\ - OR_AM_256MB|\ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 |\ - OR_GPCM_SCY_2 |\ - OR_GPCM_TRLX |\ - OR_GPCM_EAD) +/* BFTIC3 */ +#define CONFIG_SYS_BR4_PRELIM (0xB0000000 | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR4_PRELIM (OR_AM_256MB| OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_2 | OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* enable POST tests */ #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) |