Merge branch 'next'

Signed-off-by: Tom Rini <trini@konsulko.com>

1 files changed, 76 insertions, 85 deletions

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index e1c66c5dcc0..794ea84852e 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -21,7 +21,6 @@
 
 #define COUNTER_FREQUENCY_REAL		(get_board_sys_clk()/4)
 
-#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
 #define SPD_EEPROM_ADDRESS3	0x53
@@ -32,52 +31,47 @@
 
 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
 
-#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
-#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+#define CFG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CFG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CFG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
 
-#define CONFIG_SYS_NOR0_CSPR					\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+#define CFG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)		| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR0_CSPR_EARLY				\
-	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+#define CFG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)	| \
 	CSPR_PORT_SIZE_16					| \
 	CSPR_MSEL_NOR						| \
 	CSPR_V)
-#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
-#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+#define CFG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CFG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
 				FTIM0_NOR_TEADC(0x5) | \
 				FTIM0_NOR_TEAHC(0x5))
-#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+#define CFG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1a) |\
 				FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+#define CFG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
 				FTIM2_NOR_TCH(0x4) | \
 				FTIM2_NOR_TWPH(0x0E) | \
 				FTIM2_NOR_TWP(0x1c))
-#define CONFIG_SYS_NOR_FTIM3	0x04000000
-#define CONFIG_SYS_IFC_CCR	0x01000000
+#define CFG_SYS_NOR_FTIM3	0x04000000
+#define CFG_SYS_IFC_CCR	0x01000000
 
 #ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
-					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#define CFG_SYS_FLASH_BANKS_LIST	{ CFG_SYS_FLASH_BASE,\
+					 CFG_SYS_FLASH_BASE + 0x40000000}
 #endif
 
-#define CONFIG_SYS_NAND_MAX_ECCPOS	256
-#define CONFIG_SYS_NAND_MAX_OOBFREE	2
-
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -86,21 +80,20 @@
 				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
 					FTIM0_NAND_TWP(0x30)   | \
 					FTIM0_NAND_TWCHT(0x0e) | \
 					FTIM0_NAND_TWH(0x14))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
 					FTIM1_NAND_TWBE(0xab)  | \
 					FTIM1_NAND_TRR(0x1c)   | \
 					FTIM1_NAND_TRP(0x30))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
 					FTIM2_NAND_TREH(0x14) | \
 					FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
-#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 
 #define QIXIS_LBMAP_SWITCH		0x06
 #define QIXIS_LBMAP_MASK		0x0f
@@ -116,70 +109,70 @@
 #define QIXIS_RCW_SRC_NAND		0x119
 #define	QIXIS_RST_FORCE_MEM		0x01
 
-#define CONFIG_SYS_CSPR3_EXT	(0x0)
-#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+#define CFG_SYS_CSPR3_EXT	(0x0)
+#define CFG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
-#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+#define CFG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 \
 				| CSPR_MSEL_GPCM \
 				| CSPR_V)
 
-#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
-#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
+#define CFG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CFG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
 /* QIXIS Timing parameters for IFC CS3 */
-#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+#define CFG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
 					FTIM0_GPCM_TEADC(0x0e) | \
 					FTIM0_GPCM_TEAHC(0x0e))
-#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+#define CFG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
-#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+#define CFG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
 					FTIM2_GPCM_TCH(0xf) | \
 					FTIM2_GPCM_TWP(0x3E))
-#define CONFIG_SYS_CS3_FTIM3		0x0
+#define CFG_SYS_CS3_FTIM3		0x0
 
 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR2_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
 #else
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
-#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CFG_SYS_CSPR0_EXT		CFG_SYS_NOR0_CSPR_EXT
+#define CFG_SYS_CSPR0		CFG_SYS_NOR0_CSPR_EARLY
+#define CFG_SYS_CSPR0_FINAL		CFG_SYS_NOR0_CSPR
+#define CFG_SYS_AMASK0		CFG_SYS_NOR_AMASK
+#define CFG_SYS_CSOR0		CFG_SYS_NOR_CSOR
+#define CFG_SYS_CS0_FTIM0		CFG_SYS_NOR_FTIM0
+#define CFG_SYS_CS0_FTIM1		CFG_SYS_NOR_FTIM1
+#define CFG_SYS_CS0_FTIM2		CFG_SYS_NOR_FTIM2
+#define CFG_SYS_CS0_FTIM3		CFG_SYS_NOR_FTIM3
+#define CFG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CFG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CFG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CFG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CFG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CFG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CFG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CFG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 #endif
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 #ifdef CONFIG_TARGET_LS2081ARDB
 #define QIXIS_QMAP_MASK			0x07
@@ -200,7 +193,7 @@
  * I2C
  */
 #ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #endif
 #define I2C_MUX_PCA_ADDR		0x75
 #define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/
@@ -213,12 +206,10 @@
 /*
  * RTC configuration
  */
-#define RTC
 #ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SYS_I2C_RTC_ADDR         0x51
+#define CFG_SYS_I2C_RTC_ADDR         0x51
 #else
-#define CONFIG_RTC_DS3231               1
-#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CFG_SYS_I2C_RTC_ADDR         0x68
 #endif
 
 #define BOOT_TARGET_DEVICES(func) \
@@ -284,9 +275,9 @@
 #endif
 
 /* Initial environment variables */
-#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CFG_EXTRA_ENV_SETTINGS
 #ifdef CONFIG_TFABOOT
-#define CONFIG_EXTRA_ENV_SETTINGS		\
+#define CFG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"ramdisk_addr=0x800000\0"		\
 	"ramdisk_size=0x2000000\0"		\
@@ -348,7 +339,7 @@
 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 		"bootm $load_addr#$board\0"
 #else
-#define CONFIG_EXTRA_ENV_SETTINGS		\
+#define CFG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"ramdisk_addr=0x800000\0"		\
 	"ramdisk_size=0x2000000\0"		\