diff options
author | Samuel Holland <samuel@sholland.org> | 2021-09-12 11:48:43 -0500 |
---|---|---|
committer | Andre Przywara <andre.przywara@arm.com> | 2021-10-11 10:46:44 +0100 |
commit | 21d314a6612564ee202d8a8189ed37d5c6abf0dd (patch) | |
tree | 9bddefc0059714ceaa09d1584ca7a149d3b1bc9b /include | |
parent | 5427da02bebb3a375f11a5623dea07993ea0d555 (diff) | |
download | u-boot-21d314a6612564ee202d8a8189ed37d5c6abf0dd.tar.gz |
clk: sunxi: Move header out of arch directory
The CCU header is only used by the DM drivers, not any platform code.
Its current location adds an artificial dependency on CONFIG_ARM and
ARCH_SUNXI, which will be problematic when adding the CCU driver for
a RISC-V sunxi platform.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/clk/sunxi.h | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/include/clk/sunxi.h b/include/clk/sunxi.h new file mode 100644 index 00000000000..d4ad5fd0ba3 --- /dev/null +++ b/include/clk/sunxi.h @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki <jagan@amarulasolutions.com> + */ + +#ifndef _CLK_SUNXI_H +#define _CLK_SUNXI_H + +#include <linux/bitops.h> + +/** + * enum ccu_flags - ccu clock/reset flags + * + * @CCU_CLK_F_IS_VALID: is given clock gate is valid? + * @CCU_RST_F_IS_VALID: is given reset control is valid? + */ +enum ccu_flags { + CCU_CLK_F_IS_VALID = BIT(0), + CCU_RST_F_IS_VALID = BIT(1), +}; + +/** + * struct ccu_clk_gate - ccu clock gate + * @off: gate offset + * @bit: gate bit + * @flags: ccu clock gate flags + */ +struct ccu_clk_gate { + u16 off; + u32 bit; + enum ccu_flags flags; +}; + +#define GATE(_off, _bit) { \ + .off = _off, \ + .bit = _bit, \ + .flags = CCU_CLK_F_IS_VALID, \ +} + +/** + * struct ccu_reset - ccu reset + * @off: reset offset + * @bit: reset bit + * @flags: ccu reset control flags + */ +struct ccu_reset { + u16 off; + u32 bit; + enum ccu_flags flags; +}; + +#define RESET(_off, _bit) { \ + .off = _off, \ + .bit = _bit, \ + .flags = CCU_RST_F_IS_VALID, \ +} + +/** + * struct ccu_desc - clock control unit descriptor + * + * @gates: clock gates + * @resets: reset unit + */ +struct ccu_desc { + const struct ccu_clk_gate *gates; + const struct ccu_reset *resets; +}; + +/** + * struct ccu_priv - sunxi clock control unit + * + * @base: base address + * @desc: ccu descriptor + */ +struct ccu_priv { + void *base; + const struct ccu_desc *desc; +}; + +/** + * sunxi_clk_probe - common sunxi clock probe + * @dev: clock device + */ +int sunxi_clk_probe(struct udevice *dev); + +extern struct clk_ops sunxi_clk_ops; + +/** + * sunxi_reset_bind() - reset binding + * + * @dev: reset device + * @count: reset count + * @return 0 success, or error value + */ +int sunxi_reset_bind(struct udevice *dev, ulong count); + +#endif /* _CLK_SUNXI_H */ |