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| author | Vignesh Raghavendra <vigneshr@ti.com> | 2022-03-07 14:55:51 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-04-11 11:39:19 -0400 |
| commit | 7262ff7e564c8b7d81f940af242c20f832ee7511 (patch) | |
| tree | 1f9c0de78eee845b61608d18aa74ccc7b9e34b80 /lib | |
| parent | 1583c87b1b813a04c95732ae8075d79b14a26eea (diff) | |
| download | u-boot-7262ff7e564c8b7d81f940af242c20f832ee7511.tar.gz | |
ARM: dts: k3-j721s2: Correct timer frequency
MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears
incorrect.
Without this delays in R5 SPL are 10x off.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'lib')
0 files changed, 0 insertions, 0 deletions