diff options
570 files changed, 10708 insertions, 6486 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index db471e67107..d5cfa59a8a6 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -89,6 +89,7 @@ stages: options: $(container_option) steps: - script: | + set -e virtualenv -p /usr/bin/python3 /tmp/venvhtml . /tmp/venvhtml/bin/activate pip install -r doc/sphinx/requirements.txt @@ -133,8 +134,11 @@ stages: export USER=azure virtualenv -p /usr/bin/python3 /tmp/venv . /tmp/venv/bin/activate - pip install -r test/py/requirements.txt - pip install -r tools/buildman/requirements.txt + pip install -r test/py/requirements.txt \ + -r tools/binman/requirements.txt \ + -r tools/buildman/requirements.txt \ + -r tools/patman/requirements.txt \ + -r tools/u_boot_pylib/requirements.txt export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH} @@ -162,9 +166,14 @@ stages: - script: | git config --global --add safe.directory $(work_dir) export USER=azure - pip install -r test/py/requirements.txt - pip install -r tools/buildman/requirements.txt - pip install asteval pylint==2.12.2 pyopenssl + virtualenv -p /usr/bin/python3 /tmp/venv + . /tmp/venv/bin/activate + pip install -r test/py/requirements.txt \ + -r tools/binman/requirements.txt \ + -r tools/buildman/requirements.txt \ + -r tools/patman/requirements.txt \ + -r tools/u_boot_pylib/requirements.txt \ + asteval pylint==3.3.4 pyopenssl export PATH=${PATH}:~/.local/bin echo "[MASTER]" >> .pylintrc echo "load-plugins=pylint.extensions.docparams" >> .pylintrc @@ -264,7 +273,13 @@ stages: if [ -n "\${BUILD_ENV}" ]; then export \${BUILD_ENV}; fi - pip install -r tools/buildman/requirements.txt + virtualenv -p /usr/bin/python3 /tmp/venv + . /tmp/venv/bin/activate + pip install -r tools/binman/requirements.txt \ + -r tools/buildman/requirements.txt \ + -r test/py/requirements.txt \ + -r tools/u_boot_pylib/requirements.txt \ + pytest-azurepipelines tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE} cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/ cp /opt/grub/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/ @@ -288,10 +303,6 @@ stages: /opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload; /opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000; fi - virtualenv -p /usr/bin/python3 /tmp/venv - . /tmp/venv/bin/activate - pip install -r test/py/requirements.txt - pip install pytest-azurepipelines export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH} export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci # "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not @@ -581,7 +592,10 @@ stages: # make environment variables available as tests are running inside a container export BUILDMAN="${BUILDMAN}" git config --global --add safe.directory ${WORK_DIR} - pip install -r tools/buildman/requirements.txt + virtualenv -p /usr/bin/python3 /tmp/venv + . /tmp/venv/bin/activate + pip install -r tools/binman/requirements.txt \ + -r tools/buildman/requirements.txt EOF cat << "EOF" >> build.sh if [[ "${BUILDMAN}" != "" ]]; then diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a93703fdcea..2dbe6325f33 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -40,6 +40,7 @@ stages: # qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled. # The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks - ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na + - ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then @@ -55,6 +56,11 @@ stages: wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin; export BINMAN_INDIRS=/tmp; fi + # Prepare python environment + - virtualenv -p /usr/bin/python3 /tmp/venv; + . /tmp/venv/bin/activate; + pip install -r test/py/requirements.txt -r tools/binman/requirements.txt + -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt after_script: - cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} . @@ -90,9 +96,6 @@ stages: /opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload; /opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000; fi - - virtualenv -p /usr/bin/python3 /tmp/venv - - . /tmp/venv/bin/activate - - pip install -r test/py/requirements.txt # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not - export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH}; export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci; @@ -105,6 +108,7 @@ stages: paths: - "*.html" - "*.css" + - results.xml reports: junit: results.xml expire_in: 1 week @@ -119,9 +123,13 @@ build all platforms in a single job: tags: - ${HOST} script: + # Prepare python environment + - virtualenv -p /usr/bin/python3 /tmp/venv; + . /tmp/venv/bin/activate; + pip install -r tools/binman/requirements.txt + -r tools/buildman/requirements.txt - ret=0; git config --global --add safe.directory "${CI_PROJECT_DIR}"; - pip install -r tools/buildman/requirements.txt; ./tools/buildman/buildman -o /tmp -PEWM -x xtensa || ret=$?; if [[ $ret -ne 0 ]]; then ./tools/buildman/buildman -o /tmp -seP; @@ -178,8 +186,9 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites: export USER=gitlab; virtualenv -p /usr/bin/python3 /tmp/venv; . /tmp/venv/bin/activate; - pip install -r test/py/requirements.txt; - pip install -r tools/buildman/requirements.txt; + pip install -r test/py/requirements.txt -r tools/binman/requirements.txt + -r tools/buildman/requirements.txt -r tools/patman/requirements.txt + -r tools/u_boot_pylib/requirements.txt; export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only; export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"; export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"; @@ -198,9 +207,11 @@ Run pylint: extends: .testsuites script: - git config --global --add safe.directory "${CI_PROJECT_DIR}" - - pip install -r test/py/requirements.txt - - pip install -r tools/buildman/requirements.txt - - pip install asteval pylint==2.12.2 pyopenssl + - virtualenv -p /usr/bin/python3 /tmp/venv + - . /tmp/venv/bin/activate + - pip install -r test/py/requirements.txt -r tools/binman/requirements.txt + -r tools/buildman/requirements.txt -r tools/patman/requirements.txt + -r tools/u_boot_pylib/requirements.txt asteval pylint==3.3.4 pyopenssl - export PATH=${PATH}:~/.local/bin - echo "[MASTER]" >> .pylintrc - echo "load-plugins=pylint.extensions.docparams" >> .pylintrc @@ -230,31 +241,47 @@ Check packing of Python tools: # Test sandbox with test.py sandbox test.py: + parallel: + matrix: + - HOST: "fast arm64" + - HOST: "fast amd64" tags: - - ${DEFAULT_AMD64_TAG} + - ${HOST} variables: TEST_PY_BD: "sandbox" TEST_PY_EXTRA: "--timing" <<: *buildman_and_testpy_dfn sandbox with clang test.py: + parallel: + matrix: + - HOST: "fast arm64" + - HOST: "fast amd64" tags: - - ${DEFAULT_AMD64_TAG} + - ${HOST} variables: TEST_PY_BD: "sandbox" OVERRIDE: "-O clang-17" <<: *buildman_and_testpy_dfn sandbox64 test.py: + parallel: + matrix: + - HOST: "fast arm64" + - HOST: "fast amd64" tags: - - ${DEFAULT_AMD64_TAG} + - ${HOST} variables: TEST_PY_BD: "sandbox64" <<: *buildman_and_testpy_dfn sandbox64 with clang test.py: + parallel: + matrix: + - HOST: "fast arm64" + - HOST: "fast amd64" tags: - - ${DEFAULT_AMD64_TAG} + - ${HOST} variables: TEST_PY_BD: "sandbox64" OVERRIDE: "-O clang-17" @@ -523,9 +550,6 @@ coreboot test.py: dependencies: [] tags: [ 'lab' ] script: - - if [[ -z "${SJG_LAB}" ]]; then - exit 0; - fi # Environment: # SRC - source tree # OUT - output directory for builds diff --git a/MAINTAINERS b/MAINTAINERS index 247f525847e..687262b355d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -151,9 +151,11 @@ F: cmd/arm/ ARM ALTERA SOCFPGA M: Marek Vasut <marex@denx.de> M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> -M: Tien Fong Chee <tien.fong.chee@intel.com> +M: Tien Fong Chee <tien.fong.chee@altera.com> +M: Tingting Meng <tingting.meng@altera.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git +F: drivers/ddr/altera/ F: arch/arm/mach-socfpga/ F: drivers/sysreset/sysreset_socfpga* @@ -671,8 +673,7 @@ F: drivers/reset/sti-reset.c F: drivers/serial/serial_sti_asc.c F: drivers/sysreset/sysreset_sti.c F: drivers/timer/arm_global_timer.c -F: drivers/usb/host/dwc3-sti-glue.c -F: include/dwc3-sti-glue.h +F: drivers/usb/host/dwc3-sti.c F: include/dt-bindings/clock/stih407-clks.h F: include/dt-bindings/clock/stih410-clks.h F: include/dt-bindings/reset/stih407-resets.h @@ -1806,6 +1807,13 @@ M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> S: Maintained F: test/lib/uuid.c +VBE +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: boot/vbe* +F: common/spl_reloc.c +F: include/vbe.h + VIDEO M: Anatolij Gustschin <agust@denx.de> S: Maintained @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -893,9 +893,6 @@ ifdef CONFIG_POST libs-y += post/ endif libs-$(CONFIG_$(PHASE_)UNIT_TEST) += test/ -libs-$(CONFIG_UT_ENV) += test/env/ -libs-$(CONFIG_UT_OPTEE) += test/optee/ -libs-$(CONFIG_UT_OVERLAY) += test/overlay/ libs-y += $(if $(wildcard $(srctree)/board/$(BOARDDIR)/Makefile),board/$(BOARDDIR)/) @@ -1019,8 +1016,10 @@ INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi # Generate this input file for binman ifeq ($(CONFIG_SPL),) +ifneq ($(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO)),) INPUTS-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin endif +endif # Add optional build target if defined in board/cpu/soc headers ifneq ($(CONFIG_BUILD_TARGET),) @@ -2515,7 +2514,7 @@ cmd_genenv = \ sed -e '/^\s*$$/d' | \ sort -t '=' -k 1,1 -s -o $@ -u-boot-initial-env: scripts_basic $(env_h) FORCE +u-boot-initial-env: scripts_basic $(version_h) $(env_h) include/config.h FORCE $(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv $(call if_changed,genenv) diff --git a/api/Kconfig b/api/Kconfig index b5a7399d7f3..8cfd98ad6a6 100644 --- a/api/Kconfig +++ b/api/Kconfig @@ -19,24 +19,4 @@ config EXAMPLES U-Boot provides an API for standalone applications. Examples are provided in directory examples/. -config STANDALONE_LOAD_ADDR - depends on EXAMPLES - hex "Address in memory to link standalone applications to" - default 0xffffffff80200000 if MIPS && 64BIT - default 0x8c000000 if SH - default 0x82000000 if ARC - default 0x80f00000 if MICROBLAZE - default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3 - default 0x80200000 if MIPS && 32BIT - default 0x0c100000 if ARM - default 0x02000000 if NIOS2 - default 0x00040000 if PPC || X86 - default 0x00020000 if M68K - default 0x0 if RISCV - default SYS_LOAD_ADDR - help - This option defines a board specific value for the address where - standalone program gets loaded, thus overwriting the architecture - dependent default settings. - endmenu diff --git a/api/api_platform.c b/api/api_platform.c index 7a789bd2016..d5cbcd6e201 100644 --- a/api/api_platform.c +++ b/api/api_platform.c @@ -17,9 +17,15 @@ int platform_sys_info(struct sys_info *si) { int i; + si->clk_bus = gd->bus_clk; + si->clk_cpu = gd->cpu_clk; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) platform_set_mr(si, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size, MR_ATTR_DRAM); + platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM); + platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH); + return 1; } diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f504d7d0760..cf08fe63f1e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -108,6 +108,9 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE The value subtracted from CONFIG_TEXT_BASE to calculate the TEXT_OFFSET value written to the Linux kernel image header. +config NVIC + bool + config GICV2 bool @@ -117,6 +120,7 @@ config GICV3 config DRIVER_GICV2 bool "ARM GICV2 driver" select IRQ + depends on !NVIC help ARM GICV2 driver. Basic support for parsing the GICV2 node and generate ACPI tables. @@ -124,6 +128,7 @@ config DRIVER_GICV2 config GIC_V3_ITS bool "ARM GICV3 ITS" select IRQ + depends on !NVIC help ARM GICV3 Interrupt translation service (ITS). Basic support for programming locality specific peripheral @@ -134,6 +139,7 @@ config GIC_V3_ITS config GICV3_SUPPORT_GIC600 bool "ARM GICV3 GIC600 SUPPORT" + depends on !NVIC help ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame.This @@ -193,6 +199,7 @@ config SPL_SYS_DCACHE_OFF config SYS_ARM_CACHE_CP15 bool "CP15 based cache enabling support" + depends on !CPU_V7M help Select this if your processor suports enabling caches by using CP15 registers. @@ -200,6 +207,7 @@ config SYS_ARM_CACHE_CP15 config SYS_ARM_MMU bool "MMU-based Paged Memory Management Support" select SYS_ARM_CACHE_CP15 + depends on !CPU_V7M help Select if you want MMU-based virtualised addressing space support via paged memory management. @@ -350,6 +358,7 @@ config CPU_V7M select SYS_CACHE_SHIFT_5 select SYS_THUMB_BUILD select THUMB2_KERNEL + select NVIC config CPU_V7R bool @@ -1119,7 +1128,6 @@ config ARCH_SOCFPGA select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL - select GICV2 select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL @@ -1141,6 +1149,7 @@ config ARCH_SOCFPGA select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ TARGET_SOCFPGA_SOC64 + select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY @@ -2193,6 +2202,7 @@ config SERIAL_TAG config STATIC_MACH_TYPE bool "Statically define the Machine ID number" default y if TARGET_DS109 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac" + depends on SUPPORT_PASSING_ATAGS help When booting via ATAGs, enable this option if we know the correct machine ID number to use at compile time. Some systems will be diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c index 259b49ff364..492353c93df 100644 --- a/arch/arm/cpu/armv8/spl_data.c +++ b/arch/arm/cpu/armv8/spl_data.c @@ -5,23 +5,28 @@ #include <spl.h> +char __data_start[0] __section(".__data_start"); char __data_save_start[0] __section(".__data_save_start"); char __data_save_end[0] __section(".__data_save_end"); u32 cold_reboot_flag = 1; +u32 __weak reset_flag(void) +{ + return 1; +} + void spl_save_restore_data(void) { u32 data_size = __data_save_end - __data_save_start; + cold_reboot_flag = reset_flag(); if (cold_reboot_flag == 1) { /* Save data section to data_save section */ - memcpy(__data_save_start, __data_save_start - data_size, - data_size); + memcpy(__data_save_start, __data_start, data_size); } else { /* Restore the data_save section to data section */ - memcpy(__data_save_start - data_size, __data_save_start, - data_size); + memcpy(__data_start, __data_save_start, data_size); } cold_reboot_flag++; diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index 9dbdff3a4fc..85f13ccd0d2 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -9,8 +9,16 @@ #include <linux/linkage.h> #include <asm/macro.h> +.pushsection .text.armv8_switch_to_el2_prep, "ax" +WEAK(armv8_switch_to_el2_prep) + ret +ENDPROC(armv8_switch_to_el2_prep) +.popsection + .pushsection .text.armv8_switch_to_el2, "ax" ENTRY(armv8_switch_to_el2) + bl armv8_switch_to_el2_prep + nop switch_el x6, 1f, 0f, 0f 0: cmp x5, #ES_TO_AARCH64 diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds index fed69644b55..c4f83ec9cfc 100644 --- a/arch/arm/cpu/armv8/u-boot-spl.lds +++ b/arch/arm/cpu/armv8/u-boot-spl.lds @@ -37,6 +37,7 @@ SECTIONS .data : { . = ALIGN(8); + *(.__data_start) *(.data*) } >.sram diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0bf3697bdbe..85a03b512b6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -52,9 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_RK3036) += \ - rk3036-sdk.dtb - dtb-$(CONFIG_ROCKCHIP_RK3128) += \ rk3128-evb.dtb @@ -84,6 +81,7 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_TEGRA) += \ + tegra20-acer-a500-picasso.dtb \ tegra20-asus-sl101.dtb \ tegra20-asus-tf101.dtb \ tegra20-asus-tf101g.dtb \ @@ -797,7 +795,6 @@ dtb-y += \ imx6q-icore-rqs.dtb \ imx6q-kp.dtb \ imx6q-logicpd.dtb \ - imx6q-lxr.dtb \ imx6q-marsboard.dtb \ imx6q-mccmon6.dtb\ imx6q-nitrogen6x.dtb \ @@ -920,8 +917,7 @@ dtb-$(CONFIG_ARCH_IMX9) += \ imx93-var-som-symphony.dtb \ imx93-phyboard-segin.dtb -dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ - imxrt1020-evk.dtb \ +dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ dtb-$(CONFIG_RZA1) += \ diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts index 99867d2bf8e..7f00014f13c 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity.dts +++ b/arch/arm/dts/at91-sam9x60_curiosity.dts @@ -82,6 +82,11 @@ }; }; +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; +}; + &ebi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>; @@ -171,10 +176,20 @@ &macb0 { phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; status = "okay"; }; &pinctrl { + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + ebi { pinctrl_ebi_data_0_7: ebi-data-lsb-0 { atmel,pins = @@ -217,6 +232,22 @@ }; }; + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ + }; + }; + nand { pinctrl_nand_oe_we: nand-oe-we-0 { atmel,pins = @@ -240,6 +271,36 @@ <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; }; + sdhci0 { + pinctrl_sdhci0: sdhci0 { + atmel,pins = + <AT91_PIOA 17 AT91_PERIPH_A + (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */ + AT91_PIOA 16 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */ + AT91_PIOA 18 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */ + }; + }; + + sdhci1 { + pinctrl_sdhci1: sdhci1 { + atmel,pins = + <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */ + AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */ + AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */ + }; + }; + usb1 { pinctrl_usb_default: usb_default { atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE @@ -248,6 +309,16 @@ }; }; +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0>; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; +}; + &usb1 { num-ports = <3>; atmel,vbus-gpio = <0 diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi index 4ea4202737c..8d496205523 100644 --- a/arch/arm/dts/at91sam9260.dtsi +++ b/arch/arm/dts/at91sam9260.dtsi @@ -401,51 +401,11 @@ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; - pinctrl: pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x600>; - reg = <0xfffff400 0x200 /* pioA */ - 0xfffff600 0x200 /* pioB */ - 0xfffff800 0x200 /* pioC */ - >; atmel,mux-mask = < /* A B */ @@ -767,6 +727,42 @@ atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; }; dbgu: serial@fffff200 { diff --git a/arch/arm/dts/at91sam9261.dtsi b/arch/arm/dts/at91sam9261.dtsi index 804340e75d9..65e0e4f0de0 100644 --- a/arch/arm/dts/at91sam9261.dtsi +++ b/arch/arm/dts/at91sam9261.dtsi @@ -286,51 +286,12 @@ status = "disabled"; }; - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; - pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x600>; - reg = <0xfffff400 0x200 /* pioA */ - 0xfffff600 0x200 /* pioB */ - 0xfffff800 0x200 /* pioC */ - >; + atmel,mux-mask = /* A B */ <0xffffffff 0xfffffff7>, /* pioA */ @@ -573,6 +534,42 @@ <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; + + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi index 98cdd8ebcca..55b79667564 100644 --- a/arch/arm/dts/at91sam9263.dtsi +++ b/arch/arm/dts/at91sam9263.dtsi @@ -404,12 +404,6 @@ #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; - reg = <0xfffff200 0x200 - 0xfffff400 0x200 - 0xfffff600 0x200 - 0xfffff800 0x200 - 0xfffffa00 0x200 - >; atmel,mux-mask = < /* A B */ @@ -719,66 +713,65 @@ }; }; - }; - - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - bootph-all; - }; + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + bootph-all; + }; - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - bootph-all; - }; + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + bootph-all; + }; - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCDE_clk>; - bootph-all; + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCDE_clk>; + bootph-all; + }; }; dbgu: serial@ffffee00 { diff --git a/arch/arm/dts/at91sam9g45.dtsi b/arch/arm/dts/at91sam9g45.dtsi index d0bcd797359..63a061354e4 100644 --- a/arch/arm/dts/at91sam9g45.dtsi +++ b/arch/arm/dts/at91sam9g45.dtsi @@ -435,12 +435,6 @@ #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; - reg = <0xfffff200 0x200 - 0xfffff400 0x200 - 0xfffff600 0x200 - 0xfffff800 0x200 - 0xfffffa00 0x200 - >; bootph-all; atmel,mux-mask = < @@ -854,61 +848,61 @@ AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ }; }; - }; - pioA: gpio@fffff200 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; + pioA: gpio@fffff200 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; - pioB: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; + pioB: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; - pioC: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; + pioC: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + }; - pioD: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; - }; + pioD: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioDE_clk>; + }; - pioE: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioDE_clk>; + pioE: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioDE_clk>; + }; }; dbgu: serial@ffffee00 { diff --git a/arch/arm/dts/at91sam9n12.dtsi b/arch/arm/dts/at91sam9n12.dtsi index cb3a0370b86..84089837013 100644 --- a/arch/arm/dts/at91sam9n12.dtsi +++ b/arch/arm/dts/at91sam9n12.dtsi @@ -492,11 +492,6 @@ #size-cells = <1>; compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x800>; - reg = <0xfffff400 0x200 - 0xfffff600 0x200 - 0xfffff800 0x200 - 0xfffffa00 0x200 - >; atmel,mux-mask = < /* A B C */ @@ -795,54 +790,54 @@ atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; }; }; - }; - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - bootph-all; - }; + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + bootph-all; + }; - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - bootph-all; - }; + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + bootph-all; + }; - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - bootph-all; - }; + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + bootph-all; + }; - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - bootph-all; + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + bootph-all; + }; }; dbgu: serial@fffff200 { diff --git a/arch/arm/dts/at91sam9rl.dtsi b/arch/arm/dts/at91sam9rl.dtsi index b855c8fe0fe..3b99de21058 100644 --- a/arch/arm/dts/at91sam9rl.dtsi +++ b/arch/arm/dts/at91sam9rl.dtsi @@ -386,11 +386,6 @@ #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x800>; - reg = <0xfffff400 0x200 - 0xfffff600 0x200 - 0xfffff800 0x200 - 0xfffffa00 0x200 - >; atmel,mux-mask = /* A B */ @@ -768,54 +763,54 @@ <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; - }; - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; - pioD: gpio@fffffa00 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - bootph-all; + pioD: gpio@fffffa00 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + bootph-all; + }; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi index 5fca9b13c27..4c6d8b9bb65 100644 --- a/arch/arm/dts/at91sam9x5.dtsi +++ b/arch/arm/dts/at91sam9x5.dtsi @@ -461,14 +461,8 @@ #size-cells = <1>; compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x800>; - reg = <0xfffff400 0x200 /* pioA */ - 0xfffff600 0x200 /* pioB */ - 0xfffff800 0x200 /* pioC */ - 0xfffffa00 0x200 /* pioD */ - >; bootph-all; - /* shared pinctrl settings */ dbgu { bootph-all; @@ -831,52 +825,52 @@ atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>; }; }; - }; - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + }; - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <19>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioAB_clk>; - }; + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <19>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioAB_clk>; + }; - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; - }; + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + }; - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - #gpio-lines = <22>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioCD_clk>; + }; }; ssc0: ssc@f0010000 { diff --git a/arch/arm/dts/imx6q-lxr.dts b/arch/arm/dts/imx6q-lxr.dts deleted file mode 100644 index ae4f8eeb105..00000000000 --- a/arch/arm/dts/imx6q-lxr.dts +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// -// Copyright 2024 Comvetia AG - -/dts-v1/; -#include "imx6q-phytec-pfla02.dtsi" - -/ { - model = "COMVETIA QSoIP LXR-2"; - compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q"; - - chosen { - stdout-path = &uart4; - }; - - spi { - compatible = "spi-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi_gpio>; - sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; - num-chipselects = <0>; - #address-cells = <1>; - #size-cells = <0>; - - fpga@0 { - compatible = "altr,fpga-passive-serial"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fpga>; - nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; - confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&fec { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -&usdhc3 { - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_fpga: fpgagrp { - fsl,pins = < - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 - >; - }; - - pinctrl_spi_gpio: spigpiogrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 - MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi deleted file mode 100644 index 500944bd2a0..00000000000 --- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include "imx6q.dtsi" -#include "imx6qdl-phytec-pfla02.dtsi" - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; -}; diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi deleted file mode 100644 index c0c47adc586..00000000000 --- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi +++ /dev/null @@ -1,467 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH - */ - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Phytec phyFLEX-i.MX6 Quad"; - compatible = "phytec,imx6q-pfla02", "fsl,imx6q"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x80000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 0>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 0>; - enable-active-high; - }; - - gpio_leds: leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - compatible = "gpio-leds"; - - led_green: led-green { - label = "phyflex:green"; - gpios = <&gpio1 30 0>; - }; - - led_red: led-red { - label = "phyflex:red"; - gpios = <&gpio2 31 0>; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "disabled"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "disabled"; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - status = "okay"; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; - - som_flash: flash@0 { - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-handle = <ðphy>; - phy-mode = "rgmii"; - phy-reset-duration = <10>; /* in msecs */ - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - phy-supply = <&vdd_eth_io_reg>; - status = "disabled"; - - fec_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - txc-skew-ps = <1680>; - rxc-skew-ps = <1860>; - }; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - som_eeprom: eeprom@50 { - compatible = "catalyst,24c32", "atmel,24c32"; - pagesize = <32>; - reg = <0x50>; - }; - - pmic@58 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */ - #interrupt-cells = <2>; - interrupt-controller; - - regulators { - vddcore_reg: bcore1 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vddsoc_reg: bcore2 { - regulator-min-microvolt = <730000>; - regulator-max-microvolt = <1380000>; - regulator-always-on; - }; - - vdd_ddr3_reg: bpro { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - vdd_3v3_reg: bperi { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_buckmem_reg: bmem { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_eth_reg: bio { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vdd_eth_io_reg: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_mx6_snvs_reg: ldo5 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vdd_3v3_pmic_io_reg: ldo6 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd0_reg: ldo9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_sd1_reg: ldo10 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_mx6_high_reg: ldo11 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - }; - - da9063_rtc: rtc { - compatible = "dlg,da9063-rtc"; - }; - - da9063_wdog: watchdog { - compatible = "dlg,da9063-watchdog"; - }; - - onkey { - compatible = "dlg,da9063-onkey"; - status = "disabled"; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; -}; - -&iomuxc { - imx6q-phytec-pfla02 { - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 - MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 - MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* CS0 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* Reset GPIO */ - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000>; /* PMIC interrupt */ - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbh1_vbus: usbh1vbusgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - >; - }; - - pinctrl_usdhc3_cdwp: usdhc3cdwp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - >; - }; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 - MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 - MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 - MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 - >; - }; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>; - status = "disabled"; -}; - -®_arm { - vin-supply = <&vddcore_reg>; -}; - -®_pu { - vin-supply = <&vddsoc_reg>; -}; - -®_soc { - vin-supply = <&vddsoc_reg>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "disabled"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "disabled"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "disabled"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_sd1_reg>; - status = "disabled"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3 - &pinctrl_usdhc3_cdwp>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_sd0_reg>; - status = "disabled"; -}; - -&wdog1 { - /* - * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also - * used for reboot, does not reset all external PMIC voltages on reset. - */ - status = "disabled"; -}; diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts deleted file mode 100644 index 6a9c10decf5..00000000000 --- a/arch/arm/dts/imxrt1050-evk.dts +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> - */ - -/dts-v1/; -#include "imxrt1050.dtsi" -#include "imxrt1050-pinfunc.h" - -/ { - model = "NXP IMXRT1050-evk board"; - compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; - - chosen { - stdout-path = &lpuart1; - }; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - mmc0 = &usdhc1; - serial0 = &lpuart1; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x2000000>; - }; -}; - -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 - MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 - MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 - MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 - MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 - >; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc0>; - pinctrl-1 = <&pinctrl_usdhc0>; - pinctrl-2 = <&pinctrl_usdhc0>; - pinctrl-3 = <&pinctrl_usdhc0>; - cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - status = "okay"; -}; diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h deleted file mode 100644 index 22c14a3262a..00000000000 --- a/arch/arm/dts/imxrt1050-pinfunc.h +++ /dev/null @@ -1,993 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> - */ - -#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H -#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H - -#define IMX_PAD_SION 0x40000000 - -/* - * The pin function ID is a tuple of - * <mux_reg conf_reg input_reg mux_mode input_val> - */ - -#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4 -#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1 - -#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1 - -#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1 -#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3 -#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4 - -#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4 - -#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3 -#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3 - -#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3 - -#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1 - -#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2 - -#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3 - -#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2 -#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0 - -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0 -#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0 - -#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */ diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi deleted file mode 100644 index a25eae9bd38..00000000000 --- a/arch/arm/dts/imxrt1050.dtsi +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> - */ - -#include "armv7-m.dtsi" -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/imxrt1050-clock.h> -#include <dt-bindings/gpio/gpio.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - clocks { - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - osc3M: osc3M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <3000000>; - }; - }; - - soc { - lpuart1: serial@40184000 { - compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x40184000 0x4000>; - interrupts = <20>; - clocks = <&clks IMXRT1050_CLK_LPUART1>; - clock-names = "ipg"; - status = "disabled"; - }; - - iomuxc: pinctrl@401f8000 { - compatible = "fsl,imxrt1050-iomuxc"; - reg = <0x401f8000 0x4000>; - fsl,mux_mask = <0x7>; - }; - - anatop: anatop@400d8000 { - compatible = "fsl,imxrt-anatop"; - reg = <0x400d8000 0x4000>; - }; - - clks: clock-controller@400fc000 { - compatible = "fsl,imxrt1050-ccm"; - reg = <0x400fc000 0x4000>; - interrupts = <95>, <96>; - clocks = <&osc>; - clock-names = "osc"; - #clock-cells = <1>; - assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, - <&clks IMXRT1050_CLK_PLL1_BYPASS>, - <&clks IMXRT1050_CLK_PLL2_BYPASS>, - <&clks IMXRT1050_CLK_PLL3_BYPASS>, - <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, - <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, - <&clks IMXRT1050_CLK_PLL1_ARM>, - <&clks IMXRT1050_CLK_PLL2_SYS>, - <&clks IMXRT1050_CLK_PLL3_USB_OTG>, - <&clks IMXRT1050_CLK_PLL3_USB_OTG>, - <&clks IMXRT1050_CLK_PLL2_SYS>; - }; - - edma1: dma-controller@400e8000 { - #dma-cells = <2>; - compatible = "fsl,imx7ulp-edma"; - reg = <0x400e8000 0x4000>, - <0x400ec000 0x4000>; - dma-channels = <32>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, - <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; - clock-names = "dma", "dmamux0"; - clocks = <&clks IMXRT1050_CLK_DMA>, - <&clks IMXRT1050_CLK_DMA_MUX>; - }; - - usdhc1: mmc@402c0000 { - compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x402c0000 0x4000>; - interrupts = <110>; - clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, - <&clks IMXRT1050_CLK_AHB_PODF>, - <&clks IMXRT1050_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,wp-controller; - no-1-8-v; - max-frequency = <4000000>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - gpio1: gpio@401b8000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401b8000 0x4000>; - interrupts = <80>, <81>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@401bc000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401bc000 0x4000>; - interrupts = <82>, <83>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@401c0000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401c0000 0x4000>; - interrupts = <84>, <85>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@401c4000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x401c4000 0x4000>; - interrupts = <86>, <87>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@400c0000 { - compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; - reg = <0x400c0000 0x4000>; - interrupts = <88>, <89>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpt: timer@401ec000 { - compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; - reg = <0x401ec000 0x4000>; - interrupts = <100>; - clocks = <&osc3M>; - clock-names = "per"; - }; - }; -}; diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi index 8f3c3a185ae..c68a48678a2 100644 --- a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi @@ -72,6 +72,14 @@ bootph-all; }; +&main_i2c0 { + bootph-all; +}; + +&main_i2c0_pins_default { + bootph-all; +}; + &main_mmc1_pins_default { bootph-all; }; diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi index b6d2c816acc..55337179f9f 100644 --- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi @@ -14,6 +14,24 @@ spi0 = &ospi0; }; + sysinfo { + compatible = "siemens,sysinfo-iot2050"; + /* TI_SRAM_SCRATCH_BOARD_EEPROM_START */ + offset = <0x40280000>; + bootph-all; + + smbios { + system { + manufacturer = "SIEMENS AG"; + product = "SIMATIC IOT2050"; + }; + + baseboard { + manufacturer = "SIEMENS AG"; + }; + }; + }; + leds { bootph-all; status-led-red { diff --git a/arch/arm/dts/mt7981-emmc-rfb.dts b/arch/arm/dts/mt7981-emmc-rfb.dts index d6590f01cf8..ebfcee5a2ea 100644 --- a/arch/arm/dts/mt7981-emmc-rfb.dts +++ b/arch/arm/dts/mt7981-emmc-rfb.dts @@ -47,8 +47,8 @@ status = "okay"; mediatek,gmac-id = <0>; phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + mediatek,switch = "auto"; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -56,7 +56,7 @@ }; }; -&pinctrl { +&pio { spic_pins: spi1-pins-func-1 { mux { function = "spi"; diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts index d6ebd6539c3..17e6b5af7a2 100644 --- a/arch/arm/dts/mt7981-rfb.dts +++ b/arch/arm/dts/mt7981-rfb.dts @@ -38,8 +38,8 @@ status = "okay"; mediatek,gmac-id = <0>; phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + mediatek,switch = "auto"; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -47,7 +47,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7981-sd-rfb.dts b/arch/arm/dts/mt7981-sd-rfb.dts index 2adbc374725..672124657ca 100644 --- a/arch/arm/dts/mt7981-sd-rfb.dts +++ b/arch/arm/dts/mt7981-sd-rfb.dts @@ -47,8 +47,8 @@ status = "okay"; mediatek,gmac-id = <0>; phy-mode = "2500base-x"; - mediatek,switch = "mt7531"; - reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; + mediatek,switch = "auto"; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -56,7 +56,7 @@ }; }; -&pinctrl { +&pio { spic_pins: spi1-pins-func-1 { mux { function = "spi"; diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi index 2844ab010de..5b4cadc22f7 100644 --- a/arch/arm/dts/mt7981.dtsi +++ b/arch/arm/dts/mt7981.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> #include <dt-bindings/clock/mt7981-clk.h> #include <dt-bindings/reset/mt7629-reset.h> #include <dt-bindings/pinctrl/mt65xx.h> @@ -106,7 +107,7 @@ bootph-all; }; - pinctrl: pinctrl@11d00000 { + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0x11d00000 0x1000>, <0x11c00000 0x1000>, @@ -117,13 +118,11 @@ <0x11f00000 0x1000>, <0x11f10000 0x1000>, <0x1000b000 0x1000>; - reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base", - "iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base", - "iocfg_tm_base", "iocfg_tl_base", "eint"; - gpio: gpio-controller { - gpio-controller; - #gpio-cells = <2>; - }; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", + "iocfg_rb", "iocfg_lb", "iocfg_bl", + "iocfg_tm", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; }; pwm: pwm@10048000 { @@ -317,4 +316,86 @@ status = "disabled"; }; + xhci: xhci@11200000 { + compatible = "mediatek,mt7981-xhci", + "mediatek,mtk-xhci"; + reg = <0x11200000 0x2e00>, + <0x11203e00 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", + "ref_ck", + "mcu_ck", + "dma_ck", + "xhci_ck"; + mediatek,u3p-dis-msk = <0x1>; + status = "okay"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + reg = <0x11280000 0x4000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; + + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + }; + }; + + usbtphy: usb-phy@11e10000 { + compatible = "mediatek,mt7981", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + u2port0: usb-phy@11e10000 { + reg = <0x11e10000 0x700>; + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@11e10700 { + reg = <0x11e10700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + status = "okay"; + }; + }; }; diff --git a/arch/arm/dts/mt7986-u-boot.dtsi b/arch/arm/dts/mt7986-u-boot.dtsi index 096b97371b8..71e83304c74 100644 --- a/arch/arm/dts/mt7986-u-boot.dtsi +++ b/arch/arm/dts/mt7986-u-boot.dtsi @@ -28,6 +28,6 @@ bootph-all; }; -&pinctrl { +&pio { bootph-all; }; diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi index f871f2394c5..b2c57098a5e 100644 --- a/arch/arm/dts/mt7986.dtsi +++ b/arch/arm/dts/mt7986.dtsi @@ -122,7 +122,7 @@ #clock-cells = <1>; }; - pinctrl: pinctrl@1001f000 { + pio: pinctrl@1001f000 { compatible = "mediatek,mt7986-pinctrl"; reg = <0x1001f000 0x1000>, <0x11c30000 0x1000>, @@ -132,13 +132,11 @@ <0x11f00000 0x1000>, <0x11f10000 0x1000>, <0x1000b000 0x1000>; - reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", - "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", - "iocfg_tl_base", "eint"; - gpio: gpio-controller { - gpio-controller; - #gpio-cells = <2>; - }; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", + "iocfg_lt", "iocfg_lb", "iocfg_tr", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; }; pwm: pwm@10048000 { diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts index c156a813634..e01ae4c3dc7 100644 --- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts +++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts @@ -38,12 +38,12 @@ factory { label = "reset"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; }; wps { label = "wps"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; }; }; @@ -52,12 +52,12 @@ led_status_green: green { label = "green:status"; - gpios = <&gpio 69 GPIO_ACTIVE_HIGH>; + gpios = <&pio 69 GPIO_ACTIVE_HIGH>; }; led_status_blue: blue { label = "blue:status"; - gpios = <&gpio 86 GPIO_ACTIVE_HIGH>; + gpios = <&pio 86 GPIO_ACTIVE_HIGH>; }; }; @@ -78,7 +78,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -86,7 +86,7 @@ }; }; -&pinctrl { +&pio { spic_pins: spi1-pins-func-1 { mux { function = "spi"; diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts index 67d14a99dae..d4bbb23204a 100644 --- a/arch/arm/dts/mt7986a-rfb.dts +++ b/arch/arm/dts/mt7986a-rfb.dts @@ -57,7 +57,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -65,7 +65,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7986a-sd-rfb.dts b/arch/arm/dts/mt7986a-sd-rfb.dts index 4f8fa70ec99..11823e05bda 100644 --- a/arch/arm/dts/mt7986a-sd-rfb.dts +++ b/arch/arm/dts/mt7986a-sd-rfb.dts @@ -49,7 +49,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -57,7 +57,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts index f98b04ab140..0a731fe87fd 100644 --- a/arch/arm/dts/mt7986b-rfb.dts +++ b/arch/arm/dts/mt7986b-rfb.dts @@ -48,7 +48,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -56,7 +56,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-sd-rfb.dts index ec80a2fb710..e5fb4d73e70 100644 --- a/arch/arm/dts/mt7986b-sd-rfb.dts +++ b/arch/arm/dts/mt7986b-sd-rfb.dts @@ -49,7 +49,7 @@ mediatek,gmac-id = <0>; phy-mode = "2500base-x"; mediatek,switch = "mt7531"; - reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; fixed-link { speed = <2500>; @@ -57,7 +57,7 @@ }; }; -&pinctrl { +&pio { spi_flash_pins: spi0-pins-func-1 { mux { function = "flash"; diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts index 2579d7099fb..1694ef8d9c3 100644 --- a/arch/arm/dts/mt7988-rfb.dts +++ b/arch/arm/dts/mt7988-rfb.dts @@ -80,7 +80,7 @@ status = "disabled"; }; -&pinctrl { +&pio { i2c1_pins: i2c1-pins { mux { function = "i2c"; diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts index 38727a271b2..63e923137c2 100644 --- a/arch/arm/dts/mt7988-sd-rfb.dts +++ b/arch/arm/dts/mt7988-sd-rfb.dts @@ -53,7 +53,7 @@ }; }; -&pinctrl { +&pio { i2c1_pins: i2c1-pins { mux { function = "i2c"; diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi index f2bfde547e6..2d57c6f5709 100644 --- a/arch/arm/dts/mt7988.dtsi +++ b/arch/arm/dts/mt7988.dtsi @@ -110,7 +110,7 @@ #clock-cells = <1>; }; - pinctrl: pinctrl@1001f000 { + pio: pinctrl@1001f000 { compatible = "mediatek,mt7988-pinctrl"; reg = <0 0x1001f000 0 0x1000>, <0 0x11c10000 0 0x1000>, @@ -119,13 +119,11 @@ <0 0x11e00000 0 0x1000>, <0 0x11f00000 0 0x1000>, <0 0x1000b000 0 0x1000>; - reg-names = "gpio_base", "iocfg_tr_base", "iocfg_br_base", - "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", + reg-names = "gpio", "iocfg_tr", "iocfg_br", + "iocfg_rb", "iocfg_lb", "iocfg_tl", "eint"; - gpio: gpio-controller { - gpio-controller; - #gpio-cells = <2>; - }; + gpio-controller; + #gpio-cells = <2>; }; sgmiisys0: syscon@10060000 { diff --git a/arch/arm/dts/r8a779f4-s4sk-u-boot.dtsi b/arch/arm/dts/r8a779f4-s4sk-u-boot.dtsi new file mode 100644 index 00000000000..c2c743ba501 --- /dev/null +++ b/arch/arm/dts/r8a779f4-s4sk-u-boot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the S4SK board + * + * Copyright (C) 2024-2025 Renesas Electronics Corp. + */ + +#include "r8a779f0-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + /delete-property/ ethernet0; + }; +}; + +&pfc { + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <40000000>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <40000000>; + }; +}; diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/arch/arm/dts/rk3036-evb-u-boot.dtsi index ef7e0207c3e..f8857c736d0 100644 --- a/arch/arm/dts/rk3036-sdk-u-boot.dtsi +++ b/arch/arm/dts/rk3036-evb-u-boot.dtsi @@ -1,13 +1,13 @@ #include "rk3036-u-boot.dtsi" -&uart2 { +&grf { bootph-all; }; -&grf { +&pinctrl { bootph-all; }; -&pinctrl { +&uart2 { bootph-all; }; diff --git a/arch/arm/dts/rk3036-kylin-u-boot.dtsi b/arch/arm/dts/rk3036-kylin-u-boot.dtsi new file mode 100644 index 00000000000..f8857c736d0 --- /dev/null +++ b/arch/arm/dts/rk3036-kylin-u-boot.dtsi @@ -0,0 +1,13 @@ +#include "rk3036-u-boot.dtsi" + +&grf { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&uart2 { + bootph-all; +}; diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts deleted file mode 100644 index 3493150df92..00000000000 --- a/arch/arm/dts/rk3036-sdk.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rk3036.dtsi" - -/ { - model = "SDK-RK3036"; - compatible = "sdk,sdk-rk3036", "rockchip,rk3036"; - - chosen { - stdout-path = &uart2; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_host: vcc5v0-host-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&i2c1 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&usb_host { - vbus-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&pinctrl { - usb_otg { - otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi deleted file mode 100644 index 75588de4863..00000000000 --- a/arch/arm/dts/rk3036.dtsi +++ /dev/null @@ -1,439 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3036-cru.h> -#include "skeleton.dtsi" - -/ { - compatible = "rockchip,rk3036"; - - interrupt-parent = <&gic>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - i2c1 = &i2c1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3036-smp"; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - resets = <&cru SRST_CORE0>; - }; - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - arm,pl330-broken-no-flushp; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050000 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050010 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - sram: sram@10080000 { - compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; - reg = <0x10080000 0x2000>; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x10139000 0x1000>, - <0x1013a000 0x1000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = <GIC_PPI 9 0xf04>; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3036-grf", "syscon"; - reg = <0x20008000 0x1000>; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - g-use-dma; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - status = "disabled"; - }; - - emmc: dwmmc@1021c000 { - compatible = "rockchip,rk3288-dw-mshc"; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; - dmas = <&pdma 12>; - dma-names = "rx-tx"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x1021c000 0x4000>; - broken-cd; - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - disable-wp; - fifo-mode; - non-removable; - num-slots = <1>; - default-sample-phase = <158>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - }; - - sdmmc: dwmmc@10214000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3036-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>; - /* - <1 28 RK_FUNC_2 &pcfg_pull_up>, - <1 29 RK_FUNC_2 &pcfg_pull_up>, - <1 30 RK_FUNC_2 &pcfg_pull_up>, - <1 31 RK_FUNC_2 &pcfg_pull_up>; - */ - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, - <0 17 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, - <2 23 RK_FUNC_1 &pcfg_pull_none>; - }; - /* no rts / cts for uart1 */ - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 1 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 27 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; -}; diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 3b684fc63d5..60de9140226 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -17,6 +17,7 @@ /{ model = "Microchip SAM9X60 SoC"; compatible = "microchip,sam9x60"; + interrupt-parent = <&aic>; aliases { serial0 = &dbgu; @@ -122,8 +123,6 @@ assigned-clock-rates = <100000000>; assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */ bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci0>; }; sdhci1: sdhci-host@90000000 { @@ -135,8 +134,6 @@ assigned-clock-rates = <100000000>; assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */ bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1>; }; apb { @@ -176,8 +173,6 @@ macb0: ethernet@f802c000 { compatible = "cdns,sam9x60-macb", "cdns,macb"; reg = <0xf802c000 0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_macb0_rmii>; clock-names = "hclk", "pclk"; clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; status = "disabled"; @@ -199,11 +194,17 @@ reg = <0xffffea00 0x100>; }; + aic: interrupt-controller@fffff100 { + compatible = "microchip,sam9x60-aic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffff100 0x100>; + atmel,external-irqs = <31>; + }; + dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dbgu>; clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; clock-names = "usart"; }; @@ -211,99 +212,63 @@ pinctrl: pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; - compatible = "microchip,sam9x60-pinctrl", "simple-bus"; + compatible = "microchip,sam9x60-pinctrl", "simple-mfd"; ranges = <0xfffff400 0xfffff400 0x800>; - reg = <0xfffff400 0x200 /* pioA */ - 0xfffff600 0x200 /* pioB */ - 0xfffff800 0x200 /* pioC */ - 0xfffffa00 0x200>; /* pioD */ - - /* shared pinctrl settings */ - dbgu { - pinctrl_dbgu: dbgu-0 { - atmel,pins = - <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP - AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; - }; - }; - macb0 { - pinctrl_macb0_rmii: macb0_rmii-0 { - atmel,pins = - <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ - AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ - AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ - AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ - AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ - AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ - AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ - AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ - AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ - AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ - }; + /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xffe03fff 0xef00019d /* pioA */ + 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ + 0xffffffff 0xffffffff 0xf83fffff /* pioC */ + 0x003fffff 0x003f8000 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; - sdhci0 { - pinctrl_sdhci0: sdhci0 { - atmel,pins = - <AT91_PIOA 17 AT91_PERIPH_A - (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */ - AT91_PIOA 16 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */ - AT91_PIOA 15 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */ - AT91_PIOA 18 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */ - AT91_PIOA 19 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */ - AT91_PIOA 20 AT91_PERIPH_A - (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */ - }; + pioB: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <26>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; - sdhci1 { - pinctrl_sdhci1: sdhci1 { - atmel,pins = - <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */ - AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */ - AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */ - AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */ - AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */ - AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */ - }; + pioC: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; - }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - #gpio-cells = <2>; - gpio-controller; - clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; - }; - pioB: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - #gpio-cells = <2>; - gpio-controller; - clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - #gpio-cells = <2>; - gpio-controller; - clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; - }; - - pioD: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x200>; - #gpio-cells = <2>; - gpio-controller; - clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + pioD: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x200>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + #gpio-lines = <22>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + }; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index 74016f5e288..6521585ee9c 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -78,79 +78,15 @@ }; }; }; - - pinctrl { - nand { - pinctrl_nand_oe_we: nand-oe-we-0 { - atmel,pins = - <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; - }; - - pinctrl_nand_rb: nand-rb-0 { - atmel,pins = - <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; - }; - - pinctrl_nand_cs: nand-cs-0 { - atmel,pins = - <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; - }; - }; - - ebi { - pinctrl_ebi_data_0_7: ebi-data-lsb-0 { - atmel,pins = - <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; - }; - - pinctrl_ebi_addr_nand: ebi-addr-0 { - atmel,pins = - <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) - AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; - }; - }; - - pinctrl_qspi: qspi { - atmel,pins = - <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE - AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE - AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP - AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP - AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP - AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; - }; - - pinctrl_flx0: flx0_default { - atmel,pins = - <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE - AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; - }; - - pinctrl_onewire_tm_default: onewire_tm_default { - atmel,pins = - <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; - }; - - usb1 { - pinctrl_usb_default: usb_default { - atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE - AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; - }; - }; - - }; }; }; }; +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; +}; + &ebi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>; @@ -218,9 +154,148 @@ &macb0 { phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; status = "okay"; }; +&pinctrl { + /* shared pinctrl settings */ + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + qspi { + pinctrl_qspi: qspi { + atmel,pins = + <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; + }; + }; + + nand { + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins = + <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + }; + + ebi { + pinctrl_ebi_data_0_7: ebi-data-lsb-0 { + atmel,pins = + <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; + }; + + pinctrl_ebi_addr_nand: ebi-addr-0 { + atmel,pins = + <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS) + AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>; + }; + }; + + flexcom { + pinctrl_flx0: flx0_default { + atmel,pins = + <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ + AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */ + AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ + AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ + AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ + AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */ + }; + }; + + pinctrl_onewire_tm_default: onewire_tm_default { + atmel,pins = + <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; + }; + + sdhci0 { + pinctrl_sdhci0: sdhci0 { + atmel,pins = + <AT91_PIOA 17 AT91_PERIPH_A + (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */ + AT91_PIOA 16 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */ + AT91_PIOA 15 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */ + AT91_PIOA 18 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */ + AT91_PIOA 19 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */ + AT91_PIOA 20 AT91_PERIPH_A + (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */ + }; + }; + + sdhci1 { + pinctrl_sdhci1: sdhci1 { + atmel,pins = + <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */ + AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */ + AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */ + AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */ + AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */ + AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */ + }; + }; + + usb1 { + pinctrl_usb_default: usb_default { + atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE + AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; + }; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0>; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; +}; + &usb1 { num-ports = <3>; atmel,vbus-gpio = <0 diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi index 4c03a302ec7..10d6e74586d 100644 --- a/arch/arm/dts/sama5d3.dtsi +++ b/arch/arm/dts/sama5d3.dtsi @@ -492,12 +492,6 @@ 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ >; - reg = <0xfffff200 0x100 /* pioA */ - 0xfffff400 0x100 /* pioB */ - 0xfffff600 0x100 /* pioC */ - 0xfffff800 0x100 /* pioD */ - 0xfffffa00 0x100 /* pioE */ - >; /* shared pinctrl settings */ adc0 { @@ -873,66 +867,66 @@ AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ }; }; - }; - pioA: gpio@fffff200 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff200 0x100>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - bootph-all; - }; + pioA: gpio@fffff200 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + bootph-all; + }; - pioB: gpio@fffff400 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x100>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - bootph-all; - }; + pioB: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + bootph-all; + }; - pioC: gpio@fffff600 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x100>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; + pioC: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; - pioD: gpio@fffff800 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x100>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - bootph-all; - }; + pioD: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + bootph-all; + }; - pioE: gpio@fffffa00 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfffffa00 0x100>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioE_clk>; - bootph-all; + pioE: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioE_clk>; + bootph-all; + }; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi index 5e2c9a1db2f..482cf03e61b 100644 --- a/arch/arm/dts/sama5d4.dtsi +++ b/arch/arm/dts/sama5d4.dtsi @@ -1361,62 +1361,6 @@ status = "disabled"; }; - pioA: gpio@fc06a000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06a000 0x100>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fc06b000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06b000 0x100>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fc06c000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06c000 0x100>; - interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - bootph-all; - }; - - pioD: gpio@fc068000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc068000 0x100>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioD_clk>; - }; - - pioE: gpio@fc06d000 { - compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; - reg = <0xfc06d000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioE_clk>; - }; - pinctrl@fc06a000 { bootph-all; #address-cells = <1>; @@ -1433,12 +1377,62 @@ 0x0003ff00 0x8002a800 0x00000000 /* pioD */ 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ >; - reg = < 0xfc06a000 0x100 - 0xfc06b000 0x100 - 0xfc06c000 0x100 - 0xfc068000 0x100 - 0xfc06d000 0x100 - >; + + pioA: gpio@fc06a000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06a000 0x100>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fc06b000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06b000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fc06c000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06c000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + bootph-all; + }; + + pioD: gpio@fc068000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc068000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioD_clk>; + }; + + pioE: gpio@fc06d000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06d000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioE_clk>; + }; /* pinctrl pin settings */ adc0 { diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index a8167e5c14a..8d6503dd091 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -3,6 +3,7 @@ * U-Boot additions * * Copyright (C) 2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_soc64_fit-u-boot.dtsi" @@ -13,6 +14,659 @@ #size-cells = <2>; bootph-all; }; + + soc { + bootph-all; + + socfpga_ccu_config: socfpga-ccu-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUMIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* DII2_GICREGS */ + <0x00000424 0x0001d000 0xffffffff>, + <0x00000428 0x00000000 0x000000ff>, + <0x00000420 0xc0800400 0xc1f03e1f>, + /* NCAIU0_LWSOC2FPGA */ + <0x00000444 0x00020000 0xffffffff>, + <0x00000448 0x00000000 0x000000ff>, + <0x00000440 0xc1100006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_1G */ + <0x00000454 0x00040000 0xffffffff>, + <0x00000458 0x00000000 0x000000ff>, + <0x00000450 0xc1200006 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_16G */ + <0x00000474 0x00400000 0xffffffff>, + <0x00000478 0x00000000 0x000000ff>, + <0x00000470 0xc1600006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_256G */ + <0x00000494 0x04000000 0xffffffff>, + <0x00000498 0x00000000 0x000000ff>, + <0x00000490 0xc1a00006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* PSS */ + <0x00000404 0x00010000 0xffffffff>, + <0x00000408 0x00000000 0x000000ff>, + <0x00000400 0xC0F00000 0xc1f03e1f>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* NCAIU0_LWSOC2FPGA */ + <0x00000444 0x00020000 0xffffffff>, + <0x00000448 0x00000000 0x000000ff>, + <0x00000440 0xc1100006 0xc1f03e1f>, + /* NCAIU0_SOC2FPGA_1G */ + <0x00000454 0x00040000 0xffffffff>, + <0x00000458 0x00000000 0x000000ff>, + <0x00000450 0xc1200006 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_16G */ + <0x00000474 0x00400000 0xffffffff>, + <0x00000478 0x00000000 0x000000ff>, + <0x00000470 0xc1600006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* NCAIU0_SOC2FPGA_256G */ + <0x00000494 0x04000000 0xffffffff>, + <0x00000498 0x00000000 0x000000ff>, + <0x00000490 0xc1a00006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* SMMU */ + i_ccu_ncaiu2@1c003000 { + reg = <0x1c003000 0x00001000>; + intel,offset-settings = + /* NCAIU2MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3MIFSR */ + <0x000003c4 0x00000000 0x07070777>, + /* DII1_MPFEREGS */ + <0x00000414 0x00018000 0xffffffff>, + <0x00000418 0x00000000 0x000000ff>, + <0x00000410 0xc0e00200 0xc1f03e1f>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUMIFSR0 */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUMIFSR1 */ + <0x000003c4 0x00000000 0x07070777>, + /* DMI_SDRAM_2G */ + <0x00000464 0x00080000 0xffffffff>, + <0x00000468 0x00000000 0x000000ff>, + /* DMI_SDRAM_30G */ + <0x00000484 0x00800000 0xffffffff>, + <0x00000488 0x00000000 0x000000ff>, + /* DMI_SDRAM_480G */ + <0x000004a4 0x08000000 0xffffffff>, + <0x000004a8 0x00000000 0x000000ff>; + bootph-all; + }; + + /* DMI0 */ + i_ccu_dmi0@1c007000 { + reg = <0x1c007000 0x00001000>; + intel,offset-settings = + /* DMIUSMCTCR */ + <0x00000300 0x00000001 0x00000003>, + <0x00000300 0x00000003 0x00000003>; + bootph-all; + }; + + /* DMI1 */ + i_ccu_dmi0@1c008000 { + reg = <0x1c008000 0x00001000>; + intel,offset-settings = + /* DMIUSMCTCR */ + <0x00000300 0x00000001 0x00000003>, + <0x00000300 0x00000003 0x00000003>; + bootph-all; + }; + }; + + socfpga_firewall_config: socfpga-firewall-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* L4 peripherals firewall */ + noc_fw_l4_per@10d21000 { + reg = <0x10d21000 0x0000008c>; + intel,offset-settings = + /* NAND */ + <0x00000000 0x01010001 0x01010001>, + /* USB0 */ + <0x0000000c 0x01010001 0x01010001>, + /* USB1 */ + <0x00000010 0x01010001 0x01010001>, + /* SPI_MAIN0 */ + <0x0000001c 0x01010301 0x01010301>, + /* SPI_MAIN1 */ + <0x00000020 0x01010301 0x01010301>, + /* SPI_SECONDARY0 */ + <0x00000024 0x01010301 0x01010301>, + /* SPI_SECONDARY1 */ + <0x00000028 0x01010301 0x01010301>, + /* EMAC0 */ + <0x0000002c 0x01010001 0x01010001>, + /* EMAC1 */ + <0x00000030 0x01010001 0x01010001>, + /* EMAC2 */ + <0x00000034 0x01010001 0x01010001>, + /* SDMMC */ + <0x00000040 0x01010001 0x01010001>, + /* GPIO0 */ + <0x00000044 0x01010301 0x01010301>, + /* GPIO1 */ + <0x00000048 0x01010301 0x01010301>, + /* I2C0 */ + <0x00000050 0x01010301 0x01010301>, + /* I2C1 */ + <0x00000054 0x01010301 0x01010301>, + /* I2C2 */ + <0x00000058 0x01010301 0x01010301>, + /* I2C3 */ + <0x0000005c 0x01010301 0x01010301>, + /* I2C4 */ + <0x00000060 0x01010301 0x01010301>, + /* SP_TIMER0 */ + <0x00000064 0x01010301 0x01010301>, + /* SP_TIMER1 */ + <0x00000068 0x01010301 0x01010301>, + /* UART0 */ + <0x0000006c 0x01010301 0x01010301>, + /* UART1 */ + <0x00000070 0x01010301 0x01010301>, + /* I3C0 */ + <0x00000074 0x01010301 0x01010301>, + /* I3C1 */ + <0x00000078 0x01010301 0x01010301>, + /* DMA0 */ + <0x0000007c 0x01010001 0x01010001>, + /* DMA1 */ + <0x00000080 0x01010001 0x01010001>, + /* COMBO_PHY */ + <0x00000084 0x01010001 0x01010001>, + /* NAND_SDMA */ + <0x00000088 0x01010301 0x01010301>; + bootph-all; + }; + + /* L4 system firewall */ + noc_fw_l4_sys@10d21100 { + reg = <0x10d21100 0x00000098>; + intel,offset-settings = + /* DMA_ECC */ + <0x00000008 0x01010001 0x01010001>, + /* EMAC0RX_ECC */ + <0x0000000c 0x01010001 0x01010001>, + /* EMAC0TX_ECC */ + <0x00000010 0x01010001 0x01010001>, + /* EMAC1RX_ECC */ + <0x00000014 0x01010001 0x01010001>, + /* EMAC1TX_ECC */ + <0x00000018 0x01010001 0x01010001>, + /* EMAC2RX_ECC */ + <0x0000001c 0x01010001 0x01010001>, + /* EMAC2TX_ECC */ + <0x00000020 0x01010001 0x01010001>, + /* NAND_ECC */ + <0x0000002c 0x01010001 0x01010001>, + /* NAND_READ_ECC */ + <0x00000030 0x01010001 0x01010001>, + /* NAND_WRITE_ECC */ + <0x00000034 0x01010001 0x01010001>, + /* OCRAM_ECC */ + <0x00000038 0x01010001 0x01010001>, + /* SDMMC_ECC */ + <0x00000040 0x01010001 0x01010001>, + /* USB0_ECC */ + <0x00000044 0x01010001 0x01010001>, + /* USB1_CACHEECC */ + <0x00000048 0x01010001 0x01010001>, + /* CLOCK_MANAGER */ + <0x0000004c 0x01010001 0x01010001>, + /* IO_MANAGER */ + <0x00000054 0x01010001 0x01010001>, + /* RESET_MANAGER */ + <0x00000058 0x01010001 0x01010001>, + /* SYSTEM_MANAGER */ + <0x0000005c 0x01010001 0x01010001>, + /* OSC0_TIMER */ + <0x00000060 0x01010301 0x01010301>, + /* OSC1_TIMER0*/ + <0x00000064 0x01010301 0x01010301>, + /* WATCHDOG0 */ + <0x00000068 0x01010301 0x01010301>, + /* WATCHDOG1 */ + <0x0000006c 0x01010301 0x01010301>, + /* WATCHDOG2 */ + <0x00000070 0x01010301 0x01010301>, + /* WATCHDOG3 */ + <0x00000074 0x01010301 0x01010301>, + /* DAP */ + <0x00000078 0x03010001 0x03010001>, + /* WATCHDOG4 */ + <0x0000007c 0x01010301 0x01010301>, + /* POWER_MANAGER */ + <0x00000080 0x01010001 0x01010001>, + /* USB1_RXECC */ + <0x00000084 0x01010001 0x01010001>, + /* USB1_TXECC */ + <0x00000088 0x01010001 0x01010001>, + /* L4_NOC_PROBES */ + <0x00000090 0x01010001 0x01010001>, + /* L4_NOC_QOS */ + <0x00000094 0x01010001 0x01010001>; + bootph-all; + }; + + /* Light weight SoC2FPGA */ + noc_fw_lwsoc2fpga@10d21300 { + reg = <0x10d21300 0x0000004>; + intel,offset-settings = + /* LWSOC2FPGA_CSR */ + <0x00000000 0x0ffe0301 0x0ffe0301>; + bootph-all; + }; + + /* SoC2FPGA */ + noc_fw_soc2fpga@10d21200 { + reg = <0x10d21200 0x0000004>; + intel,offset-settings = + /* SOC2FPGA_CSR */ + <0x00000000 0x0ffe0301 0x0ffe0301>; + bootph-all; + }; + + /* TCU */ + noc_fw_tcu@10d21400 { + reg = <0x10d21400 0x0000004>; + intel,offset-settings = + /* TCU_CSR */ + <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + }; + + socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUAMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* SMMU */ + i_ccu_ncaiu2@1c003000 { + reg = <0x1c003000 0x00001000>; + intel,offset-settings = + /* NCAIU2AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3AMIGR */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR0 */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR1 */ + <0x000003c0 0x00000003 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81300006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81700006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81b00006 0xc1f03e1f>; + bootph-all; + }; + }; + + socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* DSU */ + i_ccu_caiu0@1c000000 { + reg = <0x1c000000 0x00001000>; + intel,offset-settings = + /* CAIUAMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* FPGA2SOC */ + i_ccu_ncaiu0@1c001000 { + reg = <0x1c001000 0x00001000>; + intel,offset-settings = + /* NCAIU0AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* GIC_M */ + i_ccu_ncaiu1@1c002000 { + reg = <0x1c002000 0x00001000>; + intel,offset-settings = + /* NCAIU1AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* SMMU */ + i_ccu_ncaiu2@1c003000 { + reg = <0x1c003000 0x00001000>; + intel,offset-settings = + /* NCAIU2AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* PSS NOC */ + i_ccu_ncaiu3@1c004000 { + reg = <0x1c004000 0x00001000>; + intel,offset-settings = + /* NCAIU3AMIGR */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE0 */ + i_ccu_dce0@1c005000 { + reg = <0x1c005000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR0 */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + + /* DCE1 */ + i_ccu_dce1@1c006000 { + reg = <0x1c006000 0x00001000>; + intel,offset-settings = + /* DCEUAMIGR1 */ + <0x000003c0 0x00000001 0x0000001f>, + /* DMI_SDRAM_2G */ + <0x00000460 0x81200006 0xc1f03e1f>, + /* DMI_SDRAM_30G */ + <0x00000480 0x81600006 0xc1f03e1f>, + /* DMI_SDRAM_480G */ + <0x000004a0 0x81a00006 0xc1f03e1f>; + bootph-all; + }; + }; + + socfpga_smmu_secure_config: socfpga-smmu-secure-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* System manager */ + i_sys_mgt_sysmgr_csr@10d12000 { + reg = <0x10d12000 0x00000500>; + intel,offset-settings = + /* dma_tbu_stream_ctrl_reg_0_dma0 */ + <0x0000017c 0x00000000 0x0000003f>, + /* dma_tbu_stream_ctrl_reg_0_dma1 */ + <0x00000180 0x00000000 0x0000003f>, + /* sdm_tbu_stream_ctrl_reg_1_sdm */ + <0x00000184 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_usb2 */ + <0x00000188 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_sdmmc */ + <0x00000190 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_nand */ + <0x00000194 0x00000000 0x0000003f>, + /* io_tbu_stream_ctrl_reg_2_etr */ + <0x00000198 0x00000000 0x0000003f>, + /* tsn_tbu_stream_ctrl_reg_3_tsn0 */ + <0x0000019c 0x00000000 0x0000003f>, + /* tsn_tbu_stream_ctrl_reg_3_tsn1 */ + <0x000001a0 0x00000000 0x0000003f>, + /* tsn_tbu_stream_ctrl_reg_3_tsn2 */ + <0x000001a4 0x00000000 0x0000003f>; + bootph-all; + }; + }; + + socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* noc fw mpfe csr */ + i_noc_fw_mpfe_csr@18000d00 { + reg = <0x18000d00 0x00000100>; + intel,offset-settings = + /* mpfe scr io96b0 reg*/ + <0x00000000 0x00000001 0x00010101>, + /* mpfe scr io96b1 reg*/ + <0x00000004 0x00000001 0x00010101>, + /* mpfe scr noc csr*/ + <0x00000008 0x00000001 0x00010101>; + bootph-all; + }; + }; + }; }; &clkmgr { @@ -57,6 +711,13 @@ bootph-all; }; +&sdr { + compatible = "intel,sdr-ctl-agilex5"; + reg = <0x18000000 0x400000>; + resets = <&rst DDRSCH_RESET>; + bootph-all; +}; + &sysmgr { compatible = "altr,sys-mgr", "syscon"; bootph-all; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi index 03b55040497..788e44f724b 100644 --- a/arch/arm/dts/socfpga_agilex5.dtsi +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ /dts-v1/; @@ -544,6 +545,13 @@ status = "disabled"; }; + sdr: sdr@18000000 { + compatible = "intel,sdr-ctl-agilex5"; + reg = <0x18000000 0x400000>; + resets = <&rst DDRSCH_RESET>; + bootph-all; + }; + /* QSPI address not available yet */ qspi: spi@108d2000 { compatible = "cdns,qspi-nor"; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 9eb21d65428..e08dd5523f2 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -3,6 +3,7 @@ * U-Boot additions * * Copyright (C) 2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_agilex5-u-boot.dtsi" @@ -21,11 +22,38 @@ }; }; - memory { - /* 8GB */ - reg = <0 0x80000000 0 0x80000000>, - <8 0x80000000 1 0x80000000>; - }; + /* + * Both Memory base address and size default info is retrieved from HW setting. + * Reconfiguration / Overwrite these info can be done with examples below. + */ + /* + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>; + * }; + */ + /* + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x80000000>; + * }; + */ + /* + * Example for memory size with 32GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>; + * }; + */ + /* + * Example for memory size with 512GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>, + * <0x88 0x00000000 0x78 0x00000000>; + * }; + */ chosen { stdout-path = "serial0:115200n8"; @@ -122,3 +150,36 @@ bootph-all; }; +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts index 852e1e5ae3c..ca87e99f9fa 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk.dts +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -62,6 +62,10 @@ status = "okay"; }; +&i2c3 { + status = "okay"; +}; + &i3c0 { status = "okay"; }; diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi index 3b080ac7a1b..e9d7ec92281 100644 --- a/arch/arm/dts/stih410-b2260-u-boot.dtsi +++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi @@ -14,20 +14,30 @@ }; }; + clk_usb: clk-usb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + ohci0: usb@9a03c00 { compatible = "generic-ohci"; + clocks = <&clk_usb>; }; ehci0: usb@9a03e00 { compatible = "generic-ehci"; + clocks = <&clk_usb>; }; ohci1: usb@9a83c00 { compatible = "generic-ohci"; + clocks = <&clk_usb>; }; ehci1: usb@9a83e00 { compatible = "generic-ehci"; + clocks = <&clk_usb>; }; }; }; diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi index 376dcdf68fb..8a629bfe703 100644 --- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi +++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi @@ -4,16 +4,9 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include "tegra-u-boot.dtsi" +#include "tegra124-u-boot.dtsi" / { - host1x@50000000 { - bootph-all; - dc@54200000 { - bootph-all; - }; - }; - spi@7000d400 { spi-deactivate-delay = <500>; spi-max-frequency = <3000000>; diff --git a/arch/arm/dts/tegra124-u-boot.dtsi b/arch/arm/dts/tegra124-u-boot.dtsi index 7c119725528..6a02714a258 100644 --- a/arch/arm/dts/tegra124-u-boot.dtsi +++ b/arch/arm/dts/tegra124-u-boot.dtsi @@ -1,3 +1,16 @@ #include <config.h> #include "tegra-u-boot.dtsi" + +/ { + host1x@50000000 { + bootph-all; + dc@54200000 { + bootph-all; + }; + + dc@54240000 { + bootph-all; + }; + }; +}; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index ffec9cae09d..cac9b112302 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -136,6 +136,38 @@ status = "disabled"; }; + dsi@54300000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_DSIBLP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x54540000 0x00040000>; @@ -737,6 +769,13 @@ #thermal-sensor-cells = <1>; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra124-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; + #nvidia,mipi-calibrate-cells = <1>; + }; + dfll: clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0x70110000 0x100>, /* DFLL control */ diff --git a/arch/arm/dts/tegra20-acer-a500-picasso.dts b/arch/arm/dts/tegra20-acer-a500-picasso.dts new file mode 100644 index 00000000000..0c301483180 --- /dev/null +++ b/arch/arm/dts/tegra20-acer-a500-picasso.dts @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra20.dtsi" + +/ { + model = "Acer Iconia Tab A500"; + compatible = "acer,picasso", "nvidia,tegra20"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + usb1 = &usb3; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp", "lm1"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lsc0", + "lsc1", "lsck", "lsda", "lspi", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "csus", "dap1", + "dap4", "dte", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", + "sdc", "sdd", "slxc", "slxd", "slxk", + "spdi", "spdo", "uac", "uad", "uda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ate { + nvidia,pins = "ate", "dap2", "dap3", + "gmd", "owc", "spia", "spib", "spic", + "spid", "spie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + conf_crtp { + nvidia,pins = "crtp", "gmb", "slxa", "spig", + "spih"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_dte { + nvidia,pins = "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", + "lvp0"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_kbca { + nvidia,pins = "kbca", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", + "uab", "uca", "ucb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + drive_ddc { + nvidia,pins = "drive_ddc", + "drive_vi1", + "drive_sdio1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + drive_dbg { + nvidia,pins = "drive_dbg", + "drive_vi2", + "drive_at1", + "drive_ao1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + + state_i2cmux_ddc: pinmux-i2cmux-ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_idle: pinmux-i2cmux-idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux-i2cmux-pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + clock-frequency = <216000000>; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + avdd_usb: ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + }; + }; + }; + + usb1: usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb3: usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + sdmmc3: sdhci@c8000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 41667>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "tps658621-out32k"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + switch-rotation-lock { + label = "Rotate-lock"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; + linux,code = <SW_ROTATE_LOCK>; + }; + }; + + panel: panel { + compatible = "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + + display-timings { + timing@0 { + clock-frequency = <71200000>; + + hactive = <1280>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + + vactive = <800>; + vfront-porch = <4>; + vback-porch = <8>; + vsync-len = <3>; + }; + }; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 1177e2ab1f4..d5de1ecaf05 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -218,10 +218,29 @@ dsi@54300000 { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_DSIB>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 84>; + reset-names = "dsi"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; }; diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts index 3d9d8476c98..d5b63ef604b 100644 --- a/arch/arm/dts/zynqmp-binman-som.dts +++ b/arch/arm/dts/zynqmp-binman-som.dts @@ -13,6 +13,8 @@ / { binman: binman { multiple-images; + +#ifdef CONFIG_SPL fit-dtb.blob { filename = "fit-dtb.blob"; pad-byte = <0>; @@ -146,8 +148,11 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; - entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + load = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + hash { + algo = "md5"; + }; tee-os { optional; }; @@ -157,7 +162,9 @@ type = "flat_dt"; arch = "arm64"; compression = "none"; - load = <0x0 0x100000>; +#if CONFIG_XILINX_OF_BOARD_DTB_ADDR + load = /bits/ 64 <CONFIG_XILINX_OF_BOARD_DTB_ADDR>; +#endif hash { algo = "md5"; }; @@ -171,8 +178,13 @@ default = "conf-1"; conf-1 { description = "Multi DTB with TF-A/TEE"; +#if CONFIG_BL31_LOAD_ADDR firmware = "atf"; loadables = "tee", "uboot", "fdt"; +#else + firmware = "uboot"; + loadables = "fdt"; +#endif }; }; }; @@ -221,5 +233,6 @@ }; }; #endif +#endif }; }; diff --git a/arch/arm/dts/zynqmp-binman.dts b/arch/arm/dts/zynqmp-binman.dts index 675f6bf51eb..252c2ad552b 100644 --- a/arch/arm/dts/zynqmp-binman.dts +++ b/arch/arm/dts/zynqmp-binman.dts @@ -14,6 +14,7 @@ binman: binman { multiple-images; +#ifdef CONFIG_SPL /* u-boot.itb generation in a static way */ itb { filename = "u-boot.itb"; @@ -60,8 +61,11 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; - entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + load = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + hash { + algo = "md5"; + }; tee-os { optional; }; @@ -71,8 +75,10 @@ type = "flat_dt"; arch = "arm64"; compression = "none"; - load = <0x0 0x100000>; - hash-1 { +#if CONFIG_XILINX_OF_BOARD_DTB_ADDR + load = /bits/ 64 <CONFIG_XILINX_OF_BOARD_DTB_ADDR>; +#endif + hash { algo = "md5"; }; }; @@ -81,9 +87,15 @@ default = "@conf-DEFAULT-SEQ"; @conf-SEQ { description = "NAME"; +#if CONFIG_BL31_LOAD_ADDR firmware = "atf"; loadables = "tee", "uboot"; fdt = "fdt-SEQ"; +#else + firmware = "uboot"; + loadables = "fdt"; +#endif + }; }; }; @@ -134,8 +146,11 @@ arch = "arm64"; compression = "none"; os = "tee"; - load = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; - entry = /bits/ 64 <CONFIG_BL31_LOAD_ADDR>; + load = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + entry = /bits/ 64 <CONFIG_BL32_LOAD_ADDR>; + hash { + algo = "md5"; + }; tee-os { optional; }; @@ -145,15 +160,16 @@ type = "flat_dt"; arch = "arm64"; compression = "none"; - load = <0x0 0x100000>; +#if CONFIG_XILINX_OF_BOARD_DTB_ADDR + load = /bits/ 64 <CONFIG_XILINX_OF_BOARD_DTB_ADDR>; +#endif + hash { + algo = "md5"; + }; uboot-fdt-blob { filename = "u-boot.dtb"; type = "blob-ext"; }; - hash-1 { - algo = "md5"; - }; - }; }; configurations { @@ -202,5 +218,6 @@ }; }; #endif +#endif }; }; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index d56e863ce1c..02be5e1e868 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -22,6 +22,10 @@ "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp"; model = "ZynqMP KD240 revA/B/1"; + aliases { + ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + ina260-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index 9d0c0c2885d..fbacfa984d7 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -20,6 +20,11 @@ "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; model = "ZynqMP KR260 revA"; + aliases { + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index a98a888d138..3c36eb52e96 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -28,6 +28,10 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revA"; + aliases { + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 7490efea98b..078d98e8ff3 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -23,6 +23,10 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revB"; + aliases { + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; diff --git a/arch/arm/include/asm/arch-npcm8xx/gmac.h b/arch/arm/include/asm/arch-npcm8xx/gmac.h new file mode 100644 index 00000000000..f84eedddc22 --- /dev/null +++ b/arch/arm/include/asm/arch-npcm8xx/gmac.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef _NPCM_GMAC_H_ +#define _NPCM_GMAC_H_ + +/* PCS registers */ +#define PCS_BA 0xF0780000 +#define PCS_IND_AC 0x1FE +#define SR_MII_MMD 0x3E0000 +#define SR_MII_MMD_CTRL 0x0 +#define SR_MII_MMD_STS 0x2 +#define VR_MII_MMD 0x3F0000 +#define VR_MII_MMD_CTRL1 0x0 +#define VR_MII_MMD_AN_CTRL 0x2 + +#define LINK_UP_TIMEOUT (3 * CONFIG_SYS_HZ) + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index dd89cd20505..e6125d6bf54 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -466,18 +466,18 @@ enum { /* GRF_GPIO4C_IOMUX */ GRF_GPIO4C0_SEL_SHIFT = 0, GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT, - GRF_UART2DGBB_SIN = 2, + GRF_UART2DBGB_SIN = 2, GRF_HDMII2C_SCL = 3, GRF_GPIO4C1_SEL_SHIFT = 2, GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT, - GRF_UART2DGBB_SOUT = 2, + GRF_UART2DBGB_SOUT = 2, GRF_HDMII2C_SDA = 3, GRF_GPIO4C2_SEL_SHIFT = 4, GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, GRF_PWM_0 = 1, GRF_GPIO4C3_SEL_SHIFT = 6, GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, - GRF_UART2DGBC_SIN = 1, + GRF_UART2DBGC_SIN = 1, GRF_GPIO4C4_SEL_SHIFT = 8, GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, GRF_UART2DBGC_SOUT = 1, diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h index 9f531253153..055948ec07a 100644 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -24,6 +24,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, CLOCK_ID_DP, /* Special for Tegra124 */ /* These are the base clocks (inputs to the Tegra SoC) */ @@ -37,7 +38,6 @@ enum clock_id { * These are clock IDs that are used in table clock_source[][] * but will not be assigned as a clock source for any peripheral. */ - CLOCK_ID_DISPLAY2, CLOCK_ID_CGENERAL2, CLOCK_ID_CGENERAL3, CLOCK_ID_MEMORY2, diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h index c6d7487e629..5c4d7fc84c4 100644 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -24,6 +24,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, CLOCK_ID_DP, /* These are the base clocks (inputs to the Tegra SoC) */ @@ -37,7 +38,6 @@ enum clock_id { * These are clock IDs that are used in table clock_source[][] * but will not be assigned as a clock source for any peripheral. */ - CLOCK_ID_DISPLAY2, CLOCK_ID_CGENERAL_0, CLOCK_ID_CGENERAL_1, CLOCK_ID_CGENERAL2, diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index dbf9ab43e28..091082281c7 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -239,6 +239,22 @@ int __asm_invalidate_l3_icache(void); void __asm_switch_ttbr(u64 new_ttbr); /* + * armv8_switch_to_el2_prep() - prepare for switch from EL3 to EL2 for ARMv8 + * + * @args: For loading 64-bit OS, fdt address. + * For loading 32-bit OS, zero. + * @mach_nr: For loading 64-bit OS, zero. + * For loading 32-bit OS, machine nr + * @fdt_addr: For loading 64-bit OS, zero. + * For loading 32-bit OS, fdt address. + * @arg4: Input argument. + * @entry_point: kernel entry point + * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 + */ +void armv8_switch_to_el2_prep(u64 args, u64 mach_nr, u64 fdt_addr, + u64 arg4, u64 entry_point, u64 es_flag); + +/* * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8 * * @args: For loading 64-bit OS, fdt address. diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 345e282e3e6..bffadfecba1 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -83,8 +83,6 @@ relocate_base: add r1, r3 /* r1 <- Run &__image_copy_start */ subs r4, r0, r1 /* r4 <- Run to copy offset */ beq relocate_done /* skip relocation */ - ldr r1, _image_copy_start_ofs - add r1, r3 /* r1 <- Run &__image_copy_start */ ldr r2, _image_copy_end_ofs add r2, r3 /* r2 <- Run &__image_copy_end */ copy_loop: diff --git a/arch/arm/lib/xferlist.c b/arch/arm/lib/xferlist.c index f9c5d88bd47..6425936d354 100644 --- a/arch/arm/lib/xferlist.c +++ b/arch/arm/lib/xferlist.c @@ -8,18 +8,16 @@ #include <bloblist.h> #include "xferlist.h" -int xferlist_from_boot_arg(ulong addr, ulong size) +int xferlist_from_boot_arg(ulong *addr) { int ret; - ret = bloblist_check(saved_args[3], size); - if (ret) - return ret; - ret = bloblist_check_reg_conv(saved_args[0], saved_args[2], - saved_args[1]); + saved_args[1], saved_args[3]); if (ret) return ret; - return bloblist_reloc((void *)addr, size); + *addr = bloblist_get_base(); + + return 0; } diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 4020e16d92d..2f873ed6ddf 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -550,6 +550,7 @@ config TARGET_LXR2 select DM_THERMAL select SUPPORT_SPL imply CMD_DM + imply OF_UPSTREAM config TARGET_PCM058 bool "Phytec PCM058 i.MX6 Quad" diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index a3ac490f677..1f8cb8e3822 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -159,6 +159,30 @@ config K3_X509_SWRV config NR_DRAM_BANKS default 2 +config K3_REMOTEPROC_R5F + bool "Enable K3 Remoteproc driver for R5F" + depends on ARM64 + imply REMOTEPROC_TI_K3_R5F + default y if (SOC_K3_AM62A7 || SOC_K3_AM654 || SOC_K3_J721E || SOC_K3_J784S4 || SOC_K3_J721S2 || SOC_K3_J722S || SOC_K3_AM62P5 || SOC_K3_AM642) + +config K3_REMOTEPROC_DSP + bool "Enable K3 Remoteproc driver for DSP" + depends on ARM64 + imply REMOTEPROC_TI_K3_DSP + default y if (SOC_K3_AM62A7 || SOC_K3_J721E || SOC_K3_J784S4 || SOC_K3_J721S2 || SOC_K3_J722S) + +config K3_REMOTEPROC_M4F + bool "Enable K3 Remoteproc driver for M4F" + depends on ARM64 + imply REMOTEPROC_TI_K3_M4F + default y if (SOC_K3_AM625 || SOC_K3_AM642) + +config K3_REMOTEPROC_PRU + bool "Enable K3 Remoteproc driver for PRU" + depends on ARM64 + imply REMOTEPROC_TI_PRU + default y if (SOC_K3_AM642 || SOC_K3_AM654) + if CPU_V7R source "arch/arm/mach-k3/r5/Kconfig" endif diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 78153c97a58..698e6d5c587 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -15,6 +15,9 @@ #include "../sysfw-loader.h" #include "../common.h" +#define CTRLMMR_MCU_RST_CTRL 0x04518170 +#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK 0xFFFDFFFF + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; @@ -70,6 +73,15 @@ static void ctrl_mmr_unlock(void) mmr_unlock(PADCFG_MMR1_BASE, 1); } +static __maybe_unused void enable_mcu_esm_reset(void) +{ + /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */ + u32 stat = readl(CTRLMMR_MCU_RST_CTRL); + + stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK; + writel(stat, CTRLMMR_MCU_RST_CTRL); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -160,6 +172,20 @@ void board_init_f(ulong dummy) /* Output System Firmware version info */ k3_sysfw_print_ver(); + if (IS_ENABLED(CONFIG_ESM_K3)) { + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) + printf("esm main init failed: %d\n", ret); + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) + printf("esm mcu init failed: %d\n", ret); + + enable_mcu_esm_reset(); + } + #if defined(CONFIG_K3_AM62A_DDRSS) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index 7a24cf39c7b..14a46fa28d2 100644 --- a/arch/arm/mach-k3/am62px/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -19,6 +19,9 @@ /* TISCI DEV ID for A53 Clock */ #define AM62PX_DEV_A53SS0_CORE_0_DEV_ID 135 +#define CTRLMMR_MCU_RST_CTRL 0x04518170 +#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK 0xFFFDFFFF + struct fwl_data cbass_main_fwls[] = { { "FSS_DAT_REG3", 7, 8 }, }; @@ -127,6 +130,15 @@ static void fixup_a53_cpu_freq_by_speed_grade(void) } #endif +static __maybe_unused void enable_mcu_esm_reset(void) +{ + /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */ + u32 stat = readl(CTRLMMR_MCU_RST_CTRL); + + stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK; + writel(stat, CTRLMMR_MCU_RST_CTRL); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -218,6 +230,20 @@ void board_init_f(ulong dummy) panic("DRAM init failed: %d\n", ret); } + if (IS_ENABLED(CONFIG_ESM_K3)) { + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) + printf("esm main init failed: %d\n", ret); + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) + printf("esm mcu init failed: %d\n", ret); + + enable_mcu_esm_reset(); + } + spl_enable_cache(); setup_qos(); diff --git a/arch/arm/mach-k3/am65x/Kconfig b/arch/arm/mach-k3/am65x/Kconfig index 72a8298aebf..056ae118c9e 100644 --- a/arch/arm/mach-k3/am65x/Kconfig +++ b/arch/arm/mach-k3/am65x/Kconfig @@ -35,6 +35,8 @@ config TARGET_IOT2050_A53 select BOARD_LATE_INIT select SYS_DISABLE_DCACHE_OPS select BINMAN + select SYSINFO + select SPL_SYSINFO if SPL help This builds U-Boot for the IOT2050 devices. diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c index f8c5c2a5edc..af211377e7c 100644 --- a/arch/arm/mach-k3/j722s/j722s_init.c +++ b/arch/arm/mach-k3/j722s/j722s_init.c @@ -27,6 +27,9 @@ struct fwl_data cbass_main_fwls[] = { u32 bootindex __section(".data"); static struct rom_extended_boot_data bootdata __section(".data"); +#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170) +#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK (~BIT(17)) + static void store_boot_info_from_rom(void) { bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); @@ -161,11 +164,40 @@ static void k3_mem_init(void) } } +static __maybe_unused void enable_mcu_esm_reset(void) +{ + /* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z to '0' (low active) */ + u32 stat = readl(CTRLMMR_MCU_RST_CTRL); + + stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK; + writel(stat, CTRLMMR_MCU_RST_CTRL); +} + void board_init_f(ulong dummy) { + int ret; + struct udevice *dev; + k3_spl_init(); k3_mem_init(); setup_qos(); + + if (IS_ENABLED(CONFIG_ESM_K3)) { + /* Probe/configure ESM0 */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev); + if (ret) { + printf("esm main init failed: %d\n", ret); + return; + } + + /* Probe/configure MCUESM */ + ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev); + if (ret) { + printf("esm mcu init failed: %d\n", ret); + return; + } + enable_mcu_esm_reset(); + } } static u32 __get_backup_bootmedia(u32 devstat) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 39eea055f70..e54c456aec0 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -6,9 +6,6 @@ config SYS_SOC config SYS_VENDOR default "mediatek" -config MT8512 - bool "MediaTek MT8512 SoC" - choice prompt "MediaTek board select" @@ -96,9 +93,8 @@ config TARGET_MT8365 I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. config TARGET_MT8512 - bool "MediaTek MT8512 M1 Board" + bool "MediaTek MT8512 SoC" select ARM64 - select MT8512 help The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53. including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, @@ -160,9 +156,8 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string - default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 + default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 - default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 default "lk=1" if TARGET_MT7623 config MTK_TZ_MOVABLE diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 344434c6029..c11d6ad8aed 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -4,7 +4,6 @@ obj-y += cpu.o obj-$(CONFIG_MTK_TZ_MOVABLE) += tzcfg.o obj-$(CONFIG_XPL_BUILD) += spl.o -obj-$(CONFIG_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT7622) += mt7622/ obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ @@ -14,5 +13,6 @@ obj-$(CONFIG_TARGET_MT7987) += mt7987/ obj-$(CONFIG_TARGET_MT7988) += mt7988/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ obj-$(CONFIG_TARGET_MT8365) += mt8365/ +obj-$(CONFIG_TARGET_MT8512) += mt8512/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4 index c2812fd75e4..c42bb9765ef 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar4 +++ b/arch/arm/mach-renesas/Kconfig.rcar4 @@ -54,6 +54,12 @@ config TARGET_SPIDER help Support for Renesas R-Car Gen4 Spider platform +config TARGET_S4SK + bool "S4SK board" + imply R8A779F0 + help + Support for Renesas R-Car Gen4 S4SK platform + config TARGET_WHITEHAWK bool "White Hawk board" imply R8A779G0 @@ -70,6 +76,7 @@ endchoice source "board/renesas/falcon/Kconfig" source "board/renesas/spider/Kconfig" +source "board/renesas/s4sk/Kconfig" source "board/renesas/whitehawk/Kconfig" source "board/renesas/grayhawk/Kconfig" diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h index fc68ffc0945..b71c157149e 100644 --- a/arch/arm/mach-renesas/include/mach/boot0.h +++ b/arch/arm/mach-renesas/include/mach/boot0.h @@ -34,7 +34,7 @@ _start: .inst 0xe380070a /* orr r0, r0, #0x280000 */ /* APMU_RVBARPLC0 = (address of 'b reset' below) | CA_CORE0_VLD_RVBARP */ - .inst 0xe28f3088 /* add r3, pc, #0x88 */ + .inst 0xe28f30a8 /* add r3, pc, #0xa8 */ .inst 0xe3833001 /* orr r3, r3, #1 */ .inst 0xe5843038 /* str r3, [r4, #56] @ 0x38 */ @@ -75,12 +75,22 @@ _start: .inst 0xe20230ff /* and r3, r2, #255 @ 0xff */ .inst 0xe3530011 /* cmp r3, #17 */ .inst 0x1afffffb /* bne 78 <reset-0x28> */ + /* Invalidate icache before jump to follow up software */ + .inst 0xe3a00000 /* mov r0, #0 */ + .inst 0xee070f15 /* mcr 15, 0, r0, cr7, cr5, {0} */ + .inst 0xf57ff04f /* dsb sy */ + .inst 0xf57ff06f /* isb sy */ + /* Jump to follow up software */ .inst 0xe1a02922 /* lsr r2, r2, #18 */ .inst 0xe1a02902 /* lsl r2, r2, #18 */ .inst 0xe1a0f002 /* mov pc, r2 */ .inst 0xeafffffe /* b 94 <reset-0xc> */ .inst 0xe1a00000 /* nop @ (mov r0, r0) */ .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ + .inst 0xe1a00000 /* nop @ (mov r0, r0) */ /* Offset 0xa0 */ #endif b reset diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4d3157b2edd..adac11a6b89 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -29,6 +29,7 @@ config ROCKCHIP_RK3036 select CPU_V7A select SUPPORT_SPL select SPL + imply OF_UPSTREAM imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB imply ROCKCHIP_COMMON_BOARD diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 1ce43c6f0d4..99597076d2c 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -7,6 +7,7 @@ #include <init.h> #include <log.h> #include <spl.h> +#include <spl_gpio.h> #include <syscon.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> @@ -15,7 +16,6 @@ #include <asm/arch-rockchip/gpio.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> -#include <asm/gpio.h> #include <linux/bitops.h> #include <linux/printk.h> #include <power/regulator.h> @@ -133,10 +133,31 @@ void board_debug_uart_init(void) GRF_GPIO3B7_SEL_MASK, GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT); #else + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; + + if (IS_ENABLED(CONFIG_XPL_BUILD) && + (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || + IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { + rk_setreg(&grf->io_vsel, 1 << 0); + + /* + * Let's enable these power rails here, we are already running + * the SPI-Flash-based code. + */ + spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), + GPIO_PULL_NORMAL); + + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), + GPIO_PULL_NORMAL); + } + /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, - GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); + GRF_UART2DBGC_SIN << GRF_GPIO4C3_SEL_SHIFT); rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C4_SEL_MASK, GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 1fb01e1c4b1..f7d32829295 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -309,6 +309,8 @@ int dram_init_banksize(void) if (ram_top > SZ_4G && top < SZ_4G) { gd->bd->bi_dram[1].start = SZ_4G; gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start; + } else if (ram_top > SZ_4G && top == SZ_4G) { + gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start; } #else #ifdef CONFIG_SPL_OPTEE_IMAGE @@ -476,6 +478,7 @@ int dram_init(void) debug("Cannot get DRAM size: %d\n", ret); return ret; } + gd->ram_base = ram.base; gd->ram_size = ram.size; debug("SDRAM base=%lx, size=%lx\n", (unsigned long)ram.base, (unsigned long)ram.size); @@ -485,7 +488,8 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + /* Make sure U-Boot only uses the space below the 4G address boundary */ + u64 top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G); return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 6b6a162f568..a76a9fb2a39 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -55,6 +55,7 @@ config TARGET_SOCFPGA_AGILEX select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX + select GICV2 select NCORE_CACHE select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 @@ -64,7 +65,6 @@ config TARGET_SOCFPGA_AGILEX5 select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX - select GICV3 select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 @@ -74,6 +74,7 @@ config TARGET_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_ARRIA10 bool + select GICV2 select SPL_ALTERA_SDRAM select SPL_BOARD_INIT if SPL select SPL_CACHE if SPL @@ -118,6 +119,7 @@ config TARGET_SOCFPGA_N5X select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select CLK + select GICV2 select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_ALTERA_SDRAM @@ -137,6 +139,7 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX + select GICV2 select TARGET_SOCFPGA_SOC64 choice diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 5fc61b4a5c6..22d48dfae1c 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -# Copyright (C) 2012-2017 Altera Corporation <www.altera.com> +# Copyright (C) 2012-2025 Altera Corporation <www.altera.com> # Copyright (C) 2017-2024 Intel Corporation <www.intel.com> obj-y += board.o @@ -62,7 +62,12 @@ obj-y += mailbox_s10.o obj-y += misc_soc64.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o +obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +obj-y += altera-sysmgr.o +obj-y += ccu_ncore3.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_N5X @@ -106,6 +111,7 @@ obj-y += spl_n5x.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 obj-y += spl_soc64.o +obj-y += spl_agilex5.o endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o diff --git a/arch/arm/mach-socfpga/altera-sysmgr.c b/arch/arm/mach-socfpga/altera-sysmgr.c new file mode 100644 index 00000000000..ca3f5ca7dd5 --- /dev/null +++ b/arch/arm/mach-socfpga/altera-sysmgr.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +/* + * This driver supports the SOCFPGA System Manager Register block which + * aggregates different peripheral function into one area. + * On 64 bit ARM parts, the system manager only can be accessed during + * EL3 mode. At lower exception level a SMC call is required to perform + * the read and write operation. + */ + +#define LOG_CATEGORY UCLASS_NOP + +#include <dm.h> +#include <log.h> +#include <misc.h> +#include <asm/io.h> +#include <asm/system.h> +#include <asm/arch/altera-sysmgr.h> +#include <asm/arch/smc_api.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/intel-smc.h> + +static int altr_sysmgr_read_generic(struct udevice *dev, u32 *addr, u32 *value) +{ + u64 args[1]; + u64 ret_arg; + int ret = 0; + + debug("%s: %s(dev=%p, addr=0x%lx):\n", __func__, + dev->name, dev, (uintptr_t)addr); + + if (current_el() == 3) { + ret_arg = readl((uintptr_t)addr); + } else { + if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) { + args[0] = (u64)(uintptr_t)addr; + ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1); + } else { + pr_err("%s Failed to read system manager at lower privilege and without BL31\n", + dev->name); + return -EPROTONOSUPPORT; + } + } + + *value = (u32)ret_arg; + return ret; +} + +static int altr_sysmgr_write_generic(struct udevice *dev, u32 *addr, u32 value) +{ + u64 args[2]; + int ret = 0; + + debug("%s: %s(dev=%p, addr=0x%lx, val=0x%x):\n", __func__, + dev->name, dev, (uintptr_t)addr, value); + + if (current_el() == 3) { + writel(value, (uintptr_t)addr); + } else { + if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) { + args[0] = (u64)(uintptr_t)(addr); + args[1] = value; + ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0); + } else { + pr_err("%s Failed to write to system manager at lower privilege and without BL31\n", + dev->name); + return -EPROTONOSUPPORT; + } + } + + return ret; +} + +static int altr_sysmgr_probe(struct udevice *dev) +{ + fdt_addr_t addr; + struct altr_sysmgr_priv *altr_priv = dev_get_priv(dev); + + debug("%s: %s(dev=%p):\n", __func__, dev->name, dev); + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) { + pr_err("%s dev_read_addr() failed\n", dev->name); + return -ENODEV; + } + + altr_priv->regs = (void __iomem *)addr; + return 0; +} + +static const struct altr_sysmgr_ops sysmgr_ops = { + .read = altr_sysmgr_read_generic, + .write = altr_sysmgr_write_generic, +}; + +static const struct udevice_id altr_sysmgr_ids[] = { + { .compatible = "altr,sys-mgr-s10" }, + { .compatible = "altr,sys-mgr" }, + { }, +}; + +U_BOOT_DRIVER(altr_sysmgr) = { + .name = "altr_sysmgr", + .id = UCLASS_NOP, + .of_match = altr_sysmgr_ids, + .probe = altr_sysmgr_probe, + .ops = &sysmgr_ops, + .priv_auto = sizeof(struct altr_sysmgr_priv), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 24a15f7903f..27072e53135 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -6,22 +6,24 @@ */ #include <config.h> -#include <asm/arch/clock_manager.h> -#include <asm/arch/mailbox_s10.h> -#include <asm/arch/misc.h> -#include <asm/arch/reset_manager.h> -#include <asm/arch/secure_vab.h> -#include <asm/arch/smc_api.h> -#include <asm/global_data.h> -#include <asm/io.h> #include <errno.h> #include <fdtdec.h> +#include <log.h> +#include <init.h> #include <hang.h> +#include <handoff.h> #include <image.h> -#include <init.h> -#include <log.h> #include <usb.h> #include <usb/dwc2_udc.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/secure_vab.h> +#include <asm/arch/smc_api.h> +#include <bloblist.h> DECLARE_GLOBAL_DATA_PTR; @@ -57,7 +59,18 @@ int board_init(void) int dram_init_banksize(void) { +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#ifndef CONFIG_SPL_BUILD + struct spl_handoff *ho; + + ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho)); + if (!ho) + return log_msg_ret("Missing SPL hand-off info", -ENOENT); + handoff_load_dram_banks(ho); +#endif +#else fdtdec_setup_memory_banksize(); +#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ return 0; } diff --git a/arch/arm/mach-socfpga/ccu_ncore3.c b/arch/arm/mach-socfpga/ccu_ncore3.c new file mode 100644 index 00000000000..a399aedcd10 --- /dev/null +++ b/arch/arm/mach-socfpga/ccu_ncore3.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + * + */ +#include <wait_bit.h> +#include <asm/arch/base_addr_soc64.h> +#include <linux/bitfield.h> + +#define CCU_DMI0_DMIUSMCTCR SOCFPGA_CCU_ADDRESS + 0x7300 +#define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_ADDRESS + 0x7340 +#define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_ADDRESS + 0x7344 +#define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0) +#define MAX_DISTRIBUTED_MEM_INTERFACE 2 +#define FLUSH_ALL_ENTRIES 0x4 +#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16) +#define ARRAY_ID_TAG 0x0 +#define ARRAY_ID_DATA 0x1 +#define CACHE_OPERATION_DONE BIT(0) +#define TIMEOUT_200MS 200 + +int __asm_flush_l3_dcache(void) +{ + int i; + int ret = 0; + + /* Flushing all entries in CCU system memory cache */ + for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) { + /* + * Skipping if the system memory cache is not enabled for + * particular DMI + */ + if (!readl((uintptr_t)(CCU_DMI0_DMIUSMCTCR + (i * 0x1000)))) + continue; + + writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | + FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG), + (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000))); + + /* Wait for cache maintenance operation done */ + ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR + + (i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS, + false); + if (ret) { + debug("%s: Timeout while waiting for flushing tag in DMI%d done\n", + __func__, i); + return ret; + } + + writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | + FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA), + (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000))); + + /* Wait for cache maintenance operation done */ + ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR + + (i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS, + false); + if (ret) + debug("%s: Timeout waiting for flushing data in DMI%d done\n", + __func__, i); + } + + return ret; +} diff --git a/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h b/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h new file mode 100644 index 00000000000..8516617efe5 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +struct altr_sysmgr_ops { + int (*read)(struct udevice *dev, u32 *addr, u32 *value); + int (*write)(struct udevice *dev, u32 *addr, u32 value); +}; + +struct altr_sysmgr_priv { + void __iomem *regs; +}; + +#define altr_sysmgr_get_ops(dev) ((struct altr_sysmgr_ops *)(dev)->driver->ops) +#define altr_sysmgr_get_priv(dev) ((struct altr_sysmgr_priv *)(dev_get_priv(dev))) diff --git a/arch/arm/mach-socfpga/include/mach/board.h b/arch/arm/mach-socfpga/include/mach/board.h new file mode 100644 index 00000000000..2c3127e629f --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/board.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +u8 socfpga_get_board_id(void); + +#endif /* _BOARD_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 5cb7f23f8f0..2b436b64816 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -126,11 +127,27 @@ struct socfpga_firwall_l4_sys { #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD 0xff +/* Firewall F2SDRAM DDR SCR registers */ +#define FW_F2SDRAM_DDR_SCR_EN 0x00 +#define FW_F2SDRAM_DDR_SCR_EN_SET 0x04 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE 0x10 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT 0x14 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT 0x18 +#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT 0x1c + #define MPUREGION0_ENABLE BIT(0) #define NONMPUREGION0_ENABLE BIT(8) +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define FW_MPU_DDR_SCR_WRITEL(data, reg) \ + writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \ + writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg)) +#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg) \ + writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg)) +#else #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg)) +#endif void firewall_setup(void); diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index d839f288411..763b077d8c1 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -17,9 +18,9 @@ #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_MAGIC_PERI 0x50455249 -#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d #else #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 #endif @@ -68,7 +69,7 @@ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) #define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) -#define SOC64_HANDOFF_SDRAM_LEN 1 +#define SOC64_HANDOFF_SDRAM_LEN 5 #endif #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 8460acb00d9..ab46415168f 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2021 Intel Corporation + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _SOCFPGA_MISC_H_ @@ -51,6 +52,7 @@ bool is_periph_program_force(void); void set_regular_boot(unsigned int status); void socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); +void socfpga_get_sys_mgr_addr(const char *compat); int qspi_flash_software_reset(void); #endif /* _SOCFPGA_MISC_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index c8bb727aa2b..058fdd6e548 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _RESET_MANAGER_SOC64_H_ @@ -23,14 +24,20 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 /* SDM, Watchdogs and MPU warm reset mask */ -#define RSTMGR_STAT_SDMWARMRST BIT(1) +#define RSTMGR_STAT_SDMWARMRST 0x2 #define RSTMGR_STAT_MPU0RST_BITPOS 8 #define RSTMGR_STAT_L4WD0RST_BITPOS 16 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define RSTMGR_STAT_L4WD0RST_BIT 0x1F0000 +#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ + RSTMGR_STAT_L4WD0RST_BIT) +#else #define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \ RSTMGR_STAT_MPU0RST_BITPOS) | \ GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \ RSTMGR_STAT_L4WD0RST_BITPOS)) +#endif /* * SocFPGA Stratix10 reset IDs, bank mapping is as follows: diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 78eff247978..c2ca0a50e35 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -11,22 +12,43 @@ void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); void populate_sysmgr_pinmux(void); -#define SYSMGR_SOC64_WDDBG 0x08 -#define SYSMGR_SOC64_DMA 0x20 -#define SYSMGR_SOC64_DMA_PERIPH 0x24 -#define SYSMGR_SOC64_SDMMC 0x28 -#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c -#define SYSMGR_SOC64_EMAC_GLOBAL 0x40 -#define SYSMGR_SOC64_EMAC0 0x44 -#define SYSMGR_SOC64_EMAC1 0x48 -#define SYSMGR_SOC64_EMAC2 0x4c -#define SYSMGR_SOC64_EMAC0_ACE 0x50 -#define SYSMGR_SOC64_EMAC1_ACE 0x54 -#define SYSMGR_SOC64_EMAC2_ACE 0x58 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SYSMGR_SOC64_SILICONID_1 0x00 +#define SYSMGR_SOC64_SILICONID_2 0x04 +#define SYSMGR_SOC64_MPU_STATUS 0x10 +#define SYSMGR_SOC64_COMBOPHY_DFISEL 0xfc +#define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC 0x1 +#define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34 +#define SYSMGR_SOC64_USB0_L3MASTER 0x38 +#define SYSMGR_SOC64_USB1_L3MASTER 0x3c +#define SYSMGR_SOC64_DMAC0_L3_MASTER 0x74 +#define SYSMGR_SOC64_ETR_L3_MASTER 0x78 +#define SYSMGR_SOC64_DMAC1_L3_MASTER 0x7C +#define SYSMGR_SOC64_SEC_CTRL_SLT 0x80 +#define SYSMGR_SOC64_OSC_TRIM 0x84 +#define SYSMGR_SOC64_DMAC0_CTRL_STATUS_REG 0x88 +#define SYSMGR_SOC64_DMAC1_CTRL_STATUS_REG 0x8C +#define SYSMGR_SOC64_ECC_INTMASK_VALUE 0x90 +#define SYSMGR_SOC64_ECC_INTMASK_SET 0x94 +#define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98 +#define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C +#define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0 +#define SYSMGR_SOC64_MPFE_CONFIG 0x228 +#define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258 +#define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(31, 0) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK GENMASK(31, 29) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT 29 +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK BIT(27) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK BIT(28) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK GENMASK(28, 27) +#define ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK BIT(1) +#define ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK BIT(0) +#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1) +#else #define SYSMGR_SOC64_NAND_AXUSER 0x5c -#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 -#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c -#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 #define SYSMGR_SOC64_DMA_L3MASTER 0x74 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE 0xb8 @@ -34,39 +56,56 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HMC_CLK 0xb4 #define SYSMGR_SOC64_IO_PA_CTRL 0xb8 #endif -#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0 -#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 -#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 -#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xcc -#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 -#define SYSMGR_SOC64_NOC_IDLESTATUS 0xd4 -#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xd8 -#define SYSMGR_SOC64_FPGA_CONFIG 0xdc #define SYSMGR_SOC64_IOCSRCLK_GATE 0xe0 #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* - * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit - * storing qspi ref clock (kHz) - */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 -/* store osc1 clock freq */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 -/* store fpga clock freq */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 -/* reserved for customer use */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c -/* store PSCI_CPU_ON value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 -/* store PSCI_CPU_ON value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 -/* store VBAR_EL3 value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 -/* store VBAR_EL3 value */ -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 -#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/ + +#define SYSMGR_SOC64_DMA 0x20 +#define SYSMGR_SOC64_DMA_PERIPH 0x24 +#define SYSMGR_SOC64_WDDBG 0x08 +#define SYSMGR_SOC64_SDMMC 0x28 +#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2C +#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 +#define SYSMGR_SOC64_FPGAINTF_EN2 0x6C +#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 +#define SYSMGR_SOC64_NOC_TIMEOUT 0xC0 +#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xC4 +#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xC8 +#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xCC +#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 +#define SYSMGR_SOC64_NOC_IDLESTATUS 0xD4 +#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xD8 +#define SYSMGR_SOC64_FPGA_CONFIG 0xDC + +#define SYSMGR_SOC64_TSN_GLOBAL 0x40 +#define SYSMGR_SOC64_TSN_0 0x44 +#define SYSMGR_SOC64_TSN_1 0x48 +#define SYSMGR_SOC64_TSN_2 0x4C +#define SYSMGR_SOC64_TSN_0_ACE 0x50 +#define SYSMGR_SOC64_TSN_1_ACE 0x54 +#define SYSMGR_SOC64_TSN_2_ACE 0x58 +#define SYSMGR_SOC64_EMAC_GLOBAL SYSMGR_SOC64_TSN_GLOBAL +#define SYSMGR_SOC64_EMAC0 SYSMGR_SOC64_TSN_0 +#define SYSMGR_SOC64_EMAC1 SYSMGR_SOC64_TSN_1 +#define SYSMGR_SOC64_EMAC2 SYSMGR_SOC64_TSN_2 +#define SYSMGR_SOC64_EMAC0_ACE SYSMGR_SOC64_TSN_0_ACE +#define SYSMGR_SOC64_EMAC1_ACE SYSMGR_SOC64_TSN_1_ACE +#define SYSMGR_SOC64_EMAC2_ACE SYSMGR_SOC64_TSN_2_ACE + +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20C +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21C +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 + #define SYSMGR_SOC64_PINSEL0 0x1000 #define SYSMGR_SOC64_IOCTRL0 0x1130 #define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300 @@ -97,7 +136,6 @@ void populate_sysmgr_pinmux(void); * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit * storing qspi ref clock (kHz) */ -#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 46f9c82bbb2..97e01140513 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -1,31 +1,33 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2025 Altera Corporation <www.altera.com> */ #include <config.h> #include <command.h> -#include <cpu_func.h> -#include <hang.h> -#include <asm/cache.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/io.h> #include <errno.h> +#include <init.h> +#include <handoff.h> +#include <hang.h> +#include <watchdog.h> #include <fdtdec.h> #include <linux/libfdt.h> -#include <altera.h> +#include <linux/printk.h> #include <miiphy.h> #include <netdev.h> -#include <watchdog.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/pl310.h> #include <asm/arch/misc.h> +#include <asm/arch/nic301.h> #include <asm/arch/reset_manager.h> #include <asm/arch/scan_manager.h> -#include <asm/arch/system_manager.h> -#include <asm/arch/nic301.h> #include <asm/arch/scu.h> -#include <asm/pl310.h> -#include <linux/printk.h> +#include <asm/arch/system_manager.h> +#include <altera.h> +#include <bloblist.h> +#include <cpu_func.h> DECLARE_GLOBAL_DATA_PTR; @@ -51,8 +53,18 @@ struct bsel bsel_str[] = { int dram_init(void) { +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + struct spl_handoff *ho; + + ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho)); + if (!ho) + return log_msg_ret("Missing SPL hand-off info", -ENOENT); + gd->ram_size = ho->ram_bank[0].size; + gd->ram_base = ho->ram_bank[0].start; +#else if (fdtdec_setup_mem_size_base() != 0) return -EINVAL; +#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ return 0; } @@ -248,21 +260,32 @@ void socfpga_get_managers_addr(void) if (ret) hang(); - ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base); + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)) + ret = socfpga_get_base_addr("intel,agilex-clkmgr", + &socfpga_clkmgr_base); + else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) + ret = socfpga_get_base_addr("intel,n5x-clkmgr", + &socfpga_clkmgr_base); + else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + ret = socfpga_get_base_addr("altr,clk-mgr", + &socfpga_clkmgr_base); + if (ret) hang(); +} -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX - ret = socfpga_get_base_addr("intel,agilex-clkmgr", - &socfpga_clkmgr_base); -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) - ret = socfpga_get_base_addr("intel,n5x-clkmgr", - &socfpga_clkmgr_base); -#else - ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); -#endif - if (ret) +void socfpga_get_sys_mgr_addr(const char *compat) +{ + int ret; + struct udevice *sysmgr_dev; + + ret = uclass_get_device_by_name(UCLASS_NOP, compat, &sysmgr_dev); + if (ret) { + printf("Altera system manager init failed: %d\n", ret); hang(); + } else { + socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(sysmgr_dev); + } } phys_addr_t socfpga_get_rstmgr_addr(void) diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index a6cc78454da..e0b2b4237e1 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -1,20 +1,23 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ #include <altera.h> +#include <env.h> +#include <errno.h> +#include <init.h> +#include <log.h> +#include <asm/arch/board.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> #include <asm/io.h> +#include <asm/system.h> #include <asm/global_data.h> -#include <env.h> -#include <errno.h> -#include <init.h> -#include <log.h> #include <mach/clock_manager.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,12 +43,26 @@ static Altera_desc altera_fpga[] = { }; /* + * The Agilex5 platform has enabled the bloblist feature, and the bloblist + * address and size are initialized based on the defconfig settings. + * During the SPL phase, this function is used to prevent the bloblist + * from initializing its address and size with the saved boot parameters, + * which may have been incorrectly set. + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + save_boot_params_ret(); +} + +/* * Print CPU information */ #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); + printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); return 0; } @@ -55,10 +72,15 @@ int print_cpuinfo(void) int arch_misc_init(void) { char qspi_string[13]; + unsigned long id; sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); env_set("qspi_clock", qspi_string); + /* Export board_id as environment variable */ + id = socfpga_get_board_id(); + env_set_ulong("board_id", id); + return 0; } #endif diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index ebaa0b8fa17..b212a94b321 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2020 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ +#include <cpu_func.h> #include <asm/ptrace.h> #include <asm/system.h> #include <linux/errno.h> @@ -40,10 +42,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, args[2] = len; args[3] = urgent; args[4] = (u64)resp_buf; - if (resp_buf_len) + + if (arg && len > 0) + flush_dcache_range((uintptr_t)arg, (uintptr_t)arg + len); + + if (resp_buf && resp_buf_len && *resp_buf_len > 0) { args[5] = *resp_buf_len; - else + flush_dcache_range((uintptr_t)resp_buf, (uintptr_t)resp_buf + *resp_buf_len); + } else { args[5] = 0; + } ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args), resp, ARRAY_SIZE(resp)); diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c new file mode 100644 index 00000000000..3451611082d --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> + * + */ + +#include <init.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <hang.h> +#include <spl.h> +#include <asm/arch/base_addr_soc64.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <wdt.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 reset_flag(void) +{ + /* Check rstmgr.stat for warm reset status */ + u32 status = readl(SOCFPGA_RSTMGR_ADDRESS); + + /* Check whether any L4 watchdogs or SDM had triggered warm reset */ + u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK; + + if (status & warm_reset_mask) + return 0; + + return 1; +} + +void board_init_f(ulong dummy) +{ + int ret; + struct udevice *dev; + + /* Enable Async */ + asm volatile("msr daifclr, #4"); + +#ifdef CONFIG_SPL_BUILD + spl_save_restore_data(); +#endif + + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_sys_mgr_addr("sysmgr@10d12000"); + socfpga_get_managers_addr(); + + sysmgr_pinmux_init(); + + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); + + timer_init(); + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + hang(); + } + + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + + preloader_console_init(); + print_reset_info(); + cm_print_clock_quick_summary(); + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-ccu-config", &dev); + if (ret) { + printf("HPS CCU settings init failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-firewall-config", &dev); + if (ret) { + printf("HPS firewall settings init failed: %d\n", ret); + hang(); + } + + if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } + } + + mbox_init(); + + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) + mbox_qspi_open(); + + /* Enable non secure access to ocram */ + clrbits_le32(SOCFPGA_OCRAM_FIREWALL_ADDRESS + 0x18, BIT(0)); +} diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index 4fe67ea0811..651d9fc9cb8 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -1,10 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2020 Intel Corporation. All rights reserved + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ +#include <hang.h> #include <spl.h> +#include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; @@ -13,6 +16,109 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; } +/* This function is to map specified node onto SPL boot devices */ +static int spl_node_to_boot_device(int node) +{ + const void *blob = gd->fdt_blob; + struct udevice *parent; + const char *prop; + + if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) + return BOOT_DEVICE_MMC1; + else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + return BOOT_DEVICE_SPI; + else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node, &parent)) + return BOOT_DEVICE_NAND; + + prop = fdt_getprop(blob, node, "device_type", NULL); + if (prop) { + if (!strcmp(prop, "memory")) + return BOOT_DEVICE_RAM; + + printf("%s: unknown device_type %s\n", __func__, prop); + } + + return -ENODEV; +} + +static void default_spl_boot_list(u32 *spl_boot_list, int length) +{ + spl_boot_list[0] = spl_boot_device(); + + if (length > 1) + spl_boot_list[1] = BOOT_DEVICE_SPI; + + if (length > 2) + spl_boot_list[2] = BOOT_DEVICE_NAND; +} + +void board_boot_order(u32 *spl_boot_list) +{ + int idx = 0; + const void *blob = gd->fdt_blob; + int chosen_node = fdt_path_offset(blob, "/chosen"); + const char *conf; + int elem; + int boot_device; + int node; + int length; + + /* expect valid initialized spl_boot_list */ + if (!spl_boot_list) + return; + + length = 1; + while (spl_boot_list[length] == spl_boot_list[length - 1]) + length++; + + debug("%s: chosen_node is %d\n", __func__, chosen_node); + if (chosen_node < 0) { + printf("%s: /chosen not found, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + return; + } + + for (elem = 0; + (conf = fdt_stringlist_get(blob, chosen_node, + "u-boot,spl-boot-order", elem, NULL)); + elem++) { + if (idx >= length) { + printf("%s: limit %d to spl_boot_list exceeded\n", __func__, + length); + break; + } + + /* Resolve conf item as a path in device tree */ + node = fdt_path_offset(blob, conf); + if (node < 0) { + debug("%s: could not find %s in FDT\n", __func__, conf); + continue; + } + + /* Try to map spl node back onto SPL boot devices */ + boot_device = spl_node_to_boot_device(node); + if (boot_device < 0) { + debug("%s: could not map node @%x to a boot-device\n", + __func__, node); + continue; + } + + spl_boot_list[idx] = boot_device; + debug("%s: spl_boot_list[%d] = %u\n", __func__, idx, + spl_boot_list[idx]); + idx++; + } + + if (idx == 0) { + if (!conf && !elem) { + printf("%s: spl-boot-order invalid, using default\n", __func__); + default_spl_boot_list(spl_boot_list, length); + } else { + printf("%s: no valid element spl-boot-order list\n", __func__); + } + } +} + #if IS_ENABLED(CONFIG_SPL_MMC) u32 spl_boot_mode(const u32 boot_device) { @@ -22,3 +128,16 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } #endif + +/* board specific function prior loading SSBL / U-Boot */ +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-smmu-secure-config", &dev); + if (ret) { + printf("HPS SMMU secure settings init failed: %d\n", ret); + hang(); + } +} diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 92051d19b73..7105cdc4905 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -1,15 +1,17 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ +#include <errno.h> #include <asm/arch/handoff_soc64.h> #include <asm/io.h> -#include <errno.h> #include "log.h" #ifndef __ASSEMBLY__ +#include <asm/types.h> enum endianness { LITTLE_ENDIAN = 0, BIG_ENDIAN, @@ -26,7 +28,12 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_MAGIC_FPGA: case SOC64_HANDOFF_MAGIC_DELAY: case SOC64_HANDOFF_MAGIC_CLOCK: + case SOC64_HANDOFF_MAGIC_SDRAM: +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + case SOC64_HANDOFF_MAGIC_PERI: +#else case SOC64_HANDOFF_MAGIC_MISC: +#endif return BIG_ENDIAN; #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) case SOC64_HANDOFF_DDR_UMCTL2_MAGIC: diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 4ac0c10c597..0ea212f80e2 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -598,6 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; @@ -852,6 +854,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA124_CLK_PLL_D: case TEGRA124_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA124_CLK_PLL_D2: + case TEGRA124_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA124_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA124_CLK_PLL_E: @@ -1194,6 +1199,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) case CLOCK_ID_EPCI: case CLOCK_ID_SFROM32KHZ: return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; case CLOCK_ID_DP: return &clkrst->plldp; default: diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 6458827d6dc..e2735d93e28 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -33,6 +33,10 @@ config TARGET_PAZ00 bool "Paz00 board" select BOARD_LATE_INIT +config TARGET_PICASSO + bool "Acer Tegra20 Picasso board" + select BOARD_LATE_INIT + config TARGET_PLUTUX bool "Avionic Design Plutux board" select BOARD_LATE_INIT @@ -73,6 +77,7 @@ config SYS_SOC source "board/nvidia/harmony/Kconfig" source "board/avionic-design/medcom-wide/Kconfig" source "board/compal/paz00/Kconfig" +source "board/acer/picasso/Kconfig" source "board/avionic-design/plutux/Kconfig" source "board/nvidia/seaboard/Kconfig" source "board/avionic-design/tec/Kconfig" diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 57ff0b2a19a..04708f97144 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -668,6 +668,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; @@ -939,6 +941,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA210_CLK_PLL_D: case TEGRA210_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA210_CLK_PLL_D2: + case TEGRA210_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA210_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA210_CLK_PLL_E: @@ -1276,6 +1281,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) case CLOCK_ID_EPCI: case CLOCK_ID_SFROM32KHZ: return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; default: return NULL; } diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 265e9ce588a..376d1bc7131 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -43,9 +43,6 @@ config SYS_VENDOR config SYS_SOC default "zynq" -config SYS_MALLOC_F_LEN - default 0x800 - config SYS_MALLOC_LEN default 0x1400000 diff --git a/arch/arm/mach-zynqmp-r5/Kconfig b/arch/arm/mach-zynqmp-r5/Kconfig index b2ba896e9b4..45d8c053577 100644 --- a/arch/arm/mach-zynqmp-r5/Kconfig +++ b/arch/arm/mach-zynqmp-r5/Kconfig @@ -19,7 +19,4 @@ config CPU_FREQ_HZ help The value, in Hz, that the CPU clock is running at. -config SYS_MALLOC_F_LEN - default 0x600 - endif diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 92d61e84319..151cfada436 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -93,9 +93,6 @@ config SPL_ZYNQMP_DRAM_BANK2_LEN help Size in bytes of the DRAM ECC bank2. A null size takes no action. -config SYS_MALLOC_F_LEN - default 0x600 - config DEFINE_TCM_OCM_MMAP bool "Define TCM and OCM memory in MMU Table" default y if MP diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index ae52b375ccb..b8f3012873e 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -13,6 +13,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/sandbox-gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/sandbox-pinmux.h> #include <dt-bindings/mux/mux.h> @@ -820,7 +821,7 @@ gpio-controller; #gpio-cells = <1>; gpio-bank-name = "a"; - sandbox,gpio-count = <20>; + sandbox,gpio-count = <25>; hog_input_active_low { gpio-hog; input; @@ -1010,6 +1011,40 @@ /* label intentionally omitted */ default-state = "off"; }; + + led-20 { + gpios = <&gpio_a 20 0>; + /* label intentionally omitted */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + function-enumerator = <20>; + }; + + led-21 { + gpios = <&gpio_a 21 0>; + /* label intentionally omitted */ + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + }; + + led-22 { + gpios = <&gpio_a 22 0>; + /* label intentionally omitted */ + function = LED_FUNCTION_STATUS; + }; + + led-23 { + gpios = <&gpio_a 23 0>; + /* label intentionally omitted */ + color = <LED_COLOR_ID_GREEN>; + }; + + led-24 { + gpios = <&gpio_a 24 0>; + label = "sandbox:function"; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + }; }; wdt-gpio-toggle { diff --git a/board/acer/picasso/Kconfig b/board/acer/picasso/Kconfig new file mode 100644 index 00000000000..73c0aa08508 --- /dev/null +++ b/board/acer/picasso/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PICASSO + +config SYS_BOARD + default "picasso" + +config SYS_VENDOR + default "acer" + +config SYS_CONFIG_NAME + default "picasso" + +endif diff --git a/board/acer/picasso/MAINTAINERS b/board/acer/picasso/MAINTAINERS new file mode 100644 index 00000000000..99f8c0b6d7f --- /dev/null +++ b/board/acer/picasso/MAINTAINERS @@ -0,0 +1,7 @@ +PICASSO BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: board/acer/picasso/ +F: configs/picasso_defconfig +F: doc/board/acer/picasso.rst +F: include/configs/picasso.h diff --git a/board/acer/picasso/Makefile b/board/acer/picasso/Makefile new file mode 100644 index 00000000000..675059c112d --- /dev/null +++ b/board/acer/picasso/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2024 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-y += picasso.o diff --git a/board/acer/picasso/picasso.c b/board/acer/picasso/picasso.c new file mode 100644 index 00000000000..d3e600cad52 --- /dev/null +++ b/board/acer/picasso/picasso.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2024 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +/* Picasso derives from Ventana board */ + +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <linux/delay.h> + +#define TPS6586X_I2C_ADDRESS 0x34 +#define TPS6586X_SUPPLYENE 0x14 +#define EXITSLREQ_BIT BIT(1) +#define SLEEP_MODE_BIT BIT(3) + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(struct cmd_tbl *cmdtp, + int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS6586X_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_read(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] &= ~EXITSLREQ_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= SLEEP_MODE_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + // wait some time and then print error + mdelay(5000); + printf("Failed to power off!!!\n"); + return 1; +} +#endif diff --git a/board/acer/picasso/picasso.env b/board/acer/picasso/picasso.env new file mode 100644 index 00000000000..d9409b07d98 --- /dev/null +++ b/board/acer/picasso/picasso.env @@ -0,0 +1,18 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} + +boot_block_size_r=0x100000 +boot_block_size=0x800 +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 584b5455e97..7e8709444fe 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -28,7 +28,7 @@ choice config TARGET_VEXPRESS64_BASE_FVP bool "Support Versatile Express ARMv8a FVP BASE model" select VEXPRESS64_BASE_MODEL - imply OF_HAS_PRIOR_STAGE + imply OF_HAS_PRIOR_STAGE if !BLOBLIST config TARGET_VEXPRESS64_BASER_FVP bool "Support Versatile Express ARMv8r64 FVP BASE model" diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile index 1878fbed4ec..b0dd1d0af87 100644 --- a/board/armltd/vexpress64/Makefile +++ b/board/armltd/vexpress64/Makefile @@ -3,5 +3,8 @@ # (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y := vexpress64.o lowlevel_init.o +obj-y := vexpress64.o + +obj-$(CONFIG_OF_HAS_PRIOR_STAGE) += lowlevel_init.o + obj-$(CONFIG_TARGET_VEXPRESS64_JUNO) += pcie.o diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index b5ede58757d..0b75c1358f0 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -100,7 +100,9 @@ int dram_init_banksize(void) * Push the variable into the .data section so that it * does not get cleared later. */ +#ifdef CONFIG_OF_HAS_PRIOR_STAGE unsigned long __section(".data") prior_stage_fdt_address[2]; +#endif #ifdef CONFIG_OF_BOARD @@ -151,6 +153,7 @@ static phys_addr_t find_dtb_in_nor_flash(const char *partname) } #endif +#ifdef CONFIG_OF_HAS_PRIOR_STAGE /* * Filter for a valid DTB, as TF-A happens to provide a pointer to some * data structure using the DTB format, which we cannot use. @@ -201,6 +204,7 @@ int board_fdt_blob_setup(void **fdtp) return -ENXIO; } #endif +#endif /* Actual reset is done via PSCI. */ void reset_cpu(void) diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile index 8a8e6530c86..b83b7fced48 100644 --- a/board/asus/grouper/Makefile +++ b/board/asus/grouper/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2021 # Svyatoslav Ryhel <clamor95@gmail.com> -obj-$(CONFIG_SPL_BUILD) += grouper-spl.o +obj-$(CONFIG_XPL_BUILD) += grouper-spl.o obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += grouper.o diff --git a/board/asus/transformer-t30/Makefile b/board/asus/transformer-t30/Makefile index 22b6160f757..b8617f820cd 100644 --- a/board/asus/transformer-t30/Makefile +++ b/board/asus/transformer-t30/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2021 # Svyatoslav Ryhel <clamor95@gmail.com> -obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o +obj-$(CONFIG_XPL_BUILD) += transformer-t30-spl.o obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += transformer-t30.o diff --git a/board/asus/transformer-t30/board-info.c b/board/asus/transformer-t30/board-info.c index a2b540c90b6..e72614164b4 100644 --- a/board/asus/transformer-t30/board-info.c +++ b/board/asus/transformer-t30/board-info.c @@ -11,14 +11,14 @@ #include <asm/arch/pinmux.h> /* - * PCB_ID[1] is kb_row5_pr5 * PCB_ID[3] is kb_col7_pq7 * PCB_ID[4] is kb_row2_pr2 * PCB_ID[5] is kb_col5_pq5 + * PCB_ID[7] is gmi_cs1_n_pj2 * * Project ID * ===================================================== - * PCB_ID[1] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project + * PCB_ID[7] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project * 0 0 0 0 TF201 * 0 0 0 1 P1801 * 0 0 1 0 TF300T @@ -45,10 +45,10 @@ static const char * const project_id_to_fdt[] = { [TF600T] = "tegra30-asus-tf600t", }; -static int id_gpio_get_value(u32 pingrp, u32 pin) +static int id_gpio_get_value(u32 pingrp, u32 func, u32 pin) { /* Configure pinmux */ - pinmux_set_func(pingrp, PMUX_FUNC_KBC); + pinmux_set_func(pingrp, func); pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN); pinmux_tristate_enable(pingrp); pinmux_set_io(pingrp, PMUX_PIN_INPUT); @@ -65,19 +65,19 @@ static int id_gpio_get_value(u32 pingrp, u32 pin) static int get_project_id(void) { - u32 pcb_id1, pcb_id3, pcb_id4, pcb_id5; + u32 pcb_id3, pcb_id4, pcb_id5, pcb_id7; - pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_ROW5_PR5, - TEGRA_GPIO(R, 5)); pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL7_PQ7, - TEGRA_GPIO(Q, 7)); + PMUX_FUNC_KBC, TEGRA_GPIO(Q, 7)); pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_ROW2_PR2, - TEGRA_GPIO(R, 2)); + PMUX_FUNC_KBC, TEGRA_GPIO(R, 2)); pcb_id5 = id_gpio_get_value(PMUX_PINGRP_KB_COL5_PQ5, - TEGRA_GPIO(Q, 5)); + PMUX_FUNC_KBC, TEGRA_GPIO(Q, 5)); + pcb_id7 = id_gpio_get_value(PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_FUNC_RSVD1, TEGRA_GPIO(J, 2)); /* Construct board ID */ - int proj_id = pcb_id1 << 3 | pcb_id5 << 2 | + int proj_id = pcb_id7 << 3 | pcb_id5 << 2 | pcb_id4 << 1 | pcb_id3; log_debug("[TRANSFORMER]: project id %d (%s)\n", proj_id, diff --git a/board/comvetia/lxr2/lxr2.env b/board/comvetia/lxr2/lxr2.env index ec213800222..26ad4f18c68 100644 --- a/board/comvetia/lxr2/lxr2.env +++ b/board/comvetia/lxr2/lxr2.env @@ -2,7 +2,6 @@ addcons=setenv bootargs ${bootargs} console=${console},${baudrate} addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off addmisc=setenv bootargs ${bootargs} ${miscargs} addmtd=run mtdnand;run mtdspi;setenv bootargs ${bootargs} ${mtdparts} -altbootcmd=run swupdate bootcmd=run nandboot;run swupdate bootcount=2 bootlimit=3 diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c index 690a29690b9..0c68087912a 100644 --- a/board/gdsys/a38x/ihs_phys.c +++ b/board/gdsys/a38x/ihs_phys.c @@ -102,102 +102,6 @@ uint calculate_octo_phy_mask(void) return octo_phy_mask; } -int register_miiphy_bus(uint k, struct mii_dev **bus) -{ - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - char *name = bb_miiphy_buses[k].name; - - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - *bus = miiphy_get_dev_by_name(name); - - return 0; -} - -struct porttype *get_porttype(uint octo_phy_mask, uint k) -{ - uint octo_index = k * 4; - - if (!k) { - if (octo_phy_mask & 0x01) - return &porttypes[PORTTYPE_MAIN_CAT]; - else if (!(octo_phy_mask & 0x03)) - return &porttypes[PORTTYPE_16C_16F]; - } else { - if (octo_phy_mask & (1 << octo_index)) - return &porttypes[PORTTYPE_TOP_CAT]; - } - - return NULL; -} - -int init_single_phy(struct porttype *porttype, struct mii_dev *bus, - uint bus_idx, uint m, uint phy_idx) -{ - struct phy_device *phydev; - - phydev = phy_find_by_mask(bus, BIT(m * 8 + phy_idx)); - printf(" %u", bus_idx * 32 + m * 8 + phy_idx); - - if (!phydev) - puts("!"); - else - ihs_phy_config(phydev, porttype->phy_invert_in_pol, - porttype->phy_invert_out_pol); - - return 0; -} - -int init_octo_phys(uint octo_phy_mask) -{ - uint bus_idx; - - /* there are up to four octo-phys on each mdio bus */ - for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; ++bus_idx) { - uint m; - uint octo_index = bus_idx * 4; - struct mii_dev *bus = NULL; - struct porttype *porttype = NULL; - int ret; - - porttype = get_porttype(octo_phy_mask, bus_idx); - - if (!porttype) - continue; - - for (m = 0; m < 4; ++m) { - uint phy_idx; - - /** - * Register a bus device if there is at least one phy - * on the current bus - */ - if (!m && octo_phy_mask & (0xf << octo_index)) { - ret = register_miiphy_bus(bus_idx, &bus); - if (ret) - return ret; - } - - if (!(octo_phy_mask & BIT(octo_index + m))) - continue; - - for (phy_idx = 0; phy_idx < 8; ++phy_idx) - init_single_phy(porttype, bus, bus_idx, m, - phy_idx); - } - } - - return 0; -} - /* * MII GPIO bitbang implementation * MDC MDIO bus @@ -315,40 +219,109 @@ static int mii_delay(struct bb_miiphy_bus *bus) return 0; } -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = "ihs0", - .init = mii_mdio_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &gpio_mii_set[0], - }, - { - .name = "ihs1", - .init = mii_mdio_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &gpio_mii_set[1], - }, - { - .name = "ihs2", - .init = mii_mdio_init, - .mdio_active = mii_mdio_active, - .mdio_tristate = mii_mdio_tristate, - .set_mdio = mii_set_mdio, - .get_mdio = mii_get_mdio, - .set_mdc = mii_set_mdc, - .delay = mii_delay, - .priv = &gpio_mii_set[2], - }, -}; +int register_miiphy_bus(uint k, struct mii_dev **bus) +{ + struct bb_miiphy_bus *bb_miiphy = bb_miiphy_alloc(); + struct mii_dev *mdiodev; + int retval; + + if (!bb_miiphy) + return -ENOMEM; + + mdiodev = &bb_miiphy->mii; + snprintf(mdiodev->name, MDIO_NAME_LEN, "ihs%d", k); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + /* Copy the bus accessors and private data */ + bb_miiphy->mdio_active = mii_mdio_active; + bb_miiphy->mdio_tristate = mii_mdio_tristate; + bb_miiphy->set_mdio = mii_set_mdio; + bb_miiphy->get_mdio = mii_get_mdio; + bb_miiphy->set_mdc = mii_set_mdc; + bb_miiphy->delay = mii_delay; + bb_miiphy->priv = &gpio_mii_set[k]; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; + *bus = &bb_miiphy->mii; + + return mii_mdio_init(bb_miiphy); +} + +struct porttype *get_porttype(uint octo_phy_mask, uint k) +{ + uint octo_index = k * 4; + + if (!k) { + if (octo_phy_mask & 0x01) + return &porttypes[PORTTYPE_MAIN_CAT]; + else if (!(octo_phy_mask & 0x03)) + return &porttypes[PORTTYPE_16C_16F]; + } else { + if (octo_phy_mask & (1 << octo_index)) + return &porttypes[PORTTYPE_TOP_CAT]; + } + + return NULL; +} + +int init_single_phy(struct porttype *porttype, struct mii_dev *bus, + uint bus_idx, uint m, uint phy_idx) +{ + struct phy_device *phydev; + + phydev = phy_find_by_mask(bus, BIT(m * 8 + phy_idx)); + printf(" %u", bus_idx * 32 + m * 8 + phy_idx); + + if (!phydev) + puts("!"); + else + ihs_phy_config(phydev, porttype->phy_invert_in_pol, + porttype->phy_invert_out_pol); + + return 0; +} + +int init_octo_phys(uint octo_phy_mask) +{ + uint bus_idx; -int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); + /* there are up to four octo-phys on each mdio bus */ + for (bus_idx = 0; bus_idx < ARRAY_SIZE(gpio_mii_set); ++bus_idx) { + uint m; + uint octo_index = bus_idx * 4; + struct mii_dev *bus = NULL; + struct porttype *porttype = NULL; + int ret; + + porttype = get_porttype(octo_phy_mask, bus_idx); + + if (!porttype) + continue; + + for (m = 0; m < 4; ++m) { + uint phy_idx; + + /** + * Register a bus device if there is at least one phy + * on the current bus + */ + if (!m && octo_phy_mask & (0xf << octo_index)) { + ret = register_miiphy_bus(bus_idx, &bus); + if (ret) + return ret; + } + + if (!(octo_phy_mask & BIT(octo_index + m))) + continue; + + for (phy_idx = 0; phy_idx < 8; ++phy_idx) + init_single_phy(porttype, bus, bus_idx, m, + phy_idx); + } + } + + return 0; +} diff --git a/board/intel/agilex5-socdk/Makefile b/board/intel/agilex5-socdk/Makefile new file mode 100644 index 00000000000..306a8cf5f0b --- /dev/null +++ b/board/intel/agilex5-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/intel/agilex5-socdk/socfpga.c b/board/intel/agilex5-socdk/socfpga.c new file mode 100644 index 00000000000..d6628cfc696 --- /dev/null +++ b/board/intel/agilex5-socdk/socfpga.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <asm/arch/misc.h> + +int board_early_init_f(void) +{ + socfpga_get_sys_mgr_addr("sysmgr@10d12000"); + return 0; +} diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt index 1bdff2f908f..cfc69357e43 100644 --- a/board/keymile/scripts/develop-common.txt +++ b/board/keymile/scripts/develop-common.txt @@ -1,4 +1,3 @@ -altbootcmd=run ${subbootcmds} bootcmd=run ${subbootcmds} configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_nfs_path && saveenv && reset subbootcmds=tftpfdt tftpkernel nfsargs add_default boot diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt index 0a4a9c80b7e..c86e6267bdc 100644 --- a/board/keymile/scripts/ramfs-common.txt +++ b/board/keymile/scripts/ramfs-common.txt @@ -1,6 +1,5 @@ addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}" boot_bank=-1 -altbootcmd=run ${subbootcmds} bootcmd=run ${subbootcmds} subbootcmds=save_and_reset_once tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot save_and_reset_once=setenv save_and_reset_once true && saveenv && reset diff --git a/board/keymile/secu1/socfpga_secu.env b/board/keymile/secu1/socfpga_secu.env index 147c4170ef5..60999882958 100644 --- a/board/keymile/secu1/socfpga_secu.env +++ b/board/keymile/secu1/socfpga_secu.env @@ -1,4 +1,3 @@ -altbootcmd=run bootcmd; bootlimit=6 bootnum=1 bootretry=CONFIG_BOOT_RETRY_TIME diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 55e93a77f0f..699e5ca54a7 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -4,6 +4,7 @@ */ #include <dm.h> +#include <event.h> #include <asm/io.h> #include <asm/arch/gcr.h> #include "../common/uart.h" @@ -98,9 +99,5 @@ int dram_init_banksize(void) return 0; } -int last_stage_init(void) -{ - board_set_console(); +EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, board_set_console); - return 0; -} diff --git a/board/nuvoton/common/uart.c b/board/nuvoton/common/uart.c index b35c795704a..06f637855f5 100644 --- a/board/nuvoton/common/uart.c +++ b/board/nuvoton/common/uart.c @@ -14,7 +14,7 @@ #define UART_LCR 0xc #define LCR_DLAB BIT(7) -void board_set_console(void) +int board_set_console(void) { const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE; struct udevice *dev = gd->cur_serial_dev; @@ -28,12 +28,12 @@ void board_set_console(void) int ret, i; if (!dev) - return; + return -ENODEV; uart_reg = dev_read_addr_ptr(dev); ret = clk_get_by_index(dev, 0, &clk); if (ret) - return; + return ret; uart_clk = clk_get_rate(&clk); setbits_8(uart_reg + UART_LCR, LCR_DLAB); @@ -67,4 +67,5 @@ void board_set_console(void) snprintf(string, sizeof(string), "ttyS0,%un8", gd->baudrate); env_set("console", string); + return 0; } diff --git a/board/nuvoton/common/uart.h b/board/nuvoton/common/uart.h index 9cc895251b3..fc8ec477c8b 100644 --- a/board/nuvoton/common/uart.h +++ b/board/nuvoton/common/uart.h @@ -6,6 +6,6 @@ #ifndef _NUVOTON_UART_H #define _NUVOTON_UART_H -void board_set_console(void); +int board_set_console(void); #endif /* _NUVOTON_COMMON_H */ diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index 3c4e5aaf294..2faa34954eb 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -6,6 +6,7 @@ #include <dm.h> #include <env.h> +#include <event.h> #include <asm/io.h> #include <asm/arch/gcr.h> #include <asm/mach-types.h> @@ -48,7 +49,7 @@ int dram_init(void) return 0; } -int last_stage_init(void) +static int last_stage_init(void) { char value[32]; @@ -68,8 +69,10 @@ int last_stage_init(void) } sprintf(value, "ttyS%d,115200n8", dev->seq_); env_set("console", value); - board_set_console(); + return board_set_console(); } return 0; } +EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); + diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 711ca3040c4..024f38ebba3 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -22,4 +22,4 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 -spi_ramdisk_addr=0x1e00000 +spi_ramdisk_addr=0x2200000 diff --git a/board/phytec/phycore_am64x/Kconfig b/board/phytec/phycore_am64x/Kconfig index 829526c3295..a709b71ba4d 100644 --- a/board/phytec/phycore_am64x/Kconfig +++ b/board/phytec/phycore_am64x/Kconfig @@ -35,3 +35,28 @@ config SYS_CONFIG_NAME source "board/phytec/common/Kconfig" endif + +config PHYCORE_AM64X_RAM_SIZE_FIX + bool "Set phyCORE-AM64x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-AM64x RAM size" + depends on PHYCORE_AM64X_RAM_SIZE_FIX + default PHYCORE_AM64X_RAM_SIZE_2GB + +config PHYCORE_AM64X_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM64x. + +config PHYCORE_AM64X_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM64x. + +endchoice diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index 8f3b22657c7..f14c87f5c72 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -11,9 +11,12 @@ #include <env.h> #include <env_internal.h> #include <spl.h> +#include <asm/arch/k3-ddr.h> #include <fdt_support.h> #include <asm/arch/hardware.h> +#include "../common/am6_som_detection.h" + DECLARE_GLOBAL_DATA_PTR; int board_init(void) @@ -21,15 +24,113 @@ int board_init(void) return 0; } +static u8 phytec_get_am64_ddr_size_default(void) +{ + int ret; + struct phytec_eeprom_data data; + + if (IS_ENABLED(CONFIG_PHYCORE_AM64X_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_AM64X_RAM_SIZE_1GB)) + return EEPROM_RAM_SIZE_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM64X_RAM_SIZE_2GB)) + return EEPROM_RAM_SIZE_2GB; + } + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (!ret && data.valid) + return phytec_get_am6_ddr_size(&data); + + /* Default DDR size is 2GB */ + return EEPROM_RAM_SIZE_2GB; +} + int dram_init(void) { - return fdtdec_setup_mem_size_base(); + u8 ram_size; + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_mem_size_base(); + + ram_size = phytec_get_am64_ddr_size_default(); + + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->ram_size = 0x40000000; + break; + case EEPROM_RAM_SIZE_2GB: + gd->ram_size = 0x80000000; + break; + default: + gd->ram_size = 0x80000000; + } + + return 0; } int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + u8 ram_size; + + memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_memory_banksize(); + + ram_size = phytec_get_am64_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x40000000; + gd->ram_size = 0x40000000; + break; + + case EEPROM_RAM_SIZE_2GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + break; + + default: + /* Continue with default 2GB setup */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + printf("DDR size %d is not supported\n", ram_size); + } + + return 0; +} + +#if defined(CONFIG_K3_DDRSS) +int do_board_detect(void) +{ + void *fdt = (void *)gd->fdt_blob; + int bank; + + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + return fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); +} +#endif + +#if IS_ENABLED(CONFIG_XPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + if (IS_ENABLED(CONFIG_K3_DDRSS) && IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + else + fixup_memory_node(spl_image); } +#endif #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CORE_VOLTAGE 0x80000000 diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index 3032b518e0b..d69dfe75674 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -21,4 +21,4 @@ get_cmd=tftp spi_fdt_addr=0x700000 spi_image_addr=0x800000 -spi_ramdisk_addr=0x1e00000 +spi_ramdisk_addr=0x2200000 diff --git a/board/renesas/s4sk/Kconfig b/board/renesas/s4sk/Kconfig new file mode 100644 index 00000000000..57013d22b8c --- /dev/null +++ b/board/renesas/s4sk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_S4SK + +config SYS_SOC + default "renesas" + +config SYS_BOARD + default "s4sk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "s4sk" + +endif diff --git a/board/renesas/s4sk/MAINTAINERS b/board/renesas/s4sk/MAINTAINERS new file mode 100644 index 00000000000..e64da079160 --- /dev/null +++ b/board/renesas/s4sk/MAINTAINERS @@ -0,0 +1,7 @@ +S4SK BOARD +M: Marek Vasut <marek.vasut+renesas@mailbox.org> +S: Maintained +F: arch/arm/dts/r8a779f4* +F: board/renesas/s4sk/ +F: configs/r8a779f4_s4sk_defconfig +F: include/configs/s4sk.h diff --git a/board/renesas/s4sk/Makefile b/board/renesas/s4sk/Makefile new file mode 100644 index 00000000000..f03e52386f2 --- /dev/null +++ b/board/renesas/s4sk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Renesas Electronics Corp. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := s4sk.o diff --git a/board/renesas/s4sk/s4sk.c b/board/renesas/s4sk/s4sk.c new file mode 100644 index 00000000000..d2beb71c684 --- /dev/null +++ b/board/renesas/s4sk/s4sk.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> + */ + +#include <dm.h> +#include <i2c.h> +#include <malloc.h> +#include <net-common.h> + +#define S4SK_FPGA_I2C_BUS "i2c5" +#define S4SK_FPGA_I2C_DEV_ADDR 0x70 +#define S4SK_FPGA_I2C_DEV_WIDTH 2 +#define S4SK_FPGA_I2C_MAC_COUNT 4 +#define S4SK_FPGA_I2C_MAC_OFFSET 0x58 +#define S4SK_FPGA_I2C_MAC_WIDTH 8 + +int board_late_init(void) +{ + /* + * Extract AVB and TSN0,1,2 MAC addresses from FPGA via I2C. + * + * In case a matching ethaddr/ethNaddr environment variable + * is not set, set it, otherwise do not override it. This + * allows users to set their own MAC addresses via ethaddr + * and ethNaddr environment variables. + * + * The ethaddr/ethNaddr mapping follows Linux kernel DT aliases + * ethernetN property assignment: + * - ethaddr ..... TSN0 (IC104 connector) + * - eth1addr .... TSN1 (IC101 connector) + * - eth2addr .... TSN2 (Expansion connector) + * - eth3addr .... AVB (CN1 connector) + */ + ofnode i2c_node = ofnode_path(S4SK_FPGA_I2C_BUS); + struct udevice *bus, *dev; + unsigned char enetaddr[6]; + unsigned char macs[32]; /* Four MAC addresses in FPGA in total. */ + int i, idx, j, ret; + + ret = uclass_get_device_by_ofnode(UCLASS_I2C, i2c_node, &bus); + if (ret < 0) { + printf("s4sk: cannot find i2c bus (%d)\n", ret); + return 0; + } + + ret = i2c_get_chip(bus, S4SK_FPGA_I2C_DEV_ADDR, + S4SK_FPGA_I2C_DEV_WIDTH, &dev); + if (ret < 0) { + printf("s4sk: cannot find i2c chip (%d)\n", ret); + return 0; + } + + ret = dm_i2c_read(dev, S4SK_FPGA_I2C_MAC_OFFSET, macs, sizeof(macs)); + if (ret < 0) { + printf("s4sk: failed to read MAC addresses via i2c (%d)\n", ret); + return 0; + } + + for (i = 0; i < S4SK_FPGA_I2C_MAC_COUNT; i++) { + /* + * Remap TSN0,1,2 to ethaddr,eth1addr,eth2addr and + * AVB to eth3addr to match Linux /aliases ethernetN + * assignment, which starts with ethernet0 for TSN. + */ + idx = (i + 3) % 4; + ret = eth_env_get_enetaddr_by_index("eth", idx, enetaddr); + if (ret) /* ethaddr is already set */ + continue; + + /* Byte-wise reverse the MAC address */ + for (j = 0; j < sizeof(enetaddr); j++) + enetaddr[j] = macs[i * S4SK_FPGA_I2C_MAC_WIDTH + (5 - j)]; + + if (!is_valid_ethaddr(enetaddr)) { + printf("s4sk: MAC address %d in FPGA not valid (%pM)\n", + i, enetaddr); + continue; + } + + eth_env_set_enetaddr_by_index("eth", idx, enetaddr); + } + + return 0; +} diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index c5cef6f19d2..0bef68d2fb2 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -19,6 +19,11 @@ int dram_init_banksize(void) int board_init(void) { - load_ldfw(); + int err; + + err = load_ldfw(); + if (err) + printf("ERROR: LDFW loading failed (%d)\n", err); + return 0; } diff --git a/board/samsung/e850-96/e850-96.env b/board/samsung/e850-96/e850-96.env index f36f90be950..5ac76bcef02 100644 --- a/board/samsung/e850-96/e850-96.env +++ b/board/samsung/e850-96/e850-96.env @@ -1,26 +1,11 @@ -partitions= - uuid_disk=${uuid_gpt_disk}; - name=efs,start=512K,size=20M,uuid=${uuid_gpt_efs}; - name=env,size=16K,uuid=${uuid_gpt_env}; - name=kernel,size=30M,uuid=${uuid_gpt_kernel}; - name=ramdisk,size=26M,uuid=${uuid_gpt_ramdisk}; - name=dtbo,size=1M,uuid=${uuid_gpt_dtbo}; - name=ldfw,size=4016K,uuid=${uuid_gpt_ldfw}; - name=keystorage,size=8K,uuid=${uuid_gpt_keystorage}; - name=tzsw,size=1M,uuid=${uuid_gpt_tzsw}; - name=harx,size=2M,uuid=${uuid_gpt_harx}; - name=harx_rkp,size=2M,uuid=${uuid_gpt_harx_rkp}; - name=logo,size=40M,uuid=${uuid_gpt_logo}; - name=super,size=3600M,uuid=${uuid_gpt_super}; - name=cache,size=300M,uuid=${uuid_gpt_cache}; - name=modem,size=100M,uuid=${uuid_gpt_modem}; - name=boot,size=100M,uuid=${uuid_gpt_boot}; - name=persist,size=30M,uuid=${uuid_gpt_persist}; - name=recovery,size=40M,uuid=${uuid_gpt_recovery}; - name=misc,size=40M,uuid=${uuid_gpt_misc}; - name=mnv,size=20M,uuid=${uuid_gpt_mnv}; - name=frp,size=512K,uuid=${uuid_gpt_frp}; - name=vbmeta,size=64K,uuid=${uuid_gpt_vbmeta}; - name=metadata,size=16M,uuid=${uuid_gpt_metadata}; - name=dtb,size=1M,uuid=${uuid_gpt_dtb}; - name=userdata,size=-,uuid=${uuid_gpt_userdata} +kernel_addr_r=0x80000000 +kernel_comp_addr_r=0x88000000 +kernel_comp_size=0x4000000 +fdt_addr_r=0x8c000000 +scriptaddr=0x8c100000 +pxefile_addr_r=0x8c200000 +ramdisk_addr_r=0x8c300000 +fdtfile=CONFIG_DEFAULT_FDT_FILE + +partitions=name=esp,start=512K,size=128M,bootable,type=system; +partitions+=name=rootfs,size=-,bootable,type=linux diff --git a/board/samsung/e850-96/fw.c b/board/samsung/e850-96/fw.c index 82a0b224c67..8f64e759b43 100644 --- a/board/samsung/e850-96/fw.c +++ b/board/samsung/e850-96/fw.c @@ -7,14 +7,16 @@ */ #include <part.h> +#include <fs.h> #include <linux/arm-smccc.h> #include "fw.h" #define EMMC_IFACE "mmc" #define EMMC_DEV_NUM 0 +#define LDFW_RAW_PART "ldfw" +#define LDFW_FAT_PART "esp" +#define LDFW_FAT_PATH "/EFI/firmware/ldfw.bin" -/* LDFW constants */ -#define LDFW_PART_NAME "ldfw" #define LDFW_NWD_ADDR 0x88000000 #define LDFW_MAGIC 0x10adab1e #define SMC_CMD_LOAD_LDFW -0x500 @@ -36,7 +38,33 @@ struct ldfw_header { char fw_name[16]; }; -static int read_fw(const char *part_name, void *buf) +/* Load LDFW binary as a file from FAT partition */ +static int read_fw_from_fat(const char *part_name, const char *path, void *buf) +{ + char dev_part_str[8]; + loff_t len_read; + int err; + + snprintf(dev_part_str, sizeof(dev_part_str), "%d#%s", EMMC_DEV_NUM, + LDFW_FAT_PART); + + err = fs_set_blk_dev(EMMC_IFACE, dev_part_str, FS_TYPE_FAT); + if (err) { + debug("%s: Can't set block device\n", __func__); + return -ENODEV; + } + + err = fs_read(path, (ulong)buf, 0, 0, &len_read); + if (err) { + debug("%s: Can't read LDFW file\n", __func__); + return -EIO; + } + + return 0; +} + +/* Load LDFW binary from raw partition on block device into RAM buffer */ +static int read_fw_from_raw(const char *part_name, void *buf) { struct blk_desc *blk_desc; struct disk_partition part; @@ -73,10 +101,13 @@ int load_ldfw(void) u64 size = 0; int err, i; - /* Load LDFW from the block device partition into RAM buffer */ - err = read_fw(LDFW_PART_NAME, buf); - if (err) - return err; + /* First try to read LDFW from EFI partition, then from the raw one */ + err = read_fw_from_fat(LDFW_FAT_PART, LDFW_FAT_PATH, buf); + if (err) { + err = read_fw_from_raw(LDFW_RAW_PART, buf); + if (err) + return err; + } /* Validate LDFW by magic number in its header */ hdr = buf; diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig index 4ae12b1c973..3808257cd07 100644 --- a/board/siemens/common/Kconfig +++ b/board/siemens/common/Kconfig @@ -3,4 +3,5 @@ config FACTORYSET config DDR_SI_TEST bool "DDR signal integrity test implementations" + depends on TARGET_CAPRICORN default y diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index e6bedc38917..d827f728a08 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -25,28 +25,7 @@ #include <asm/gpio.h> #include <asm/io.h> -#define IOT2050_INFO_MAGIC 0x20502050 - -struct iot2050_info { - u32 magic; - u16 size; - char name[20 + 1]; - char serial[16 + 1]; - char mlfb[18 + 1]; - char uuid[32 + 1]; - char a5e[18 + 1]; - u8 mac_addr_cnt; - u8 mac_addr[8][ARP_HLEN]; - char seboot_version[40 + 1]; - u8 padding[3]; - u32 ddr_size_mb; -} __packed; - -/* - * Scratch SRAM (available before DDR RAM) contains extracted EEPROM data. - */ -#define IOT2050_INFO_DATA ((struct iot2050_info *) \ - TI_SRAM_SCRATCH_BOARD_EEPROM_START) +#include "../../../../drivers/sysinfo/iot2050.h" DECLARE_GLOBAL_DATA_PTR; @@ -117,6 +96,8 @@ static const char *m2_connector_mode_name[] = { static enum m2_connector_mode connector_mode; +static char iot2050_board_name[21]; + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) static void *connector_overlay; static u32 connector_overlay_size; @@ -149,37 +130,57 @@ static void set_pinvalue(const char *gpio_name, const char *label, int value) dm_gpio_set_value(&gpio, value); } +static bool setup_sysinfo(struct udevice **sysinfo_ptr) +{ + if (sysinfo_get(sysinfo_ptr)) { + pr_err("Could not find sysinfo device.\n"); + return false; + } + if (sysinfo_detect(*sysinfo_ptr)) { + pr_err("Board info parsing error\n"); + return false; + } + return true; +} + +static void get_board_name(void) +{ + struct udevice *sysinfo; + + if (iot2050_board_name[0] != 0) + return; + + if (!setup_sysinfo(&sysinfo)) + return; + + sysinfo_get_str(sysinfo, BOARD_NAME, sizeof(iot2050_board_name), + iot2050_board_name); +} + static bool board_is_advanced(void) { - struct iot2050_info *info = IOT2050_INFO_DATA; - return info->magic == IOT2050_INFO_MAGIC && - strstr((char *)info->name, "IOT2050-ADVANCED") != NULL; + get_board_name(); + return strstr(iot2050_board_name, "IOT2050-ADVANCED") != NULL; } static bool board_is_pg1(void) { - struct iot2050_info *info = IOT2050_INFO_DATA; - - return info->magic == IOT2050_INFO_MAGIC && - (strcmp((char *)info->name, "IOT2050-BASIC") == 0 || - strcmp((char *)info->name, "IOT2050-ADVANCED") == 0); + get_board_name(); + return strcmp(iot2050_board_name, "IOT2050-BASIC") == 0 || + strcmp(iot2050_board_name, "IOT2050-ADVANCED") == 0; } static bool board_is_m2(void) { - struct iot2050_info *info = IOT2050_INFO_DATA; - - return info->magic == IOT2050_INFO_MAGIC && - strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0; + get_board_name(); + return strcmp(iot2050_board_name, "IOT2050-ADVANCED-M2") == 0; } static bool board_is_sm(void) { - struct iot2050_info *info = IOT2050_INFO_DATA; - - return info->magic == IOT2050_INFO_MAGIC && - strcmp((char *)info->name, "IOT2050-ADVANCED-SM") == 0; + get_board_name(); + return strcmp(iot2050_board_name, "IOT2050-ADVANCED-SM") == 0; } static void remove_mmc1_target(void) @@ -206,33 +207,43 @@ static void enable_pcie_connector_power(void) void set_board_info_env(void) { - struct iot2050_info *info = IOT2050_INFO_DATA; - u8 __maybe_unused mac_cnt; + struct udevice *sysinfo; const char *fdtfile; + char buf[41]; - if (info->magic != IOT2050_INFO_MAGIC) { - pr_err("IOT2050: Board info parsing error!\n"); + if (env_get("board_uuid")) return; - } - if (env_get("board_uuid")) + if (!setup_sysinfo(&sysinfo)) return; - env_set("board_name", info->name); - env_set("board_serial", info->serial); - env_set("mlfb", info->mlfb); - env_set("board_uuid", info->uuid); - env_set("board_a5e", info->a5e); + if (sysinfo_get_str(sysinfo, BOARD_NAME, sizeof(buf), buf) == 0) + env_set("board_name", buf); + if (sysinfo_get_str(sysinfo, SYSID_SM_SYSTEM_SERIAL, sizeof(buf), buf) == 0) + env_set("board_serial", buf); + if (sysinfo_get_str(sysinfo, BOARD_MLFB, sizeof(buf), buf) == 0) + env_set("mlfb", buf); + if (sysinfo_get_str(sysinfo, BOARD_UUID, sizeof(buf), buf) == 0) + env_set("board_uuid", buf); + if (sysinfo_get_str(sysinfo, BOARD_A5E, sizeof(buf), buf) == 0) + env_set("board_a5e", buf); + if (sysinfo_get_str(sysinfo, BOARD_SEBOOT_VER, sizeof(buf), buf) == 0) + env_set("seboot_version", buf); env_set("fw_version", PLAIN_VERSION); - env_set("seboot_version", info->seboot_version); if (IS_ENABLED(CONFIG_NET)) { + int mac_cnt; + + mac_cnt = sysinfo_get_item_count(sysinfo, SYSID_BOARD_MAC_ADDR); /* set MAC addresses to ensure forwarding to the OS */ - for (mac_cnt = 0; mac_cnt < info->mac_addr_cnt; mac_cnt++) { - if (is_valid_ethaddr(info->mac_addr[mac_cnt])) - eth_env_set_enetaddr_by_index("eth", - mac_cnt + 1, - info->mac_addr[mac_cnt]); + for (int i = 0; i < mac_cnt; i++) { + u8 *mac = NULL; + size_t bytes = 0; + + sysinfo_get_data_by_index(sysinfo, SYSID_BOARD_MAC_ADDR, + i, (void **)&mac, &bytes); + if (bytes == ARP_HLEN && is_valid_ethaddr(mac)) + eth_env_set_enetaddr_by_index("eth", i + 1, mac); } } @@ -288,7 +299,7 @@ static void do_overlay_prepare(const char *overlay_path) return; fit_error: - pr_err("M.2 device tree overlay %s not available,\n", overlay_path); + pr_err("M.2 device tree overlay %s not available.\n", overlay_path); #endif } @@ -362,8 +373,15 @@ int board_init(void) int dram_init(void) { - struct iot2050_info *info = IOT2050_INFO_DATA; - gd->ram_size = ((phys_size_t)(info->ddr_size_mb)) << 20; + struct udevice *sysinfo; + u32 ddr_size_mb; + + if (!setup_sysinfo(&sysinfo)) + return -ENODEV; + + sysinfo_get_int(sysinfo, SYSID_BOARD_RAM_SIZE_MB, &ddr_size_mb); + + gd->ram_size = ((phys_size_t)(ddr_size_mb)) << 20; return 0; } @@ -405,18 +423,18 @@ int dram_init_banksize(void) #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { - struct iot2050_info *info = IOT2050_INFO_DATA; char upper_name[32]; + get_board_name(); + /* skip the prefix "ti/k3-am65x8-" */ name += 13; - if (info->magic != IOT2050_INFO_MAGIC || - strlen(name) >= sizeof(upper_name)) + if (strlen(name) >= sizeof(upper_name)) return -1; str_to_upper(name, upper_name, sizeof(upper_name)); - if (!strcmp(upper_name, (char *)info->name)) + if (!strcmp(upper_name, iot2050_board_name)) return 0; return -1; diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index a912712c9dd..8ad593cccdd 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -7,11 +7,6 @@ #include <cpu_func.h> #include <init.h> #include <asm/cache.h> -#include <asm/global_data.h> -#include <linux/usb/otg.h> -#include <dwc3-sti-glue.h> -#include <dwc3-uboot.h> -#include <usb.h> DECLARE_GLOBAL_DATA_PTR; @@ -43,31 +38,6 @@ int board_init(void) } #ifdef CONFIG_USB_DWC3 -static struct dwc3_device dwc3_device_data = { - .maximum_speed = USB_SPEED_HIGH, - .dr_mode = USB_DR_MODE_PERIPHERAL, - .index = 0, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const void *blob = gd->fdt_blob; - - /* find the snps,dwc3 node */ - node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3"); - - dwc3_device_data.base = fdtdec_get_addr(blob, node, "reg"); - - return dwc3_uboot_init(&dwc3_device_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - dwc3_uboot_exit(index); - return 0; -} - int g_dnl_board_usb_cable_connected(void) { return 1; diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS index d7f638f9b41..898e284ce2c 100644 --- a/board/starfive/visionfive2/MAINTAINERS +++ b/board/starfive/visionfive2/MAINTAINERS @@ -1,8 +1,7 @@ STARFIVE JH7110 VISIONFIVE2 BOARD M: Minda Chen <minda.chen@starfivetech.com> +M: Hal Feng <hal.feng@starfivetech.com> S: Maintained -F: arch/riscv/include/asm/arch-jh7110/ -F: board/starfive/visionfive2/ -F: include/configs/starfive-visionfive2.h -F: configs/starfive_visionfive2_defconfig -F: drivers/pci/pcie_starfive_jh7110.c +F: drivers/ram/starfive/ +N: jh7110 +N: visionfive2 diff --git a/board/storopack/smegw01/smegw01.env b/board/storopack/smegw01/smegw01.env index 93de8669109..c0d408e4a20 100644 --- a/board/storopack/smegw01/smegw01.env +++ b/board/storopack/smegw01/smegw01.env @@ -12,21 +12,6 @@ setenv bootmenu_${emmc_priority} eMMC=run boot_emmc; \ setenv bootmenu_${sd_priority} SD=run boot_sd; #endif - -altbootcmd= - echo Performing rollback...; - if test "${mmcpart_committed}" = 1; then - setenv mmcpart 2; - setenv mmcpart_committed 2; - else - setenv mmcpart 1; - setenv mmcpart_committed 1; - fi; - setenv bootcount 0; - setenv upgrade_available; - setenv ustate 3; - saveenv; - run bootcmd; boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd; boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd; bootcmd= diff --git a/board/ti/am62px/am62px.env b/board/ti/am62px/am62px.env index 7ef54079aa8..f19e158d8d6 100644 --- a/board/ti/am62px/am62px.env +++ b/board/ti/am62px/am62px.env @@ -1,5 +1,12 @@ #include <env/ti/ti_common.env> #include <env/ti/mmc.env> +#include <env/ti/k3_dfu.env> + +#if CONFIG_CMD_REMOTEPROC +#include <env/ti/k3_rproc.env> +#endif + +rproc_fw_binaries= 0 /lib/firmware/am62p-mcu-r5f0_0-fw name_kern=Image console=ttyS2,115200n8 @@ -7,7 +14,7 @@ args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 ${mtdparts} run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr} -boot_targets=mmc1 mmc0 pxe dhcp +boot_targets=mmc1 mmc0 usb pxe dhcp boot=mmc mmcdev=1 bootpart=1:2 @@ -17,4 +24,4 @@ rd_spec=- #if CONFIG_BOOTMETH_ANDROID #include <env/ti/android.env> adtb_idx=3 -#endif
\ No newline at end of file +#endif diff --git a/board/ti/am62px/rm-cfg.yaml b/board/ti/am62px/rm-cfg.yaml index caa2f7a5a83..dc445a4b72f 100644 --- a/board/ti/am62px/rm-cfg.yaml +++ b/board/ti/am62px/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62P # @@ -244,7 +244,7 @@ rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 984 + resasg_entries_size: 1048 reserved: 0 resasg_entries: - @@ -476,13 +476,13 @@ rm-cfg: host_id: 12 reserved: 0 - - start_resource: 45 + start_resource: 44 num_resource: 35 type: 1802 host_id: 35 reserved: 0 - - start_resource: 45 + start_resource: 44 num_resource: 35 type: 1802 host_id: 36 @@ -494,31 +494,31 @@ rm-cfg: host_id: 30 reserved: 0 - - start_resource: 14 + start_resource: 13 num_resource: 512 type: 1805 host_id: 12 reserved: 0 - - start_resource: 526 + start_resource: 525 num_resource: 256 type: 1805 host_id: 35 reserved: 0 - - start_resource: 526 + start_resource: 525 num_resource: 256 type: 1805 host_id: 36 reserved: 0 - - start_resource: 782 + start_resource: 781 num_resource: 128 type: 1805 host_id: 30 reserved: 0 - - start_resource: 910 + start_resource: 909 num_resource: 626 type: 1805 host_id: 128 @@ -645,17 +645,29 @@ rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 64 + num_resource: 32 type: 1937 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 64 + num_resource: 32 type: 1937 host_id: 36 reserved: 0 - + start_resource: 51 + num_resource: 32 + type: 1937 + host_id: 12 + reserved: 0 + - + start_resource: 51 + num_resource: 32 + type: 1937 + host_id: 30 + reserved: 0 + - start_resource: 83 num_resource: 8 type: 1938 @@ -699,17 +711,29 @@ rm-cfg: reserved: 0 - start_resource: 118 - num_resource: 16 + num_resource: 6 type: 1943 host_id: 12 reserved: 0 - start_resource: 118 - num_resource: 16 + num_resource: 6 type: 1943 host_id: 36 reserved: 0 - + start_resource: 124 + num_resource: 10 + type: 1943 + host_id: 12 + reserved: 0 + - + start_resource: 124 + num_resource: 10 + type: 1943 + host_id: 30 + reserved: 0 + - start_resource: 134 num_resource: 8 type: 1944 @@ -765,17 +789,29 @@ rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 8 + num_resource: 4 type: 1956 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 8 + num_resource: 4 type: 1956 host_id: 36 reserved: 0 - + start_resource: 23 + num_resource: 4 + type: 1956 + host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 4 + type: 1956 + host_id: 30 + reserved: 0 + - start_resource: 27 num_resource: 1 type: 1957 @@ -861,17 +897,29 @@ rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 16 + num_resource: 6 type: 1964 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 16 + num_resource: 6 type: 1964 host_id: 36 reserved: 0 - + start_resource: 25 + num_resource: 10 + type: 1964 + host_id: 12 + reserved: 0 + - + start_resource: 25 + num_resource: 10 + type: 1964 + host_id: 30 + reserved: 0 + - start_resource: 20 num_resource: 1 type: 1965 diff --git a/board/ti/am62px/tifs-rm-cfg.yaml b/board/ti/am62px/tifs-rm-cfg.yaml index a80a2750467..80269748057 100644 --- a/board/ti/am62px/tifs-rm-cfg.yaml +++ b/board/ti/am62px/tifs-rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62P # @@ -244,7 +244,7 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 840 + resasg_entries_size: 904 reserved: 0 resasg_entries: - @@ -423,13 +423,13 @@ tifs-rm-cfg: reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 35 reserved: 0 - start_resource: 44 - num_resource: 36 + num_resource: 35 type: 1802 host_id: 36 reserved: 0 @@ -555,17 +555,29 @@ tifs-rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 64 + num_resource: 32 type: 1937 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 64 + num_resource: 32 type: 1937 host_id: 36 reserved: 0 - + start_resource: 51 + num_resource: 32 + type: 1937 + host_id: 12 + reserved: 0 + - + start_resource: 51 + num_resource: 32 + type: 1937 + host_id: 30 + reserved: 0 + - start_resource: 83 num_resource: 8 type: 1938 @@ -609,17 +621,29 @@ tifs-rm-cfg: reserved: 0 - start_resource: 118 - num_resource: 16 + num_resource: 6 type: 1943 host_id: 12 reserved: 0 - start_resource: 118 - num_resource: 16 + num_resource: 6 type: 1943 host_id: 36 reserved: 0 - + start_resource: 124 + num_resource: 10 + type: 1943 + host_id: 12 + reserved: 0 + - + start_resource: 124 + num_resource: 10 + type: 1943 + host_id: 30 + reserved: 0 + - start_resource: 134 num_resource: 8 type: 1944 @@ -675,17 +699,29 @@ tifs-rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 8 + num_resource: 4 type: 1956 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 8 + num_resource: 4 type: 1956 host_id: 36 reserved: 0 - + start_resource: 23 + num_resource: 4 + type: 1956 + host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 4 + type: 1956 + host_id: 30 + reserved: 0 + - start_resource: 27 num_resource: 1 type: 1957 @@ -771,17 +807,29 @@ tifs-rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 16 + num_resource: 6 type: 1964 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 16 + num_resource: 6 type: 1964 host_id: 36 reserved: 0 - + start_resource: 25 + num_resource: 10 + type: 1964 + host_id: 12 + reserved: 0 + - + start_resource: 25 + num_resource: 10 + type: 1964 + host_id: 30 + reserved: 0 + - start_resource: 20 num_resource: 1 type: 1965 diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env index 078cc4b5ac9..60b5fd5e6ca 100644 --- a/board/ti/am62x/am62x.env +++ b/board/ti/am62x/am62x.env @@ -2,6 +2,12 @@ #include <env/ti/mmc.env> #include <env/ti/k3_dfu.env> +#if CONFIG_CMD_REMOTEPROC +#include <env/ti/k3_rproc.env> +#endif + +rproc_fw_binaries= 0 /lib/firmware/am62-mcu-m4f0_0-fw + name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000 diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env index 8ad805a613c..c8ab57b807c 100644 --- a/board/ti/am64x/am64x.env +++ b/board/ti/am64x/am64x.env @@ -2,6 +2,12 @@ #include <env/ti/mmc.env> #include <env/ti/k3_dfu.env> +#if CONFIG_CMD_REMOTEPROC +#include <env/ti/k3_rproc.env> +#endif + +rproc_fw_binaries= 0 /lib/firmware/am64-mcu-m4f0_0-fw 1 /lib/firmware/am64-main-r5f0_0-fw 2 /lib/firmware/am64-main-r5f0_1-fw 3 /lib/firmware/am64-main-r5f1_0-fw 4 /lib/firmware/am64-main-r5f1_1-fw + name_kern=Image console=ttyS2,115200n8 args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 ${mtdparts} diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env index 10d62034e1a..4cc66e8d6da 100644 --- a/board/ti/j722s/j722s.env +++ b/board/ti/j722s/j722s.env @@ -1,5 +1,6 @@ #include <env/ti/ti_common.env> #include <env/ti/mmc.env> +#include <env/ti/k3_dfu.env> #if CONFIG_CMD_REMOTEPROC #include <env/ti/k3_rproc.env> diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index e948fc16ba9..b80b39b6767 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -35,6 +35,17 @@ int dram_init(void) return 0; } +int dram_init_banksize(void) +{ + s32 ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret); + + return ret; +} + /* * Avoid relocated U-Boot clash with Linux reserved-memory on 512 MB SoM */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 8cdd9d86009..820fb252a3f 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -488,7 +488,7 @@ static int boot_targets_setup(void) if (bootseq >= 0) { bootseq_len = snprintf(NULL, 0, "%i", bootseq); debug("Bootseq len: %x\n", bootseq_len); - env_set_hex("bootseq", bootseq); + env_set_ulong("bootseq", (unsigned long)bootseq); } /* diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index b0c2ac6f2e8..75b604a1f76 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -43,6 +43,7 @@ script_size_f=0x80000 scriptaddr=0x20000000 usb_boot=usb start; if usb dev ${devnum}; then devtype=usb; run scan_dev_for_boot_part; fi preboot=setenv boot_targets; setenv modeboot; run board_setup +usb_pgood_delay=1000 # SOM specific boot methods usb_boot_devices='usb0 usb1 usb2 usb3 usb4' diff --git a/boot/Kconfig b/boot/Kconfig index 20935a269c6..c09a98c3233 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -711,6 +711,20 @@ config BOOTMETH_VBE_SIMPLE firmware image in boot media such as MMC. It does not support any sort of rollback, recovery or A/B boot. +config BOOTMETH_VBE_ABREC + bool "Bootdev support for VBE 'a/b/recovery' method" + imply SPL_CRC8 + imply VPL_CRC8 + help + Enables support for VBE 'abrec' boot. This allows updating one of an + A or B firmware image in boot media such as MMC. The new firmware is + tried and if it boots, it is copied to the other image, so that both + A and B have the same version. If neither firmware image passes the + verification step, a recovery image is booted. This method will + eventually provide rollback protection as well. + +if BOOTMETH_VBE_SIMPLE + config BOOTMETH_VBE_SIMPLE_OS bool "Bootdev support for VBE 'simple' method OS phase" default y @@ -769,6 +783,65 @@ config TPL_BOOTMETH_VBE_SIMPLE_FW endif # BOOTMETH_VBE_SIMPLE +if BOOTMETH_VBE_ABREC + +config SPL_BOOTMETH_VBE_ABREC + bool "Bootdev support for VBE 'abrec' method (SPL)" + depends on SPL + default y if VPL + help + Enables support for VBE 'abrec' boot. The SPL part of this + implementation simply loads U-Boot from the image selected by the + VPL phase. + +config TPL_BOOTMETH_VBE_ABREC + bool "Bootdev support for VBE 'abrec' method (TPL)" + depends on TPL + select TPL_FIT + default y + help + Enables support for VBE 'abrec' boot. The TPL part of this + implementation simply jumps to VPL after device init is completed. + +config VPL_BOOTMETH_VBE_ABREC + bool "Bootdev support for VBE 'abrec' method (VPL)" + depends on VPL + default y + help + Enables support for VBE 'abrec' boot. The VPL part of this + implementation selects which SPL to use (A, B or recovery) and then + boots into SPL. + +config SPL_BOOTMETH_VBE_ABREC_FW + bool "Bootdev support for VBE 'abrec' method firmware phase (SPL)" + depends on SPL + default y if VPL + help + Enables support for VBE 'abrec' boot. The SPL part of this + implementation simply loads U-Boot from the image selected by the + VPL phase. + +config TPL_BOOTMETH_VBE_ABREC_FW + bool "Bootdev support for VBE 'abrec' method firmware phase (TPL)" + depends on TPL + default y if VPL + help + Enables support for VBE 'abrec' boot. The TPL part of this + implementation simply jumps to VPL after device init is completed. + +config VPL_BOOTMETH_VBE_ABREC_FW + bool "Bootdev support for VBE 'abrec' method firmware phase (VPL)" + depends on VPL + default y + help + Enables support for VBE 'abrec' boot. The VPL part of this + implementation selects which SPL to use (A, B or recovery) and then + boots into SPL. + +endif # BOOTMETH_VBE_ABREC + +endif # BOOTMETH_VBE + config EXPO bool "Support for expos - groups of scenes displaying a UI" depends on VIDEO diff --git a/boot/Makefile b/boot/Makefile index c2753de8163..34bac26c4e2 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -70,3 +70,7 @@ obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_SIMPLE_FW) += vbe_simple_fw.o obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_SIMPLE_OS) += vbe_simple_os.o obj-$(CONFIG_$(PHASE_)BOOTMETH_ANDROID) += bootmeth_android.o + +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_ABREC) += vbe_abrec.o vbe_common.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_ABREC_FW) += vbe_abrec_fw.o +obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE_ABREC_OS) += vbe_abrec_os.o diff --git a/boot/image-android.c b/boot/image-android.c index fa4e14ca469..1746b018900 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -696,7 +696,10 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img, ulong dtb_addr; /* address of DTB blob with specified index */ u32 i; /* index iterator */ - android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, &dtb_img_addr); + if (!android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, + &dtb_img_addr)) + return false; + /* Check if DTB area of boot image is in DTBO format */ if (android_dt_check_header(dtb_img_addr)) { return android_dt_get_fdt_by_index(dtb_img_addr, index, addr, diff --git a/boot/image-fit.c b/boot/image-fit.c index 70080d1a6c0..41ab1f552b0 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -1907,24 +1907,30 @@ int fit_conf_get_prop_node(const void *fit, int noffset, const char *prop_name, count = fit_conf_get_prop_node_count(fit, noffset, prop_name); if (count < 0) return count; + log_debug("looking for %s (%s, image-count %d):\n", prop_name, + genimg_get_phase_name(image_ph_phase(sel_phase)), count); /* check each image in the list */ for (i = 0; i < count; i++) { - enum image_phase_t phase; + enum image_phase_t phase = IH_PHASE_NONE; int ret, node; node = fit_conf_get_prop_node_index(fit, noffset, prop_name, i); ret = fit_image_get_phase(fit, node, &phase); + log_debug("- %s (%s): ", fdt_get_name(fit, node, NULL), + genimg_get_phase_name(phase)); /* if the image is for any phase, let's use it */ - if (ret == -ENOENT) + if (ret == -ENOENT || phase == sel_phase) { + log_debug("found\n"); return node; - else if (ret < 0) + } else if (ret < 0) { + log_debug("err=%d\n", ret); return ret; - - if (phase == sel_phase) - return node; + } + log_debug("no match\n"); } + log_debug("- not found\n"); return -ENOENT; } @@ -2012,13 +2018,15 @@ int fit_get_node_from_config(struct bootm_headers *images, } /** - * fit_get_image_type_property() - get property name for IH_TYPE_... + * fit_get_image_type_property() - get property name for sel_phase * * Return: the properly name where we expect to find the image in the * config node */ -static const char *fit_get_image_type_property(int type) +static const char *fit_get_image_type_property(int ph_type) { + int type = image_ph_type(ph_type); + /* * This is sort-of available in the uimage_type[] table in image.c * but we don't have access to the short name, and "fdt" is different @@ -2070,8 +2078,9 @@ int fit_image_load(struct bootm_headers *images, ulong addr, fit_uname = fit_unamep ? *fit_unamep : NULL; fit_uname_config = fit_uname_configp ? *fit_uname_configp : NULL; fit_base_uname_config = NULL; - prop_name = fit_get_image_type_property(image_type); - printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr); + prop_name = fit_get_image_type_property(ph_type); + printf("## Loading %s (%s) from FIT Image at %08lx ...\n", + prop_name, genimg_get_phase_name(image_ph_phase(ph_type)), addr); bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT); ret = fit_check_format(fit, IMAGE_SIZE_INVAL); @@ -2166,6 +2175,7 @@ int fit_image_load(struct bootm_headers *images, ulong addr, type_ok = fit_image_check_type(fit, noffset, image_type) || fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE) || fit_image_check_type(fit, noffset, IH_TYPE_TEE) || + fit_image_check_type(fit, noffset, IH_TYPE_TFA_BL31) || (image_type == IH_TYPE_KERNEL && fit_image_check_type(fit, noffset, IH_TYPE_KERNEL_NOLOAD)); @@ -2346,10 +2356,17 @@ int boot_get_fdt_fit(struct bootm_headers *images, ulong addr, char *next_config = NULL; ulong load, len; #ifdef CONFIG_OF_LIBFDT_OVERLAY - ulong image_start, image_end; ulong ovload, ovlen, ovcopylen; const char *uconfig; const char *uname; + /* + * of_flat_tree is storing the void * returned by map_sysmem, then its + * address is passed to boot_relocate_fdt which expects a char ** and it + * is then cast into a ulong. Setting its type to void * would require + * to cast its address to char ** when passing it to boot_relocate_fdt. + * Instead, let's be lazy and use void *. + */ + char *of_flat_tree; void *base, *ov, *ovcopy = NULL; int i, err, noffset, ov_noffset; #endif @@ -2393,17 +2410,18 @@ int boot_get_fdt_fit(struct bootm_headers *images, ulong addr, /* we need to apply overlays */ #ifdef CONFIG_OF_LIBFDT_OVERLAY - image_start = addr; - image_end = addr + fit_get_size(fit); - /* verify that relocation took place by load address not being in fit */ - if (load >= image_start && load < image_end) { - /* check is simplified; fit load checks for overlaps */ - printf("Overlayed FDT requires relocation\n"); + /* Relocate FDT so resizing does not overwrite other data in FIT. */ + of_flat_tree = map_sysmem(load, len); + len = ALIGN(fdt_totalsize(load), SZ_4K); + err = boot_relocate_fdt(&of_flat_tree, &len); + if (err) { + printf("Required FDT relocation for applying DTOs failed: %d\n", + err); fdt_noffset = -EBADF; goto out; } - base = map_sysmem(load, len); + load = (ulong)of_flat_tree; /* apply extra configs in FIT first, followed by args */ for (i = 1; ; i++) { diff --git a/boot/image-pre-load.c b/boot/image-pre-load.c index cc19017404c..adf3b341a20 100644 --- a/boot/image-pre-load.c +++ b/boot/image-pre-load.c @@ -3,13 +3,24 @@ * Copyright (C) 2021 Philippe Reynes <philippe.reynes@softathome.com> */ +#ifdef USE_HOSTCC +#include "mkimage.h" +#else #include <asm/global_data.h> -DECLARE_GLOBAL_DATA_PTR; -#include <image.h> #include <mapmem.h> +DECLARE_GLOBAL_DATA_PTR; +#endif /* !USE_HOSTCC*/ +#include <image.h> #include <u-boot/sha256.h> +#ifdef USE_HOSTCC +/* Define compat stuff for use in tools. */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +#endif + /* * Offset of the image * @@ -17,6 +28,47 @@ DECLARE_GLOBAL_DATA_PTR; */ ulong image_load_offset; +#ifdef USE_HOSTCC +/* Host tools use these implementations to setup information related to the + * pre-load signatures + */ +static struct image_sig_info *host_info; + +#define log_info(fmt, args...) printf(fmt, ##args) +#define log_err(fmt, args...) printf(fmt, ##args) + +void image_pre_load_sig_set_info(struct image_sig_info *info) +{ + host_info = info; +} + +/* + * This function sets a pointer to information for the signature check. + * It expects that host_info has been initially provision by the host + * application. + * + * return: + * < 0 => an error has occurred + * 0 => OK + */ +static int image_pre_load_sig_setup(struct image_sig_info *info) +{ + if (!info) { + log_err("ERROR: info is NULL\n"); + return -EINVAL; + } + + if (!host_info) { + log_err("ERROR: host_info is NULL\n"); + log_err("ERROR: Set it with image_pre_load_sig_set_info()\n"); + return -EINVAL; + } + + memcpy(info, host_info, sizeof(struct image_sig_info)); + + return 0; +} +#else /* * This function gathers information about the signature check * that could be done before launching the image. @@ -106,6 +158,7 @@ static int image_pre_load_sig_setup(struct image_sig_info *info) out: return ret; } +#endif /* !USE_HOSTCC */ static int image_pre_load_sig_get_magic(ulong addr, u32 *magic) { diff --git a/boot/image.c b/boot/image.c index abac254e026..139c5bd035a 100644 --- a/boot/image.c +++ b/boot/image.c @@ -183,6 +183,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat Device Tree ", }, { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" }, { IH_TYPE_STARFIVE_SPL, "sfspl", "StarFive SPL Image" }, + { IH_TYPE_TFA_BL31, "tfa-bl31", "TFA BL31 Image", }, { -1, "", "", }, }; diff --git a/boot/vbe_abrec.c b/boot/vbe_abrec.c new file mode 100644 index 00000000000..6d0f622262d --- /dev/null +++ b/boot/vbe_abrec.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Verified Boot for Embedded (VBE) 'simple' method + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY LOGC_BOOT + +#include <dm.h> +#include <memalign.h> +#include <mmc.h> +#include <dm/ofnode.h> +#include "vbe_abrec.h" + +int abrec_read_priv(ofnode node, struct abrec_priv *priv) +{ + memset(priv, '\0', sizeof(*priv)); + if (ofnode_read_u32(node, "area-start", &priv->area_start) || + ofnode_read_u32(node, "area-size", &priv->area_size) || + ofnode_read_u32(node, "version-offset", &priv->version_offset) || + ofnode_read_u32(node, "version-size", &priv->version_size) || + ofnode_read_u32(node, "state-offset", &priv->state_offset) || + ofnode_read_u32(node, "state-size", &priv->state_size)) + return log_msg_ret("read", -EINVAL); + ofnode_read_u32(node, "skip-offset", &priv->skip_offset); + priv->storage = strdup(ofnode_read_string(node, "storage")); + if (!priv->storage) + return log_msg_ret("str", -EINVAL); + + return 0; +} + +int abrec_read_nvdata(struct abrec_priv *priv, struct udevice *blk, + struct abrec_state *state) +{ + ALLOC_CACHE_ALIGN_BUFFER(u8, buf, MMC_MAX_BLOCK_LEN); + const struct vbe_nvdata *nvd = (struct vbe_nvdata *)buf; + uint flags; + int ret; + + ret = vbe_read_nvdata(blk, priv->area_start + priv->state_offset, + priv->state_size, buf); + if (ret == -EPERM) { + memset(buf, '\0', MMC_MAX_BLOCK_LEN); + log_warning("Starting with empty state\n"); + } else if (ret) { + return log_msg_ret("nv", ret); + } + + state->fw_vernum = nvd->fw_vernum; + flags = nvd->flags; + state->try_count = flags & VBEF_TRY_COUNT_MASK; + state->try_b = flags & VBEF_TRY_B; + state->recovery = flags & VBEF_RECOVERY; + state->pick = (flags & VBEF_PICK_MASK) >> VBEF_PICK_SHIFT; + + return 0; +} + +int abrec_read_state(struct udevice *dev, struct abrec_state *state) +{ + struct abrec_priv *priv = dev_get_priv(dev); + struct udevice *blk; + int ret; + + ret = vbe_get_blk(priv->storage, &blk); + if (ret) + return log_msg_ret("blk", ret); + + ret = vbe_read_version(blk, priv->area_start + priv->version_offset, + state->fw_version, MAX_VERSION_LEN); + if (ret) + return log_msg_ret("ver", ret); + log_debug("version=%s\n", state->fw_version); + + ret = abrec_read_nvdata(priv, blk, state); + if (ret) + return log_msg_ret("nvd", ret); + + return 0; +} diff --git a/boot/vbe_abrec.h b/boot/vbe_abrec.h new file mode 100644 index 00000000000..63c73297351 --- /dev/null +++ b/boot/vbe_abrec.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Verified Boot for Embedded (VBE) vbe-abrec common file + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __VBE_ABREC_H +#define __VBE_ABREC_H + +#include <vbe.h> +#include <dm/ofnode_decl.h> + +#include "vbe_common.h" + +struct bootflow; +struct udevice; + +/** + * struct abrec_priv - information read from the device tree + * + * @area_start: Start offset of the VBE area in the device, in bytes + * @area_size: Total size of the VBE area + * @skip_offset: Size of an initial part of the device to skip, when using + * area_start. This is effectively added to area_start to calculate the + * actual start position on the device + * @state_offset: Offset from area_start of the VBE state, in bytes + * @state_size: Size of the state information + * @version_offset: Offset from from area_start of the VBE version info + * @version_size: Size of the version info + * @storage: Storage device to use, in the form <uclass><devnum>, e.g. "mmc1" + */ +struct abrec_priv { + u32 area_start; + u32 area_size; + u32 skip_offset; + u32 state_offset; + u32 state_size; + u32 version_offset; + u32 version_size; + const char *storage; +}; + +/** struct abrec_state - state information read from media + * + * The state on the media is converted into this more code-friendly structure. + * + * @fw_version: Firmware version string + * @fw_vernum: Firmware version number + * @try_count: Number of times the B firmware has been tried + * @try_b: true to try B firmware on the next boot + * @recovery: true to enter recovery firmware on the next boot + * @try_result: Result of trying to boot with the last firmware + * @pick: Firmware which was chosen in this boot + */ +struct abrec_state { + char fw_version[MAX_VERSION_LEN]; + u32 fw_vernum; + u8 try_count; + bool try_b; + bool recovery; + enum vbe_try_result try_result; + enum vbe_pick_t pick; +}; + +/** + * abrec_read_fw_bootflow() - Read a bootflow for firmware + * + * Locates and loads the firmware image (FIT) needed for the next phase. The FIT + * should ideally use external data, to reduce the amount of it that needs to be + * read. + * + * @bdev: bootdev device containing the firmwre + * @bflow: Place to put the created bootflow, on success + * @return 0 if OK, -ve on error + */ +int abrec_read_bootflow_fw(struct udevice *dev, struct bootflow *bflow); + +/** + * vbe_simple_read_state() - Read the VBE simple state information + * + * @dev: VBE bootmeth + * @state: Place to put the state + * @return 0 if OK, -ve on error + */ +int abrec_read_state(struct udevice *dev, struct abrec_state *state); + +/** + * abrec_read_nvdata() - Read non-volatile data from a block device + * + * Reads the ABrec VBE nvdata from a device. This function reads a single block + * from the device, so the nvdata cannot be larger than that. + * + * @blk: Device to read from + * @offset: Offset to read, in bytes + * @size: Number of bytes to read + * @buf: Buffer to hold the data + * Return: 0 if OK, -E2BIG if @size > block size, -EBADF if the offset is not + * block-aligned, -EIO if an I/O error occurred, -EPERM if the header version is + * incorrect, the header size is invalid or the data fails its CRC check + */ +int abrec_read_nvdata(struct abrec_priv *priv, struct udevice *blk, + struct abrec_state *state); + +/** + * abrec_read_priv() - Read info from the devicetree + * + * @node: Node to read from + * @priv: Information to fill in + * Return 0 if OK, -EINVAL if something is wrong with the devicetree node + */ +int abrec_read_priv(ofnode node, struct abrec_priv *priv); + +#endif /* __VBE_ABREC_H */ diff --git a/boot/vbe_abrec_fw.c b/boot/vbe_abrec_fw.c new file mode 100644 index 00000000000..d52bd9ddff0 --- /dev/null +++ b/boot/vbe_abrec_fw.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Verified Boot for Embedded (VBE) loading firmware phases + * + * Copyright 2022 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY LOGC_BOOT + +#include <binman_sym.h> +#include <bloblist.h> +#include <bootdev.h> +#include <bootflow.h> +#include <bootmeth.h> +#include <bootstage.h> +#include <display_options.h> +#include <dm.h> +#include <image.h> +#include <log.h> +#include <mapmem.h> +#include <memalign.h> +#include <mmc.h> +#include <spl.h> +#include <vbe.h> +#include <dm/device-internal.h> +#include "vbe_abrec.h" +#include "vbe_common.h" + +binman_sym_declare(ulong, spl_a, image_pos); +binman_sym_declare(ulong, spl_b, image_pos); +binman_sym_declare(ulong, spl_recovery, image_pos); + +binman_sym_declare(ulong, spl_a, size); +binman_sym_declare(ulong, spl_b, size); +binman_sym_declare(ulong, spl_recovery, size); + +binman_sym_declare(ulong, u_boot_a, image_pos); +binman_sym_declare(ulong, u_boot_b, image_pos); +binman_sym_declare(ulong, u_boot_recovery, image_pos); + +binman_sym_declare(ulong, u_boot_a, size); +binman_sym_declare(ulong, u_boot_b, size); +binman_sym_declare(ulong, u_boot_recovery, size); + +binman_sym_declare(ulong, vpl, image_pos); +binman_sym_declare(ulong, vpl, size); + +static const char *const pick_names[] = {"A", "B", "Recovery"}; + +/** + * abrec_read_bootflow_fw() - Create a bootflow for firmware + * + * Locates and loads the firmware image (FIT) needed for the next phase. The FIT + * should ideally use external data, to reduce the amount of it that needs to be + * read. + * + * @bdev: bootdev device containing the firmwre + * @meth: VBE abrec bootmeth + * @blow: Place to put the created bootflow, on success + * @return 0 if OK, -ve on error + */ +int abrec_read_bootflow_fw(struct udevice *dev, struct bootflow *bflow) +{ + struct udevice *media = dev_get_parent(bflow->dev); + struct udevice *meth = bflow->method; + struct abrec_priv *priv = dev_get_priv(meth); + ulong len, load_addr; + struct udevice *blk; + int ret; + + log_debug("media=%s\n", media->name); + ret = blk_get_from_parent(media, &blk); + if (ret) + return log_msg_ret("med", ret); + + ret = vbe_read_fit(blk, priv->area_start + priv->skip_offset, + priv->area_size, NULL, &load_addr, &len, &bflow->name); + if (ret) + return log_msg_ret("vbe", ret); + + /* set up the bootflow with the info we obtained */ + bflow->blk = blk; + bflow->buf = map_sysmem(load_addr, len); + bflow->size = len; + + return 0; +} + +static int abrec_run_vpl(struct udevice *blk, struct spl_image_info *image, + struct vbe_handoff *handoff) +{ + uint flags, tries, prev_result; + struct abrec_priv priv; + struct abrec_state state; + enum vbe_pick_t pick; + uint try_count; + ulong offset, size; + ulong ub_offset, ub_size; + ofnode node; + int ret; + + node = vbe_get_node(); + if (!ofnode_valid(node)) + return log_msg_ret("nod", -EINVAL); + + ret = abrec_read_priv(node, &priv); + if (ret) + return log_msg_ret("pri", ret); + + ret = abrec_read_nvdata(&priv, blk, &state); + if (ret) + return log_msg_ret("sta", ret); + + prev_result = state.try_result; + try_count = state.try_count; + + if (state.recovery) { + pick = VBEP_RECOVERY; + + /* if we are trying B but ran out of tries, use A */ + } else if ((prev_result == VBETR_TRYING) && !tries) { + pick = VBEP_A; + state.try_result = VBETR_BAD; + + /* if requested, try B */ + } else if (flags & VBEF_TRY_B) { + pick = VBEP_B; + + /* decrement the try count if not already zero */ + if (try_count) + try_count--; + state.try_result = VBETR_TRYING; + } else { + pick = VBEP_A; + } + state.try_count = try_count; + + switch (pick) { + case VBEP_A: + offset = binman_sym(ulong, spl_a, image_pos); + size = binman_sym(ulong, spl_a, size); + ub_offset = binman_sym(ulong, u_boot_a, image_pos); + ub_size = binman_sym(ulong, u_boot_a, size); + break; + case VBEP_B: + offset = binman_sym(ulong, spl_b, image_pos); + size = binman_sym(ulong, spl_b, size); + ub_offset = binman_sym(ulong, u_boot_b, image_pos); + ub_size = binman_sym(ulong, u_boot_b, size); + break; + case VBEP_RECOVERY: + offset = binman_sym(ulong, spl_recovery, image_pos); + size = binman_sym(ulong, spl_recovery, size); + ub_offset = binman_sym(ulong, u_boot_recovery, image_pos); + ub_size = binman_sym(ulong, u_boot_recovery, size); + break; + } + log_debug("pick=%d, offset=%lx size=%lx\n", pick, offset, size); + log_info("VBE: Firmware pick %s at %lx\n", pick_names[pick], offset); + + ret = vbe_read_fit(blk, offset, size, image, NULL, NULL, NULL); + if (ret) + return log_msg_ret("vbe", ret); + handoff->offset = ub_offset; + handoff->size = ub_size; + handoff->pick = pick; + image->load_addr = spl_get_image_text_base(); + image->entry_point = image->load_addr; + + return 0; +} + +static int abrec_run_spl(struct udevice *blk, struct spl_image_info *image, + struct vbe_handoff *handoff) +{ + int ret; + + log_info("VBE: Firmware pick %s at %lx\n", pick_names[handoff->pick], + handoff->offset); + ret = vbe_read_fit(blk, handoff->offset, handoff->size, image, NULL, + NULL, NULL); + if (ret) + return log_msg_ret("vbe", ret); + image->load_addr = spl_get_image_text_base(); + image->entry_point = image->load_addr; + + return 0; +} + +static int abrec_load_from_image(struct spl_image_info *image, + struct spl_boot_device *bootdev) +{ + struct vbe_handoff *handoff; + int ret; + + printf("load: %s\n", ofnode_read_string(ofnode_root(), "model")); + if (xpl_phase() != PHASE_VPL && xpl_phase() != PHASE_SPL && + xpl_phase() != PHASE_TPL) + return -ENOENT; + + ret = bloblist_ensure_size(BLOBLISTT_VBE, sizeof(struct vbe_handoff), + 0, (void **)&handoff); + if (ret) + return log_msg_ret("ro", ret); + + if (USE_BOOTMETH) { + struct udevice *meth, *bdev; + struct abrec_priv *priv; + struct bootflow bflow; + + vbe_find_first_device(&meth); + if (!meth) + return log_msg_ret("vd", -ENODEV); + log_debug("vbe dev %s\n", meth->name); + ret = device_probe(meth); + if (ret) + return log_msg_ret("probe", ret); + + priv = dev_get_priv(meth); + log_debug("abrec %s\n", priv->storage); + ret = bootdev_find_by_label(priv->storage, &bdev, NULL); + if (ret) + return log_msg_ret("bd", ret); + log_debug("bootdev %s\n", bdev->name); + + bootflow_init(&bflow, bdev, meth); + ret = bootmeth_read_bootflow(meth, &bflow); + log_debug("\nfw ret=%d\n", ret); + if (ret) + return log_msg_ret("rd", ret); + + /* jump to the image */ + image->flags = SPL_SANDBOXF_ARG_IS_BUF; + image->arg = bflow.buf; + image->size = bflow.size; + log_debug("Image: %s at %p size %x\n", bflow.name, bflow.buf, + bflow.size); + + /* this is not used from now on, so free it */ + bootflow_free(&bflow); + } else { + struct udevice *media; + struct udevice *blk; + + ret = uclass_get_device_by_seq(UCLASS_MMC, 1, &media); + if (ret) + return log_msg_ret("vdv", ret); + ret = blk_get_from_parent(media, &blk); + if (ret) + return log_msg_ret("med", ret); + + if (xpl_phase() == PHASE_TPL) { + ulong offset, size; + + offset = binman_sym(ulong, vpl, image_pos); + size = binman_sym(ulong, vpl, size); + log_debug("VPL at offset %lx size %lx\n", offset, size); + ret = vbe_read_fit(blk, offset, size, image, NULL, + NULL, NULL); + if (ret) + return log_msg_ret("vbe", ret); + } else if (xpl_phase() == PHASE_VPL) { + ret = abrec_run_vpl(blk, image, handoff); + } else { + ret = abrec_run_spl(blk, image, handoff); + } + } + + /* Record that VBE was used in this phase */ + handoff->phases |= 1 << xpl_phase(); + + return 0; +} +SPL_LOAD_IMAGE_METHOD("vbe_abrec", 5, BOOT_DEVICE_VBE, + abrec_load_from_image); diff --git a/boot/vbe_common.c b/boot/vbe_common.c index 0d51fe762c3..a86986d86e9 100644 --- a/boot/vbe_common.c +++ b/boot/vbe_common.c @@ -202,29 +202,30 @@ int vbe_read_fit(struct udevice *blk, ulong area_offset, ulong area_size, phase = IS_ENABLED(CONFIG_TPL_BUILD) ? IH_PHASE_NONE : IS_ENABLED(CONFIG_VPL_BUILD) ? IH_PHASE_SPL : IH_PHASE_U_BOOT; - /* - * Load the image from the FIT. We ignore any load-address information - * so in practice this simply locates the image in the external-data - * region and returns its address and size. Since we only loaded the FIT - * itself, only a part of the image will be present, at best. - */ - fit_uname = NULL; - fit_uname_config = NULL; log_debug("loading FIT\n"); if (xpl_phase() == PHASE_SPL && !IS_ENABLED(CONFIG_SANDBOX)) { struct spl_load_info info; spl_load_init(&info, h_vbe_load_read, desc, desc->blksz); + xpl_set_fdt_update(&info, false); xpl_set_phase(&info, IH_PHASE_U_BOOT); log_debug("doing SPL from %s blksz %lx log2blksz %x area_offset %lx + fdt_size %lx\n", blk->name, desc->blksz, desc->log2blksz, area_offset, ALIGN(size, 4)); ret = spl_load_simple_fit(image, &info, area_offset, buf); - log_debug("spl_load_abrec_fit() ret=%d\n", ret); + log_debug("spl_load_simple_fit() ret=%d\n", ret); return ret; } + /* + * Load the image from the FIT. We ignore any load-address information + * so in practice this simply locates the image in the external-data + * region and returns its address and size. Since we only loaded the FIT + * itself, only a part of the image will be present, at best. + */ + fit_uname = NULL; + fit_uname_config = NULL; ret = fit_image_load(&images, addr, &fit_uname, &fit_uname_config, IH_ARCH_DEFAULT, image_ph(phase, IH_TYPE_FIRMWARE), BOOTSTAGE_ID_FIT_SPL_START, FIT_LOAD_IGNORED, @@ -373,3 +374,8 @@ int vbe_read_fit(struct udevice *blk, ulong area_offset, ulong area_size, return 0; } + +ofnode vbe_get_node(void) +{ + return ofnode_path("/bootstd/firmware0"); +} diff --git a/boot/vbe_common.h b/boot/vbe_common.h index 84117815a19..493cbdc3694 100644 --- a/boot/vbe_common.h +++ b/boot/vbe_common.h @@ -9,6 +9,8 @@ #ifndef __VBE_COMMON_H #define __VBE_COMMON_H +#include <dm/ofnode_decl.h> +#include <linux/bitops.h> #include <linux/types.h> struct spl_image_info; @@ -39,6 +41,40 @@ enum { }; /** + * enum vbe_try_result - result of trying a firmware pick + * + * @VBETR_UNKNOWN: Unknown / invalid result + * @VBETR_TRYING: Firmware pick is being tried + * @VBETR_OK: Firmware pick is OK and can be used from now on + * @VBETR_BAD: Firmware pick is bad and should be removed + */ +enum vbe_try_result { + VBETR_UNKNOWN, + VBETR_TRYING, + VBETR_OK, + VBETR_BAD, +}; + +/** + * enum vbe_flags - flags controlling operation + * + * @VBEF_TRY_COUNT_MASK: mask for the 'try count' value + * @VBEF_TRY_B: Try the B slot + * @VBEF_RECOVERY: Use recovery slot + */ +enum vbe_flags { + VBEF_TRY_COUNT_MASK = 0x3, + VBEF_TRY_B = BIT(2), + VBEF_RECOVERY = BIT(3), + + VBEF_RESULT_SHIFT = 4, + VBEF_RESULT_MASK = 3 << VBEF_RESULT_SHIFT, + + VBEF_PICK_SHIFT = 6, + VBEF_PICK_MASK = 3 << VBEF_PICK_SHIFT, +}; + +/** * struct vbe_nvdata - basic storage format for non-volatile data * * This is used for all VBE methods @@ -134,4 +170,11 @@ int vbe_read_fit(struct udevice *blk, ulong area_offset, ulong area_size, struct spl_image_info *image, ulong *load_addrp, ulong *lenp, char **namep); +/** + * vbe_get_node() - Get the node containing the VBE settings + * + * Return: VBE node (typically "/bootstd/firmware0") + */ +ofnode vbe_get_node(void); + #endif /* __VBE_ABREC_H */ diff --git a/cmd/Kconfig b/cmd/Kconfig index e62817bd977..8dd42571abc 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1178,16 +1178,30 @@ config CMD_FPGA help FPGA support. -config CMD_FPGA_LOADBP - bool "fpga loadbp - load partial bitstream (Xilinx only)" +config CMD_FPGA_LOADB + bool "fpga loadb - load bitstream file" + default y + depends on CMD_FPGA && FPGA_XILINX + help + Supports loading an FPGA device from a bitstream file (.BIT) + +config CMD_FPGA_LOADP + bool "fpga loadp - load partial bitstream" depends on CMD_FPGA help - Supports loading an FPGA device from a bitstream buffer containing - a partial bitstream. + Supports loading an FPGA device from a bitstream buffer (.BIN) + containing a partial bitstream. + +config CMD_FPGA_LOADBP + bool "fpga loadbp - load partial bitstream file" + depends on CMD_FPGA && FPGA_XILINX + help + Supports loading an FPGA device from a bitstream file (.BIT) + containing a partial bitstream. config CMD_FPGA_LOADFS - bool "fpga loadfs - load bitstream from FAT filesystem (Xilinx only)" - depends on CMD_FPGA + bool "fpga loadfs - load bitstream from FAT filesystem" + depends on CMD_FPGA && FPGA_XILINX help Supports loading an FPGA device from a FAT filesystem. @@ -1197,16 +1211,9 @@ config CMD_FPGA_LOADMK help Supports loading an FPGA device from a image generated by mkimage. -config CMD_FPGA_LOADP - bool "fpga loadp - load partial bitstream" - depends on CMD_FPGA - help - Supports loading an FPGA device from a bitstream buffer containing - a partial bitstream. - config CMD_FPGA_LOAD_SECURE bool "fpga loads - loads secure bitstreams" - depends on CMD_FPGA + depends on CMD_FPGA && FPGA_XILINX select FPGA_LOAD_SECURE help Enables the fpga loads command which is used to load secure @@ -1595,6 +1602,7 @@ config CMD_READ config CMD_REMOTEPROC bool "remoteproc" depends on REMOTEPROC + default y if ARCH_K3 help Support for Remote Processor control @@ -2154,6 +2162,7 @@ config WGET_HTTPS depends on CMD_WGET depends on PROT_TCP_LWIP depends on MBEDTLS_LIB + depends on DM_RNG select SHA256 select RSA select ASYMMETRIC_KEY_TYPE diff --git a/cmd/fpga.c b/cmd/fpga.c index 93f14098ccb..9dc7b63db5d 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -67,7 +67,8 @@ static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size, } #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) -int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +static int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) { size_t data_size = 0; long fpga_data, dev; @@ -180,6 +181,7 @@ static int do_fpga_load(struct cmd_tbl *cmdtp, int flag, int argc, return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL, 0); } +#if defined(CONFIG_CMD_FPGA_LOADB) static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -194,7 +196,7 @@ static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc, return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL); } - +#endif #if defined(CONFIG_CMD_FPGA_LOADP) static int do_fpga_loadp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -356,7 +358,9 @@ static struct cmd_tbl fpga_commands[] = { U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""), U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""), U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""), +#if defined(CONFIG_CMD_FPGA_LOADB) U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""), +#endif #if defined(CONFIG_CMD_FPGA_LOADP) U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""), #endif @@ -408,49 +412,40 @@ U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper, #else U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper, #endif - "loadable FPGA image support", - "[operation type] [device number] [image address] [image size]\n" - "fpga operations:\n" - " dump\t[dev] [address] [size]\tLoad device to memory buffer\n" - " info\t[dev]\t\t\tlist known device information\n" - " load\t[dev] [address] [size]\tLoad device from memory buffer\n" + "loadable FPGA image support", + "info [dev] List known device information\n" + "fpga dump <dev> <address> <size> Load device to memory buffer\n" + "fpga load <dev> <address> <size> Load device from memory buffer\n" +#if defined(CONFIG_CMD_FPGA_LOADP) + "fpga loadb <dev> <address> <size> Load device from bitstream buffer\n" +#endif #if defined(CONFIG_CMD_FPGA_LOADP) - " loadp\t[dev] [address] [size]\t" - "Load device from memory buffer with partial bitstream\n" + "fpga loadp <dev> <address> <size> Load device from memory buffer\n" + " with partial bitstream\n" #endif - " loadb\t[dev] [address] [size]\t" - "Load device from bitstream buffer (Xilinx only)\n" #if defined(CONFIG_CMD_FPGA_LOADBP) - " loadbp\t[dev] [address] [size]\t" - "Load device from bitstream buffer with partial bitstream" - "(Xilinx only)\n" + "fpga loadbp <dev> <address> <size> Load device from bitstream buffer\n" + " with partial bitstream\n" #endif #if defined(CONFIG_CMD_FPGA_LOADFS) - "Load device from filesystem (FAT by default) (Xilinx only)\n" - " loadfs [dev] [address] [image size] [blocksize] <interface>\n" - " [<dev[:part]>] <filename>\n" + "fpga loadfs <dev> <address> <size> <blocksize> <interface> [<dev[:part]>] <filename>\n" + " Load device from filesystem (FAT by default)\n" #endif #if defined(CONFIG_CMD_FPGA_LOADMK) - " loadmk [dev] [address]\tLoad device generated with mkimage" + "fpga loadmk <dev> <address> Load device generated with mkimage\n" #if defined(CONFIG_FIT) - "\n" - "\tFor loadmk operating on FIT format uImage address must include\n" - "\tsubimage unit name in the form of addr:<subimg_uname>" + " NOTE: loadmk operating on FIT must include subimage unit\n" + " name in the form of addr:<subimg_uname>\n" #endif #endif #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) - "Load encrypted bitstream (Xilinx only)\n" - " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n" - " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n" - "Loads the secure bistreams(authenticated/encrypted/both\n" - "authenticated and encrypted) of [size] from [address].\n" - "The auth-OCM/DDR flag specifies to perform authentication\n" - "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n" - "The enc flag specifies which key to be used for decryption\n" - "0-device key, 1-user key, 2-no encryption.\n" - "The optional Userkey address specifies from which address key\n" - "has to be used for decryption if user key is selected.\n" - "NOTE: the secure bitstream has to be created using Xilinx\n" - "bootgen tool only.\n" + "fpga loads <dev> <address> <size> <authflag> <encflag> [Userkey address]\n" + " Load device from memory buffer with secure bistream\n" + " (authenticated/encrypted/both)\n" + " -authflag: 0 for OCM, 1 for DDR, 2 for no authentication\n" + " (specifies where to perform authentication)\n" + " -encflag: 0 for device key, 1 for user key, 2 for no encryption\n" + " -Userkey address: address where user key is stored\n" + " NOTE: secure bitstream has to be created using Xilinx bootgen tool\n" #endif ); diff --git a/cmd/setexpr.c b/cmd/setexpr.c index e111b8ba98a..c45fa85c887 100644 --- a/cmd/setexpr.c +++ b/cmd/setexpr.c @@ -35,9 +35,37 @@ struct expr_arg { }; }; +/** + * arg_set_str() - copy string to expression argument + * + * The string is truncated to 64 KiB plus NUL terminator. + * + * @p: pointer to string + * @argp: pointer to expression argument + * Return: 0 on success, -ENOMEM if out of memory + */ +static int arg_set_str(void *p, struct expr_arg *argp) +{ + int len; + char *str; + + /* Maximum string length of 64 KiB plus NUL terminator */ + len = strnlen((char *)p, SZ_64K) + 1; + str = malloc(len); + if (!str) { + printf("Out of memory\n"); + return -ENOMEM; + } + memcpy(str, p, len); + str[len - 1] = '\0'; + argp->sval = str; + return 0; +} + static int get_arg(char *s, int w, struct expr_arg *argp) { struct expr_arg arg; + int ret; /* * If the parameter starts with a '*' then assume it is a pointer to @@ -47,8 +75,6 @@ static int get_arg(char *s, int w, struct expr_arg *argp) ulong *p; ulong addr; ulong val; - int len; - char *str; addr = hextoul(&s[1], NULL); switch (w) { @@ -66,18 +92,10 @@ static int get_arg(char *s, int w, struct expr_arg *argp) break; case CMD_DATA_SIZE_STR: p = map_sysmem(addr, SZ_64K); - - /* Maximum string length of 64KB plus terminator */ - len = strnlen((char *)p, SZ_64K) + 1; - str = malloc(len); - if (!str) { - printf("Out of memory\n"); - return -ENOMEM; - } - memcpy(str, p, len); - str[len - 1] = '\0'; + ret = arg_set_str(p, &arg); unmap_sysmem(p); - arg.sval = str; + if (ret) + return ret; break; case 4: p = map_sysmem(addr, sizeof(u32)); @@ -93,9 +111,13 @@ static int get_arg(char *s, int w, struct expr_arg *argp) break; } } else { - if (w == CMD_DATA_SIZE_STR) - return -EINVAL; - arg.ival = hextoul(s, NULL); + if (w == CMD_DATA_SIZE_STR) { + ret = arg_set_str(s, &arg); + if (ret) + return ret; + } else { + arg.ival = hextoul(s, NULL); + } } *argp = arg; diff --git a/common/Kconfig b/common/Kconfig index 7685914fa6f..1d6de8badf7 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1055,8 +1055,8 @@ choice config BLOBLIST_FIXED bool "Place bloblist at a fixed address in memory" help - Select this to used a fixed memory address for the bloblist. If the - bloblist exists at this address from a previous phase, it used as is. + Select this to use a fixed memory address for the bloblist. If the + bloblist exists at this address from a previous phase, it is used as is. If not it is created at this address in U-Boot. config BLOBLIST_ALLOC @@ -1066,6 +1066,16 @@ config BLOBLIST_ALLOC specify a fixed address on systems where this is unknown or can change at runtime. +config BLOBLIST_PASSAGE_MANDATORY + bool "Use bloblist in-place mandatorily" + help + By default U-Boot will use a bloblist in the incoming standard passage. + This option controls whether U-Boot tries to load a static bloblist or + allocate one if a valid incoming bloblist does not exist. + Select this option to mark incoming standard passage as mandatory and + U-Boot will report an error when a valid incoming bloblist does not + exist. + endchoice config BLOBLIST_ADDR @@ -1080,17 +1090,17 @@ config BLOBLIST_ADDR config BLOBLIST_SIZE hex "Size of bloblist" + default 0x0 if BLOBLIST_PASSAGE_MANDATORY default 0x400 help Sets the size of the bloblist in bytes. This must include all overhead (alignment, bloblist header, record header). The bloblist is set up in the first part of U-Boot to run (TPL, SPL or U-Boot - proper), and this sane bloblist is used for subsequent phases. + proper), and this same bloblist is used for subsequent phases. config BLOBLIST_SIZE_RELOC hex "Size of bloblist after relocation" default BLOBLIST_SIZE if BLOBLIST_FIXED || BLOBLIST_ALLOC - default 0x0 if BLOBLIST_PASSAGE default 0x20000 if (ARM && EFI_LOADER && GENERATE_ACPI_TABLE) help Sets the size of the bloblist in bytes after relocation. Since U-Boot diff --git a/common/autoboot.c b/common/autoboot.c index 898a57bc92b..0a254498d40 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -186,10 +186,15 @@ static int passwd_abort_sha256(uint64_t etime) ret = hash_parse_string(algo_name, sha_env_str, sha_env); if (ret) { printf("Hash %s not supported!\n", algo_name); + free(presskey); return 0; } sha = malloc_cache_aligned(SHA256_SUM_LEN); + if (!sha) { + free(presskey); + return -ENOMEM; + } size = SHA256_SUM_LEN; /* * We don't know how long the stop-string is, so we need to diff --git a/common/bloblist.c b/common/bloblist.c index ab48a3cdb98..6e4f020d7c4 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -488,6 +488,9 @@ int bloblist_reloc(void *to, uint to_size) { struct bloblist_hdr *hdr; + if (!to_size) + return 0; + if (to_size < gd->bloblist->total_size) return -ENOSPC; @@ -502,8 +505,7 @@ int bloblist_reloc(void *to, uint to_size) /* * Weak default function for getting bloblist from boot args. */ -int __weak xferlist_from_boot_arg(ulong __always_unused addr, - ulong __always_unused size) +int __weak xferlist_from_boot_arg(ulong __always_unused *addr) { return -ENOENT; } @@ -511,38 +513,46 @@ int __weak xferlist_from_boot_arg(ulong __always_unused addr, int bloblist_init(void) { bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED); - int ret = -ENOENT; + int ret = 0; ulong addr = 0, size; - /* - * If U-Boot is not in the first phase, an existing bloblist must be - * at a fixed address. - */ - bool from_addr = fixed && !xpl_is_first_phase(); - /* - * If U-Boot is in the first phase that an arch custom routine should - * install the bloblist passed from previous loader to this fixed - * address. - */ - bool from_boot_arg = fixed && xpl_is_first_phase(); - if (xpl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST)) - from_addr = false; - if (fixed) - addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED, - CONFIG_BLOBLIST_ADDR); - size = CONFIG_BLOBLIST_SIZE; + /* Check if a valid transfer list passed in */ + if (!xferlist_from_boot_arg(&addr)) { + size = bloblist_get_total_size(); + } else { + /* + * If U-Boot is not in the first phase, an existing bloblist must + * be at a fixed address. + */ + bool from_addr = fixed && !xpl_is_first_phase(); + + /* + * If Firmware Handoff is mandatory but no transfer list is + * observed, report it as an error. + */ + if (IS_ENABLED(CONFIG_BLOBLIST_PASSAGE_MANDATORY)) + return -ENOENT; - if (from_boot_arg) - ret = xferlist_from_boot_arg(addr, size); - else if (from_addr) - ret = bloblist_check(addr, size); + ret = -ENOENT; - if (ret) - log_warning("Bloblist at %lx not found (err=%d)\n", - addr, ret); - else - /* Get the real size */ - size = gd->bloblist->total_size; + if (xpl_prev_phase() == PHASE_TPL && + !IS_ENABLED(CONFIG_TPL_BLOBLIST)) + from_addr = false; + if (fixed) + addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED, + CONFIG_BLOBLIST_ADDR); + size = CONFIG_BLOBLIST_SIZE; + + if (from_addr) + ret = bloblist_check(addr, size); + + if (ret) + log_warning("Bloblist at %lx not found (err=%d)\n", + addr, ret); + else + /* Get the real size */ + size = gd->bloblist->total_size; + } if (ret) { /* @@ -567,6 +577,7 @@ int bloblist_init(void) log_debug("Found existing bloblist size %lx at %lx\n", size, addr); } + if (ret) return log_msg_ret("ini", ret); gd->flags |= GD_FLG_BLOBLIST_READY; @@ -587,10 +598,11 @@ int bloblist_maybe_init(void) return 0; } -int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig) +int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig, ulong xlist) { u64 version = BLOBLIST_REGCONV_VER; ulong sigval; + int ret; if ((IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_SPL_BUILD)) || (IS_ENABLED(CONFIG_SPL_64BIT) && IS_ENABLED(CONFIG_SPL_BUILD))) { @@ -601,8 +613,14 @@ int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig) ((version & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_32)); } - if (rzero || rsig != sigval || - rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) { + if (rzero || rsig != sigval) + return -EIO; + + ret = bloblist_check(xlist, 0); + if (ret) + return ret; + + if (rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) { gd->bloblist = NULL; /* Reset the gd bloblist pointer */ return -EIO; } diff --git a/common/board_f.c b/common/board_f.c index 6c5c3bfab48..2912320054f 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -624,11 +624,14 @@ static int reserve_stacks(void) static int reserve_bloblist(void) { #ifdef CONFIG_BLOBLIST + ulong size = bloblist_get_total_size(); + + if (size < CONFIG_BLOBLIST_SIZE_RELOC) + size = CONFIG_BLOBLIST_SIZE_RELOC; + /* Align to a 4KB boundary for easier reading of addresses */ - gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp - - CONFIG_BLOBLIST_SIZE_RELOC, 0x1000); - gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp, - CONFIG_BLOBLIST_SIZE_RELOC); + gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp - size, 0x1000); + gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp, size); #endif return 0; @@ -698,11 +701,14 @@ static int reloc_bloblist(void) return 0; } if (gd->boardf->new_bloblist) { - debug("Copying bloblist from %p to %p, size %x\n", - gd->bloblist, gd->boardf->new_bloblist, - gd->bloblist->total_size); - return bloblist_reloc(gd->boardf->new_bloblist, - CONFIG_BLOBLIST_SIZE_RELOC); + ulong size = bloblist_get_total_size(); + + if (size < CONFIG_BLOBLIST_SIZE_RELOC) + size = CONFIG_BLOBLIST_SIZE_RELOC; + + debug("Copying bloblist from %p to %p, size %lx\n", + gd->bloblist, gd->boardf->new_bloblist, size); + return bloblist_reloc(gd->boardf->new_bloblist, size); } #endif diff --git a/common/board_r.c b/common/board_r.c index 179259b00de..db0c5cb8032 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -749,9 +749,6 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_BOARD_LATE_INIT board_late_init, #endif -#ifdef CONFIG_BITBANGMII - bb_miiphy_init, -#endif #ifdef CONFIG_PCI_ENDPOINT pci_ep_init, #endif diff --git a/common/cli_hush.c b/common/cli_hush.c index a6a8edce1f4..9f437ae5f47 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -3626,7 +3626,13 @@ static char *make_string(char **inp, int *nonnull) noeval = 1; for (n = 0; inp[n]; n++) { p = insert_var_value_sub(inp[n], noeval); - str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n]))); + char *new_str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n]))); + if (!new_str) { + free(str); + if (p != inp[n]) free(p); + return NULL; + } + str = new_str; if (n) { strcat(str, " "); } else { diff --git a/common/hash.c b/common/hash.c index 8dd9da85768..0c45992d5c7 100644 --- a/common/hash.c +++ b/common/hash.c @@ -143,7 +143,8 @@ static int __maybe_unused hash_finish_sha512(struct hash_algo *algo, void *ctx, return 0; } -static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp) +static int __maybe_unused hash_init_crc16_ccitt(struct hash_algo *algo, + void **ctxp) { uint16_t *ctx = malloc(sizeof(uint16_t)); *ctx = 0; @@ -151,16 +152,18 @@ static int hash_init_crc16_ccitt(struct hash_algo *algo, void **ctxp) return 0; } -static int hash_update_crc16_ccitt(struct hash_algo *algo, void *ctx, - const void *buf, unsigned int size, - int is_last) +static int __maybe_unused hash_update_crc16_ccitt(struct hash_algo *algo, + void *ctx, const void *buf, + unsigned int size, + int is_last) { *((uint16_t *)ctx) = crc16_ccitt(*((uint16_t *)ctx), buf, size); return 0; } -static int hash_finish_crc16_ccitt(struct hash_algo *algo, void *ctx, - void *dest_buf, int size) +static int __maybe_unused hash_finish_crc16_ccitt(struct hash_algo *algo, + void *ctx, void *dest_buf, + int size) { if (size < algo->digest_size) return -1; @@ -295,6 +298,7 @@ static struct hash_algo hash_algo[] = { #endif }, #endif +#if CONFIG_IS_ENABLED(CRC16) { .name = "crc16-ccitt", .digest_size = 2, @@ -304,6 +308,7 @@ static struct hash_algo hash_algo[] = { .hash_update = hash_update_crc16_ccitt, .hash_finish = hash_finish_crc16_ccitt, }, +#endif #if CONFIG_IS_ENABLED(CRC8) && IS_ENABLED(CONFIG_HASH_CRC8) { .name = "crc8", diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 9b8744e5d8b..2a034d3a77c 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -65,6 +65,14 @@ void miiphy_init(void) current_mii = NULL; } +void mdio_init(struct mii_dev *bus) +{ + memset(bus, 0, sizeof(*bus)); + + /* initialize mii_dev struct fields */ + INIT_LIST_HEAD(&bus->link); +} + struct mii_dev *mdio_alloc(void) { struct mii_dev *bus; @@ -73,10 +81,7 @@ struct mii_dev *mdio_alloc(void) if (!bus) return bus; - memset(bus, 0, sizeof(*bus)); - - /* initalize mii_dev struct fields */ - INIT_LIST_HEAD(&bus->link); + mdio_init(bus); return bus; } diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 94e118f8465..7d6780936d1 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1287,6 +1287,7 @@ config SPL_RAM_DEVICE config SPL_REMOTEPROC bool "Support REMOTEPROCS" + default y if (CPU_V7R && ARCH_K3) help Enable support for REMOTEPROCs in SPL. This permits to load a remote processor firmware in SPL. diff --git a/common/spl/Kconfig.vpl b/common/spl/Kconfig.vpl index 97dfc630152..cf6b36c8e38 100644 --- a/common/spl/Kconfig.vpl +++ b/common/spl/Kconfig.vpl @@ -9,6 +9,19 @@ config VPL_BANNER_PRINT info. Disabling this option could be useful to reduce VPL boot time (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). +config VPL_LDSCRIPT + string "Linker script for the VPL stage" + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 + default "arch/\$(ARCH)/cpu/u-boot-spl.lds" + help + The TPL stage will usually require a different linker-script + (as it runs from a different memory region) than the regular + U-Boot stage. Set this to the path of the linker-script to + be used for TPL. + + May be left empty to trigger the Makefile infrastructure to + fall back to the linker-script used for the SPL stage. + config VPL_BOARD_INIT bool "Call board-specific initialization in VPL" help diff --git a/common/spl/spl.c b/common/spl/spl.c index 9af0a4954d4..76fd56dfe4b 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -50,8 +50,10 @@ u32 *boot_params_ptr = NULL; #if CONFIG_IS_ENABLED(BINMAN_UBOOT_SYMBOLS) /* See spl.h for information about this */ +#if defined(CONFIG_SPL_BUILD) binman_sym_declare(ulong, u_boot_any, image_pos); binman_sym_declare(ulong, u_boot_any, size); +#endif #ifdef CONFIG_TPL binman_sym_declare(ulong, u_boot_spl_any, image_pos); @@ -179,9 +181,15 @@ ulong spl_get_image_pos(void) if (xpl_next_phase() == PHASE_VPL) return binman_sym(ulong, u_boot_vpl_any, image_pos); #endif - return xpl_next_phase() == PHASE_SPL ? - binman_sym(ulong, u_boot_spl_any, image_pos) : - binman_sym(ulong, u_boot_any, image_pos); +#if defined(CONFIG_TPL) && !defined(CONFIG_VPL) + if (xpl_next_phase() == PHASE_SPL) + return binman_sym(ulong, u_boot_spl_any, image_pos); +#endif +#if defined(CONFIG_SPL_BUILD) + return binman_sym(ulong, u_boot_any, image_pos); +#endif + + return BINMAN_SYM_MISSING; } ulong spl_get_image_size(void) @@ -263,14 +271,20 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) */ if (u_boot_pos && u_boot_pos != BINMAN_SYM_MISSING) { /* Binman does not support separated entry addresses */ - spl_image->entry_point = u_boot_pos; - spl_image->load_addr = u_boot_pos; + spl_image->entry_point = spl_get_image_text_base(); + spl_image->load_addr = spl_get_image_text_base(); + spl_image->size = spl_get_image_size(); + log_debug("Next load addr %lx\n", spl_image->load_addr); } else { spl_image->entry_point = CONFIG_SYS_UBOOT_START; spl_image->load_addr = CONFIG_TEXT_BASE; + log_debug("Default load addr %x (u_boot_pos=%lx)\n", + CONFIG_TEXT_BASE, u_boot_pos); } spl_image->os = IH_OS_U_BOOT; - spl_image->name = "U-Boot"; + spl_image->name = xpl_name(xpl_next_phase()); + log_debug("Next phase: %s at %lx size %lx\n", spl_image->name, + spl_image->load_addr, (ulong)spl_image->size); } __weak int spl_parse_board_header(struct spl_image_info *spl_image, diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 64c4349b138..49b4df60560 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -199,7 +199,9 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, * the image gets loaded to the address pointed to by the * load_addr member in this struct, if load_addr is not 0 * - * Return: 0 on success or a negative error number. + * Return: 0 on success, -EPERM if this image is not the correct phase + * (for CONFIG_BOOTMETH_VBE_SIMPLE_FW), or another negative error number on + * other error. */ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, const struct spl_fit_info *ctx, int node, @@ -218,6 +220,25 @@ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, const void *fit = ctx->fit; bool external_data = false; + log_debug("starting\n"); + if (CONFIG_IS_ENABLED(BOOTMETH_VBE) && + xpl_get_phase(info) != IH_PHASE_NONE) { + enum image_phase_t phase; + int ret; + + ret = fit_image_get_phase(fit, node, &phase); + /* if the image is for any phase, let's use it */ + if (ret == -ENOENT || phase == xpl_get_phase(info)) { + log_debug("found\n"); + } else if (ret < 0) { + log_debug("err=%d\n", ret); + return ret; + } else { + log_debug("- phase mismatch, skipping this image\n"); + return -EPERM; + } + } + if (IS_ENABLED(CONFIG_SPL_FPGA) || (IS_ENABLED(CONFIG_SPL_OS_BOOT) && spl_decompression_enabled())) { if (fit_image_get_type(fit, node, &type)) @@ -278,10 +299,7 @@ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, log_debug("reading from offset %x / %lx size %lx to %p: ", offset, read_offset, size, src_ptr); - if (info->read(info, - fit_offset + - get_aligned_image_offset(info, offset), size, - src_ptr) < length) + if (info->read(info, read_offset, size, src_ptr) < length) return -EIO; debug("External data: dst=%p, offset=%x, size=%lx\n", @@ -456,7 +474,9 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, image_info.load_addr = (ulong)tmpbuffer; ret = load_simple_fit(info, offset, ctx, node, &image_info); - if (ret < 0) + if (ret == -EPERM) + continue; + else if (ret < 0) break; /* Make room in FDT for changes from the overlay */ @@ -495,9 +515,6 @@ static int spl_fit_record_loadable(const struct spl_fit_info *ctx, int index, const char *name; int node; - if (CONFIG_IS_ENABLED(FIT_IMAGE_TINY)) - return 0; - ret = spl_fit_get_image_name(ctx, "loadables", index, &name); if (ret < 0) return ret; @@ -817,7 +834,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, image_info.load_addr = 0; ret = load_simple_fit(info, offset, &ctx, node, &image_info); - if (ret < 0) { + if (ret < 0 && ret != -EPERM) { printf("%s: can't load image loadables index %d (ret = %d)\n", __func__, index, ret); return ret; @@ -843,7 +860,8 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, spl_image->entry_point = image_info.entry_point; /* Record our loadables into the FDT */ - if (spl_image->fdt_addr) + if (!CONFIG_IS_ENABLED(FIT_IMAGE_TINY) && + xpl_get_fdt_update(info) && spl_image->fdt_addr) spl_fit_record_loadable(&ctx, index, spl_image->fdt_addr, &image_info); diff --git a/common/spl/spl_reloc.c b/common/spl/spl_reloc.c index be8349b535b..324b98eaf98 100644 --- a/common/spl/spl_reloc.c +++ b/common/spl/spl_reloc.c @@ -154,7 +154,7 @@ int spl_reloc_jump(struct spl_image_info *image, spl_jump_to_image_t jump) rcode_func loader; int ret; - log_debug("malloc usage %lx bytes (%ld KB of %d KB)\n", gd->malloc_ptr, + log_debug("malloc usage %x bytes (%d KB of %d KB)\n", gd->malloc_ptr, gd->malloc_ptr / 1024, CONFIG_VAL(SYS_MALLOC_F_LEN) / 1024); if (*image->stack_prot != STACK_PROT_VALUE) { diff --git a/config.mk b/config.mk index e294be2a4c4..abed9cb65c6 100644 --- a/config.mk +++ b/config.mk @@ -76,4 +76,3 @@ export PLATFORM_CPPFLAGS export RELFLAGS export LDFLAGS_FINAL export LDFLAGS_STANDALONE -export CONFIG_STANDALONE_LOAD_ADDR diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 4059d07b5c8..c550e5e121e 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -77,6 +77,7 @@ CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_AM33XX_NVMEM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="setenv boot_syslinux_conf \"extlinux/extlinux-rollback.conf\"; run distro_bootcmd; setenv boot_syslinux_conf \"extlinux/extlinux.conf\"; run bootcmd_ubifs0;" CONFIG_CLK=y CONFIG_CLK_CCF=y CONFIG_CLK_TI_AM3_DPLL=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index d10d2a5940f..13260edf3f0 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -10,7 +10,6 @@ CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL_TEXT_BASE=0x40300000 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y @@ -54,8 +53,7 @@ CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y +# CONFIG_ENV_IS_IN_FAT is not set CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 5cacd7f9cc5..a406e899d42 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -13,7 +13,6 @@ CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 CONFIG_TARGET_AM57XX_EVM=y CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_ARMV7_LPAE=y @@ -50,8 +49,7 @@ CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y +# CONFIG_ENV_IS_IN_FAT is not set CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index bf6e9639901..d77ff2d7221 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -41,7 +41,6 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_MMC=y CONFIG_MMC_SPEED_MODE_SET=y -CONFIG_CMD_REMOTEPROC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y @@ -95,9 +94,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y -CONFIG_REMOTEPROC_TI_K3_DSP=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y @@ -107,3 +103,5 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 + +#include <configs/am62x_a53_usbdfu.config> diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index 1f7750c4c03..cbdc219e25e 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-sk" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145 CONFIG_SPL_TEXT_BASE=0x43c00000 @@ -47,7 +48,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y @@ -55,7 +55,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -82,6 +81,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_ESM_K3=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y @@ -95,7 +95,6 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig index 30b4a24ee9a..4b5d1ec1613 100644 --- a/configs/am62px_evm_a53_defconfig +++ b/configs/am62px_evm_a53_defconfig @@ -40,14 +40,11 @@ CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y -CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_RAM_SUPPORT=y -CONFIG_SPL_RAM_DEVICE=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -57,7 +54,6 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -84,17 +80,12 @@ CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y -CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_TI_SCI=y -CONFIG_DFU_MMC=y CONFIG_DFU_MTD=y -CONFIG_DFU_RAM=y CONFIG_DFU_SF=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 -CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -146,9 +137,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y -CONFIG_REMOTEPROC_TI_K3_DSP=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y @@ -163,22 +151,10 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_DM_THERMAL=y -CONFIG_USB=y -CONFIG_DM_USB_GADGET=y -CONFIG_SPL_DM_USB_GADGET=y CONFIG_SPL_USB_HOST=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_SPL_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_SPL_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" -CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 -CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_EFI_SET_TIME=y #include <configs/k3_efi_capsule.config> +#include <configs/am62x_a53_usbdfu.config> diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index c3adfb8697a..39b6a83ab42 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_TEXT_BASE=0x43c00000 @@ -48,7 +49,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -60,7 +60,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -87,6 +86,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y +CONFIG_ESM_K3=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y @@ -109,7 +109,6 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config index 812f99ee70b..16cd4c89f41 100644 --- a/configs/am62x_a53_usbdfu.config +++ b/configs/am62x_a53_usbdfu.config @@ -6,6 +6,7 @@ CONFIG_SPL_USB_GADGET=y CONFIG_SPL_DFU=y CONFIG_CMD_DFU=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SYSCON=y CONFIG_SPL_SYSCON=y CONFIG_DFU_MMC=y diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig index af54f9670a7..cedd0f75378 100644 --- a/configs/am62x_beagleplay_a53_defconfig +++ b/configs/am62x_beagleplay_a53_defconfig @@ -30,7 +30,6 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y -CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" @@ -111,7 +110,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_TPS65219=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index bbc55417a7e..5a465bff158 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -50,14 +50,12 @@ CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -95,7 +93,6 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index c77e09db156..d9596cb7224 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -33,7 +33,6 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y -CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_BOOTCOMMAND="run findfdt; run envboot; bootflow scan -lb" CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 @@ -120,7 +119,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index b47f2f2d1f3..8eb59400eb2 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -53,7 +53,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -64,7 +63,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -110,7 +108,6 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y diff --git a/configs/am62x_r5_usbdfu.config b/configs/am62x_r5_usbdfu.config index 62c9247c582..5bbb99ec30d 100644 --- a/configs/am62x_r5_usbdfu.config +++ b/configs/am62x_r5_usbdfu.config @@ -25,3 +25,6 @@ CONFIG_SPL_DFU=y # CONFIG_CMD_GPT is not set # CONFIG_CMD_FAT is not set # CONFIG_MMC is not set +# CONFIG_SPL_MTD is not set +# CONFIG_DMA_CHANNELS is not set +# CONFIG_TI_K3_NAVSS_UDMA is not set diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index a501f3f567e..3f002aecfa7 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -148,9 +148,6 @@ CONFIG_PMIC_TPS65219=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_TPS65219=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y -CONFIG_REMOTEPROC_TI_PRU=y -CONFIG_CMD_REMOTEPROC=y CONFIG_RESET_TI_SCI=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 0ceac16dd20..b222bcd6e43 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -59,7 +59,6 @@ CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL" CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -71,7 +70,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set @@ -138,7 +136,6 @@ CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index e9b736714a5..12c4cb96815 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -66,7 +66,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_PCI=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_TIME=y CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0" @@ -144,8 +143,6 @@ CONFIG_TI_SCI_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_REMOTEPROC_TI_K3_R5F=y -CONFIG_REMOTEPROC_TI_PRU=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 4bd5e8f63ff..386749ebabd 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -24,7 +24,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c7effc CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y @@ -54,7 +53,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -66,7 +64,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -124,7 +121,6 @@ CONFIG_DM_REGULATOR_TPS62360=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index ae57007d898..227de53795b 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -22,7 +22,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c7effc CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_LIBDISK_SUPPORT=y @@ -48,7 +47,6 @@ CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -56,7 +54,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -105,7 +102,6 @@ CONFIG_DM_REGULATOR_TPS62360=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SYSRESET=y diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index 3aa17eb77f0..90a857b8b95 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -22,7 +22,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c7effc CONFIG_SPL_BSS_MAX_SIZE=0xc00 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0x7ec00 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y @@ -48,14 +47,12 @@ CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -102,7 +99,6 @@ CONFIG_DM_REGULATOR_TPS62360=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SYSRESET=y diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index b4aebf3e9fb..8bee002777a 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -17,6 +17,7 @@ CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_REMAKE_ELF=y +CONFIG_EFI_HTTP_BOOT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y @@ -30,6 +31,8 @@ CONFIG_SYS_PROMPT="versal2> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y @@ -39,15 +42,13 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_MMC_SPEED_MODE_SET=y +CONFIG_CMD_OPTEE=y CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y @@ -67,9 +68,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y @@ -152,5 +151,7 @@ CONFIG_UFS_AMD_VERSAL2=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y # CONFIG_OPTEE_LIB is not set +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 2b0b8b2d3b7..f5c05fd4616 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -25,7 +25,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run common_bootargs; run romboot" -CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" CONFIG_SYS_MAXARGS=32 @@ -81,7 +80,6 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_GIGE=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index afff2d54f2c..edb49de207c 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -44,10 +44,10 @@ CONFIG_SYS_PROMPT="antminer> " CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 3ed587a1060..2b72ec91632 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=500 CONFIG_NETCONSOLE=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="led 5 on; boot" CONFIG_VYBRID_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig index f02aef24048..d468465a9cc 100644 --- a/configs/brppt2_defconfig +++ b/configs/brppt2_defconfig @@ -76,6 +76,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_OF_TRANSLATE is not set # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="setenv b_mode 0; run b_default;" CONFIG_SYS_I2C_MXC=y CONFIG_MMC_BROKEN_CD=y # CONFIG_SPL_DM_MMC is not set diff --git a/configs/capricorn_cxg3_defconfig b/configs/capricorn_cxg3_defconfig index 4832a795e50..10e0cbd9ad2 100644 --- a/configs/capricorn_cxg3_defconfig +++ b/configs/capricorn_cxg3_defconfig @@ -95,6 +95,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SPL_CLK=y CONFIG_CLK_IMX8=y CONFIG_CPU=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 1b018ef4d7c..5b8c0d35de6 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y +CONFIG_TPL_GPIO=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 1ee0c0e6c9d..a29a04aadde 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y +CONFIG_TPL_GPIO=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/dh_imx6.config b/configs/dh_imx6.config new file mode 100644 index 00000000000..01db41be2a0 --- /dev/null +++ b/configs/dh_imx6.config @@ -0,0 +1,76 @@ +#include <configs/imx_dhsom.config> + +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QDL=y +CONFIG_TARGET_DHCOMIMX6=y +CONFIG_SPL_SYS_L2_PL310=y +CONFIG_MX6_DDRCAL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_UPSTREAM=y +CONFIG_FIT_VERBOSE=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_LTO=y + +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SYS_MAXARGS=32 +CONFIG_SYS_MEMTEST_END=0x20000000 +CONFIG_SYS_MEMTEST_START=0x10000000 +CONFIG_SYS_MONITOR_LEN=409600 +CONFIG_SYS_PBSIZE=532 + +CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 +CONFIG_SYS_BOOTCOUNT_BE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTDELAY=3 + +CONFIG_BZIP2=y +CONFIG_CMD_SATA=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_WDT=y +CONFIG_DISTRO_DEFAULTS=y + +CONFIG_ENV_OFFSET=0x100000 +CONFIG_ENV_OFFSET_REDUND=0x110000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SIZE=0x4000 + +# CONFIG_CMD_SCSI is not set +CONFIG_AHCI=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DWC_AHSATA=y +CONFIG_LBA48=y +CONFIG_SCSI=y + +CONFIG_ARP_TIMEOUT=200 +CONFIG_ETHPRIME="FEC" +CONFIG_USE_ETHPRIME=y +CONFIG_PHYLIB=y + +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_UNLOCK_ALL=y + +CONFIG_MISC=y + +CONFIG_PINCTRL_IMX6=y + +CONFIG_SDP_LOADADDR=0x17ffffc0 +CONFIG_SPL_FIT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y + +CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 43ac5a567ba..552d743b7df 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -1,78 +1,4 @@ -#include <configs/imx_dhsom.config> +#include <configs/dh_imx6.config> -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_MX6QDL=y -CONFIG_TARGET_DHCOMIMX6=y -CONFIG_SPL_SYS_L2_PL310=y CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-dhcom-pdk2" -CONFIG_MX6_DDRCAL=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_LIST="nxp/imx/imx6q-dhcom-pdk2 nxp/imx/imx6dl-dhcom-pdk2 nxp/imx/imx6s-dhcom-drc02 nxp/imx/imx6dl-dhcom-picoitx" -CONFIG_OF_UPSTREAM=y -CONFIG_FIT_VERBOSE=y -CONFIG_MULTI_DTB_FIT=y -CONFIG_LTO=y - -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SYS_I2C_MXC=y -CONFIG_SYS_MALLOC_F_LEN=0x1000 -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_MEMTEST_END=0x20000000 -CONFIG_SYS_MEMTEST_START=0x10000000 -CONFIG_SYS_MONITOR_LEN=409600 -CONFIG_SYS_PBSIZE=532 - -CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 -CONFIG_SYS_BOOTCOUNT_BE=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTDELAY=3 - -CONFIG_BZIP2=y -CONFIG_CMD_SATA=y -CONFIG_CMD_UNZIP=y -CONFIG_CMD_WDT=y -CONFIG_DISTRO_DEFAULTS=y - -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_OFFSET_REDUND=0x110000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_ENV_SIZE=0x4000 - -# CONFIG_CMD_SCSI is not set -CONFIG_AHCI=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_DWC_AHSATA=y -CONFIG_LBA48=y -CONFIG_SCSI=y - -CONFIG_ARP_TIMEOUT=200 -CONFIG_ETHPRIME="FEC" -CONFIG_USE_ETHPRIME=y -CONFIG_PHYLIB=y - -CONFIG_SF_DEFAULT_SPEED=25000000 -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_UNLOCK_ALL=y - -CONFIG_MISC=y - -CONFIG_PINCTRL_IMX6=y - -CONFIG_SDP_LOADADDR=0x17ffffc0 -CONFIG_SPL_FIT=y -CONFIG_SPL_SPI=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_SDP_SUPPORT=y -CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 -CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y - -CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 765920bd5d1..55f9bbaa1cf 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -96,6 +96,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run recovery" CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2 diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig index f650dbca660..6c175dd73b9 100644 --- a/configs/draco-etamin_defconfig +++ b/configs/draco-etamin_defconfig @@ -79,6 +79,7 @@ CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_CLK=y CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig index 511956ec844..521a090e376 100644 --- a/configs/draco-rastaban_defconfig +++ b/configs/draco-rastaban_defconfig @@ -76,6 +76,7 @@ CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_CLK=y CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig index 1b2ce3b0104..2c16db237f8 100644 --- a/configs/draco-thuban_defconfig +++ b/configs/draco-thuban_defconfig @@ -76,6 +76,7 @@ CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_CLK=y CONFIG_CLK_TI_CTRL=y CONFIG_DFU_NAND=y diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index c36196c510c..5facd418260 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -8,23 +8,40 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ARCH_EXYNOS9=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96" CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_ENV_OFFSET_REDUND=0x10000 # CONFIG_PSCI_RESET is not set +CONFIG_EFI_SET_TIME=y CONFIG_ANDROID_BOOT_IMAGE=y -# CONFIG_AUTOBOOT is not set +CONFIG_BOOTSTD_FULL=y +CONFIG_DEFAULT_FDT_FILE="exynos850-e850-96.dtb" # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ABOOTIMG=y +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_CLK=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y +CONFIG_CMD_EFIDEBUG=y +# CONFIG_CMD_DATE is not set +CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y CONFIG_CMD_RNG=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 CONFIG_NO_NET=y CONFIG_CLK_EXYNOS850=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y CONFIG_SOC_SAMSUNG=y CONFIG_EXYNOS_PMU=y CONFIG_EXYNOS_USI=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index ba79960495e..d215af0c046 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -11,7 +11,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-evb" CONFIG_ROCKCHIP_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0x10081fff @@ -23,7 +23,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index 215858c789b..fec4b67aee2 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -78,6 +78,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_DM_BOOTCOUNT_SPI_FLASH=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; run hasfirstboot || setenv mmcpart 0; if test ${mmcpart} != 0; then setenv bootcause REVERT; run swappartitions loadimage doboot; fi; run failbootcmd" CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index c24513f6ab1..676b5bc8a28 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -52,6 +52,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run doquiet; setenv partnum 1; run hasfirstboot || setenv partnum 2; run hasfirstboot || setenv partnum 0; if test ${partnum} != 0; then run swappartitions loadimage doboot; fi; run failbootcmd" CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_I2C_MUX=y diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig index e4b9a9a5abb..6cb2a21ed2d 100644 --- a/configs/ibex-ast2700_defconfig +++ b/configs/ibex-ast2700_defconfig @@ -27,7 +27,6 @@ CONFIG_TARGET_ASPEED_AST2700_IBEX=y # CONFIG_SPL_SMP is not set CONFIG_XIP=y CONFIG_SPL_XIP=y -# CONFIG_AVAILABLE_HARTS is not set CONFIG_STACK_SIZE_SHIFT=11 CONFIG_ENV_VARS_UBOOT_CONFIG=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/imx6_dhcom_drc02_defconfig b/configs/imx6_dhcom_drc02_defconfig new file mode 100644 index 00000000000..72a0498d9b2 --- /dev/null +++ b/configs/imx6_dhcom_drc02_defconfig @@ -0,0 +1,4 @@ +#include <configs/dh_imx6.config> + +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6s-dhcom-drc02" +CONFIG_OF_LIST="nxp/imx/imx6s-dhcom-drc02" diff --git a/configs/imx6_dhcom_pdk2_defconfig b/configs/imx6_dhcom_pdk2_defconfig new file mode 100644 index 00000000000..6cc81f624f7 --- /dev/null +++ b/configs/imx6_dhcom_pdk2_defconfig @@ -0,0 +1,4 @@ +#include <configs/dh_imx6.config> + +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-dhcom-pdk2" +CONFIG_OF_LIST="nxp/imx/imx6q-dhcom-pdk2 nxp/imx/imx6dl-dhcom-pdk2" diff --git a/configs/imx6_dhcom_picoitx_defconfig b/configs/imx6_dhcom_picoitx_defconfig new file mode 100644 index 00000000000..837aab6810f --- /dev/null +++ b/configs/imx6_dhcom_picoitx_defconfig @@ -0,0 +1,4 @@ +#include <configs/dh_imx6.config> + +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-dhcom-picoitx" +CONFIG_OF_LIST="nxp/imx/imx6dl-dhcom-picoitx" diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index 54758df8c01..017c27479d2 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -86,6 +86,7 @@ CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run handle_ustate; run switch_bootset; run save_env; run bootcmd" CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index fb0787d1beb..269fe271a76 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -72,6 +72,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run recoveryboot" CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config index 2164c754915..37e11e518a8 100644 --- a/configs/imx8m_data_modul.config +++ b/configs/imx8m_data_modul.config @@ -13,6 +13,7 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_ARM=y CONFIG_BOARD_LATE_INIT=y CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_BOOTCOUNT_LIMIT=y CONFIG_CLK_COMPOSITE_CCF=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index ae9595e82b4..ad310750c77 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -102,6 +102,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SPL_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="mmc partconf 0 mmcpart ; if test ${mmcpart} -eq 1 ; then mmc partconf 0 1 2 0 ; else mmc partconf 0 1 1 0 ; fi ; boot" CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y diff --git a/configs/imx8mp_dhsom.config b/configs/imx8mp_dhsom.config index 416143178c8..7adbb9a84de 100644 --- a/configs/imx8mp_dhsom.config +++ b/configs/imx8mp_dhsom.config @@ -70,6 +70,7 @@ CONFIG_NXP_FSPI=y CONFIG_SF_DEFAULT_SPEED=50000000 # CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd ; reset" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index b488ff1b7da..918713a1c7d 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -13,7 +13,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000 CONFIG_ENV_OFFSET=0x80000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imxrt1050-evk" CONFIG_TARGET_IMXRT1050_EVK=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -48,6 +48,7 @@ CONFIG_CMD_USB=y # CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig index 5d58e723a70..86acd158391 100644 --- a/configs/imxrt1050-evk_fspi_defconfig +++ b/configs/imxrt1050-evk_fspi_defconfig @@ -15,7 +15,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000 CONFIG_ENV_OFFSET=0x80000 CONFIG_IMX_CONFIG="board/freescale/imxrt1050-evk/imximage-nor.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imxrt1050-evk" CONFIG_TARGET_IMXRT1050_EVK=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -50,6 +50,7 @@ CONFIG_CMD_USB=y # CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 2d5f18e5bd4..72d4b8e3695 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -70,7 +70,6 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y # CONFIG_CMD_SETEXPR is not set @@ -131,7 +130,6 @@ CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_SCI_POWER_DOMAIN=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index e1ef6e86d49..4760f7509f5 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -67,7 +67,6 @@ CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus" @@ -144,6 +143,7 @@ CONFIG_SPI_FLASH_S28HX_T=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y CONFIG_MULTIPLEXER=y +CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83869=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y @@ -166,7 +166,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_SCSI=y CONFIG_DM_SERIAL=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 265ae2e8e07..ae5849baf13 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -57,7 +57,6 @@ CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -68,7 +67,6 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -138,7 +136,6 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_TPS65941=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index a5d95975fb4..fad01c27104 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -67,7 +67,6 @@ CONFIG_CMD_GPIO_READ=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y @@ -144,8 +143,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_REMOTEPROC_TI_K3_DSP=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig index 77e44963fd4..086ad99ff6d 100644 --- a/configs/j721e_beagleboneai64_r5_defconfig +++ b/configs/j721e_beagleboneai64_r5_defconfig @@ -52,13 +52,11 @@ CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -111,7 +109,6 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_TPS65941=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 3928430f166..71e6c2061b3 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -68,7 +68,6 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -151,7 +150,7 @@ CONFIG_SPI_FLASH_MT35XU=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y CONFIG_MULTIPLEXER=y -CONFIG_SPL_MUX_MMIO=y +CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83867=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y @@ -171,8 +170,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_REMOTEPROC_TI_K3_DSP=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 42000cc5dc5..c8324d4c068 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41cf59f0 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0xf59f0 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y @@ -62,7 +61,6 @@ CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -73,7 +71,6 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -149,7 +146,6 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_TPS65941=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index ab943ebfab2..5e84abf8f21 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -64,7 +64,6 @@ CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTD=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_UFS=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus" @@ -161,8 +160,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_REMOTEPROC_TI_K3_DSP=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_SCSI=y CONFIG_DM_SERIAL=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 23ae991e2f6..6ea1d712be1 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -26,7 +26,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x41c76000 CONFIG_SPL_BSS_MAX_SIZE=0xa000 CONFIG_SPL_STACK_R=y -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SPL_SIZE_LIMIT=0x80000 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 CONFIG_SPL_FS_FAT=y @@ -63,7 +62,6 @@ CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -75,7 +73,6 @@ CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -149,7 +146,6 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_TPS65941=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig index 667d633c899..5d2bb52b440 100644 --- a/configs/j722s_evm_a53_defconfig +++ b/configs/j722s_evm_a53_defconfig @@ -55,7 +55,6 @@ CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_CLK=y CONFIG_CMD_MTD=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y @@ -131,9 +130,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y -CONFIG_REMOTEPROC_TI_K3_DSP=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y @@ -154,6 +150,8 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_DWC3_AM62=y CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_SPL_USB_GADGET=y diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig index a78a66d33a7..d96392db479 100644 --- a/configs/j722s_evm_r5_defconfig +++ b/configs/j722s_evm_r5_defconfig @@ -49,7 +49,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -61,7 +60,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -113,7 +111,6 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y @@ -127,4 +124,7 @@ CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_LIB_RATIONAL=y +CONFIG_ESM_K3=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_MISC=y CONFIG_SPL_LIB_RATIONAL=y diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index f058e3b1c00..1ba2bfed2cf 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -14,13 +15,13 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j784s4-evm" -CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_TEXT_BASE=0x80080000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80a00000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 @@ -29,6 +30,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_EFI_SET_TIME=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y @@ -38,10 +40,8 @@ CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_DMA=y -CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y @@ -49,7 +49,6 @@ CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y @@ -58,11 +57,9 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_BOOTEFI_SELFTEST=y -CONFIG_CMD_ASKENV=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MTD=y -CONFIG_CMD_REMOTEPROC=y -CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -73,6 +70,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y @@ -82,6 +80,8 @@ CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_CLK_CCF=y CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 @@ -140,8 +140,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_RAM=y CONFIG_SPL_RAM=y -CONFIG_REMOTEPROC_TI_K3_DSP=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y @@ -157,7 +155,20 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y CONFIG_DM_THERMAL=y -CONFIG_EFI_SET_TIME=y -CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6168 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y #include <configs/k3_efi_capsule.config> diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index b991ffb73be..5a5b0458b9b 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -55,7 +55,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -63,6 +62,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_THERMAL=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_TIME=y @@ -85,6 +85,7 @@ CONFIG_SPL_CLK=y CONFIG_SPL_CLK_CCF=y CONFIG_SPL_CLK_K3_PLL=y CONFIG_SPL_CLK_K3=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000 CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y @@ -128,7 +129,6 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR_TPS6287X=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y @@ -144,6 +144,19 @@ CONFIG_DM_THERMAL=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6168 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_PANIC_HANG=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 4e37df2e614..76e98c9b2a4 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -60,6 +60,7 @@ CONFIG_ENV_ADDR_REDUND=0xebf00000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="fm1-mac5" CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 6b2fc2ec6e7..cf50e2d27d8 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -166,6 +166,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 55e87b0215a..7638fc2f5cf 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -145,6 +145,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index df419b01c68..1c750455fc6 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -152,6 +152,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 1436860f1cc..5dd98175cd3 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -137,6 +137,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index cce7a044aee..2b240b3380d 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -151,6 +151,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index dd25fd60107..bc60bc57075 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -12,7 +12,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-kylin" CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_KYLIN_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 @@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-kylin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set diff --git a/configs/lxr2_defconfig b/configs/lxr2_defconfig index 7ab817960a2..0bc4ae0c7a5 100644 --- a/configs/lxr2_defconfig +++ b/configs/lxr2_defconfig @@ -13,7 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6Q=y CONFIG_TARGET_LXR2=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6q-lxr" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-lxr" CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -77,6 +77,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run swupdate" CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C4000 CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DM_I2C=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index 6130cd8e466..ccd1cb7475b 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -79,6 +79,7 @@ CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="m53menlo" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="if test ${mmcpart} -eq 1 ; then setenv mmcpart 2 ; else setenv mmcpart 1 ; fi ; boot" CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 2e618d81544..87756cb26df 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_GPIO=y CONFIG_CMD_SAVES=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 5ea6cc371aa..f8acaa98672 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig index 00e3cea5264..c6a88e7e9d3 100644 --- a/configs/mt7987_rfb_defconfig +++ b/configs/mt7987_rfb_defconfig @@ -12,7 +12,6 @@ CONFIG_SYS_LOAD_ADDR=0x48000000 CONFIG_DEBUG_UART_BASE=0x11000000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_DEBUG_UART=y -# CONFIG_EFI_LOADER is not set CONFIG_FIT=y # CONFIG_AUTOBOOT is not set CONFIG_DEFAULT_FDT_FILE="mt7987a-rfb" diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index d91c59ffe46..4ec8516015f 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -47,6 +47,7 @@ CONFIG_ARP_TIMEOUT=200 CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run doquiet; setenv partnum 1; run hasfirstboot || setenv partnum 2; run hasfirstboot || setenv partnum 0; if test ${partnum} != 0; then run swappartitions loadimage doboot; fi; run failbootcmd" CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_I2C_MUX=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index 1120191585c..4b82b077ea7 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -73,6 +73,7 @@ CONFIG_HOSTNAME="EXPU1" CONFIG_VERSION_VARIABLE=y # CONFIG_SCSI_AHCI is not set CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 772aa210fc2..53d54789687 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -71,6 +71,7 @@ CONFIG_HOSTNAME="EXPU1" CONFIG_VERSION_VARIABLE=y # CONFIG_SCSI_AHCI is not set CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 6cde217a34c..731ca435089 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -73,6 +73,7 @@ CONFIG_HOSTNAME="SELI8" CONFIG_VERSION_VARIABLE=y # CONFIG_SCSI_AHCI is not set CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index e8afc95d607..2598e477ed5 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -71,6 +71,7 @@ CONFIG_HOSTNAME="SELI8" CONFIG_VERSION_VARIABLE=y # CONFIG_SCSI_AHCI is not set CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 CONFIG_SYS_FSL_DDR3=y diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index 421dd851506..8c4fcc3b144 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -67,7 +67,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y @@ -143,8 +142,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_K3_SYSTEM_CONTROLLER=y CONFIG_REMOTEPROC_TI_K3_ARM64=y -CONFIG_REMOTEPROC_TI_K3_DSP=y -CONFIG_REMOTEPROC_TI_K3_R5F=y CONFIG_RESET_TI_SCI=y CONFIG_DM_RTC=y CONFIG_RTC_RV3028=y diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig index a71ebf0dc2c..25d2d9babba 100644 --- a/configs/phycore_am62ax_r5_defconfig +++ b/configs/phycore_am62ax_r5_defconfig @@ -49,7 +49,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_THERMAL=y @@ -59,7 +58,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -112,7 +110,6 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 0494fc408b7..d7aa59bf1dd 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -13,6 +13,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-phyboard-lyra-rdk" CONFIG_OF_LIBFDT_OVERLAY=y @@ -84,6 +85,7 @@ CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 25adca467b5..f157103be4a 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -55,7 +55,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -66,7 +65,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_CMD_FAT=y @@ -114,7 +112,6 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index f0c7ee26384..4ee1bd829a3 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -14,6 +14,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x680000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-phyboard-electra-rdk" @@ -91,6 +92,7 @@ CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index 6b0fd8d1402..2552479713f 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SOC_K3_AM642=y CONFIG_TARGET_PHYCORE_AM64X_R5=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7019b800 CONFIG_SF_DEFAULT_SPEED=25000000 @@ -15,6 +16,7 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-phycore-som-2gb" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y @@ -59,7 +61,6 @@ CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL" CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y # CONFIG_SPL_SPI_FLASH_TINY is not set CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y @@ -71,7 +72,6 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set @@ -138,7 +138,6 @@ CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y diff --git a/configs/picasso_defconfig b/configs/picasso_defconfig new file mode 100644 index 00000000000..994951bb81e --- /dev/null +++ b/configs/picasso_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x00110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="picasso" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra20-acer-a500-picasso" +CONFIG_SPL_STACK=0xffffc +CONFIG_SPL_TEXT_BASE=0x00108000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_TEGRA20=y +CONFIG_TARGET_PICASSO=y +CONFIG_TEGRA_ENABLE_UARTD=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; poweroff" +CONFIG_SYS_PBSIZE=2085 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra20 (Picasso) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x11000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Acer" +CONFIG_USB_GADGET_VENDOR_NUM=0x0502 +CONFIG_USB_GADGET_PRODUCT_NUM=0x3325 +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +# CONFIG_VIDEO_BPP8 is not set +CONFIG_VIDEO_TEGRA20=y diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index 74f4092d288..365f6434f83 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm750-evb" CONFIG_DM_RESET=y CONFIG_SYS_LOAD_ADDR=0x10000000 CONFIG_TARGET_POLEG=y +CONFIG_SYS_SKIP_UART_INIT=y CONFIG_ENV_ADDR=0x80100000 CONFIG_FIT=y CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 162b1f1c748..fd2727e48d7 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -85,6 +85,7 @@ CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_DM_I2C=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 763fc14468a..03028c76acc 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -74,5 +74,5 @@ CONFIG_USB_EHCI_PCI=y CONFIG_SEMIHOSTING=y CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y -CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y CONFIG_TPM_PCR_ALLOCATE=y +CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y diff --git a/configs/r8a779f0_spider_defconfig b/configs/r8a779f0_spider_defconfig index 7274038a202..6b16ff55480 100644 --- a/configs/r8a779f0_spider_defconfig +++ b/configs/r8a779f0_spider_defconfig @@ -1,32 +1,11 @@ -#include <configs/renesas_rcar4.config> +#include <configs/renesas_rcar4_s4.config> CONFIG_ARM=y CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN4=y -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0xD00000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779f0-spider" CONFIG_TARGET_SPIDER=y -CONFIG_SYS_CLK_FREQ=20000000 -CONFIG_SYS_BOOT_GET_CMDLINE=y -CONFIG_SYS_BARGSIZE=2048 +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779f0-spider" CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779f0-spider.dtb && booti 0x48080000 - 0x48000000" CONFIG_DEFAULT_FDT_FILE="r8a779f0-spider.dtb" -CONFIG_SYS_CBSIZE=2048 -CONFIG_CMD_PART=y -CONFIG_CMD_UFS=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_LBA48=y -CONFIG_SYS_64BIT_LBA=y -CONFIG_CLK_GPIO=y -CONFIG_DM_PCA953X=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_MARVELL_10G=y -CONFIG_RENESAS_ETHER_SWITCH=y -CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y -CONFIG_SCSI=y CONFIG_BAUDRATE=1843200 -CONFIG_UFS=y -CONFIG_UFS_RENESAS=y -CONFIG_FS_FAT_MAX_CLUSTSIZE=131072 +CONFIG_DM_PCA953X=y diff --git a/configs/r8a779f4_s4sk_defconfig b/configs/r8a779f4_s4sk_defconfig new file mode 100644 index 00000000000..1b353492d04 --- /dev/null +++ b/configs/r8a779f4_s4sk_defconfig @@ -0,0 +1,11 @@ +#include <configs/renesas_rcar4_s4.config> + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_RCAR_GEN4=y +CONFIG_TARGET_S4SK=y +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779f4-s4sk" +CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779f4-s4sk.dtb && booti 0x48080000 - 0x48000000" +CONFIG_DEFAULT_FDT_FILE="r8a779f4-s4sk.dtb" +CONFIG_BAUDRATE=921600 +CONFIG_BOARD_LATE_INIT=y diff --git a/configs/renesas_rcar4_s4.config b/configs/renesas_rcar4_s4.config new file mode 100644 index 00000000000..866e5759e63 --- /dev/null +++ b/configs/renesas_rcar4_s4.config @@ -0,0 +1,23 @@ +#include <configs/renesas_rcar4.config> + +CONFIG_CLK_GPIO=y +CONFIG_CMD_PART=y +CONFIG_CMD_UFS=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_OFFSET=0xD00000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_FS_FAT_MAX_CLUSTSIZE=131072 +CONFIG_LBA48=y +CONFIG_PHYLIB_10G=y +CONFIG_PHY_MARVELL_10G=y +CONFIG_PHY_R8A779F0_ETHERNET_SERDES=y +CONFIG_RENESAS_ETHER_SWITCH=y +CONFIG_SCSI=y +CONFIG_SYS_64BIT_LBA=y +CONFIG_SYS_BARGSIZE=2048 +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_CLK_FREQ=20000000 +CONFIG_UFS=y +CONFIG_UFS_RENESAS=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index dd8df542aa3..b2930e8044d 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -86,6 +86,7 @@ CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_DM_I2C=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index 46329395ba5..f0315f6ab33 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -252,6 +252,8 @@ CONFIG_FS_CBFS=y CONFIG_FS_CRAMFS=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_CMD_DHRYSTONE=y +CONFIG_VPL_SHA1_LEGACY=y +CONFIG_VPL_SHA256_LEGACY=y CONFIG_RSA_VERIFY_WITH_PKEY=y CONFIG_TPM=y CONFIG_ZSTD=y diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index 6dc95e551e3..ae6c9b60cd5 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -60,6 +60,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="echo Performing rollback...; if test \"${mmcpart_committed}\" = 1; then setenv mmcpart 2; setenv mmcpart_committed 2; else setenv mmcpart 1; setenv mmcpart_committed 1; fi; setenv bootcount 0; setenv upgrade_available; setenv ustate 3; saveenv; run bootcmd;" CONFIG_DFU_MMC=y CONFIG_DM_I2C=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 8577ac610c2..ca3ec23acfe 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -1,8 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_TEXT_BASE=0x80200000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000 CONFIG_SF_DEFAULT_MODE=0x2003 @@ -10,7 +9,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" CONFIG_DM_RESET=y -CONFIG_SPL_STACK=0x7f000 +CONFIG_SPL_STACK=0x7d000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xbff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 @@ -30,10 +29,15 @@ CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe" CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_CACHE=y CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_SPL_MTD=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 CONFIG_SPL_ATF=y @@ -82,9 +86,15 @@ CONFIG_DESIGNWARE_APB_TIMER=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_DWC2=y -# CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y CONFIG_SPL_CRC32=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_SIZE=0x1000 +CONFIG_BLOBLIST_ADDR=0x7e000 +CONFIG_HANDOFF=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_DWC_ETH_XGMAC=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index dc6d66ade23..84badec60aa 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -74,6 +74,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_DM_BOOTCOUNT_RTC=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd;" CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index c3f2142ae1b..1e0a99ed17b 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -75,7 +75,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y -CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" @@ -84,6 +84,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_LWIP=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 815f7557d69..1e5190dc828 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y @@ -48,11 +49,13 @@ CONFIG_MMC_SDHCI_STI=y CONFIG_PHY=y CONFIG_STI_USB_PHY=y CONFIG_PINCTRL=y +CONFIG_DM_REGULATOR=y CONFIG_STI_RESET=y CONFIG_STI_ASC_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y @@ -60,6 +63,8 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_DWC3_STI=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig index ff948b904be..4dc3954128d 100644 --- a/configs/stm32mp13_dhcor_defconfig +++ b/configs/stm32mp13_dhcor_defconfig @@ -44,3 +44,4 @@ CONFIG_OPTEE=y CONFIG_USB_ONBOARD_HUB=y CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000 CONFIG_ERRNO_STR=y +CONFIG_BOOTCOUNT_ALTBOOTCMD=" diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index a28f2862048..f89c921925d 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -8,3 +8,4 @@ CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_SYS_I2C_EEPROM_BUS=3 CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx" CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_BOOTCOUNT_ALTBOOTCMD=" diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index f6f2af6e7a2..bde668761b3 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -8,3 +8,4 @@ CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_BOOTCOUNT_ALTBOOTCMD=" diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index e7e15c64ba2..27ff3915050 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -36,10 +36,10 @@ CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000 CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index cecd26175d1..e64bb768440 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -9,10 +9,11 @@ CONFIG_EFI_LOADER=n CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_TIMESTAMP=y CONFIG_FIT=y -CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTD_FULL=n CONFIG_BOOTMETH_CROS=n CONFIG_BOOTMETH_VBE=n +CONFIG_IMAGE_PRE_LOAD=y +CONFIG_IMAGE_PRE_LOAD_SIG=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_CMD_BOOTD=n diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index d1b771993cf..ab0fd12bc48 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -137,6 +137,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 1dc737e4954..e5a99b24dab 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -151,6 +151,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_BOOTCOUNT_MEM=y +CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xF0001001 CONFIG_SYS_OR0_PRELIM=0xF0000E55 diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index e7a88c9788d..ecd3284faaf 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -76,7 +76,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_READ=y -CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BOOTCOUNT=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index d4f904ac07d..9ac4b534f6c 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -48,14 +48,12 @@ CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y -CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_OF_CONTROL=y @@ -97,7 +95,6 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_TI_POWER_DOMAIN=y CONFIG_K3_SYSTEM_CONTROLLER=y -CONFIG_REMOTEPROC_TI_K3_ARM64=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y diff --git a/configs/vexpress_fvp_bloblist_defconfig b/configs/vexpress_fvp_bloblist_defconfig new file mode 100644 index 00000000000..4d52b96202b --- /dev/null +++ b/configs/vexpress_fvp_bloblist_defconfig @@ -0,0 +1,5 @@ +#include <configs/vexpress_fvp_defconfig> + +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_PASSAGE_MANDATORY=y +CONFIG_BLOBLIST_SIZE_RELOC=0x10000 diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 9af3817c82f..e1cdc186fb4 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MALLOC_F_LEN=0x500 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFFFE00 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x80 # CONFIG_DM_GPIO is not set diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 30d79ab8c8c..5ef5fd44fd3 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y @@ -44,10 +46,7 @@ CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y @@ -69,9 +68,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y @@ -102,6 +99,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y @@ -152,4 +150,5 @@ CONFIG_USB_FUNCTION_THOR=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index fb757c1067d..f228eef7c95 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y @@ -50,10 +52,7 @@ CONFIG_MMC_SPEED_MODE_SET=y CONFIG_CMD_MTD=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y @@ -73,9 +72,7 @@ CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y @@ -112,6 +109,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y CONFIG_SPI_FLASH_SST=y @@ -167,4 +165,6 @@ CONFIG_USB_FUNCTION_THOR=y CONFIG_VIRTIO_MMIO=y CONFIG_VIRTIO_NET=y CONFIG_VIRTIO_BLK=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index ed3d1019485..9196a95e88a 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -56,13 +56,15 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -71,9 +73,6 @@ CONFIG_CMD_MTD=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_USB=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y @@ -92,8 +91,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SIMPLE_PM_BUS=y @@ -158,4 +156,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SYS_TIMER_COUNTS_DOWN=y +CONFIG_MBEDTLS_LIB=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index a68bd522f90..1a6bd67afb8 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -63,13 +63,15 @@ CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_PWM=y @@ -82,11 +84,7 @@ CONFIG_CMD_SDRAM=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y @@ -118,8 +116,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SIMPLE_PM_BUS=y @@ -129,7 +126,6 @@ CONFIG_SATA_CEVA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y CONFIG_DFU_MTD=y @@ -138,10 +134,6 @@ CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 CONFIG_DMA=y CONFIG_XILINX_DPDMA=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y @@ -229,5 +221,6 @@ CONFIG_VIRTIO_BLK=y # CONFIG_BINMAN_FDT is not set CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman-som.dtb" CONFIG_PANIC_HANG=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index b13079cdf70..e5e56babf4c 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -59,17 +59,17 @@ CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_SMBIOS=y CONFIG_CMD_BOOTMENU=y -CONFIG_CMD_THOR_DOWNLOAD=y -CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_PWM=y @@ -84,11 +84,7 @@ CONFIG_CMD_SDRAM=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_BOOTP_MAY_FAIL=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_NFS=y +CONFIG_WGET_HTTPS=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y @@ -119,8 +115,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SIMPLE_PM_BUS=y @@ -130,7 +125,6 @@ CONFIG_SATA_CEVA=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK_ZYNQMP=y -CONFIG_DFU_TFTP=y CONFIG_DFU_TIMEOUT=y CONFIG_DFU_MMC=y CONFIG_DFU_MTD=y @@ -138,10 +132,6 @@ CONFIG_DFU_NAND=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000 -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_ZYNQMPPL=y @@ -245,5 +235,7 @@ CONFIG_VIRTIO_BLK=y # CONFIG_BINMAN_FDT is not set CONFIG_BINMAN_DTB="./arch/arm/dts/zynqmp-binman.dtb" CONFIG_PANIC_HANG=y +CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y CONFIG_SPL_GZIP=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/doc/board/acer/index.rst b/doc/board/acer/index.rst new file mode 100644 index 00000000000..3741a700ccd --- /dev/null +++ b/doc/board/acer/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ACER +==== + +.. toctree:: + :maxdepth: 2 + + picasso diff --git a/doc/board/acer/picasso.rst b/doc/board/acer/picasso.rst new file mode 100644 index 00000000000..b1d360defd8 --- /dev/null +++ b/doc/board/acer/picasso.rst @@ -0,0 +1,125 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Acer Iconia Tab A500 +=================================== + +``DISCLAMER!`` Moving your Acer Iconia Tab A500 to use U-Boot assumes +replacement of the vendor Acer bootloader. Vendor Android firmwares will no +longer be able to run on the device. This replacement IS reversible. + +Quick Start +----------- + +- Build U-Boot +- Process U-Boot +- Flashing U-Boot into the eMMC +- Boot +- Self Upgrading + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make picasso_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for further processing. + +Process U-Boot +-------------- + +``DISCLAMER!`` All questions related to the re-crypt work should be asked +in re-crypt repo issues. NOT HERE! + +re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form +usable by device. This process is required only on the first installation or +to recover the device in case of a failed update. + +Permanent installation can be performed either by using the nv3p protocol or by +pre-loading just built U-Boot into RAM. + +Processing for the NV3P protocol +******************************** + +.. code-block:: bash + + $ git clone https://gitlab.com/grate-driver/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-tegra.bin here + $ ./re-crypt.py --dev a500 + +The script will produce a ``repart-block.bin`` ready to flash. + +Processing for pre-loaded U-Boot +******************************** + +The procedure is the same, but the ``--split`` argument is used with the +``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready +to flash. + +Flashing U-Boot into the eMMC +----------------------------- + +``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! + +Permanent installation can be performed either by using the nv3p protocol or by +pre-loading just built U-Boot into RAM. + +Flashing with the NV3P protocol +******************************* + +Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can +enter it either by pre-loading vendor bootloader into RAM with the nvflash. + +With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in +encrypted state in form, which can just be written RAW at the start of eMMC. + +.. code-block:: bash + + $ nvflash --setbct --bct picasso.bct --configfile flash.cfg --bl bootloader.bin + --sbk 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX --sync # replace with your SBK + $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + +When flashing is done, reboot the device. + +Flashing with a pre-loaded U-Boot +********************************* + +U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently +U-Boot supports bootmenu entry fastboot, which allows to write a processed copy +of U-Boot permanently into eMMC. + +While pre-loading U-Boot, hold the ``volume down`` button which will trigger +the bootmenu. There, select ``fastboot`` using the volume and power buttons. +After, on host PC, do: + +.. code-block:: bash + + $ fastboot flash 0.1 bct.img + $ fastboot flash 0.2 ebt.img + $ fastboot reboot + +Device will reboot. + +Boot +---- + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on +eMMC. Additionally, if the Volume Down button is pressed while booting, the +device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC +as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console +and update bootloader (check the next chapter). + +Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows +the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card +and insert it into the tablet. Enter bootmenu, choose update the bootloader +option with the Power button and U-Boot should update itself. Once the process +is completed, U-Boot will ask to press any button to reboot. diff --git a/doc/board/armltd/vexpress64.rst b/doc/board/armltd/vexpress64.rst index a7f771d2667..a732fac899d 100644 --- a/doc/board/armltd/vexpress64.rst +++ b/doc/board/armltd/vexpress64.rst @@ -43,6 +43,22 @@ Juno is an Arm development board with the following features: More details can be found in the board documentation [3]_. +Bloblist Support +---------------- + +The ``vexpress_fvp_bloblist_defconfig`` configures U-Boot to be compiled for +Vexpress64 with Bloblist as the primary method for information handoff between +boot stages. U-Boot offers three methods to set up a bloblist: using a +predefined bloblist at a specified address, dynamically allocating memory for a +bloblist, or utilizing a standard passage-provided bloblist with automatic size +detection. + +By default, ``vexpress_fvp_bloblist_defconfig`` uses the standard passage method mandatorily +(CONFIG_BLOBLIST_PASSAGE_MANDATORY) because TF-A provides a Transfer List in non-secure +memory that U-Boot can utilise. This Bloblist, which is referred to as a Transfer List in +TF-A, contains all necessary data for the handoff process, including DT and ACPI +tables. + References ---------- diff --git a/doc/board/asus/grouper.rst b/doc/board/asus/grouper.rst index d56a9ca3921..14469582907 100644 --- a/doc/board/asus/grouper.rst +++ b/doc/board/asus/grouper.rst @@ -25,7 +25,7 @@ along with cellular one. .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make grouper_defconfig # For all grouper versions and tilapia $ make @@ -79,18 +79,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/grouper.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that if you have cellular version, +use ``tilapia.bct``. Flashing with a pre-loaded U-Boot ********************************* diff --git a/doc/board/asus/transformer_t20.rst b/doc/board/asus/transformer_t20.rst index d4bc12d1619..4f4f893c3a8 100644 --- a/doc/board/asus/transformer_t20.rst +++ b/doc/board/asus/transformer_t20.rst @@ -25,7 +25,7 @@ defconfig. Valid fragments are ``tf101.config``, ``tf101g.config`` and .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make transformer_t20_defconfig tf101.config # For TF101 $ make @@ -84,8 +84,8 @@ encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ wheelie -1 --bl bootloader.bin --bct tf101.bct --odm 0x300d8011 || break + $ nvflash --resume --rawdevicewrite 0 2048 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst index bebc4b9fad3..012a38251aa 100644 --- a/doc/board/asus/transformer_t30.rst +++ b/doc/board/asus/transformer_t30.rst @@ -22,6 +22,7 @@ Build U-Boot U-Boot features ability to detect transformer device model on which it is loaded. The list of supported devices include: + - ASUS Transformer Prime TF201 - ASUS Transformer Pad (3G/LTE) TF300T/TG/TL - ASUS Transformer Infinity TF700T @@ -30,7 +31,7 @@ loaded. The list of supported devices include: .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make transformer_t30_defconfig $ make @@ -84,18 +85,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/tf201.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that you should adjust bct file +name according to your device. Flashing with a pre-loaded U-Boot ********************************* diff --git a/doc/board/htc/endeavoru.rst b/doc/board/htc/endeavoru.rst index e0edefe28ae..53df2d09a6f 100644 --- a/doc/board/htc/endeavoru.rst +++ b/doc/board/htc/endeavoru.rst @@ -21,7 +21,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make endeavoru_defconfig $ make @@ -72,16 +72,15 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/endeavoru.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/board/index.rst b/doc/board/index.rst index 74c4dd1f42d..b055046e649 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -6,6 +6,7 @@ Board-specific doc .. toctree:: :maxdepth: 2 + acer/index actions/index advantech/index andestech/index diff --git a/doc/board/lg/x3_t30.rst b/doc/board/lg/x3_t30.rst index 618b00d34e3..9ff75034b72 100644 --- a/doc/board/lg/x3_t30.rst +++ b/doc/board/lg/x3_t30.rst @@ -24,7 +24,7 @@ board defconfig. Valid fragments are ``p880.config`` and ``p895.config``. .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make x3_t30_defconfig p895.config # For LG Optimus Vu $ make @@ -75,18 +75,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/p895.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that if you have Optimus 4x HD, +use ``p880.bct``. Flashing with a pre-loaded U-Boot ********************************* @@ -122,7 +122,7 @@ the user to use/partition it in any way the user desires. Self Upgrading -------------- -Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC (using -ability of u-boot to mount it). Enter bootmenu, choose update bootloader option -with Power button and U-Boot should update itself. Once the process is -completed, U-Boot will ask to press any button to reboot. +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC or MicroSD +card if it is supported (using ability of u-boot to mount it). Enter bootmenu, +choose update bootloader option with Power button and U-Boot should update itself. +Once the process is completed, U-Boot will ask to press any button to reboot. diff --git a/doc/board/microsoft/surface-rt.rst b/doc/board/microsoft/surface-rt.rst index b5645e79340..2b29cce40a9 100644 --- a/doc/board/microsoft/surface-rt.rst +++ b/doc/board/microsoft/surface-rt.rst @@ -14,7 +14,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make surface-rt_defconfig $ make @@ -38,4 +38,4 @@ directory with To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on eMMC. Additionally, if the Volume Down button is pressed while loading, the device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC -as mass storage, fastboot, reboot, reboot RCM, poweroffand enter U-Boot console. +as mass storage, fastboot, reboot, reboot RCM, poweroff and enter U-Boot console. diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst index 7d961e862e4..0a38ff42eae 100644 --- a/doc/board/renesas/renesas.rst +++ b/doc/board/renesas/renesas.rst @@ -169,6 +169,12 @@ Renesas is a SoC solutions provider for automotive and industrial applications. - r8a779f0_spider_defconfig * - + - S4SK + - R8A779F4 (S4) + - arm64 + - r8a779f4_s4sk_defconfig + + * - - White Hawk - R8A779G0 (V4H) - arm64 diff --git a/doc/board/wexler/qc750.rst b/doc/board/wexler/qc750.rst index b61e40176b0..169629c7e47 100644 --- a/doc/board/wexler/qc750.rst +++ b/doc/board/wexler/qc750.rst @@ -21,7 +21,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make qc750_defconfig $ make @@ -71,16 +71,15 @@ pre-loading just built U-Boot into RAM. Flashing with the NV3P protocol ******************************* -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +Nv3p is a custom Nvidia protocol used to recover bricked devices. Tegrarcm is +used to handle such state. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --bct qc750.bct --bl bootloader.bin + $ tegrarcm --bct qc750.bct --bootloader android_bootloader.bin --loadaddr 0x80108000 $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 9ecd6b6ab87..b6ad7218614 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -55,7 +55,7 @@ Current Status * The Merge Window for the next release (v2025.04) is **closed**. -* The next branch is now **closed** until the -rc2 release on Mon 10 February +* The next branch is now **open** with the -rc2 release on Mon 10 February 2025. * Release "v2025.04" is scheduled for 07 April 2025. @@ -70,9 +70,9 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.04-rc1 was released on Mon 27 January 2025. -.. * U-Boot v2025.04-rc2 was released on Mon 10 February 2025. +* U-Boot v2025.04-rc2 was released on Mon 10 February 2025. -.. * U-Boot v2025.04-rc3 was released on Mon 24 February 2025. +* U-Boot v2025.04-rc3 was released on Mon 24 February 2025. .. * U-Boot v2025.04-rc4 was released on Mon 10 March 2025. diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst index 54efb7e1b04..5f3c43d5da2 100644 --- a/doc/develop/tests_writing.rst +++ b/doc/develop/tests_writing.rst @@ -261,7 +261,7 @@ with the suite. For example, to add a new mem_search test:: /* Test 'ms' command with 32-bit values */ static int mem_test_ms_new_thing(struct unit_test_state *uts) { - /* test code here*/ + /* test code here */ return 0; } @@ -291,32 +291,20 @@ suite. For example:: /* Declare a new wibble test */ #define WIBBLE_TEST(_name, _flags) UNIT_TEST(_name, _flags, wibble_test) - /* Tetss go here */ - - /* At the bottom of the file: */ - - int do_ut_wibble(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) - { - struct unit_test *tests = UNIT_TEST_SUITE_START(wibble_test); - const int n_ents = UNIT_TEST_SUITE_COUNT(wibble_test); - - return cmd_ut_category("cmd_wibble", "wibble_test_", tests, n_ents, argc, argv); - } + /* Tests go here */ Then add new tests to it as above. Register this new suite in test/cmd_ut.c by adding to cmd_ut_sub[]:: - /* Within cmd_ut_sub[]... */ - - U_BOOT_CMD_MKENT(wibble, CONFIG_SYS_MAXARGS, 1, do_ut_wibble, "", ""), + /* with the other SUITE_DECL() declarations */ + SUITE_DECL(wibble); -and adding new help to ut_help_text[]:: + /* Within suites[]... */ + SUITE(wibble, "my test of wibbles"); - "ut wibble - Test the wibble feature\n" - -If your feature is conditional on a particular Kconfig, then you can use #ifdef -to control that. +If your feature is conditional on a particular Kconfig, you do not need to add +an #ifdef since the suite will automatically be compiled out in that case. Finally, add the test to the build by adding to the Makefile in the same directory:: @@ -326,17 +314,35 @@ directory:: Note that CMDLINE is never enabled in SPL, so this test will only be present in U-Boot proper. See below for how to do SPL tests. -As before, you can add an extra Kconfig check if needed:: +You can add an extra Kconfig check if needed:: ifneq ($(CONFIG_$(XPL_)WIBBLE),) obj-$(CONFIG_$(XPL_)CMDLINE) += wibble.o endif +Each suite can have an optional init and uninit function. These are run before +and after any suite tests, respectively:: + + #define WIBBLE_TEST_INIT(_name, _flags) UNIT_TEST_INIT(_name, _flags, wibble_test) + #define WIBBLE_TEST_UNINIT(_name, _flags) UNIT_TEST_UNINIT(_name, _flags, wibble_test) -Example commit: 919e7a8fb64 ("test: Add a simple test for bloblist") [1] + static int wibble_test_init(struct unit_test_state *uts) + { + /* init code here */ + + return 0; + } + WIBBLE_TEST_INIT(wibble_test_init, 0); -[1] https://gitlab.denx.de/u-boot/u-boot/-/commit/919e7a8fb64 + static int wibble_test_uninit(struct unit_test_state *uts) + { + /* uninit code here */ + + return 0; + } + WIBBLE_TEST_INIT(wibble_test_uninit, 0); +Both functions are included in the totals for each suite. Making the test run from pytest ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/doc/device-tree-bindings/leds/common.txt b/doc/device-tree-bindings/leds/common.txt deleted file mode 100644 index 2d88816dd55..00000000000 --- a/doc/device-tree-bindings/leds/common.txt +++ /dev/null @@ -1,23 +0,0 @@ -Common leds properties. - -Optional properties for child nodes: -- label : The label for this LED. If omitted, the label is - taken from the node name (excluding the unit address). - -- linux,default-trigger : This parameter, if present, is a - string defining the trigger assigned to the LED. Current triggers are: - "backlight" - LED will act as a back-light, controlled by the framebuffer - system - "default-on" - LED will turn on (but for leds-gpio see "default-state" - property in Documentation/devicetree/bindings/gpio/led.txt) - "heartbeat" - LED "double" flashes at a load average based rate - "ide-disk" - LED indicates disk activity - "timer" - LED flashes at a fixed, configurable rate - -Examples: - -system-status { - label = "Status"; - linux,default-trigger = "heartbeat"; - ... -}; diff --git a/doc/usage/cmd/ut.rst b/doc/usage/cmd/ut.rst index e794922c806..1acf3126680 100644 --- a/doc/usage/cmd/ut.rst +++ b/doc/usage/cmd/ut.rst @@ -11,34 +11,44 @@ Synopsis :: - ut [-r<runs>] [-fs] [-I<n>:<one_test>] [<suite> [<test>]] - - <runs> Number of times to run each test - -f Force 'manual' tests to run as well - <n> Run <one test> after <n> other tests have run - <one_test> Name of the 'one' test to run - <suite> Test suite to run, or `all` - <test> Name of single test to run + ut [-r<runs>] [-f] [-I<n>:<one_test>] [-r<n>] [<suite> | 'all' [<test>]] + ut [-s] info Description ----------- The ut command runs unit tests written in C. +suite + Specifies the suite to run, This can be a single suite, or a comma-separated + list + +test + Speciifes a particular test to run, within a suite, or all suites + +-f + Forces running of a manual test. + +-r <n> + Specifies the number of types to run each test + +-I <n>:<one_test> + Test to run after <n> other tests have run. This is used to find which test + causes another test to fail. If the one test fails, testing stops + immediately. + Typically the command is run on :ref:`arch/sandbox/sandbox:sandbox` since it includes a near-complete set of emulators, no code-size limits, many CONFIG options enabled and runs easily in CI without needing QEMU. It is also possible to run some tests on real boards. -For a list of available test suites, type `ut info -s`. - Each test is normally run once, although those marked with `UTF_DM` are run with livetree and flattree where possible. To run a test more than once, use the `-r` flag. Manual tests are normally skipped by this command. Use `-f` to run them. See -See :ref:`develop/tests_writing:mixing python and c` for more information on -manual test. +:ref:`develop/tests_writing:mixing python and c` for more information on manual +tests. When running unit tests, some may have side effects which cause a subsequent test to break. This can sometimes be seen when using 'ut dm' or similar. To @@ -50,9 +60,22 @@ the problem. Generally all tests in the suite are run. To run just a single test from the suite, provide the <test> argument. +To specify a list of suites to run, <suites> can also be a comma-separated list. + See :ref:`develop/tests_writing:writing c tests` for more information on how to write unit tests. +ut all +~~~~~~ + +Instead of a suite name 'all' may be used to run all tests. + +ut info +~~~~~~~ + +This provides information about the total number of suites and tests. Use the +`-s` flag to show a detailed list of suites. + Example ------- @@ -97,26 +120,84 @@ List available unit-test suites:: Run one of the suites:: - => ut bloblist - Running 14 bloblist tests - Test: bloblist_test_align: bloblist.c - Test: bloblist_test_bad_blob: bloblist.c - Test: bloblist_test_blob: bloblist.c - Test: bloblist_test_blob_ensure: bloblist.c - Test: bloblist_test_blob_maxsize: bloblist.c - Test: bloblist_test_checksum: bloblist.c - Test: bloblist_test_cmd_info: bloblist.c - Test: bloblist_test_cmd_list: bloblist.c - Test: bloblist_test_grow: bloblist.c - Test: bloblist_test_init: bloblist.c - Test: bloblist_test_reloc: bloblist.c - Test: bloblist_test_resize_fail: bloblist.c - Test: bloblist_test_resize_last: bloblist.c - Test: bloblist_test_shrink: bloblist.c - Failures: 0 + => ut common + Running 14 common tests + Test: cli_ch_test: cread.c + Test: cread_test: cread.c + Test: dm_test_cyclic_running: cyclic.c + Test: print_display_buffer: print.c + Test: print_do_hex_dump: print.c + Test: print_efi_ut: print.c + Test: print_guid: print.c + Test: print_hexdump_line: print.c + Test: print_printf: print.c + Test: snprint: print.c + Test: test_autoboot: test_autoboot.c + Enter password "a" in 1 seconds to stop autoboot + Enter password "a" in 1 seconds to stop autoboot + Enter password "a" in 1 seconds to stop autoboot + Enter password "a" in 1 seconds to stop autoboot + Enter password "a" in 1 seconds to stop autoboot + Enter password "a" in 1 seconds to stop autoboot + Autoboot password unlock not successful + Test: test_event_base: event.c + Test: test_event_probe: event.c + Test: test_event_probe: event.c (flat tree) + Test: test_event_simple: event.c + Tests run: 14, 2611 ms, average 186 ms, skipped: 2, failures: 0 Run just a single test in a suite:: - => ut bloblist bloblist_test_grow - Test: bloblist_test_grow: bloblist.c - Failures: 0 + => ut fdt_overlay change_int_property + Test: fdt_overlay_init: cmd_ut_fdt_overlay.c + Test: change_int_property: cmd_ut_fdt_overlay.c + Tests run: 2, 0 ms, average 0 ms, failures: 0 + +Run a selection of three suites:: + + => ut bloblist,mem,fdt_overlay + Running 14 bloblist tests + Test: align: bloblist.c + Test: bad_blob: bloblist.c + Test: blob: bloblist.c + Test: blob_ensure: bloblist.c + Test: blob_maxsize: bloblist.c + Test: checksum: bloblist.c + Test: cmd_info: bloblist.c + Test: cmd_list: bloblist.c + Test: grow: bloblist.c + Test: init: bloblist.c + Test: reloc: bloblist.c + Test: resize_fail: bloblist.c + Test: resize_last: bloblist.c + Test: shrink: bloblist.c + Tests run: 14, 1 ms, average: 0 ms, failures: 0 + Running 13 mem tests + Test: cp_b: mem_copy.c + Test: cp_l: mem_copy.c + Test: cp_q: mem_copy.c + Test: cp_w: mem_copy.c + Test: ms_b: mem_search.c + Test: ms_cont: mem_search.c + Test: ms_cont_end: mem_search.c + Test: ms_l: mem_search.c + Test: ms_limit: mem_search.c + Test: ms_mult: mem_search.c + Test: ms_quiet: mem_search.c + Test: ms_s: mem_search.c + Test: ms_w: mem_search.c + Tests run: 13, 13 ms, average: 1 ms, failures: 0 + Running 10 fdt_overlay tests + Test: fdt_overlay_init: cmd_ut_fdt_overlay.c + Test: add_node_by_path: cmd_ut_fdt_overlay.c + Test: add_node_by_phandle: cmd_ut_fdt_overlay.c + Test: add_str_property: cmd_ut_fdt_overlay.c + Test: add_subnode_property: cmd_ut_fdt_overlay.c + Test: change_int_property: cmd_ut_fdt_overlay.c + Test: change_str_property: cmd_ut_fdt_overlay.c + Test: local_phandle: cmd_ut_fdt_overlay.c + Test: local_phandles: cmd_ut_fdt_overlay.c + Test: stacked: cmd_ut_fdt_overlay.c + Tests run: 10, 12 ms, average: 1 ms, failures: 0 + Suites run: 3, total tests run: 37, 26 ms, average: 0 ms, failures: 0 + Average test time: 0 ms, worst case 'mem' took 1 ms diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 0080d2a165c..99b6c7534fd 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -183,6 +183,9 @@ config BOOTCOUNT_BOOTLIMIT counter being cleared. If set to 0, do not set a boot limit in the environment. +config BOOTCOUNT_ALTBOOTCMD + string "Alternative boot command when BOOTLIMIT is reached" + config SYS_BOOTCOUNT_SINGLEWORD bool "Use single word to pack boot count and magic value" depends on BOOTCOUNT_GENERIC diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index 716c71598bc..fb1e72ffc5c 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -1,13 +1,13 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ -#include <clk-uclass.h> #include <config.h> -#include <errno.h> -#include <dm.h> #include <log.h> +#include <dm.h> +#include <errno.h> #include <stdarg.h> #include <stdio.h> #include <time.h> @@ -23,9 +23,14 @@ #include <linux/types.h> #include <asm/arch/clock_manager.h> #include <dt-bindings/clock/agilex5-clock.h> +#include <wait_bit.h> +#include <clk-uclass.h> DECLARE_GLOBAL_DATA_PTR; +#define CLKMGR_CTRL_SWCTRLBTCLKEN_MASK BIT(8) +#define CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK BIT(9) + struct socfpga_clk_plat { void __iomem *regs; }; @@ -36,21 +41,30 @@ struct socfpga_clk_plat { */ static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val) { + uintptr_t base_addr = (uintptr_t)plat->regs; + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS); - cm_wait_for_fsm(); + wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), CLKMGR_STAT_BUSY, + false, 20000, false); } static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val) { + uintptr_t base_addr = (uintptr_t)plat->regs; + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS); - cm_wait_for_fsm(); + wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), CLKMGR_STAT_BUSY, + false, 20000, false); } /* function to write the ctrl register which requires a poll of the busy bit */ static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val) { + uintptr_t base_addr = (uintptr_t)plat->regs; + CM_REG_WRITEL(plat, val, CLKMGR_CTRL); - cm_wait_for_fsm(); + wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), CLKMGR_STAT_BUSY, + false, 20000, false); } static const struct { @@ -59,15 +73,6 @@ static const struct { u32 mask; } membus_pll[] = { { - MEMBUS_CLKSLICE_REG, - /* - * BIT[7:7] - * Enable source synchronous mode - */ - BIT(7), - BIT(7) - }, - { MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG, /* * BIT[0:0] @@ -238,6 +243,7 @@ static void clk_basic_init(struct udevice *dev, { struct socfpga_clk_plat *plat = dev_get_plat(dev); u32 vcocalib; + uintptr_t base_addr = (uintptr_t)plat->regs; if (!cfg) return; @@ -249,7 +255,8 @@ static void clk_basic_init(struct udevice *dev, CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB, CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); - cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), + CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false); /* Put both PLLs in bypass */ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL); @@ -264,9 +271,14 @@ static void clk_basic_init(struct udevice *dev, CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); } else { #ifdef CONFIG_XPL_BUILD - /* Always force clock manager into boot mode before any configuration */ - clk_write_ctrl(plat, - CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); + /* + * Configure HPS Internal Oscillator as default boot_clk source, + * always force clock manager into boot mode before any configuration + */ + clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) | + CLKMGR_CTRL_BOOTMODE | + CLKMGR_CTRL_SWCTRLBTCLKEN_MASK | + CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK); #else /* Skip clock configuration in SSBL if it's not in boot mode */ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE)) @@ -365,7 +377,8 @@ static void clk_basic_init(struct udevice *dev, CLKMGR_PLLCX_EN_SET_MSK, CLKMGR_PERPLL_PLLC3); - cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), + CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false); CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK); CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK); diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e412c92cafc..12893687b68 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,7 +3,6 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o # SoC Drivers -obj-$(CONFIG_MT8512) += clk-mt8512.o obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o @@ -13,5 +12,6 @@ obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o +obj-$(CONFIG_TARGET_MT8512) += clk-mt8512.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index c1d6a6b6c59..b19f3601813 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> -# Copyright (C) 2014-2021 Altera Corporation <www.altera.com> +# Copyright (C) 2014-2025 Altera Corporation <www.altera.com> ifdef CONFIG_$(XPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o @@ -12,4 +12,5 @@ obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o endif diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c new file mode 100644 index 00000000000..db9435db657 --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.c @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + * + */ + +#include <hang.h> +#include <string.h> +#include <wait_bit.h> +#include <asm/arch/base_addr_soc64.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include "iossm_mailbox.h" + +#define TIMEOUT_120000MS 120000 +#define TIMEOUT_60000MS 60000 +#define TIMEOUT TIMEOUT_120000MS +#define IOSSM_STATUS_CAL_SUCCESS BIT(0) +#define IOSSM_STATUS_CAL_FAIL BIT(1) +#define IOSSM_STATUS_CAL_BUSY BIT(2) +#define IOSSM_STATUS_COMMAND_RESPONSE_READY BIT(0) +#define IOSSM_CMD_RESPONSE_STATUS_OFFSET 0x45C +#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x458 +#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x454 +#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x450 +#define IOSSM_CMD_REQ_OFFSET 0x43C +#define IOSSM_CMD_PARAM_0_OFFSET 0x438 +#define IOSSM_CMD_PARAM_1_OFFSET 0x434 +#define IOSSM_CMD_PARAM_2_OFFSET 0x430 +#define IOSSM_CMD_PARAM_3_OFFSET 0x42C +#define IOSSM_CMD_PARAM_4_OFFSET 0x428 +#define IOSSM_CMD_PARAM_5_OFFSET 0x424 +#define IOSSM_CMD_PARAM_6_OFFSET 0x420 +#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) +#define IOSSM_CMD_RESPONSE_DATA_SHORT(n) FIELD_GET(IOSSM_CMD_RESPONSE_DATA_SHORT_MASK, n) +#define IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5) +#define IOSSM_STATUS_CMD_RESPONSE_ERROR(n) FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n) +#define IOSSM_STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) +#define IOSSM_STATUS_GENERAL_ERROR(n) FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n) + +/* Offset of Mailbox Read-only Registers */ +#define IOSSM_MAILBOX_HEADER_OFFSET 0x0 +#define IOSSM_MEM_INTF_INFO_0_OFFSET 0X200 +#define IOSSM_MEM_INTF_INFO_1_OFFSET 0x280 +#define IOSSM_MEM_TECHNOLOGY_INTF0_OFFSET 0x210 +#define IOSSM_MEM_TECHNOLOGY_INTF1_OFFSET 0x290 +#define IOSSM_MEM_WIDTH_INFO_INTF0_OFFSET 0x230 +#define IOSSM_MEM_WIDTH_INFO_INTF1_OFFSET 0x2B0 +#define IOSSM_MEM_TOTAL_CAPACITY_INTF0_OFFSET 0x234 +#define IOSSM_MEM_TOTAL_CAPACITY_INTF1_OFFSET 0x2B4 +#define IOSSM_ECC_ENABLE_INTF0_OFFSET 0x240 +#define IOSSM_ECC_ENABLE_INTF1_OFFSET 0x2C0 +#define IOSSM_ECC_SCRUB_STATUS_INTF0_OFFSET 0x244 +#define IOSSM_ECC_SCRUB_STATUS_INTF1_OFFSET 0x2C4 +#define IOSSM_LP_MODE_INTF0_OFFSET 0x250 +#define IOSSM_LP_MODE_INTF1_OFFSET 0x2D0 +#define IOSSM_MEM_INIT_STATUS_INTF0_OFFSET 0x260 +#define IOSSM_MEM_INIT_STATUS_INTF1_OFFSET 0x2E0 +#define IOSSM_BIST_STATUS_INTF0_OFFSET 0x264 +#define IOSSM_BIST_STATUS_INTF1_OFFSET 0x2E4 +#define IOSSM_ECC_ERR_STATUS_OFFSET 0x300 +#define IOSSM_ECC_ERR_DATA_START_OFFSET 0x310 +#define IOSSM_STATUS_OFFSET 0x400 +#define IOSSM_STATUS_CAL_INTF0_OFFSET 0x404 +#define IOSSM_STATUS_CAL_INTF1_OFFSET 0x408 + +#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C +#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0 +#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16) +#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17) + +/* offset info of GET_MEM_INTF_INFO */ +#define INTF_IP_TYPE_MASK GENMASK(31, 29) +#define INTF_INSTANCE_ID_MASK GENMASK(28, 24) + +/* offset info of GET_MEM_CAL_STATUS */ +#define INTF_UNUSED 0x0 +#define INTF_MEM_CAL_STATUS_SUCCESS 0x1 +#define INTF_MEM_CAL_STATUS_FAIL 0x2 +#define INTF_MEM_CAL_STATUS_ONGOING 0x4 + +/* offset info of MEM_TECHNOLOGY_INTF */ +#define INTF_DDR_TYPE_MASK GENMASK(2, 0) + +/* offset info of MEM_TOTAL_CAPACITY_INTF */ +#define INTF_CAPACITY_GBITS_MASK GENMASK(7, 0) + +/* offset info of ECC_ENABLE_INTF */ +#define INTF_ECC_ENABLE_TYPE_MASK GENMASK(1, 0) + +/* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */ +#define BIST_FULL_MEM BIT(6) + +/* offset info of ECC_ENABLE_INTF */ +#define INTF_BIST_STATUS_MASK BIT(0) + +/* offset info of ECC_ERR_STATUS */ +#define ECC_ERR_COUNTER_MASK GENMASK(15, 0) + +/* offset info of ECC_ERR_DATA */ +#define ECC_ERR_IP_TYPE_MASK GENMASK(24, 22) +#define ECC_ERR_INSTANCE_ID_MASK GENMASK(21, 17) +#define ECC_ERR_SOURCE_ID_MASK GENMASK(16, 10) +#define ECC_ERR_TYPE_MASK GENMASK(9, 6) +#define ECC_ERR_ADDR_UPPER_MASK GENMASK(5, 0) +#define ECC_ERR_ADDR_LOWER_MASK GENMASK(31, 0) + +#define MAX_ECC_ERR_INFO_COUNT 16 + +#define IO96B_MB_REQ_SETUP(v, w, x, y, z) \ + usr_req.ip_type = v; \ + usr_req.ip_id = w; \ + usr_req.usr_cmd_type = x; \ + usr_req.usr_cmd_opcode = y; \ + usr_req.cmd_param[0] = z; \ + for (n = 1; n < NUM_CMD_PARAM; n++) \ + usr_req.cmd_param[n] = 0 +#define MAX_RETRY_COUNT 3 +#define NUM_CMD_RESPONSE_DATA 3 + +#define IO96B0_PLL_A_MASK BIT(0) +#define IO96B0_PLL_B_MASK BIT(1) +#define IO96B1_PLL_A_MASK BIT(2) +#define IO96B1_PLL_B_MASK BIT(3) + +/* supported DDR type list */ +static const char *ddr_type_list[7] = { + "DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN" +}; + +/* Define an enumeration for ECC error types */ +enum ecc_error_type { + SINGLE_BIT_ERROR = 0, /* 0b0000 */ + MULTIPLE_SINGLE_BIT_ERRORS = 1, /* 0b0001 */ + DOUBLE_BIT_ERROR = 2, /* 0b0010 */ + MULTIPLE_DOUBLE_BIT_ERRORS = 3, /* 0b0011 */ + SINGLE_BIT_ERROR_SCRUBBING = 8, /* 0b1000 */ + WRITE_LINK_SINGLE_BIT_ERROR = 9, /* 0b1001 */ + WRITE_LINK_DOUBLE_BIT_ERROR = 10, /* 0b1010 */ + READ_LINK_SINGLE_BIT_ERROR = 11, /* 0b1011 */ + READ_LINK_DOUBLE_BIT_ERROR = 12, /* 0b1100 */ + READ_MODIFY_WRITE_DOUBLE_BIT_ERROR = 13 /* 0b1101 */ +}; + +/* + * ecc error info + * + * @ip_type: The IP type of the interface that produced the ECC interrupt. + * @instance_id: The instance ID of the interface that produced the ECC interrupt. + * @ecc_err_source_id: The source ID associated with the ECC event. + * @ecc_err_type: The ECC error type of the ECC event. + * @ecc_err_addr_upper: Upper 6 bits of the address of the read data that caused the ECC event. + * @ecc_err_addr_lower: Lower 32 bits of the address of the read data that caused the ECC event. + */ +struct ecc_err_info { + u32 ip_type; + u32 instance_id; + u32 source_id; + enum ecc_error_type err_type; + u32 addr_upper; + u32 addr_lower; +}; + +static int is_ddr_csr_clkgen_locked(u8 io96b_pll) +{ + int ret = 0; + const char *pll_names[MAX_IO96B_SUPPORTED][2] = { + {"io96b_0 clkgenA", "io96b_0 clkgenB"}, + {"io96b_1 clkgenA", "io96b_1 clkgenB"} + }; + u32 masks[MAX_IO96B_SUPPORTED][2] = { + {IO96B0_PLL_A_MASK, IO96B0_PLL_B_MASK}, + {IO96B1_PLL_A_MASK, IO96B1_PLL_B_MASK} + }; + u32 lock_masks[MAX_IO96B_SUPPORTED] = { + DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK, + DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK + }; + + for (int i = 0; i < MAX_IO96B_SUPPORTED ; i++) { + /* Check for PLL_A */ + if (io96b_pll & masks[i][0]) { + ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR), lock_masks[i], + true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr %s locked is timeout\n", + __func__, pll_names[i][0]); + goto err; + } else { + debug("%s: ddr csr %s is successfully locked\n", + __func__, pll_names[i][0]); + } + } + + /* Check for PLL_B */ + if (io96b_pll & masks[i][1]) { + ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR), lock_masks[i], + true, TIMEOUT, false); + + if (ret) { + debug("%s: ddr csr %s locked is timeout\n", + __func__, pll_names[i][1]); + goto err; + } else { + debug("%s: ddr csr %s is successfully locked\n", + __func__, pll_names[i][1]); + } + } + } + +err: + return ret; +} + +/* + * Mailbox request function + * This function will send the request to IOSSM mailbox and wait for response return + * + * @io96b_csr_addr: CSR address for the target IO96B + * @req: Structure contain command request for IOSSM mailbox command + * @resp_data_len: User desire extra response data fields other than + * CMD_RESPONSE_DATA_SHORT field on CMD_RESPONSE_STATUS + * @resp: Structure contain responses returned from the requested IOSSM + * mailbox command + */ +int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req, + u32 resp_data_len, struct io96b_mb_resp *resp) +{ + int i, ret; + u32 cmd_req; + + if (!resp) { + ret = -EINVAL; + goto err; + } + + /* Zero initialization for responses */ + resp->cmd_resp_status = 0; + + /* Ensure CMD_REQ is cleared before write any command request */ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET), + GENMASK(31, 0), false, TIMEOUT, false); + if (ret) { + printf("%s: Timeout of waiting DDR mailbox ready to be functioned!\n", + __func__); + goto err; + } + + /* Write CMD_PARAM_* */ + for (i = 0; i < NUM_CMD_PARAM ; i++) { + switch (i) { + case 0: + if (req.cmd_param[0]) + writel(req.cmd_param[0], io96b_csr_addr + IOSSM_CMD_PARAM_0_OFFSET); + break; + case 1: + if (req.cmd_param[1]) + writel(req.cmd_param[1], io96b_csr_addr + IOSSM_CMD_PARAM_1_OFFSET); + break; + case 2: + if (req.cmd_param[2]) + writel(req.cmd_param[2], io96b_csr_addr + IOSSM_CMD_PARAM_2_OFFSET); + break; + case 3: + if (req.cmd_param[3]) + writel(req.cmd_param[3], io96b_csr_addr + IOSSM_CMD_PARAM_3_OFFSET); + break; + case 4: + if (req.cmd_param[4]) + writel(req.cmd_param[4], io96b_csr_addr + IOSSM_CMD_PARAM_4_OFFSET); + break; + case 5: + if (req.cmd_param[5]) + writel(req.cmd_param[5], io96b_csr_addr + IOSSM_CMD_PARAM_5_OFFSET); + break; + case 6: + if (req.cmd_param[6]) + writel(req.cmd_param[6], io96b_csr_addr + IOSSM_CMD_PARAM_6_OFFSET); + break; + } + } + + /* Write CMD_REQ (IP_TYPE, IP_INSTANCE_ID, CMD_TYPE and CMD_OPCODE) */ + cmd_req = FIELD_PREP(CMD_TARGET_IP_TYPE_MASK, req.ip_type) | + FIELD_PREP(CMD_TARGET_IP_INSTANCE_ID_MASK, req.ip_id) | + FIELD_PREP(CMD_TYPE_MASK, req.usr_cmd_type) | + FIELD_PREP(CMD_OPCODE_MASK, req.usr_cmd_opcode); + writel(cmd_req, io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + + debug("%s: Write 0x%x to IOSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req, + io96b_csr_addr + IOSSM_CMD_REQ_OFFSET); + + /* Read CMD_RESPONSE_READY in CMD_RESPONSE_STATUS */ + ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET), + IOSSM_STATUS_COMMAND_RESPONSE_READY, true, TIMEOUT, false); + + /* read CMD_RESPONSE_STATUS */ + resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET); + + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr + + IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status); + + if (ret) { + printf("%s: CMD_RESPONSE ERROR:\n", __func__); + + printf("%s: STATUS_GENERAL_ERROR: 0x%lx\n", __func__, + IOSSM_STATUS_GENERAL_ERROR(resp->cmd_resp_status)); + printf("%s: STATUS_CMD_RESPONSE_ERROR: 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(resp->cmd_resp_status)); + goto err; + } + + /* read CMD_RESPONSE_DATA_* */ + for (i = 0; i < resp_data_len; i++) { + switch (i) { + case 0: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET, + resp->cmd_resp_data[i]); + break; + case 1: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET, + resp->cmd_resp_data[i]); + break; + case 2: + resp->cmd_resp_data[i] = + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET); + + debug("%s: IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET, + resp->cmd_resp_data[i]); + break; + default: + resp->cmd_resp_data[i] = 0; + printf("%s: Invalid response data\n", __func__); + } + } + + /* write CMD_RESPONSE_READY = 0 */ + clrbits_le32((u32 *)(uintptr_t)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET), + IOSSM_STATUS_COMMAND_RESPONSE_READY); + + debug("%s: After clear CMD_RESPONSE_READY bit: 0x%llx: 0x%x\n", __func__, + io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET, + readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET)); + +err: + return ret; +} + +/* + * Initial function to be called to set memory interface IP type and instance ID + * IP type and instance ID need to be determined before sending mailbox command + */ +void io96b_mb_init(struct io96b_info *io96b_ctrl) +{ + int i, j; + u32 mem_intf_info_0, mem_intf_info_1; + + debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance); + + for (i = 0; i < io96b_ctrl->num_instance; i++) { + debug("%s: get memory interface IO96B %d\n", __func__, i); + io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface = 0; + + mem_intf_info_0 = readl(io96b_ctrl->io96b[i].io96b_csr_addr + + IOSSM_MEM_INTF_INFO_0_OFFSET); + mem_intf_info_1 = readl(io96b_ctrl->io96b[i].io96b_csr_addr + + IOSSM_MEM_INTF_INFO_1_OFFSET); + + io96b_ctrl->io96b[i].mb_ctrl.ip_type[0] = FIELD_GET(INTF_IP_TYPE_MASK, + mem_intf_info_0); + io96b_ctrl->io96b[i].mb_ctrl.ip_id[0] = FIELD_GET(INTF_INSTANCE_ID_MASK, + mem_intf_info_0); + io96b_ctrl->io96b[i].mb_ctrl.ip_type[1] = FIELD_GET(INTF_IP_TYPE_MASK, + mem_intf_info_1); + io96b_ctrl->io96b[i].mb_ctrl.ip_id[1] = FIELD_GET(INTF_INSTANCE_ID_MASK, + mem_intf_info_1); + + for (j = 0; j < MAX_MEM_INTERFACE_SUPPORTED; j++) { + if (io96b_ctrl->io96b[i].mb_ctrl.ip_type[j]) { + io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface++; + + debug("%s: IO96B %d mem_interface %d: ip_type_ret: 0x%x\n", + __func__, i, j, io96b_ctrl->io96b[i].mb_ctrl.ip_type[j]); + debug("%s: IO96B %d mem_interface %d: instance_id_ret: 0x%x\n", + __func__, i, j, io96b_ctrl->io96b[i].mb_ctrl.ip_id[j]); + } + } + + debug("%s: IO96B %d: num_mem_interface: 0x%x\n", __func__, i, + io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface); + } +} + +int io96b_cal_status(phys_addr_t addr) +{ + u32 cal_success, cal_fail; + phys_addr_t status_addr = addr + IOSSM_STATUS_OFFSET; + u32 start = get_timer(0); + + do { + if (get_timer(start) > TIMEOUT_60000MS) { + printf("%s: SDRAM calibration for IO96B instance 0x%llx timeout!\n", + __func__, status_addr); + hang(); + } + + udelay(1); + schedule(); + + /* Polling until getting any calibration result */ + cal_success = readl(status_addr) & IOSSM_STATUS_CAL_SUCCESS; + cal_fail = readl(status_addr) & IOSSM_STATUS_CAL_FAIL; + } while (!cal_success && !cal_fail); + + debug("%s: Calibration for IO96B instance 0x%llx done at %ld msec!\n", + __func__, status_addr, get_timer(start)); + + if (cal_success && !cal_fail) + return 0; + else + return -EPERM; +} + +void init_mem_cal(struct io96b_info *io96b_ctrl) +{ + int count, i, ret; + + /* Initialize overall calibration status */ + io96b_ctrl->overall_cal_status = false; + + if (io96b_ctrl->ckgen_lock) { + ret = is_ddr_csr_clkgen_locked(io96b_ctrl->io96b_pll); + if (ret) { + printf("%s: iossm IO96B ckgena_lock is not locked\n", __func__); + hang(); + } + } + + /* Check initial calibration status for the assigned IO96B */ + count = 0; + for (i = 0; i < io96b_ctrl->num_instance; i++) { + ret = io96b_cal_status(io96b_ctrl->io96b[i].io96b_csr_addr); + if (ret) { + io96b_ctrl->io96b[i].cal_status = false; + + printf("%s: Initial DDR calibration IO96B_%d failed %d\n", __func__, + i, ret); + + hang(); + } + + io96b_ctrl->io96b[i].cal_status = true; + + printf("%s: Initial DDR calibration IO96B_%d succeed\n", __func__, i); + + count++; + } + + if (count == io96b_ctrl->num_instance) + io96b_ctrl->overall_cal_status = true; +} + +int get_mem_technology(struct io96b_info *io96b_ctrl) +{ + int i, j, ret = 0; + u32 mem_technology_intf; + u8 ddr_type_ret; + + u32 mem_technology_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = { + IOSSM_MEM_TECHNOLOGY_INTF0_OFFSET, + IOSSM_MEM_TECHNOLOGY_INTF1_OFFSET + }; + + /* Initialize ddr type */ + io96b_ctrl->ddr_type = ddr_type_list[6]; + + /* Get and ensure all memory interface(s) same DDR type */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + mem_technology_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr + + mem_technology_intf_offset[j]); + + ddr_type_ret = FIELD_GET(INTF_DDR_TYPE_MASK, mem_technology_intf); + + if (!strcmp(io96b_ctrl->ddr_type, "UNKNOWN")) + io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret]; + + if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) { + printf("%s: Mismatch DDR type on IO96B_%d\n", __func__, i); + + ret = -EINVAL; + goto err; + } + } + } + +err: + return ret; +} + +int get_mem_width_info(struct io96b_info *io96b_ctrl) +{ + int i, j, ret = 0; + u32 mem_width_info; + u16 memory_size, total_memory_size = 0; + + u32 mem_total_capacity_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = { + IOSSM_MEM_TOTAL_CAPACITY_INTF0_OFFSET, + IOSSM_MEM_TOTAL_CAPACITY_INTF1_OFFSET + }; + + /* Get all memory interface(s) total memory size on all instance(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + memory_size = 0; + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + mem_width_info = readl(io96b_ctrl->io96b[i].io96b_csr_addr + + mem_total_capacity_intf_offset[j]); + + memory_size = memory_size + + FIELD_GET(INTF_CAPACITY_GBITS_MASK, mem_width_info); + } + + if (!memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + ret = -EINVAL; + goto err; + } + + io96b_ctrl->io96b[i].size = memory_size; + + total_memory_size = total_memory_size + memory_size; + } + + if (!total_memory_size) { + printf("%s: Failed to get valid memory size\n", __func__); + ret = -EINVAL; + } + + io96b_ctrl->overall_size = total_memory_size; + +err: + return ret; +} + +int ecc_enable_status(struct io96b_info *io96b_ctrl) +{ + int i, j, ret = 0; + u32 ecc_enable_intf; + bool ecc_stat, ecc_stat_set = false; + + u32 ecc_enable_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = { + IOSSM_ECC_ENABLE_INTF0_OFFSET, + IOSSM_ECC_ENABLE_INTF1_OFFSET + }; + + /* Initialize ECC status */ + io96b_ctrl->ecc_status = false; + + /* Get and ensure all memory interface(s) same ECC status */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + ecc_enable_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr + + ecc_enable_intf_offset[j]); + + ecc_stat = (FIELD_GET(INTF_ECC_ENABLE_TYPE_MASK, ecc_enable_intf) + == 0) ? false : true; + + if (!ecc_stat_set) { + io96b_ctrl->ecc_status = ecc_stat; + ecc_stat_set = true; + } + + if (ecc_stat != io96b_ctrl->ecc_status) { + printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i); + + ret = -EINVAL; + goto err; + } + } + } + + debug("%s: ECC enable status: %d\n", __func__, io96b_ctrl->ecc_status); + +err: + return ret; +} + +bool is_double_bit_error(enum ecc_error_type err_type) +{ + switch (err_type) { + case DOUBLE_BIT_ERROR: + case MULTIPLE_DOUBLE_BIT_ERRORS: + case WRITE_LINK_DOUBLE_BIT_ERROR: + case READ_LINK_DOUBLE_BIT_ERROR: + case READ_MODIFY_WRITE_DOUBLE_BIT_ERROR: + return true; + + default: + return false; + } +} + +bool ecc_interrupt_status(struct io96b_info *io96b_ctrl) +{ + int i, j; + u32 ecc_err_status; + u16 ecc_err_counter; + bool ecc_error_flag = false; + + /* Get ECC double-bit error status */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + ecc_err_status = readl(io96b_ctrl->io96b[i].io96b_csr_addr + + IOSSM_ECC_ERR_STATUS_OFFSET); + ecc_err_counter = FIELD_GET(ECC_ERR_COUNTER_MASK, ecc_err_status); + debug("%s: ECC error number detected on IO96B_%d: %d\n", + __func__, i, ecc_err_counter); + + if (ecc_err_counter != 0) { + phys_addr_t address; + u32 ecc_err_data; + struct ecc_err_info err_info; + + address = io96b_ctrl->io96b[i].io96b_csr_addr + + IOSSM_ECC_ERR_DATA_START_OFFSET; + + for (j = 0; j < ecc_err_counter && j < MAX_ECC_ERR_INFO_COUNT; j++) { + ecc_err_data = readl(address); + err_info.err_type = FIELD_GET(ECC_ERR_TYPE_MASK, + ecc_err_data); + err_info.ip_type = FIELD_GET(ECC_ERR_IP_TYPE_MASK, + ecc_err_data); + err_info.instance_id = FIELD_GET(ECC_ERR_INSTANCE_ID_MASK, + ecc_err_data); + err_info.source_id = FIELD_GET(ECC_ERR_SOURCE_ID_MASK, + ecc_err_data); + err_info.addr_upper = FIELD_GET(ECC_ERR_ADDR_UPPER_MASK, + ecc_err_data); + err_info.addr_lower = readl(address + sizeof(u32)); + + debug("%s: ECC double-bit error detected on IO96B_%d:\n", + __func__, i); + debug("- error info address :0x%llx\n", address); + debug("- error ip type: %d\n", err_info.ip_type); + debug("- error instance id: %d\n", err_info.instance_id); + debug("- error source id: %d\n", err_info.source_id); + debug("- error type: %d\n", err_info.err_type); + debug("- error address upper: 0x%x\n", err_info.addr_upper); + debug("- error address lower: 0x%x\n", err_info.addr_lower); + + if (is_double_bit_error(err_info.err_type)) { + if (!ecc_error_flag) + ecc_error_flag = true; + } + + address += sizeof(u32) * 2; + } + } + } + + if (ecc_error_flag) + printf("\n%s: ECC double-bit error detected!\n", __func__); + + return ecc_error_flag; +} + +int bist_mem_init_start(struct io96b_info *io96b_ctrl) +{ + struct io96b_mb_req usr_req; + struct io96b_mb_resp usr_resp; + int i, j, n, ret = 0; + bool bist_start, bist_success; + u32 mem_init_status_intf, start; + + u32 mem_init_status_offset[MAX_MEM_INTERFACE_SUPPORTED] = { + IOSSM_MEM_INIT_STATUS_INTF0_OFFSET, + IOSSM_MEM_INIT_STATUS_INTF1_OFFSET + }; + + /* Full memory initialization BIST performed on all memory interface(s) */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) { + bist_start = false; + bist_success = false; + + /* Start memory initialization BIST on full memory address */ + IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j], + io96b_ctrl->io96b[i].mb_ctrl.ip_id[j], + CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START, + BIST_FULL_MEM); + + ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr, + usr_req, 0, &usr_resp); + if (ret) + goto err; + + bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) + & BIT(0); + + if (!bist_start) { + printf("%s: Failed to initialize memory on IO96B_%d\n", __func__, + i); + printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + ret = -EINVAL; + goto err; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + udelay(1); + + mem_init_status_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr + + mem_init_status_offset[j]); + + bist_success = FIELD_GET(INTF_BIST_STATUS_MASK, + mem_init_status_intf); + + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initialize memory on IO96B_%d\n", + __func__, i); + printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n", + __func__, + IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status)); + + ret = -ETIMEDOUT; + goto err; + } + } + } + + debug("%s: Memory initialized successfully on IO96B_%d\n", __func__, i); + } + +err: + return ret; +} diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h new file mode 100644 index 00000000000..6f794781d30 --- /dev/null +++ b/drivers/ddr/altera/iossm_mailbox.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + * + */ + +#define MAX_IO96B_SUPPORTED 2 +#define MAX_MEM_INTERFACE_SUPPORTED 2 +#define NUM_CMD_RESPONSE_DATA 3 +#define NUM_CMD_PARAM 7 + +/* supported mailbox command type */ +enum iossm_mailbox_cmd_type { + CMD_NOP, + CMD_GET_SYS_INFO, + CMD_GET_MEM_INFO, + CMD_GET_MEM_CAL_INFO, + CMD_TRIG_CONTROLLER_OP, + CMD_TRIG_MEM_CAL_OP +}; + +/* supported mailbox command opcode */ +enum iossm_mailbox_cmd_opcode { + ECC_ENABLE_SET = 0x0101, + ECC_INTERRUPT_MASK = 0x0105, + ECC_WRITEBACK_ENABLE = 0x0106, + ECC_INJECT_ERROR = 0x0109, + ECC_SCRUB_MODE_0_START = 0x0202, + ECC_SCRUB_MODE_1_START = 0x0203, + BIST_STANDARD_MODE_START = 0x0301, + BIST_MEM_INIT_START = 0x0303, + BIST_SET_DATA_PATTERN_UPPER = 0x0305, + BIST_SET_DATA_PATTERN_LOWER = 0x0306, + TRIG_MEM_CAL = 0x000a +}; + +/* + * IOSSM mailbox required information + * + * @num_mem_interface: Number of memory interfaces instantiated + * @ip_type: IP type implemented on the IO96B + * @ip_instance_id: IP identifier for every IP instance implemented on the IO96B + */ +struct io96b_mb_ctrl { + u32 num_mem_interface; + u32 ip_type[2]; + u32 ip_id[2]; +}; + +/* CMD_REQ Register Definition */ +#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29) +#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24) +#define CMD_TYPE_MASK GENMASK(23, 16) +#define CMD_OPCODE_MASK GENMASK(15, 0) + +/* + * IOSSM mailbox request + * @ip_type: IP type for the specified memory interface + * @ip_id: IP instance ID for the specified memory interface + * @usr_cmd_type: User desire IOSSM mailbox command type + * @usr_cmd_opcode: User desire IOSSM mailbox command opcode + * @cmd_param_*: Parameters (if applicable) for the requested IOSSM mailbox command + */ +struct io96b_mb_req { + u32 ip_type; + u32 ip_id; + u32 usr_cmd_type; + u32 usr_cmd_opcode; + u32 cmd_param[NUM_CMD_PARAM]; +}; + +/* + * IOSSM mailbox response outputs + * + * @cmd_resp_status: Command Interface status + * @cmd_resp_data_*: More spaces for command response + */ +struct io96b_mb_resp { + u32 cmd_resp_status; + u32 cmd_resp_data[NUM_CMD_RESPONSE_DATA]; +}; + +/* + * IO96B instance specific information + * + * @size: Memory size + * @io96b_csr_addr: IO96B instance CSR address + * @cal_status: IO96B instance calibration status + * @mb_ctrl: IOSSM mailbox required information + */ +struct io96b_instance { + u16 size; + phys_addr_t io96b_csr_addr; + bool cal_status; + struct io96b_mb_ctrl mb_ctrl; +}; + +/* + * Overall IO96B instance(s) information + * + * @num_instance: Number of instance(s) assigned to HPS + * @overall_cal_status: Overall calibration status for all IO96B instance(s) + * @ddr_type: DDR memory type + * @ecc_status: ECC enable status (false = disabled, true = enabled) + * @overall_size: Total DDR memory size + * @io96b[]: IO96B instance specific information + * @ckgen_lock: IO96B GEN PLL lock (false = not locked, true = locked) + * @num_port: Number of IO96B port. + * @io96b_pll: Selected IO96B PLL. Example bit 0: EMIF0 PLL A selected, + * bit 1: EMIF0 PLL B selected, bit 2 - EMIF1 PLL A selected, + * bit 3: EMIF1 PLL B selected + */ +struct io96b_info { + u8 num_instance; + bool overall_cal_status; + const char *ddr_type; + bool ecc_status; + u16 overall_size; + struct io96b_instance io96b[MAX_IO96B_SUPPORTED]; + bool ckgen_lock; + u8 num_port; + u8 io96b_pll; +}; + +int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req, + u32 resp_data_len, struct io96b_mb_resp *resp); + +/* Supported IOSSM mailbox function */ +void io96b_mb_init(struct io96b_info *io96b_ctrl); +int io96b_cal_status(phys_addr_t addr); +void init_mem_cal(struct io96b_info *io96b_ctrl); +int get_mem_technology(struct io96b_info *io96b_ctrl); +int get_mem_width_info(struct io96b_info *io96b_ctrl); +int ecc_enable_status(struct io96b_info *io96b_ctrl); +int bist_mem_init_start(struct io96b_info *io96b_ctrl); +bool ecc_interrupt_status(struct io96b_info *io96b_ctrl); diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c new file mode 100644 index 00000000000..801a6bbab46 --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + * + */ + +#include <stdlib.h> +#include <div64.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <hang.h> +#include <log.h> +#include <ram.h> +#include <reset.h> +#include <wait_bit.h> +#include <wdt.h> +#include <linux/bitfield.h> +#include <linux/sizes.h> +#include <asm/arch/firewall.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include "iossm_mailbox.h" +#include "sdram_soc64.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* MPFE NOC registers */ +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 0x58 +#define SIDEBANDMGR_FLAGOUTSET0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSET0 +#define SIDEBANDMGR_FLAGOUTSTATUS0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 +#define BOOT_SCRATCH_COLD3_REG (socfpga_get_sysmgr_addr() +\ + SYSMGR_SOC64_BOOT_SCRATCH_COLD3) +#define PORT_EMIF_CONFIG_OFFSET 4 +#define EMIF_PLL_MASK GENMASK(19, 16) + +#define IO96B0_DUAL_PORT_MASK BIT(0) +#define IO96B0_DUAL_EMIF_MASK BIT(1) + +#define FIREWALL_MPFE_SCR_IO96B0_REG 0x18000d00 +#define FIREWALL_MPFE_SCR_IO96B1_REG 0x18000d04 +#define FIREWALL_MPFE_NOC_CSR_REG 0x18000d08 + +#define MEMORY_BANK_MAX_COUNT 3 + +/* Reset type */ +enum reset_type { + POR_RESET, + WARM_RESET, + COLD_RESET, + NCONFIG, + JTAG_CONFIG, + RSU_RECONFIG +}; + +phys_addr_t io96b_csr_reg_addr[] = { + 0x18400000, /* IO96B_0 CSR registers address */ + 0x18800000 /* IO96B_1 CSR registers address */ +}; + +struct dram_bank_info_s { + phys_addr_t start; + phys_size_t max_size; +}; + +struct dram_bank_info_s dram_bank_info[MEMORY_BANK_MAX_COUNT] = { + {0x80000000, 0x80000000}, /* Memory Bank 0 */ + {0x880000000, 0x780000000}, /* Memory Bank 1 */ + {0x8800000000, 0x7800000000} /* Memory Bank 2 */ +}; + +static enum reset_type get_reset_type(u32 reg) +{ + return FIELD_GET(ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK, reg); +} + +static void update_io96b_assigned_to_hps(bool dual_port_flag, bool dual_emif_flag) +{ + clrsetbits_le32(BOOT_SCRATCH_COLD3_REG, + ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK, + FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK, dual_port_flag) | + FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK, dual_emif_flag)); + + debug("%s: update dual port dual emif info: 0x%x\n", __func__, + readl(BOOT_SCRATCH_COLD3_REG)); +} + +static void set_mpfe_config(void) +{ + /* Set mpfe_lite_intfcsel */ + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(2)); + + /* Set mpfe_lite_active */ + setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(8)); + + debug("%s: mpfe_config: 0x%x\n", __func__, + readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG)); +} + +static bool is_ddr_init_hang(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_POR0); + + debug("%s: 0x%x\n", __func__, reg); + + if (reg & ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK) + return true; + + return false; +} + +static void ddr_init_inprogress(bool start) +{ + if (start) + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_POR0, + ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK); + else + clrbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_POR0, + ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK); +} + +static void populate_ddr_handoff(struct udevice *dev, struct io96b_info *io96b_ctrl) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + int i; + u32 len = SOC64_HANDOFF_SDRAM_LEN; + u32 handoff_table[len]; + + /* Read handoff for DDR configuration */ + socfpga_handoff_read((void *)SOC64_HANDOFF_SDRAM, handoff_table, len); + + /* Read handoff - dual port */ + plat->dualport = FIELD_GET(IO96B0_DUAL_PORT_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]); + debug("%s: dualport from handoff: 0x%x\n", __func__, plat->dualport); + + if (plat->dualport) + io96b_ctrl->num_port = 2; + else + io96b_ctrl->num_port = 1; + + /* Read handoff - dual EMIF */ + plat->dualemif = FIELD_GET(IO96B0_DUAL_EMIF_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]); + debug("%s: dualemif from handoff: 0x%x\n", __func__, plat->dualemif); + + if (plat->dualemif) + io96b_ctrl->num_instance = 2; + else + io96b_ctrl->num_instance = 1; + + io96b_ctrl->io96b_pll = FIELD_GET(EMIF_PLL_MASK, + handoff_table[PORT_EMIF_CONFIG_OFFSET]); + debug("%s: io96b enabled pll from handoff: 0x%x\n", __func__, io96b_ctrl->io96b_pll); + + update_io96b_assigned_to_hps(plat->dualport, plat->dualemif); + + /* Assign IO96B CSR base address if it is valid */ + for (i = 0; i < io96b_ctrl->num_instance; i++) { + io96b_ctrl->io96b[i].io96b_csr_addr = io96b_csr_reg_addr[i]; + debug("%s: IO96B 0x%llx CSR enabled\n", __func__, + io96b_ctrl->io96b[i].io96b_csr_addr); + } +} + +static void config_mpfe_sideband_mgr(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + + /* Dual port setting */ + if (plat->dualport) + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(4)); + + /* Dual EMIF setting */ + if (plat->dualemif) { + set_mpfe_config(); + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(5)); + } + + debug("%s: SIDEBANDMGR_FLAGOUTSTATUS0: 0x%x\n", __func__, + readl(SIDEBANDMGR_FLAGOUTSTATUS0_REG)); +} + +static void config_ccu_mgr(struct udevice *dev) +{ + int ret = 0; + struct altera_sdram_plat *plat = dev_get_plat(dev); + + if (plat->dualport || plat->dualemif) { + debug("%s: config interleaving on ccu reg\n", __func__); + ret = uclass_get_device_by_name(UCLASS_NOP, + "socfpga-ccu-ddr-interleaving-on", &dev); + } else { + debug("%s: config interleaving off ccu reg\n", __func__); + ret = uclass_get_device_by_name(UCLASS_NOP, + "socfpga-ccu-ddr-interleaving-off", &dev); + } + + if (ret) { + printf("interleaving on/off ccu settings init failed: %d\n", ret); + hang(); + } +} + +static void config_firewall_mpfe_csr(struct udevice *dev) +{ + int ret = 0; + + debug("%s: config Firewall setting for MPFE CSR\n", __func__); + ret = uclass_get_device_by_name(UCLASS_NOP, + "socfpga-noc-fw-mpfe-csr", &dev); + + if (ret) { + printf("Firewall setting for MPFE CSR init failed: %d\n", ret); + hang(); + } +} + +static bool hps_ocram_dbe_status(void) +{ + u32 reg = readl(BOOT_SCRATCH_COLD3_REG); + + if (reg & ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK) + return true; + + return false; +} + +int sdram_mmr_init_full(struct udevice *dev) +{ + int i, ret = 0; + phys_size_t hw_size; + struct altera_sdram_plat *plat = dev_get_plat(dev); + struct altera_sdram_priv *priv = dev_get_priv(dev); + struct io96b_info *io96b_ctrl = malloc(sizeof(*io96b_ctrl)); + + u32 reg = readl(BOOT_SCRATCH_COLD3_REG); + enum reset_type reset_t = get_reset_type(reg); + bool full_mem_init = false; + + /* DDR initialization progress status tracking */ + bool is_ddr_hang_be4_rst = is_ddr_init_hang(); + + debug("DDR: SDRAM init in progress ...\n"); + ddr_init_inprogress(true); + + gd->bd = (struct bd_info *)malloc(sizeof(struct bd_info)); + memset(gd->bd, '\0', sizeof(struct bd_info)); + + debug("DDR: Address MPFE 0x%llx\n", plat->mpfe_base_addr); + + /* Populating DDR handoff data */ + debug("DDR: Checking SDRAM configuration in progress ...\n"); + populate_ddr_handoff(dev, io96b_ctrl); + + /* Configuring MPFE sideband manager registers - dual port & dual emif */ + config_mpfe_sideband_mgr(dev); + + /* Configuring Interleave/Non-interleave ccu registers */ + config_ccu_mgr(dev); + + /* Configure if polling is needed for IO96B GEN PLL locked */ + io96b_ctrl->ckgen_lock = true; + + /* Ensure calibration status passing */ + init_mem_cal(io96b_ctrl); + + printf("DDR: Calibration success\n"); + + /* Initiate IOSSM mailbox */ + io96b_mb_init(io96b_ctrl); + + /* DDR type, DDR size and ECC status) */ + ret = get_mem_technology(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR type\n"); + + goto err; + } + + ret = get_mem_width_info(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR size\n"); + + goto err; + } + + hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8; + + /* Get bank configuration from devicetree */ + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, + (phys_size_t *)&gd->ram_size, gd->bd); + if (ret) { + puts("DDR: Failed to decode memory node\n"); + ret = -ENXIO; + + goto err; + } + + if (gd->ram_size > hw_size) { + printf("DDR: Warning: DRAM size from device tree (%lld MiB) exceeds\n", + gd->ram_size >> 20); + printf(" the actual hardware capacity(%lld MiB). Memory configuration will be\n", + hw_size >> 20); + printf(" adjusted to match the detected hardware size.\n"); + gd->ram_size = 0; + } + + if (gd->ram_size > 0 && gd->ram_size != hw_size) { + printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n", + gd->ram_size >> 20); + printf(" mismatch with hardware capacity(%lld MiB).\n", + hw_size >> 20); + } + + if (gd->ram_size == 0 && hw_size > 0) { + phys_size_t remaining_size, size_counter = 0; + u8 config_dram_banks; + + if (CONFIG_NR_DRAM_BANKS > MEMORY_BANK_MAX_COUNT) { + printf("DDR: Warning: CONFIG_NR_DRAM_BANKS(%d) is bigger than Max Memory Bank count(%d).\n", + CONFIG_NR_DRAM_BANKS, MEMORY_BANK_MAX_COUNT); + printf(" Max Memory Bank count is in use instead of CONFIG_NR_DRAM_BANKS.\n"); + config_dram_banks = MEMORY_BANK_MAX_COUNT; + } else { + config_dram_banks = CONFIG_NR_DRAM_BANKS; + } + + for (i = 0; i < config_dram_banks; i++) { + remaining_size = hw_size - size_counter; + if (remaining_size <= dram_bank_info[i].max_size) { + gd->bd->bi_dram[i].start = dram_bank_info[i].start; + gd->bd->bi_dram[i].size = remaining_size; + debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", + i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + break; + } + + gd->bd->bi_dram[i].start = dram_bank_info[i].start; + gd->bd->bi_dram[i].size = dram_bank_info[i].max_size; + + debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", + i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + size_counter += gd->bd->bi_dram[i].size; + } + + gd->ram_size = hw_size; + } + + printf("%s: %lld MiB\n", io96b_ctrl->ddr_type, gd->ram_size >> 20); + + ret = ecc_enable_status(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get ECC enabled status\n"); + + goto err; + } + + /* Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC + * enabled to preserve memory content + */ + if (io96b_ctrl->ecc_status) { + if (ecc_interrupt_status(io96b_ctrl)) { + if (CONFIG_IS_ENABLED(WDT)) { + struct udevice *wdt; + + printf("DDR: ECC error recover start now\n"); + ret = uclass_first_device_err(UCLASS_WDT, &wdt); + if (ret) { + printf("DDR: Failed to trigger watchdog reset\n"); + hang(); + } + + wdt_expire_now(wdt, 0); + } + hang(); + } + + full_mem_init = hps_ocram_dbe_status() | is_ddr_hang_be4_rst; + if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) { + ret = bist_mem_init_start(io96b_ctrl); + if (ret) { + printf("DDR: Failed to fully initialize DDR memory\n"); + + goto err; + } + } + + printf("SDRAM-ECC: Initialized success\n"); + } + + sdram_size_check(gd->bd); + printf("DDR: size check success\n"); + + sdram_set_firewall(gd->bd); + + /* Firewall setting for MPFE CSR */ + config_firewall_mpfe_csr(dev); + + printf("DDR: firewall init success\n"); + + priv->info.base = gd->bd->bi_dram[0].start; + priv->info.size = gd->ram_size; + + /* Ending DDR driver initialization success tracking */ + ddr_init_inprogress(false); + + printf("DDR: init success\n"); + +err: + free(io96b_ctrl); + + return ret; +} diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 10a8e64af3d..c8c9211adce 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -28,6 +29,7 @@ #define PGTABLE_OFF 0x4000 +#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -99,8 +101,9 @@ int emif_reset(struct altera_sdram_plat *plat) debug("DDR: %s triggered successly\n", __func__); return 0; } +#endif -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + @@ -252,7 +255,7 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) return size; } -void sdram_set_firewall(struct bd_info *bd) +static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) { u32 i; phys_size_t value; @@ -288,7 +291,7 @@ void sdram_set_firewall(struct bd_info *bd) FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT + (i * 4 * sizeof(u32))); - /* Setting non-secure MPU limit and limit extexded */ + /* Setting non-secure MPU limit and limit extended */ value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; lower = lower_32_bits(value); @@ -301,7 +304,7 @@ void sdram_set_firewall(struct bd_info *bd) FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT + (i * 4 * sizeof(u32))); - /* Setting non-secure Non-MPU limit and limit extexded */ + /* Setting non-secure Non-MPU limit and limit extended */ FW_MPU_DDR_SCR_WRITEL(lower, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT + (i * 4 * sizeof(u32))); @@ -314,15 +317,77 @@ void sdram_set_firewall(struct bd_info *bd) } } +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +static void sdram_set_firewall_f2sdram(struct bd_info *bd) +{ + u32 i, lower, upper; + phys_size_t value; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (!bd->bi_dram[i].size) + continue; + + value = bd->bi_dram[i].start; + + /* Keep first 1MB of SDRAM memory region as secure region when + * using ATF flow, where the ATF code is located. + */ + if (IS_ENABLED(CONFIG_SPL_ATF) && i == 0) + value += SZ_1M; + + /* Setting base and base extended */ + lower = lower_32_bits(value); + upper = upper_32_bits(value); + FW_F2SDRAM_DDR_SCR_WRITEL(lower, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE + + (i * 4 * sizeof(u32))); + FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT + + (i * 4 * sizeof(u32))); + + /* Setting limit and limit extended */ + value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + + lower = lower_32_bits(value); + upper = upper_32_bits(value); + + FW_F2SDRAM_DDR_SCR_WRITEL(lower, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT + + (i * 4 * sizeof(u32))); + FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff, + FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT + + (i * 4 * sizeof(u32))); + + FW_F2SDRAM_DDR_SCR_WRITEL(BIT(i), FW_F2SDRAM_DDR_SCR_EN_SET); + } +} +#endif + +void sdram_set_firewall(struct bd_info *bd) +{ + sdram_set_firewall_non_f2sdram(bd); + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + sdram_set_firewall_f2sdram(bd); +#endif +} + static int altera_sdram_of_to_plat(struct udevice *dev) { +#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) struct altera_sdram_plat *plat = dev_get_plat(dev); fdt_addr_t addr; +#endif /* These regs info are part of DDR handoff in bitstream */ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) return 0; -#endif +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->mpfe_base_addr = addr; +#else addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) @@ -338,7 +403,7 @@ static int altera_sdram_of_to_plat(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; plat->hmc = (void __iomem *)addr; - +#endif return 0; } @@ -385,6 +450,7 @@ static const struct udevice_id altera_sdram_ids[] = { { .compatible = "altr,sdr-ctl-s10" }, { .compatible = "intel,sdr-ctl-agilex" }, { .compatible = "intel,sdr-ctl-n5x" }, + { .compatible = "intel,sdr-ctl-agilex5" }, { /* sentinel */ } }; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 87a70a861ba..183b1a33080 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> + * */ #ifndef _SDRAM_SOC64_H_ @@ -13,11 +15,19 @@ struct altera_sdram_priv { struct reset_ctl_bulk resets; }; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +struct altera_sdram_plat { + fdt_addr_t mpfe_base_addr; + bool dualport; + bool dualemif; +}; +#else struct altera_sdram_plat { void __iomem *hmc; void __iomem *ddr_sch; void __iomem *iomhc; }; +#endif /* ECC HMC registers */ #define DDRIOCTRL 0x8 diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 3013c4741d0..723265ab2e5 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -36,6 +36,7 @@ #include "k3-psil-priv.h" #define K3_UDMA_MAX_RFLOWS 1024 +#define K3_UDMA_MAX_TR 2 struct udma_chan; @@ -74,7 +75,6 @@ struct udma_tchan { struct k3_nav_ring *t_ring; /* Transmit ring */ struct k3_nav_ring *tc_ring; /* Transmit Completion ring */ int tflow_id; /* applicable only for PKTDMA */ - }; #define udma_bchan udma_tchan @@ -175,6 +175,7 @@ struct udma_dev { struct udma_rflow *rflows; struct udma_match_data *match_data; + void *bc_desc; struct udma_chan *channels; u32 psil_base; @@ -1349,6 +1350,7 @@ static int udma_setup_resources(struct udma_dev *ud) struct ti_sci_resource_desc *rm_desc; struct ti_sci_resource *rm_res; struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + size_t desc_size; ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt), sizeof(unsigned long), GFP_KERNEL); @@ -1366,9 +1368,11 @@ static int udma_setup_resources(struct udma_dev *ud) ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows), GFP_KERNEL); + desc_size = cppi5_trdesc_calc_size(K3_UDMA_MAX_TR, sizeof(struct cppi5_tr_type15_t)); + ud->bc_desc = devm_kzalloc(dev, ALIGN(desc_size, ARCH_DMA_MINALIGN), GFP_KERNEL); if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map || !ud->rflow_map_reserved || !ud->tchans || !ud->rchans || - !ud->rflows) + !ud->rflows || !ud->bc_desc) return -ENOMEM; /* @@ -1444,6 +1448,7 @@ static int bcdma_setup_resources(struct udma_dev *ud) struct ti_sci_resource_desc *rm_desc; struct ti_sci_resource *rm_res; struct udma_tisci_rm *tisci_rm = &ud->tisci_rm; + size_t desc_size; ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt), sizeof(unsigned long), GFP_KERNEL); @@ -1460,9 +1465,12 @@ static int bcdma_setup_resources(struct udma_dev *ud) ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows), GFP_KERNEL); + desc_size = cppi5_trdesc_calc_size(K3_UDMA_MAX_TR, sizeof(struct cppi5_tr_type15_t)); + ud->bc_desc = devm_kzalloc(dev, ALIGN(desc_size, ARCH_DMA_MINALIGN), GFP_KERNEL); + if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map || !ud->bchans || !ud->tchans || !ud->rchans || - !ud->rflows) + !ud->rflows || !ud->bc_desc) return -ENOMEM; /* Get resource ranges from tisci */ @@ -1718,8 +1726,7 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest, int num_tr; size_t tr_size = sizeof(struct cppi5_tr_type15_t); u16 tr0_cnt0, tr0_cnt1, tr1_cnt0; - unsigned long dummy; - void *tr_desc; + void *tr_desc = uc->ud->bc_desc; size_t desc_size; if (len < SZ_64K) { @@ -1748,9 +1755,6 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest, } desc_size = cppi5_trdesc_calc_size(num_tr, tr_size); - tr_desc = dma_alloc_coherent(desc_size, &dummy); - if (!tr_desc) - return NULL; memset(tr_desc, 0, desc_size); cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0); diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 1f6782537de..f88267e01b6 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -33,9 +33,9 @@ static void fpga_no_sup(char *fn, char *msg) /* fpga_get_desc * map a device number to a descriptor */ -const fpga_desc *const fpga_get_desc(int devnum) +const fpga_desc *fpga_get_desc(int devnum) { - fpga_desc *desc = (fpga_desc *)NULL; + const fpga_desc *desc = NULL; if ((devnum >= 0) && (devnum < next_desc)) { desc = &desc_table[devnum]; @@ -50,8 +50,8 @@ const fpga_desc *const fpga_get_desc(int devnum) * fpga_validate * generic parameter checking code */ -const fpga_desc *const fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn) +const fpga_desc *fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn) { const fpga_desc *desc = fpga_get_desc(devnum); @@ -60,7 +60,7 @@ const fpga_desc *const fpga_validate(int devnum, const void *buf, if (!buf) { printf("%s: Null buffer.\n", fn); - return (fpga_desc * const)NULL; + return NULL; } return desc; } @@ -72,7 +72,7 @@ const fpga_desc *const fpga_validate(int devnum, const void *buf, static int fpga_dev_info(int devnum) { int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc * const desc = fpga_get_desc(devnum); + const fpga_desc *desc = fpga_get_desc(devnum); if (desc) { debug("%s: Device Descriptor @ 0x%p\n", @@ -374,7 +374,7 @@ int fpga_info(int devnum) #if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) int fpga_compatible2flag(int devnum, const char *compatible) { - const fpga_desc * const desc = fpga_get_desc(devnum); + const fpga_desc *desc = fpga_get_desc(devnum); if (!desc) return 0; diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index da929c33447..3d9f8b32b8d 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -1145,29 +1145,9 @@ static int gpio_request_tail(int ret, const char *nodename, ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node, &desc->dev); if (ret) { -#if CONFIG_IS_ENABLED(MAX77663_GPIO) || CONFIG_IS_ENABLED(PALMAS_GPIO) - struct udevice *pmic; - ret = uclass_get_device_by_ofnode(UCLASS_PMIC, args->node, - &pmic); - if (ret) { - log_debug("%s: PMIC device get failed, err %d\n", - __func__, ret); - goto err; - } - - device_foreach_child(desc->dev, pmic) { - if (device_get_uclass_id(desc->dev) == UCLASS_GPIO) - break; - } - - /* if loop exits without GPIO device return error */ - if (device_get_uclass_id(desc->dev) != UCLASS_GPIO) - goto err; -#else debug("%s: uclass_get_device_by_ofnode failed\n", __func__); goto err; -#endif } } ret = gpio_find_and_xlate(desc, args); diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index e84038f312e..523ca8473a8 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -393,6 +393,8 @@ static const struct udevice_id pca953x_ids[] = { { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, + { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, + { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, { .compatible = "maxim,max7310", .data = OF_953X(8, 0), }, diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index 760750568c0..22f61d12d38 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -13,6 +13,25 @@ #include <dm/lists.h> #include <dm/root.h> #include <dm/uclass-internal.h> +#include <dt-bindings/leds/common.h> + +static const char * const led_colors[LED_COLOR_ID_MAX] = { + [LED_COLOR_ID_WHITE] = "white", + [LED_COLOR_ID_RED] = "red", + [LED_COLOR_ID_GREEN] = "green", + [LED_COLOR_ID_BLUE] = "blue", + [LED_COLOR_ID_AMBER] = "amber", + [LED_COLOR_ID_VIOLET] = "violet", + [LED_COLOR_ID_YELLOW] = "yellow", + [LED_COLOR_ID_IR] = "ir", + [LED_COLOR_ID_MULTI] = "multicolor", + [LED_COLOR_ID_RGB] = "rgb", + [LED_COLOR_ID_PURPLE] = "purple", + [LED_COLOR_ID_ORANGE] = "orange", + [LED_COLOR_ID_PINK] = "pink", + [LED_COLOR_ID_CYAN] = "cyan", + [LED_COLOR_ID_LIME] = "lime", +}; int led_bind_generic(struct udevice *parent, const char *driver_name) { @@ -232,11 +251,58 @@ int led_activity_blink(void) #endif #endif -static const char *led_get_label(ofnode node) +static const char *led_get_function_name(struct udevice *dev) +{ + struct led_uc_plat *uc_plat; + const char *func; + u32 color; + u32 enumerator; + int ret; + int cp; + + if (!dev) + return NULL; + + uc_plat = dev_get_uclass_plat(dev); + if (!uc_plat) + return NULL; + + if (uc_plat->label) + return uc_plat->label; + + /* Now try to detect function label name */ + func = dev_read_string(dev, "function"); + cp = dev_read_u32(dev, "color", &color); + // prevent coverity scan error CID 541279: (TAINTED_SCALAR) + if (color < LED_COLOR_ID_WHITE || color >= LED_COLOR_ID_MAX) + cp = -EINVAL; + + if (cp == 0 || func) { + ret = dev_read_u32(dev, "function-enumerator", &enumerator); + if (!ret) { + snprintf(uc_plat->name, LED_MAX_NAME_SIZE, + "%s:%s-%d", + cp ? "" : led_colors[color], + func ? func : "", enumerator); + } else { + snprintf(uc_plat->name, LED_MAX_NAME_SIZE, + "%s:%s", + cp ? "" : led_colors[color], + func ? func : ""); + } + uc_plat->label = uc_plat->name; + } + + return uc_plat->label; +} + +static const char *led_get_label(struct udevice *dev, ofnode node) { const char *label; label = ofnode_read_string(node, "label"); + if (!label) + label = led_get_function_name(dev); if (!label && !ofnode_read_string(node, "compatible")) label = ofnode_get_name(node); @@ -249,7 +315,7 @@ static int led_post_bind(struct udevice *dev) const char *default_state; if (!uc_plat->label) - uc_plat->label = led_get_label(dev_ofnode(dev)); + uc_plat->label = led_get_label(dev, dev_ofnode(dev)); uc_plat->default_state = LEDST_COUNT; @@ -314,14 +380,14 @@ static int led_init(struct uclass *uc) #ifdef CONFIG_LED_BOOT ret = ofnode_options_get_by_phandle("boot-led", &led_node); if (!ret) - priv->boot_led_label = led_get_label(led_node); + priv->boot_led_label = led_get_label(NULL, led_node); priv->boot_led_period = ofnode_options_read_int("boot-led-period-ms", 250); #endif #ifdef CONFIG_LED_ACTIVITY ret = ofnode_options_get_by_phandle("activity-led", &led_node); if (!ret) - priv->activity_led_label = led_get_label(led_node); + priv->activity_led_label = led_get_label(NULL, led_node); priv->activity_led_period = ofnode_options_read_int("activity-led-period-ms", 250); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index e1110cace89..a51494380ce 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -724,7 +724,7 @@ static int dwmci_init(struct mmc *mmc) return 0; } -#ifdef CONFIG_DM_MMC +#if CONFIG_IS_ENABLED(DM_MMC) int dwmci_probe(struct udevice *dev) { struct mmc *mmc = mmc_get_mmc_dev(dev); @@ -749,7 +749,7 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, u32 max_clk, u32 min_clk) { cfg->name = host->name; -#ifndef CONFIG_DM_MMC +#if !CONFIG_IS_ENABLED(DM_MMC) cfg->ops = &dwmci_ops; #endif cfg->f_min = min_clk; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 799586891af..31a72366206 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2376,7 +2376,7 @@ static int mmc_startup_v4(struct mmc *mmc) | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; capacity *= MMC_MAX_BLOCK_LEN; - if ((capacity >> 20) > 2 * 1024) + if (mmc->high_capacity) mmc->capacity_user = capacity; } diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 88094b81e7a..3f8edeb5093 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -208,7 +208,7 @@ int mtd_parse_partitions(struct mtd_info *parent, const char **_mtdparts, { struct mtd_partition partition = {}, *parts; const char *mtdparts = *_mtdparts; - uint64_t cur_off = 0, cur_sz = 0; + uint64_t cur_off = 0; int nparts = 0; int ret, idx; u64 sz; @@ -237,8 +237,7 @@ int mtd_parse_partitions(struct mtd_info *parent, const char **_mtdparts, return ret; if (parts[idx].size == MTD_SIZE_REMAINING) - parts[idx].size = parent->size - cur_sz; - cur_sz += parts[idx].size; + parts[idx].size = parent->size - parts[idx].offset; sz = parts[idx].size; if (sz < parent->writesize || do_div(sz, parent->writesize)) { diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index 56fbd64ef68..c90a4eab8df 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1127,7 +1127,7 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, const struct nand_data_interface *conf, struct atmel_smc_cs_conf *smcconf) { - u32 ncycles, totalcycles, timeps, mckperiodps; + u32 ncycles, totalcycles, timeps, mckperiodps, pulse; struct atmel_nand_controller *nc; int ret; @@ -1253,11 +1253,16 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, ATMEL_SMC_MODE_TDFMODE_OPTIMIZED; /* - * Read pulse timing directly matches tRP: + * Read pulse timing would directly match tRP, + * but some NAND flash chips (S34ML01G2 and W29N02KVxxAF) + * do not work properly in timing mode 3. + * The workaround is to extend the SMC NRD pulse to meet tREA + * timing. * - * NRD_PULSE = tRP + * NRD_PULSE = max(tRP, tREA) */ - ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); + pulse = max(conf->timings.sdr.tRP_min, conf->timings.sdr.tREA_max); + ncycles = DIV_ROUND_UP(pulse, mckperiodps); totalcycles += ncycles; ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT, ncycles); diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 94d8f1b4c04..5a6e89c0575 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -33,6 +33,9 @@ #include <linux/printk.h> #include <power/regulator.h> #include "designware.h" +#if IS_ENABLED(CONFIG_ARCH_NPCM8XX) +#include <asm/arch/gmac.h> +#endif static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { @@ -223,6 +226,124 @@ static int dw_dm_mdio_init(const char *name, void *priv) } #endif +#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) +static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + struct gpio_desc *desc = &priv->mdio_gpio; + + desc->flags = 0; + dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + return 0; +} + +static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + struct gpio_desc *desc = &priv->mdio_gpio; + + desc->flags = 0; + dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN); + + return 0; +} + +static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct dw_eth_dev *priv = bus->priv; + + if (v) + dm_gpio_set_value(&priv->mdio_gpio, 1); + else + dm_gpio_set_value(&priv->mdio_gpio, 0); + + return 0; +} + +static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct dw_eth_dev *priv = bus->priv; + + *v = dm_gpio_get_value(&priv->mdio_gpio); + + return 0; +} + +static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct dw_eth_dev *priv = bus->priv; + + if (v) + dm_gpio_set_value(&priv->mdc_gpio, 1); + else + dm_gpio_set_value(&priv->mdc_gpio, 0); + + return 0; +} + +static int dw_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + + udelay(priv->bb_delay); + return 0; +} + +static int dw_bb_mdio_init(const char *name, struct udevice *dev) +{ + struct dw_eth_dev *dwpriv = dev_get_priv(dev); + struct bb_miiphy_bus *bb_miiphy = bb_miiphy_alloc(); + struct mii_dev *bus; + int ret; + + if (!bb_miiphy) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus = &bb_miiphy->mii; + + debug("\n%s: use bitbang mii..\n", dev->name); + ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0, + &dwpriv->mdc_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + debug("no mdc-gpio\n"); + return ret; + } + ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0, + &dwpriv->mdio_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + debug("no mdio-gpio\n"); + return ret; + } + dwpriv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1); + + dwpriv->bus = bus; + dwpriv->dev = dev; + + snprintf(bus->name, sizeof(bus->name), "%s", name); + bus->read = bb_miiphy_read; + bus->write = bb_miiphy_write; +#if CONFIG_IS_ENABLED(DM_GPIO) + bus->reset = dw_mdio_reset; +#endif + bus->priv = dwpriv; + + /* Copy the bus accessors and private data */ + bb_miiphy->mdio_active = dw_eth_bb_mdio_active; + bb_miiphy->mdio_tristate = dw_eth_bb_mdio_tristate; + bb_miiphy->set_mdio = dw_eth_bb_set_mdio; + bb_miiphy->get_mdio = dw_eth_bb_get_mdio; + bb_miiphy->set_mdc = dw_eth_bb_set_mdc; + bb_miiphy->delay = dw_eth_bb_delay; + + return mdio_register(bus); +} +#endif + static void tx_descs_init(struct dw_eth_dev *priv) { struct eth_dma_regs *dma_p = priv->dma_regs_p; @@ -352,10 +473,35 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); #ifdef CONFIG_ARCH_NPCM8XX + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + unsigned int start; + + /* Indirect access to VR_MII_MMD registers */ + writew((VR_MII_MMD >> 9), PCS_BA + PCS_IND_AC); + /* Set PCS_Mode to SGMII */ + clrsetbits_le16(PCS_BA + VR_MII_MMD_AN_CTRL, BIT(1), BIT(2)); + /* Set Auto Speed Mode Change */ + setbits_le16(PCS_BA + VR_MII_MMD_CTRL1, BIT(9)); + /* Indirect access to SR_MII_MMD registers */ + writew((SR_MII_MMD >> 9), PCS_BA + PCS_IND_AC); + /* Restart Auto-Negotiation */ + setbits_le16(PCS_BA + SR_MII_MMD_CTRL, BIT(9) | BIT(12)); + + printf("SGMII PHY Wait for link up \n"); + /* SGMII PHY Wait for link up */ + start = get_timer(0); + while (!(readw(PCS_BA + SR_MII_MMD_STS) & BIT(2))) { + if (get_timer(start) >= LINK_UP_TIMEOUT) { + printf("PHY link up timeout\n"); + return -ETIMEDOUT; + } + mdelay(1); + }; + } /* Pass all Multicast Frames */ setbits_le32(&mac_p->framefilt, BIT(4)); - #endif + return 0; } @@ -694,6 +840,7 @@ int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct dw_eth_dev *priv = dev_get_priv(dev); + bool __maybe_unused bbmiiphy = false; phys_addr_t iobase = pdata->iobase; void *ioaddr; int ret, err; @@ -741,6 +888,18 @@ int designware_eth_probe(struct udevice *dev) puts("Error enabling phy supply\n"); return ret; } +#if IS_ENABLED(CONFIG_ARCH_NPCM8XX) + int phy_uv; + + phy_uv = dev_read_u32_default(dev, "phy-supply-microvolt", 0); + if (phy_uv) { + ret = regulator_set_value(phy_supply, phy_uv); + if (ret) { + puts("Error setting phy voltage\n"); + return ret; + } + } +#endif } #endif @@ -772,51 +931,30 @@ int designware_eth_probe(struct udevice *dev) priv->interface = pdata->phy_interface; priv->max_speed = pdata->max_speed; -#if IS_ENABLED(CONFIG_DM_MDIO) - ret = dw_dm_mdio_init(dev->name, dev); -#else - ret = dw_mdio_init(dev->name, dev); -#endif - if (ret) { - err = ret; - goto mdio_err; - } - priv->bus = miiphy_get_dev_by_name(dev->name); - priv->dev = dev; - #if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) - if (dev_read_bool(dev, "snps,bitbang-mii")) { - int bus_idx; - - debug("\n%s: use bitbang mii..\n", dev->name); - ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0, - &priv->mdc_gpio, GPIOD_IS_OUT - | GPIOD_IS_OUT_ACTIVE); + bbmiiphy = dev_read_bool(dev, "snps,bitbang-mii"); + if (bbmiiphy) { + ret = dw_bb_mdio_init(dev->name, dev); if (ret) { - debug("no mdc-gpio\n"); - return ret; + err = ret; + goto mdio_err; } - ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0, - &priv->mdio_gpio, GPIOD_IS_OUT - | GPIOD_IS_OUT_ACTIVE); + } else +#endif + { +#if IS_ENABLED(CONFIG_DM_MDIO) + ret = dw_dm_mdio_init(dev->name, dev); +#else + ret = dw_mdio_init(dev->name, dev); +#endif if (ret) { - debug("no mdio-gpio\n"); - return ret; - } - priv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1); - - for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; bus_idx++) { - if (!bb_miiphy_buses[bus_idx].priv) { - bb_miiphy_buses[bus_idx].priv = priv; - strlcpy(bb_miiphy_buses[bus_idx].name, priv->bus->name, - MDIO_NAME_LEN); - priv->bus->read = bb_miiphy_read; - priv->bus->write = bb_miiphy_write; - break; - } + err = ret; + goto mdio_err; } + priv->bus = miiphy_get_dev_by_name(dev->name); + priv->dev = dev; } -#endif + ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); if (!ret) @@ -825,7 +963,12 @@ int designware_eth_probe(struct udevice *dev) /* continue here for cleanup if no PHY found */ err = ret; mdio_unregister(priv->bus); - mdio_free(priv->bus); +#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) + if (bbmiiphy) + bb_miiphy_free(container_of(priv->bus, struct bb_miiphy_bus, mii)); + else +#endif + mdio_free(priv->bus); mdio_err: #ifdef CONFIG_CLK @@ -927,83 +1070,3 @@ static struct pci_device_id supported[] = { }; U_BOOT_PCI_DEVICE(eth_designware, supported); - -#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO) -static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus) -{ - struct dw_eth_dev *priv = bus->priv; - struct gpio_desc *desc = &priv->mdio_gpio; - - desc->flags = 0; - dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); - - return 0; -} - -static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct dw_eth_dev *priv = bus->priv; - struct gpio_desc *desc = &priv->mdio_gpio; - - desc->flags = 0; - dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN); - - return 0; -} - -static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct dw_eth_dev *priv = bus->priv; - - if (v) - dm_gpio_set_value(&priv->mdio_gpio, 1); - else - dm_gpio_set_value(&priv->mdio_gpio, 0); - - return 0; -} - -static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - struct dw_eth_dev *priv = bus->priv; - - *v = dm_gpio_get_value(&priv->mdio_gpio); - - return 0; -} - -static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct dw_eth_dev *priv = bus->priv; - - if (v) - dm_gpio_set_value(&priv->mdc_gpio, 1); - else - dm_gpio_set_value(&priv->mdc_gpio, 0); - - return 0; -} - -static int dw_eth_bb_delay(struct bb_miiphy_bus *bus) -{ - struct dw_eth_dev *priv = bus->priv; - - udelay(priv->bb_delay); - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = BB_MII_DEVNAME, - .mdio_active = dw_eth_bb_mdio_active, - .mdio_tristate = dw_eth_bb_mdio_tristate, - .set_mdio = dw_eth_bb_set_mdio, - .get_mdio = dw_eth_bb_get_mdio, - .set_mdc = dw_eth_bb_set_mdc, - .delay = dw_eth_bb_delay, - .priv = NULL, - } -}; - -int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); -#endif diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index 9fc8c686b88..f3a0f63003e 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -46,6 +46,10 @@ struct rockchip_platform_data { #define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16)) #define GRF_CLR_BIT(nr) (BIT((nr) + 16)) +#define DELAY_ENABLE(soc, tx, rx) \ + (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ + ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) + #define RK3568_GRF_GMAC0_CON0 0x0380 #define RK3568_GRF_GMAC0_CON1 0x0384 #define RK3568_GRF_GMAC1_CON0 0x0388 @@ -85,8 +89,7 @@ static int rk3568_set_to_rgmii(struct udevice *dev, regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RGMII | - RK3568_GMAC_RXCLK_DLY_ENABLE | - RK3568_GMAC_TXCLK_DLY_ENABLE); + DELAY_ENABLE(RK3568, tx_delay, rx_delay)); return 0; } @@ -131,6 +134,10 @@ static int rk3568_set_gmac_speed(struct udevice *dev) return 0; } +#define RK3588_DELAY_ENABLE(id, tx, rx) \ + (((tx) ? RK3588_GMAC_TXCLK_DLY_ENABLE(id) : RK3588_GMAC_TXCLK_DLY_DISABLE(id)) | \ + ((rx) ? RK3588_GMAC_RXCLK_DLY_ENABLE(id) : RK3588_GMAC_RXCLK_DLY_DISABLE(id))) + /* sys_grf */ #define RK3588_GRF_GMAC_CON7 0x031c #define RK3588_GRF_GMAC_CON8 0x0320 @@ -189,8 +196,7 @@ static int rk3588_set_to_rgmii(struct udevice *dev, RK3588_GMAC_CLK_RGMII_MODE(id)); regmap_write(data->grf, RK3588_GRF_GMAC_CON7, - RK3588_GMAC_RXCLK_DLY_ENABLE(id) | - RK3588_GMAC_TXCLK_DLY_ENABLE(id)); + RK3588_DELAY_ENABLE(id, tx_delay, rx_delay)); regmap_write(data->grf, offset_con, RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index 171c1719b5b..553af2c1032 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -14,31 +14,31 @@ #include <ioports.h> #include <ppc_asm.tmpl> +#include <malloc.h> #include <miiphy.h> #include <asm/global_data.h> -int bb_miiphy_init(void) +static inline struct bb_miiphy_bus *bb_miiphy_getbus(struct mii_dev *miidev) { - int i; + return container_of(miidev, struct bb_miiphy_bus, mii); +} - for (i = 0; i < bb_miiphy_buses_num; i++) - if (bb_miiphy_buses[i].init != NULL) - bb_miiphy_buses[i].init(&bb_miiphy_buses[i]); +struct bb_miiphy_bus *bb_miiphy_alloc(void) +{ + struct bb_miiphy_bus *bus; - return 0; + bus = malloc(sizeof(*bus)); + if (!bus) + return bus; + + mdio_init(&bus->mii); + + return bus; } -static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname) +void bb_miiphy_free(struct bb_miiphy_bus *bus) { - int i; - - /* Search the correct bus */ - for (i = 0; i < bb_miiphy_buses_num; i++) { - if (!strcmp(bb_miiphy_buses[i].name, devname)) { - return &bb_miiphy_buses[i]; - } - } - return NULL; + free(bus); } /***************************************************************************** @@ -133,7 +133,7 @@ int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg) int j; /* counter */ struct bb_miiphy_bus *bus; - bus = bb_miiphy_getbus(miidev->name); + bus = bb_miiphy_getbus(miidev); if (bus == NULL) { return -1; } @@ -183,9 +183,7 @@ int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg) bus->set_mdc(bus, 1); bus->delay(bus); -#ifdef DEBUG - printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg); -#endif + debug("%s[%s](0x%x) @ 0x%x = 0x%04x\n", __func__, miidev->name, reg, addr, rdreg); return rdreg; } @@ -203,7 +201,7 @@ int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, struct bb_miiphy_bus *bus; int j; /* counter */ - bus = bb_miiphy_getbus(miidev->name); + bus = bb_miiphy_getbus(miidev); if (bus == NULL) { /* Bus not found! */ return -1; diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 7286ad19598..cb727ae9bc1 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -490,10 +490,70 @@ static void ravb_stop(struct udevice *dev) ravb_reset(dev); } +/* Bitbang MDIO access */ +static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct ravb_priv *eth = bus->priv; + + setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD); + + return 0; +} + +static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct ravb_priv *eth = bus->priv; + + clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD); + + return 0; +} + +static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct ravb_priv *eth = bus->priv; + + if (v) + setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO); + else + clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO); + + return 0; +} + +static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct ravb_priv *eth = bus->priv; + + *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3; + + return 0; +} + +static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct ravb_priv *eth = bus->priv; + + if (v) + setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC); + else + clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC); + + return 0; +} + +static int ravb_bb_delay(struct bb_miiphy_bus *bus) +{ + udelay(10); + + return 0; +} + static int ravb_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct ravb_priv *eth = dev_get_priv(dev); + struct bb_miiphy_bus *bb_miiphy; struct mii_dev *mdiodev; void __iomem *iobase; int ret; @@ -505,22 +565,32 @@ static int ravb_probe(struct udevice *dev) if (ret < 0) goto err_mdio_alloc; - mdiodev = mdio_alloc(); - if (!mdiodev) { + bb_miiphy = bb_miiphy_alloc(); + if (!bb_miiphy) { ret = -ENOMEM; goto err_mdio_alloc; } + mdiodev = &bb_miiphy->mii; + mdiodev->read = bb_miiphy_read; mdiodev->write = bb_miiphy_write; - bb_miiphy_buses[0].priv = eth; snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name); + /* Copy the bus accessors and private data */ + bb_miiphy->mdio_active = ravb_bb_mdio_active; + bb_miiphy->mdio_tristate = ravb_bb_mdio_tristate; + bb_miiphy->set_mdio = ravb_bb_set_mdio; + bb_miiphy->get_mdio = ravb_bb_get_mdio; + bb_miiphy->set_mdc = ravb_bb_set_mdc; + bb_miiphy->delay = ravb_bb_delay; + bb_miiphy->priv = eth; + ret = mdio_register(mdiodev); if (ret < 0) goto err_mdio_register; - eth->bus = miiphy_get_dev_by_name(dev->name); + eth->bus = &bb_miiphy->mii; /* Bring up PHY */ ret = clk_enable_bulk(ð->clks); @@ -540,7 +610,7 @@ static int ravb_probe(struct udevice *dev) err_mdio_reset: clk_release_bulk(ð->clks); err_mdio_register: - mdio_free(mdiodev); + bb_miiphy_free(bb_miiphy); err_mdio_alloc: unmap_physmem(eth->iobase, MAP_NOCACHE); return ret; @@ -560,83 +630,6 @@ static int ravb_remove(struct udevice *dev) return 0; } -static int ravb_bb_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) -{ - struct ravb_priv *eth = bus->priv; - - setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD); - - return 0; -} - -static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct ravb_priv *eth = bus->priv; - - clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD); - - return 0; -} - -static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct ravb_priv *eth = bus->priv; - - if (v) - setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO); - else - clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO); - - return 0; -} - -static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - struct ravb_priv *eth = bus->priv; - - *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3; - - return 0; -} - -static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct ravb_priv *eth = bus->priv; - - if (v) - setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC); - else - clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC); - - return 0; -} - -static int ravb_bb_delay(struct bb_miiphy_bus *bus) -{ - udelay(10); - - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = "ravb", - .init = ravb_bb_init, - .mdio_active = ravb_bb_mdio_active, - .mdio_tristate = ravb_bb_mdio_tristate, - .set_mdio = ravb_bb_set_mdio, - .get_mdio = ravb_bb_get_mdio, - .set_mdc = ravb_bb_set_mdc, - .delay = ravb_bb_delay, - }, -}; -int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); - static const struct eth_ops ravb_ops = { .start = ravb_start, .send = ravb_send, @@ -658,8 +651,6 @@ int ravb_of_to_plat(struct udevice *dev) pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000); - sprintf(bb_miiphy_buses[0].name, dev->name); - return 0; } diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index f1ce994cfd5..83e48609224 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -643,11 +643,80 @@ static void sh_ether_stop(struct udevice *dev) sh_eth_stop(&priv->shdev); } +/******* for bb_miiphy *******/ +static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct sh_eth_dev *eth = bus->priv; + struct sh_eth_info *port_info = ð->port_info[eth->port]; + + sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR); + + return 0; +} + +static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct sh_eth_dev *eth = bus->priv; + struct sh_eth_info *port_info = ð->port_info[eth->port]; + + sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR); + + return 0; +} + +static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + struct sh_eth_info *port_info = ð->port_info[eth->port]; + + if (v) + sh_eth_write(port_info, + sh_eth_read(port_info, PIR) | PIR_MDO, PIR); + else + sh_eth_write(port_info, + sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR); + + return 0; +} + +static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct sh_eth_dev *eth = bus->priv; + struct sh_eth_info *port_info = ð->port_info[eth->port]; + + *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3; + + return 0; +} + +static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + struct sh_eth_info *port_info = ð->port_info[eth->port]; + + if (v) + sh_eth_write(port_info, + sh_eth_read(port_info, PIR) | PIR_MDC, PIR); + else + sh_eth_write(port_info, + sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR); + + return 0; +} + +static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + udelay(10); + + return 0; +} + static int sh_ether_probe(struct udevice *udev) { struct eth_pdata *pdata = dev_get_plat(udev); struct sh_ether_priv *priv = dev_get_priv(udev); struct sh_eth_dev *eth = &priv->shdev; + struct bb_miiphy_bus *bb_miiphy; struct mii_dev *mdiodev; int ret; @@ -658,22 +727,32 @@ static int sh_ether_probe(struct udevice *udev) if (ret < 0) return ret; #endif - mdiodev = mdio_alloc(); - if (!mdiodev) { + bb_miiphy = bb_miiphy_alloc(); + if (!bb_miiphy) { ret = -ENOMEM; return ret; } + mdiodev = &bb_miiphy->mii; + mdiodev->read = bb_miiphy_read; mdiodev->write = bb_miiphy_write; - bb_miiphy_buses[0].priv = eth; snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name); + /* Copy the bus accessors and private data */ + bb_miiphy->mdio_active = sh_eth_bb_mdio_active; + bb_miiphy->mdio_tristate = sh_eth_bb_mdio_tristate; + bb_miiphy->set_mdio = sh_eth_bb_set_mdio; + bb_miiphy->get_mdio = sh_eth_bb_get_mdio; + bb_miiphy->set_mdc = sh_eth_bb_set_mdc; + bb_miiphy->delay = sh_eth_bb_delay; + bb_miiphy->priv = eth; + ret = mdio_register(mdiodev); if (ret < 0) goto err_mdio_register; - priv->bus = miiphy_get_dev_by_name(udev->name); + priv->bus = &bb_miiphy->mii; eth->port = CFG_SH_ETHER_USE_PORT; eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR; @@ -703,7 +782,7 @@ err_phy_config: clk_disable(&priv->clk); #endif err_mdio_register: - mdio_free(mdiodev); + bb_miiphy_free(bb_miiphy); return ret; } @@ -748,8 +827,6 @@ int sh_ether_of_to_plat(struct udevice *dev) if (cell) pdata->max_speed = fdt32_to_cpu(*cell); - sprintf(bb_miiphy_buses[0].name, dev->name); - return 0; } @@ -775,91 +852,3 @@ U_BOOT_DRIVER(eth_sh_ether) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; - -/******* for bb_miiphy *******/ -static int sh_eth_bb_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) -{ - struct sh_eth_dev *eth = bus->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; - - sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR); - - return 0; -} - -static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct sh_eth_dev *eth = bus->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; - - sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR); - - return 0; -} - -static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct sh_eth_dev *eth = bus->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; - - if (v) - sh_eth_write(port_info, - sh_eth_read(port_info, PIR) | PIR_MDO, PIR); - else - sh_eth_write(port_info, - sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR); - - return 0; -} - -static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - struct sh_eth_dev *eth = bus->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; - - *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3; - - return 0; -} - -static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct sh_eth_dev *eth = bus->priv; - struct sh_eth_info *port_info = ð->port_info[eth->port]; - - if (v) - sh_eth_write(port_info, - sh_eth_read(port_info, PIR) | PIR_MDC, PIR); - else - sh_eth_write(port_info, - sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR); - - return 0; -} - -static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) -{ - udelay(10); - - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = "sh_eth", - .init = sh_eth_bb_init, - .mdio_active = sh_eth_bb_mdio_active, - .mdio_tristate = sh_eth_bb_mdio_tristate, - .set_mdio = sh_eth_bb_set_mdio, - .get_mdio = sh_eth_bb_get_mdio, - .set_mdc = sh_eth_bb_set_mdc, - .delay = sh_eth_bb_delay, - } -}; - -int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 84c3996c542..6b9769067b0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -1051,8 +1051,9 @@ static const struct mtk_function_desc mt7981_functions[] = { }; static const char *const mt7981_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_rt_base", "iocfg_rm_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_bl_base", "iocfg_tm_base", "iocfg_tl_base", + "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", + "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", + "eint", }; static const struct mtk_pinctrl_soc mt7981_data = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/drivers/pinctrl/mediatek/pinctrl-mt7988.c index 1f384e86f4e..639e2415c63 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -1233,8 +1233,7 @@ static const struct mtk_function_desc mt7988_functions[] = { }; static const char *const mt7988_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_tl_base", + "gpio", "iocfg_tr", "iocfg_br", "iocfg_rb", "iocfg_lb", "iocfg_tl", }; static const struct mtk_pinctrl_soc mt7988_data = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 3760c4611ce..4aecb84504a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -816,7 +816,11 @@ int mtk_pinctrl_common_probe(struct udevice *dev, nbase_names = 1; for (i = 0; i < nbase_names; i++) { - addr = devfdt_get_addr_index(dev, i); + if (soc->base_names) + addr = dev_read_addr_name(dev, soc->base_names[i]); + else + addr = dev_read_addr_index(dev, i); + if (addr == FDT_ADDR_T_NONE) return -EINVAL; priv->base[i] = (void __iomem *)addr; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 5038cb535e3..2938635ed95 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -9,6 +9,8 @@ #include <dm.h> #include <log.h> #include <asm/global_data.h> +#include <dm/device-internal.h> +#include <dm/lists.h> #include <dm/pinctrl.h> #include <asm/hardware.h> #include <linux/bitops.h> @@ -492,21 +494,58 @@ const struct pinctrl_ops at91_pinctrl_ops = { .set_state = at91_pinctrl_set_state, }; +/** + * at91_pinctrl_bind() - Iterates through all subnodes of the pinctrl device + * in the DT and binds them to U-Boot's device model. Each subnode + * typically represents a GPIO controller or pin configuration data. + * + * @dev: Pointer to the pinctrl device + * + * Returns 0 on success or negative error on failure + */ +static int at91_pinctrl_bind(struct udevice *dev) +{ + ofnode gpio_node; + struct udevice *gpio; + int ret; + + ofnode_for_each_subnode(gpio_node, dev_ofnode(dev)) { + ret = lists_bind_fdt(dev, gpio_node, &gpio, NULL, false); + if (ret) + return ret; + } + + return 0; +} + static int at91_pinctrl_probe(struct udevice *dev) { struct at91_pinctrl_priv *priv = dev_get_priv(dev); fdt_addr_t addr_base; + struct udevice *gpio_node; int index; - for (index = 0; index < MAX_GPIO_BANKS; index++) { - addr_base = devfdt_get_addr_index(dev, index); - if (addr_base == FDT_ADDR_T_NONE) - break; + if (list_empty(&dev->child_head)) { + for (index = 0; index < MAX_GPIO_BANKS; index++) { + addr_base = devfdt_get_addr_index(dev, index); + if (addr_base == FDT_ADDR_T_NONE) + break; - priv->reg_base[index] = (struct at91_port *)addr_base; + priv->reg_base[index] = (struct at91_port *)addr_base; + } + } else { + index = 0; + list_for_each_entry(gpio_node, &dev->child_head, sibling_node) { + addr_base = dev_read_addr(gpio_node); + if (addr_base == FDT_ADDR_T_NONE) + break; + + priv->reg_base[index] = (struct at91_port *)addr_base; + index++; + } } - priv->nbanks = index; + priv->nbanks = index < MAX_GPIO_BANKS ? index : MAX_GPIO_BANKS; return 0; } @@ -524,6 +563,7 @@ U_BOOT_DRIVER(atmel_sama5d3_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = at91_pinctrl_match, .probe = at91_pinctrl_probe, + .bind = at91_pinctrl_bind, .priv_auto = sizeof(struct at91_pinctrl_priv), .ops = &at91_pinctrl_ops, }; diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 47c2e923a1b..dd0dc2eff27 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -14,23 +14,68 @@ static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { - .num = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x3 - }, { + /* gpio2_b7_sel */ .num = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7 }, { + /* gpio2_c7_sel */ .num = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x3 + }, { + /* gpio3_b1_sel */ + .num = 3, + .pin = 9, + .reg = 0x44, + .bit = 2, + .mask = 0x3 + }, { + /* gpio3_b2_sel */ + .num = 3, + .pin = 10, + .reg = 0x44, + .bit = 4, + .mask = 0x3 + }, { + /* gpio3_b3_sel */ + .num = 3, + .pin = 11, + .reg = 0x44, + .bit = 6, + .mask = 0x3 + }, { + /* gpio3_b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x44, + .bit = 8, + .mask = 0x3 + }, { + /* gpio3_b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x44, + .bit = 10, + .mask = 0x3 + }, { + /* gpio3_b6_sel */ + .num = 3, + .pin = 14, + .reg = 0x44, + .bit = 12, + .mask = 0x3 + }, { + /* gpio3_b7_sel */ + .num = 3, + .pin = 15, + .reg = 0x44, + .bit = 14, + .mask = 0x3 }, }; @@ -275,7 +320,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT, + IOMUX_8WIDTH_2BIT, IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index d5171b8be23..d59b3ec7b5d 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -97,9 +97,9 @@ static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config) * then actual pins setup (with node name prefix * conf_*) and then drive setup. */ - if (!strncmp(child->name, "conf_", 5)) + if (!strncmp(child->name, "conf", 4)) tegra_pinctrl_set_pin(child); - else if (!strncmp(child->name, "drive_", 6)) + else if (!strncmp(child->name, "drive", 5)) debug("%s: drive configuration is not supported\n", __func__); else tegra_pinctrl_set_func(child); diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c index cf08b6a7e1d..c2a7cbf7e40 100644 --- a/drivers/power/pmic/max77663.c +++ b/drivers/power/pmic/max77663.c @@ -47,8 +47,9 @@ static int max77663_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) { - ret = device_bind_driver(dev, MAX77663_RST_DRIVER, - "sysreset", NULL); + ret = device_bind_driver_to_node(dev, MAX77663_RST_DRIVER, + "sysreset", dev_ofnode(dev), + NULL); if (ret) { log_err("cannot bind SYSRESET (ret = %d)\n", ret); return ret; @@ -56,8 +57,8 @@ static int max77663_bind(struct udevice *dev) } if (IS_ENABLED(CONFIG_MAX77663_GPIO)) { - ret = device_bind_driver(dev, MAX77663_GPIO_DRIVER, - "gpio", NULL); + ret = device_bind_driver_to_node(dev, MAX77663_GPIO_DRIVER, + "gpio", dev_ofnode(dev), NULL); if (ret) { log_err("cannot bind GPIOs (ret = %d)\n", ret); return ret; diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index f676bf64169..37d4190fabe 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -49,8 +49,9 @@ static int palmas_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) { - ret = device_bind_driver(dev, PALMAS_RST_DRIVER, - "sysreset", NULL); + ret = device_bind_driver_to_node(dev, PALMAS_RST_DRIVER, + "sysreset", dev_ofnode(dev), + NULL); if (ret) { log_err("cannot bind SYSRESET (ret = %d)\n", ret); return ret; diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c index bc4d153fd84..13f94b730d4 100644 --- a/drivers/power/regulator/tps65941_regulator.c +++ b/drivers/power/regulator/tps65941_regulator.c @@ -388,6 +388,14 @@ static int tps65941_ldo_enable(struct udevice *dev, int op, bool *enable) return 0; } +static int tps65941_ldo_volt2val(__maybe_unused int idx, int uV) +{ + if (uV > TPS65941_LDO_VOLT_MAX || uV < TPS65941_LDO_VOLT_MIN) + return -EINVAL; + + return ((uV - 600000) / 50000 + 0x4) << TPS65941_LDO_MODE_MASK; +} + static int tps65941_ldo_val2volt(__maybe_unused int idx, int val) { if (val > TPS65941_LDO_VOLT_MAX_HEX || val < TPS65941_LDO_VOLT_MIN_HEX) @@ -459,7 +467,7 @@ static int tps65224_ldo_val2volt(int idx, int val) static const struct tps65941_reg_conv_ops ldo_conv_ops[] = { [TPS65941_LDO_CONV_OPS_IDX] = { .volt_mask = TPS65941_LDO_VOLT_MASK, - .volt2val = tps65941_buck_volt2val, + .volt2val = tps65941_ldo_volt2val, .val2volt = tps65941_ldo_val2volt, }, [TPS65224_LDO_CONV_OPS_IDX] = { @@ -472,7 +480,7 @@ static const struct tps65941_reg_conv_ops ldo_conv_ops[] = { static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) { unsigned int hex, adr; - int ret, ret_volt, idx; + int ret, ret_volt, idx, ldo_bypass; struct dm_regulator_uclass_plat *uc_pdata; const struct tps65941_reg_conv_ops *conv_ops; ulong chip_id; @@ -502,7 +510,9 @@ static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) if (ret < 0) return ret; + ldo_bypass = ret & TPS65941_LDO_BYPASS_EN; ret &= conv_ops->volt_mask; + ret = ret >> TPS65941_LDO_MODE_MASK; ret_volt = conv_ops->val2volt(idx, ret); if (ret_volt < 0) return ret_volt; @@ -531,7 +541,7 @@ static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) ret &= ~TPS65224_LDO_VOLT_MASK; ret |= hex; } else { - ret = hex; + ret = hex | ldo_bypass; } ret = pmic_reg_write(dev->parent, adr, ret); diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 2790b168b19..3d2831a3e36 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -55,6 +55,7 @@ config REMOTEPROC_TI_K3_ARM64 depends on DM depends on ARCH_K3 depends on OF_CONTROL + default y if SYS_K3_SPL_ATF help Say y here to support TI's ARM64 processor subsystems on various TI K3 family of SoCs through the remote processor @@ -70,6 +71,16 @@ config REMOTEPROC_TI_K3_DSP on various TI K3 family of SoCs through the remote processor framework. +config REMOTEPROC_TI_K3_M4F + bool "TI K3 M4F remoteproc support" + select REMOTEPROC + depends on ARCH_K3 + depends on TI_SCI_PROTOCOL + help + Say y here to support TI's M4F remote processor subsystems + on various TI K3 family of SoCs through the remote processor + framework. + config REMOTEPROC_TI_K3_R5F bool "TI K3 R5F remoteproc support" select REMOTEPROC diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 3a092b7660e..f81e5009c5e 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o +obj-$(CONFIG_REMOTEPROC_TI_K3_M4F) += ti_k3_m4_rproc.o obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o diff --git a/drivers/remoteproc/renesas_apmu.c b/drivers/remoteproc/renesas_apmu.c index 32d138e6487..1a50cd3289b 100644 --- a/drivers/remoteproc/renesas_apmu.c +++ b/drivers/remoteproc/renesas_apmu.c @@ -68,6 +68,13 @@ static int renesas_apmu_rproc_load(struct udevice *dev, ulong addr, ulong size) flush_dcache_range(trampolineaddr, trampolineaddr + sizeof(renesas_apmu_rproc_trampoline)); + invalidate_dcache_range(trampolineaddr, + trampolineaddr + + sizeof(renesas_apmu_rproc_trampoline)); + flush_dcache_range(addr, addr + size); + invalidate_dcache_range(addr, addr + size); + asm volatile("dsb sy\n"); + asm volatile("isb sy\n"); /* CR52 boot address set */ writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP, diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index e90f75a188c..5a7d6377283 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -15,6 +15,7 @@ #include <clk.h> #include <reset.h> #include <asm/io.h> +#include <asm/system.h> #include <power-domain.h> #include <dm/device_compat.h> #include <linux/err.h> @@ -56,7 +57,9 @@ struct k3_dsp_boot_data { * @data: Pointer to DSP specific boot data structure * @mem: Array of available memories * @num_mem: Number of available memories - * @in_use: flag to tell if the core is already in use. + * @cached_addr: Cached memory address + * @cached_size: Cached memory size + * @in_use: flag to tell if the core is already in use. */ struct k3_dsp_privdata { struct reset_ctl dsp_rst; @@ -64,6 +67,8 @@ struct k3_dsp_privdata { struct k3_dsp_boot_data *data; struct k3_dsp_mem *mem; int num_mems; + void __iomem *cached_addr; + size_t cached_size; bool in_use; }; @@ -158,6 +163,13 @@ static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size) goto unprepare; } + if (dsp->cached_addr && IS_ENABLED(CONFIG_SYS_DISABLE_DCACHE_OPS)) { + dev_dbg(dev, "final flush 0x%lx to 0x%lx\n", + (ulong)dsp->cached_addr, dsp->cached_size); + __asm_invalidate_dcache_range((u64)dsp->cached_addr, + (u64)dsp->cached_addr + (u64)dsp->cached_size); + } + boot_vector = rproc_elf_get_boot_addr(dev, addr); if (boot_vector & (data->boot_align_addr - 1)) { ret = -EINVAL; @@ -253,7 +265,6 @@ static void *k3_dsp_da_to_va(struct udevice *dev, ulong da, ulong len) { struct k3_dsp_privdata *dsp = dev_get_priv(dev); phys_addr_t bus_addr, dev_addr; - void __iomem *va = NULL; size_t size; u32 offset; int i; @@ -263,6 +274,16 @@ static void *k3_dsp_da_to_va(struct udevice *dev, ulong da, ulong len) if (len <= 0) return NULL; + if (dsp->cached_addr && IS_ENABLED(CONFIG_SYS_DISABLE_DCACHE_OPS)) { + dev_dbg(dev, "flush 0x%lx to 0x%lx\n", (ulong)dsp->cached_addr, + dsp->cached_size); + __asm_invalidate_dcache_range((u64)dsp->cached_addr, + (u64)dsp->cached_addr + (u64)dsp->cached_size); + } + + dsp->cached_size = len; + dsp->cached_addr = NULL; + for (i = 0; i < dsp->num_mems; i++) { bus_addr = dsp->mem[i].bus_addr; dev_addr = dsp->mem[i].dev_addr; @@ -270,19 +291,20 @@ static void *k3_dsp_da_to_va(struct udevice *dev, ulong da, ulong len) if (da >= dev_addr && ((da + len) <= (dev_addr + size))) { offset = da - dev_addr; - va = dsp->mem[i].cpu_addr + offset; - return (__force void *)va; + dsp->cached_addr = dsp->mem[i].cpu_addr + offset; } if (da >= bus_addr && (da + len) <= (bus_addr + size)) { offset = da - bus_addr; - va = dsp->mem[i].cpu_addr + offset; - return (__force void *)va; + dsp->cached_addr = dsp->mem[i].cpu_addr + offset; } } /* Assume it is DDR region and return da */ - return map_physmem(da, len, MAP_NOCACHE); + if (!dsp->cached_addr) + dsp->cached_addr = map_physmem(da, len, MAP_NOCACHE); + + return dsp->cached_addr; } static const struct dm_rproc_ops k3_dsp_ops = { diff --git a/drivers/remoteproc/ti_k3_m4_rproc.c b/drivers/remoteproc/ti_k3_m4_rproc.c new file mode 100644 index 00000000000..31b9de71579 --- /dev/null +++ b/drivers/remoteproc/ti_k3_m4_rproc.c @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' K3 M4 Remoteproc driver + * + * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ + * Hari Nagalla <hnagalla@ti.com> + */ + +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <remoteproc.h> +#include <errno.h> +#include <clk.h> +#include <reset.h> +#include <asm/io.h> +#include <power-domain.h> +#include <dm/device_compat.h> +#include <linux/err.h> +#include <linux/sizes.h> +#include <linux/soc/ti/ti_sci_protocol.h> +#include "ti_sci_proc.h" +#include <mach/security.h> + +/** + * struct k3_m4_mem - internal memory structure + * @cpu_addr: MPU virtual address of the memory region + * @bus_addr: Bus address used to access the memory region + * @dev_addr: Device address from remoteproc view + * @size: Size of the memory region + */ +struct k3_m4_mem { + void __iomem *cpu_addr; + phys_addr_t bus_addr; + phys_addr_t dev_addr; + size_t size; +}; + +/** + * struct k3_m4_mem_data - memory definitions for m4 remote core + * @name: name for this memory entry + * @dev_addr: device address for the memory entry + */ +struct k3_m4_mem_data { + const char *name; + const u32 dev_addr; +}; + +/** + * struct k3_m4_boot_data - internal data structure used for boot + * @boot_align_addr: Boot vector address alignment granularity + */ +struct k3_m4_boot_data { + u32 boot_align_addr; +}; + +/** + * struct k3_m4_privdata - Structure representing Remote processor data. + * @m4_rst: m4 rproc reset control data + * @tsp: Pointer to TISCI proc contrl handle + * @data: Pointer to DSP specific boot data structure + * @mem: Array of available memories + * @num_mem: Number of available memories + */ +struct k3_m4_privdata { + struct reset_ctl m4_rst; + struct ti_sci_proc tsp; + struct k3_m4_boot_data *data; + struct k3_m4_mem *mem; + int num_mems; +}; + +/* + * The M4 cores have a local reset that affects only the CPU, and a + * generic module reset that powers on the device and allows the M4 internal + * memories to be accessed while the local reset is asserted. This function is + * used to release the global reset on M4F to allow loading into the M4F + * internal RAMs. This helper function is invoked in k3_m4_load() before any + * actual firmware loading happens and is undone only in k3_m4_stop(). The local + * reset cannot be released on M4 cores until after the firmware images are loaded. + */ +static int k3_m4_prepare(struct udevice *dev) +{ + struct k3_m4_privdata *m4 = dev_get_priv(dev); + int ret; + + ret = ti_sci_proc_power_domain_on(&m4->tsp); + if (ret) + dev_err(dev, "cannot enable internal RAM loading, ret = %d\n", + ret); + + return ret; +} + +/* + * This function is the counterpart to k3_m4_prepare() and is used to assert + * the global reset on M4 cores. This completes the second step of powering + * down the M4 cores. The cores themselves are halted through the local reset + * in first step. This function is invoked in k3_m4_stop() after the local + * reset is asserted. + */ +static int k3_m4_unprepare(struct udevice *dev) +{ + struct k3_m4_privdata *m4 = dev_get_priv(dev); + + return ti_sci_proc_power_domain_off(&m4->tsp); +} + +/** + * k3_m4_load() - Load up the Remote processor image + * @dev: rproc device pointer + * @addr: Address at which image is available + * @size: size of the image + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int k3_m4_load(struct udevice *dev, ulong addr, ulong size) +{ + struct k3_m4_privdata *m4 = dev_get_priv(dev); + void *image_addr = (void *)addr; + int ret; + + ret = ti_sci_proc_request(&m4->tsp); + if (ret) + return ret; + + ret = k3_m4_prepare(dev); + if (ret) { + dev_err(dev, "Prepare failed for core %d\n", + m4->tsp.proc_id); + goto proc_release; + } + + ti_secure_image_post_process(&image_addr, &size); + + ret = rproc_elf_load_image(dev, addr, size); + if (ret < 0) { + dev_err(dev, "Loading elf failed %d\n", ret); + goto unprepare; + } + +unprepare: + if (ret) + k3_m4_unprepare(dev); +proc_release: + ti_sci_proc_release(&m4->tsp); + return ret; +} + +/** + * k3_m4_start() - Start the remote processor + * @dev: rproc device pointer + * + * Return: 0 if all went ok, else return appropriate error + */ +static int k3_m4_start(struct udevice *dev) +{ + struct k3_m4_privdata *m4 = dev_get_priv(dev); + int ret; + + ret = ti_sci_proc_request(&m4->tsp); + if (ret) + return ret; + + ret = reset_deassert(&m4->m4_rst); + + ti_sci_proc_release(&m4->tsp); + + return ret; +} + +static int k3_m4_stop(struct udevice *dev) +{ + struct k3_m4_privdata *m4 = dev_get_priv(dev); + + ti_sci_proc_request(&m4->tsp); + reset_assert(&m4->m4_rst); + k3_m4_unprepare(dev); + ti_sci_proc_release(&m4->tsp); + + return 0; +} + +static void *k3_m4_da_to_va(struct udevice *dev, ulong da, ulong len) +{ + struct k3_m4_privdata *m4 = dev_get_priv(dev); + phys_addr_t bus_addr, dev_addr; + void __iomem *va = NULL; + size_t size; + u32 offset; + int i; + + if (len <= 0) + return NULL; + + for (i = 0; i < m4->num_mems; i++) { + bus_addr = m4->mem[i].bus_addr; + dev_addr = m4->mem[i].dev_addr; + size = m4->mem[i].size; + + if (da >= dev_addr && ((da + len) <= (dev_addr + size))) { + offset = da - dev_addr; + va = m4->mem[i].cpu_addr + offset; + return (__force void *)va; + } + + if (da >= bus_addr && (da + len) <= (bus_addr + size)) { + offset = da - bus_addr; + va = m4->mem[i].cpu_addr + offset; + return (__force void *)va; + } + } + + /* Assume it is DDR region and return da */ + return map_physmem(da, len, MAP_NOCACHE); +} + +static const struct dm_rproc_ops k3_m4_ops = { + .load = k3_m4_load, + .start = k3_m4_start, + .stop = k3_m4_stop, + .device_to_virt = k3_m4_da_to_va, +}; + +static int ti_sci_proc_of_to_priv(struct udevice *dev, struct ti_sci_proc *tsp) +{ + u32 ids[2]; + int ret; + + tsp->sci = ti_sci_get_by_phandle(dev, "ti,sci"); + if (IS_ERR(tsp->sci)) { + dev_err(dev, "ti_sci get failed: %ld\n", PTR_ERR(tsp->sci)); + return PTR_ERR(tsp->sci); + } + + ret = dev_read_u32_array(dev, "ti,sci-proc-ids", ids, 2); + if (ret) { + dev_err(dev, "Proc IDs not populated %d\n", ret); + return ret; + } + + tsp->ops = &tsp->sci->ops.proc_ops; + tsp->proc_id = ids[0]; + tsp->host_id = ids[1]; + tsp->dev_id = dev_read_u32_default(dev, "ti,sci-dev-id", + TI_SCI_RESOURCE_NULL); + if (tsp->dev_id == TI_SCI_RESOURCE_NULL) { + dev_err(dev, "Device ID not populated %d\n", ret); + return -ENODEV; + } + + return 0; +} + +static const struct k3_m4_mem_data am6_m4_mems[] = { + { .name = "iram", .dev_addr = 0x0 }, + { .name = "dram", .dev_addr = 0x30000 }, +}; + +static int k3_m4_of_get_memories(struct udevice *dev) +{ + struct k3_m4_privdata *m4 = dev_get_priv(dev); + int i; + + m4->num_mems = ARRAY_SIZE(am6_m4_mems); + m4->mem = calloc(m4->num_mems, sizeof(*m4->mem)); + if (!m4->mem) + return -ENOMEM; + + for (i = 0; i < m4->num_mems; i++) { + m4->mem[i].bus_addr = dev_read_addr_size_name(dev, + am6_m4_mems[i].name, + (fdt_addr_t *)&m4->mem[i].size); + if (m4->mem[i].bus_addr == FDT_ADDR_T_NONE) { + dev_err(dev, "%s bus address not found\n", + am6_m4_mems[i].name); + return -EINVAL; + } + m4->mem[i].cpu_addr = map_physmem(m4->mem[i].bus_addr, + m4->mem[i].size, + MAP_NOCACHE); + m4->mem[i].dev_addr = am6_m4_mems[i].dev_addr; + } + + return 0; +} + +/** + * k3_of_to_priv() - generate private data from device tree + * @dev: corresponding k3 m4 processor device + * @m4: pointer to driver specific private data + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int k3_m4_of_to_priv(struct udevice *dev, struct k3_m4_privdata *m4) +{ + int ret; + + ret = reset_get_by_index(dev, 0, &m4->m4_rst); + if (ret) { + dev_err(dev, "reset_get() failed: %d\n", ret); + return ret; + } + + ret = ti_sci_proc_of_to_priv(dev, &m4->tsp); + if (ret) + return ret; + + ret = k3_m4_of_get_memories(dev); + if (ret) + return ret; + + m4->data = (struct k3_m4_boot_data *)dev_get_driver_data(dev); + + return 0; +} + +/** + * k3_m4_probe() - Basic probe + * @dev: corresponding k3 remote processor device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int k3_m4_probe(struct udevice *dev) +{ + struct k3_m4_privdata *m4; + int ret; + + m4 = dev_get_priv(dev); + ret = k3_m4_of_to_priv(dev, m4); + if (ret) + return ret; + + /* + * The M4 local resets are deasserted by default on Power-On-Reset. + * Assert the local resets to ensure the M4s don't execute bogus code + * in .load() callback when the module reset is released to support + * internal memory loading. This is needed for M4 cores. + */ + reset_assert(&m4->m4_rst); + + return 0; +} + +static int k3_m4_remove(struct udevice *dev) +{ + struct k3_m4_privdata *m4 = dev_get_priv(dev); + + free(m4->mem); + + return 0; +} + +static const struct k3_m4_boot_data m4_data = { + .boot_align_addr = SZ_1K, +}; + +static const struct udevice_id k3_m4_ids[] = { + { .compatible = "ti,am64-m4fss", .data = (ulong)&m4_data, }, + {} +}; + +U_BOOT_DRIVER(k3_m4) = { + .name = "k3_m4", + .of_match = k3_m4_ids, + .id = UCLASS_REMOTEPROC, + .ops = &k3_m4_ops, + .probe = k3_m4_probe, + .remove = k3_m4_remove, + .priv_auto = sizeof(struct k3_m4_privdata), +}; diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index d78b3fa1bbd..57268e7f8ff 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -886,6 +886,7 @@ static const struct udevice_id k3_r5f_rproc_ids[] = { { .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_j721s2_data, }, { .compatible = "ti,j721s2-r5f", .data = (ulong)&j7200_j721s2_data, }, { .compatible = "ti,am62-r5f", .data = (ulong)&am62_data, }, + { .compatible = "ti,am64-r5f", .data = (ulong)&j7200_j721s2_data, }, {} }; @@ -930,6 +931,7 @@ static const struct udevice_id k3_r5fss_ids[] = { { .compatible = "ti,j7200-r5fss"}, { .compatible = "ti,j721s2-r5fss"}, { .compatible = "ti,am62-r5fss"}, + { .compatible = "ti,am64-r5fss"}, {} }; diff --git a/drivers/rtc/emul_rtc.c b/drivers/rtc/emul_rtc.c index 97a8d9bb7df..6817daad18f 100644 --- a/drivers/rtc/emul_rtc.c +++ b/drivers/rtc/emul_rtc.c @@ -58,7 +58,7 @@ static int emul_rtc_set(struct udevice *dev, const struct rtc_time *time) return 0; } -int emul_rtc_probe(struct udevice *dev) +static int emul_rtc_probe(struct udevice *dev) { struct emul_rtc *priv = dev_get_priv(dev); const char *epoch_str; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 0e267d097c5..7e460f6d2c7 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -112,9 +112,9 @@ static void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr, } else if (plat->reg_width == 4) { if (plat->flags & NS16550_FLAG_ENDIAN) { if (plat->flags & NS16550_FLAG_BE) - out_be32(addr, value); + out_be32((u32 *)addr, value); else - out_le32(addr, value); + out_le32((u32 *)addr, value); } else { writel(value, addr); } @@ -132,9 +132,9 @@ static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr) } else if (plat->reg_width == 4) { if (plat->flags & NS16550_FLAG_ENDIAN) { if (plat->flags & NS16550_FLAG_BE) - return in_be32(addr); + return in_be32((u32 *)addr); else - return in_le32(addr); + return in_le32((u32 *)addr); } else { return readl(addr); } diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 96ea033082b..a916b711ba8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -85,7 +85,7 @@ config ATH79_SPI config ATMEL_QSPI bool "Atmel Quad SPI Controller" - depends on ARCH_AT91 + depends on ARCH_AT91 && SPI_MEM help Enable the Atmel Quad SPI controller in master mode. This driver does not support generic SPI. The implementation supports only the @@ -135,7 +135,7 @@ config BCMSTB_SPI config CORTINA_SFLASH bool "Cortina-Access Serial Flash controller driver" - depends on DM_SPI && SPI_MEM + depends on SPI_MEM help Enable the Cortina-Access Serial Flash controller driver. This driver can be used to access the SPI NOR/NAND flash on platforms embedding this diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 3efb661803b..8aa7a83aef4 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -10,11 +10,13 @@ */ #include <malloc.h> +#include <asm/gpio.h> #include <asm/io.h> #include <clk.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> +#include <log.h> #include <dm/device_compat.h> #include <linux/bitfield.h> #include <linux/bitops.h> @@ -258,6 +260,7 @@ struct atmel_qspi_caps { struct atmel_qspi_priv_ops; +#define MAX_CS_COUNT 2 struct atmel_qspi { void __iomem *regs; void __iomem *mem; @@ -267,6 +270,7 @@ struct atmel_qspi { struct udevice *dev; ulong bus_clk_rate; u32 mr; + struct gpio_desc cs_gpios[MAX_CS_COUNT]; }; struct atmel_qspi_priv_ops { @@ -395,6 +399,26 @@ static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset) writel(value, aq->regs + offset); } +static int atmel_qspi_reg_sync(struct atmel_qspi *aq) +{ + u32 val; + + return readl_poll_timeout(aq->regs + QSPI_SR2, val, + !(val & QSPI_SR2_SYNCBSY), + ATMEL_QSPI_SYNC_TIMEOUT); +} + +static int atmel_qspi_update_config(struct atmel_qspi *aq) +{ + int ret; + + ret = atmel_qspi_reg_sync(aq); + if (ret) + return ret; + atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); + return atmel_qspi_reg_sync(aq); +} + static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, const struct atmel_qspi_mode *mode) { @@ -458,6 +482,29 @@ static bool atmel_qspi_supports_op(struct spi_slave *slave, return true; } +/* + * Switch QSPI controller between regular SPI mode or Serial Memory Mode (SMM). + */ +static int atmel_qspi_set_serial_memory_mode(struct atmel_qspi *aq, + bool enable) +{ + int ret = 0; + + /* only write if designated state differs from current state */ + if (!!(aq->mr & QSPI_MR_SMM) != enable) { + if (enable) + aq->mr |= QSPI_MR_SMM; + else + aq->mr &= ~QSPI_MR_SMM; + atmel_qspi_write(aq->mr, aq, QSPI_MR); + + if (aq->caps->has_gclk) + ret = atmel_qspi_update_config(aq); + } + + return ret; +} + static int atmel_qspi_set_cfg(struct atmel_qspi *aq, const struct spi_mem_op *op, u32 *offset) { @@ -474,7 +521,7 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, return mode; ifr |= atmel_qspi_modes[mode].config; - if (op->dummy.buswidth && op->dummy.nbytes) + if (op->dummy.nbytes) dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; /* @@ -529,43 +576,39 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, if (dummy_cycles) ifr |= QSPI_IFR_NBDUM(dummy_cycles); - /* Set data enable */ - if (op->data.nbytes) + /* Set data enable and data transfer type. */ + if (op->data.nbytes) { ifr |= QSPI_IFR_DATAEN; - /* - * If the QSPI controller is set in regular SPI mode, set it in - * Serial Memory Mode (SMM). - */ - if (aq->mr != QSPI_MR_SMM) { - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); - aq->mr = QSPI_MR_SMM; + if (op->addr.nbytes) + ifr |= QSPI_IFR_TFRTYP_MEM; } + mode = atmel_qspi_set_serial_memory_mode(aq, true); + if (mode < 0) + return mode; + /* Clear pending interrupts */ (void)atmel_qspi_read(aq, QSPI_SR); - if (aq->caps->has_ricr) { - if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN) - ifr |= QSPI_IFR_APBTFRTYP_READ; - - /* Set QSPI Instruction Frame registers */ + /* Set QSPI Instruction Frame registers. */ + if (op->addr.nbytes && !op->data.nbytes) atmel_qspi_write(iar, aq, QSPI_IAR); + + if (aq->caps->has_ricr) { if (op->data.dir == SPI_MEM_DATA_IN) atmel_qspi_write(icr, aq, QSPI_RICR); else atmel_qspi_write(icr, aq, QSPI_WICR); - atmel_qspi_write(ifr, aq, QSPI_IFR); } else { - if (op->data.dir == SPI_MEM_DATA_OUT) + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR; - /* Set QSPI Instruction Frame registers */ - atmel_qspi_write(iar, aq, QSPI_IAR); atmel_qspi_write(icr, aq, QSPI_ICR); - atmel_qspi_write(ifr, aq, QSPI_IFR); } + atmel_qspi_write(ifr, aq, QSPI_IFR); + return 0; } @@ -597,26 +640,6 @@ static int atmel_qspi_transfer(struct atmel_qspi *aq, ATMEL_QSPI_TIMEOUT); } -static int atmel_qspi_reg_sync(struct atmel_qspi *aq) -{ - u32 val; - - return readl_poll_timeout(aq->regs + QSPI_SR2, val, - !(val & QSPI_SR2_SYNCBSY), - ATMEL_QSPI_SYNC_TIMEOUT); -} - -static int atmel_qspi_update_config(struct atmel_qspi *aq) -{ - int ret; - - ret = atmel_qspi_reg_sync(aq); - if (ret) - return ret; - atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); - return atmel_qspi_reg_sync(aq); -} - static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, const struct spi_mem_op *op, u32 *offset) { @@ -668,17 +691,9 @@ static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, ifr |= QSPI_IFR_TFRTYP_MEM; } - /* - * If the QSPI controller is set in regular SPI mode, set it in - * Serial Memory Mode (SMM). - */ - if (aq->mr != QSPI_MR_SMM) { - atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); - ret = atmel_qspi_update_config(aq); - if (ret) - return ret; - aq->mr = QSPI_MR_SMM; - } + ret = atmel_qspi_set_serial_memory_mode(aq, true); + if (ret < 0) + return ret; /* Clear pending interrupts */ (void)atmel_qspi_read(aq, QSPI_SR); @@ -902,11 +917,10 @@ static int atmel_qspi_sama7g5_set_speed(struct udevice *bus, uint hz) } /* Set the QSPI controller by default in Serial Memory Mode */ - atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); - ret = atmel_qspi_update_config(aq); - if (ret) + aq->mr |= QSPI_MR_DQSDLYEN; + ret = atmel_qspi_set_serial_memory_mode(aq, true); + if (ret < 0) return ret; - aq->mr = QSPI_MR_SMM; /* Enable the QSPI controller. */ ret = atmel_qspi_reg_sync(aq); @@ -930,6 +944,135 @@ static int atmel_qspi_sama7g5_set_speed(struct udevice *bus, uint hz) return ret; } +static int atmel_qspi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_qspi *aq = dev_get_priv(bus); + int ret; + + aq->mr &= ~QSPI_MR_CSMODE_MASK; + aq->mr |= QSPI_MR_CSMODE_LASTXFER | QSPI_MR_WDRBT; + atmel_qspi_write(aq->mr, aq, QSPI_MR); + + ret = atmel_qspi_set_serial_memory_mode(aq, false); + if (ret) + return log_ret(ret); + + /* de-assert all chip selects */ + if (IS_ENABLED(CONFIG_DM_GPIO)) { + for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) { + if (dm_gpio_is_valid(&aq->cs_gpios[i])) + dm_gpio_set_value(&aq->cs_gpios[i], 0); + } + } + + atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); + + return 0; +} + +static int atmel_qspi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_qspi *aq = dev_get_priv(bus); + + /* de-assert all chip selects */ + if (IS_ENABLED(CONFIG_DM_GPIO)) { + for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) { + if (dm_gpio_is_valid(&aq->cs_gpios[i])) + dm_gpio_set_value(&aq->cs_gpios[i], 0); + } + } + + atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); + + return 0; +} + +static int atmel_qspi_set_cs(struct udevice *dev, int value) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_qspi *aq = dev_get_priv(bus); + int cs = spi_chip_select(dev); + + if (IS_ENABLED(CONFIG_DM_GPIO)) { + if (!dm_gpio_is_valid(&aq->cs_gpios[cs])) + return log_ret(-ENOENT); + + return dm_gpio_set_value(&aq->cs_gpios[cs], value); + } else { + return -ENOENT; + } +} + +static int atmel_qspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct atmel_qspi *aq = dev_get_priv(bus); + unsigned int len, len_rx, len_tx; + const u8 *txp = dout; + u8 *rxp = din; + u32 reg; + int ret; + + if (bitlen == 0) + goto out; + + if (bitlen % 8) { + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (flags & SPI_XFER_BEGIN) { + ret = atmel_qspi_set_cs(dev, 1); + if (ret) + return log_ret(ret); + reg = atmel_qspi_read(aq, QSPI_RD); + } + + for (len_tx = 0, len_rx = 0; len_rx < len; ) { + u32 status = atmel_qspi_read(aq, QSPI_SR); + u8 value; + + if (status & QSPI_SR_OVRES) + return log_ret(-1); + + if (len_tx < len && (status & QSPI_SR_TDRE)) { + if (txp) + value = *txp++; + else + value = 0; + atmel_qspi_write(value, aq, QSPI_TD); + len_tx++; + } + + if (status & QSPI_SR_RDRF) { + value = atmel_qspi_read(aq, QSPI_RD); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + +out: + if (flags & SPI_XFER_END) { + readl_poll_timeout(aq->regs + QSPI_SR, reg, + reg & QSPI_SR_TXEMPTY, + ATMEL_QSPI_TIMEOUT); + + atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); + + ret = atmel_qspi_set_cs(dev, 0); + if (ret) + return log_ret(ret); + } + + return 0; +} + static int atmel_qspi_set_speed(struct udevice *bus, uint hz) { struct atmel_qspi *aq = dev_get_priv(bus); @@ -939,6 +1082,7 @@ static int atmel_qspi_set_speed(struct udevice *bus, uint hz) return atmel_qspi_sama7g5_set_speed(bus, hz); /* Compute the QSPI baudrate */ + dev_dbg(bus, "bus_clk_rate: %lu, hz: %u\n", aq->bus_clk_rate, hz); scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz); if (scbr > 0) scbr--; @@ -1046,10 +1190,6 @@ static int atmel_qspi_init(struct atmel_qspi *aq) /* Reset the QSPI controller */ atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); - /* Set the QSPI controller by default in Serial Memory Mode */ - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); - aq->mr = QSPI_MR_SMM; - /* Enable the QSPI controller */ atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); @@ -1075,7 +1215,7 @@ static int atmel_qspi_probe(struct udevice *dev) aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev); if (!aq->caps) { dev_err(dev, "Could not retrieve QSPI caps\n"); - return -EINVAL; + return log_ret(-EINVAL); }; if (aq->caps->has_gclk) @@ -1083,36 +1223,53 @@ static int atmel_qspi_probe(struct udevice *dev) else aq->ops = &atmel_qspi_priv_ops; + if (IS_ENABLED(CONFIG_DM_GPIO)) { + ret = gpio_request_list_by_name(dev, "cs-gpios", aq->cs_gpios, + ARRAY_SIZE(aq->cs_gpios), 0); + if (ret < 0) { + pr_err("Can't get %s gpios! Error: %d", dev->name, ret); + return log_ret(ret); + } + + for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) { + if (!dm_gpio_is_valid(&aq->cs_gpios[i])) + continue; + + dm_gpio_set_dir_flags(&aq->cs_gpios[i], + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + } + } + /* Map the registers */ ret = dev_read_resource_byname(dev, "qspi_base", &res); if (ret) { dev_err(dev, "missing registers\n"); - return ret; + return log_ret(ret); } aq->regs = devm_ioremap(dev, res.start, resource_size(&res)); if (IS_ERR(aq->regs)) - return PTR_ERR(aq->regs); + return log_ret(PTR_ERR(aq->regs)); /* Map the AHB memory */ ret = dev_read_resource_byname(dev, "qspi_mmap", &res); if (ret) { dev_err(dev, "missing AHB memory\n"); - return ret; + return log_ret(ret); } aq->mem = devm_ioremap(dev, res.start, resource_size(&res)); if (IS_ERR(aq->mem)) - return PTR_ERR(aq->mem); + return log_ret(PTR_ERR(aq->mem)); aq->mmap_size = resource_size(&res); ret = atmel_qspi_enable_clk(dev); if (ret) - return ret; + return log_ret(ret); aq->dev = dev; - return atmel_qspi_init(aq); + return log_ret(atmel_qspi_init(aq)); } static const struct spi_controller_mem_ops atmel_qspi_mem_ops = { @@ -1121,9 +1278,12 @@ static const struct spi_controller_mem_ops atmel_qspi_mem_ops = { }; static const struct dm_spi_ops atmel_qspi_ops = { + .claim_bus = atmel_qspi_claim_bus, + .release_bus = atmel_qspi_release_bus, + .xfer = atmel_qspi_xfer, + .mem_ops = &atmel_qspi_mem_ops, .set_speed = atmel_qspi_set_speed, .set_mode = atmel_qspi_set_mode, - .mem_ops = &atmel_qspi_mem_ops, }; static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {}; diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index dcf28c75596..816916de16d 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -24,6 +24,13 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, u8 opcode, addr_bytes, *rxbuf, dummy_cycles; n_rx = op->data.nbytes; + + if (op->addr.dtr && (op->addr.val % 2)) { + n_rx += 1; + writel(op->addr.val & ~0x1, + priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); + } + rxbuf = op->data.buf.in; rx_rem = n_rx % 4; bytes_to_dma = n_rx - rx_rem; @@ -104,6 +111,11 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, memcpy(rxbuf, &data, rx_rem); } + if (op->addr.dtr && (op->addr.val % 2)) { + rxbuf -= bytes_to_dma; + memcpy(rxbuf, rxbuf + 1, n_rx - 1); + } + return 0; } diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 693474a2871..1f9125cd239 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -307,7 +307,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op); int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv); int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); -int cadence_qspi_versal_flash_reset(struct udevice *dev); +int cadence_qspi_flash_reset(struct udevice *dev); ofnode cadence_qspi_get_subnode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable); diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index a8ec2f4f7b4..50bd7be5640 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -124,8 +124,19 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, u8 *rxd = din; int cpha = !!(priv->mode & SPI_CPHA); int cidle = !!(priv->mode & SPI_CPOL); + int txrx = plat->flags; unsigned int j; + if (priv->mode & SPI_3WIRE) { + if (txd && rxd) + return -EINVAL; + + txrx = txd ? SPI_MASTER_NO_RX : SPI_MASTER_NO_TX; + dm_gpio_set_dir_flags(&plat->mosi, + txd ? GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE : + GPIOD_IS_IN | GPIOD_PULL_UP); + } + debug("spi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n", dev->parent->name, dev->name, *(uint *)txd, *(uint *)rxd, bitlen); @@ -160,7 +171,7 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, */ if (cpha) soft_spi_scl(dev, !cidle); - if ((plat->flags & SPI_MASTER_NO_TX) == 0) + if ((txrx & SPI_MASTER_NO_TX) == 0) soft_spi_sda(dev, !!(tmpdout & 0x80)); udelay(plat->spi_delay_us); @@ -174,8 +185,10 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, else soft_spi_scl(dev, cidle); tmpdin <<= 1; - if ((plat->flags & SPI_MASTER_NO_RX) == 0) - tmpdin |= dm_gpio_get_value(&plat->miso); + if ((txrx & SPI_MASTER_NO_RX) == 0) + tmpdin |= dm_gpio_get_value((priv->mode & SPI_3WIRE) ? + &plat->mosi : + &plat->miso); tmpdout <<= 1; udelay(plat->spi_delay_us); diff --git a/drivers/sysinfo/Kconfig b/drivers/sysinfo/Kconfig index 2030e4babc9..df83df69ffb 100644 --- a/drivers/sysinfo/Kconfig +++ b/drivers/sysinfo/Kconfig @@ -31,6 +31,13 @@ config SYSINFO_RCAR3 help Support querying SoC version information for Renesas R-Car Gen3. +config SYSINFO_IOT2050 + bool "Enable sysinfo driver for the Siemens IOT2050" + depends on TARGET_IOT2050_A53 + default y if TARGET_IOT2050_A53 + help + Support querying device information for Siemens IOT2050. + config SYSINFO_SANDBOX bool "Enable sysinfo driver for the Sandbox board" help diff --git a/drivers/sysinfo/Makefile b/drivers/sysinfo/Makefile index 680dde77fe8..26ca3150999 100644 --- a/drivers/sysinfo/Makefile +++ b/drivers/sysinfo/Makefile @@ -5,6 +5,7 @@ obj-y += sysinfo-uclass.o obj-$(CONFIG_SYSINFO_GAZERBEAM) += gazerbeam.o obj-$(CONFIG_SYSINFO_GPIO) += gpio.o +obj-$(CONFIG_SYSINFO_IOT2050) += iot2050.o obj-$(CONFIG_SYSINFO_RCAR3) += rcar3.o obj-$(CONFIG_SYSINFO_SANDBOX) += sandbox.o obj-$(CONFIG_SYSINFO_SMBIOS) += smbios.o diff --git a/drivers/sysinfo/iot2050.c b/drivers/sysinfo/iot2050.c new file mode 100644 index 00000000000..579a9f4711d --- /dev/null +++ b/drivers/sysinfo/iot2050.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2025 + */ + +#include <dm.h> +#include <sysinfo.h> +#include <net.h> +#include <u-boot/uuid.h> +#include <asm/arch/hardware.h> + +#include "iot2050.h" + +#define IOT2050_INFO_MAGIC 0x20502050 + +#define IOT2050_UUID_STR_LEN (32) + +struct iot2050_info { + u32 magic; + u16 size; + char name[20 + 1]; + char serial[16 + 1]; + char mlfb[18 + 1]; + char uuid[IOT2050_UUID_STR_LEN + 1]; + char a5e[18 + 1]; + u8 mac_addr_cnt; + u8 mac_addr[8][ARP_HLEN]; + char seboot_version[40 + 1]; + u8 padding[3]; + u32 ddr_size_mb; +} __packed; + +/** + * struct sysinfo_iot2050_priv - sysinfo private data + * @info: iot2050 board info + */ +struct sysinfo_iot2050_priv { + struct iot2050_info *info; + u8 uuid_smbios[16]; +}; + +static int sysinfo_iot2050_detect(struct udevice *dev) +{ + struct sysinfo_iot2050_priv *priv = dev_get_priv(dev); + + if (!priv->info || priv->info->magic != IOT2050_INFO_MAGIC) + return -EFAULT; + + return 0; +} + +static int sysinfo_iot2050_get_str(struct udevice *dev, int id, size_t size, + char *val) +{ + struct sysinfo_iot2050_priv *priv = dev_get_priv(dev); + + switch (id) { + case BOARD_NAME: + case SYSID_SM_BASEBOARD_VERSION: + strlcpy(val, priv->info->name, size); + break; + case SYSID_SM_SYSTEM_SERIAL: + strlcpy(val, priv->info->serial, size); + break; + case BOARD_MLFB: + case SYSID_SM_SYSTEM_VERSION: + strlcpy(val, priv->info->mlfb, size); + break; + case BOARD_UUID: + strlcpy(val, priv->info->uuid, size); + break; + case BOARD_A5E: + case SYSID_SM_BASEBOARD_PRODUCT: + strlcpy(val, priv->info->a5e, size); + break; + case BOARD_SEBOOT_VER: + case SYSID_PRIOR_STAGE_VERSION: + strlcpy(val, priv->info->seboot_version, size); + break; + default: + return -EINVAL; + }; + + val[size - 1] = '\0'; + return 0; +} + +static int sysinfo_iot2050_get_int(struct udevice *dev, int id, int *val) +{ + struct sysinfo_iot2050_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_BOARD_RAM_SIZE_MB: + *val = priv->info->ddr_size_mb; + return 0; + default: + return -EINVAL; + }; +} + +static int sysinfo_iot2050_get_data(struct udevice *dev, int id, void **data, + size_t *size) +{ + struct sysinfo_iot2050_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_SM_SYSTEM_UUID: + *data = priv->uuid_smbios; + *size = 16; + return 0; + default: + return -EINVAL; + }; +} + +static int sysinfo_iot2050_get_item_count(struct udevice *dev, int id) +{ + struct sysinfo_iot2050_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_BOARD_MAC_ADDR: + return priv->info->mac_addr_cnt; + default: + return -EINVAL; + }; +} + +static int sysinfo_iot2050_get_data_by_index(struct udevice *dev, int id, + int index, void **data, + size_t *size) +{ + struct sysinfo_iot2050_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_BOARD_MAC_ADDR: + if (index >= priv->info->mac_addr_cnt) + return -EINVAL; + *data = priv->info->mac_addr[index]; + *size = ARP_HLEN; + return 0; + default: + return -EINVAL; + }; +} + +static const struct sysinfo_ops sysinfo_iot2050_ops = { + .detect = sysinfo_iot2050_detect, + .get_str = sysinfo_iot2050_get_str, + .get_int = sysinfo_iot2050_get_int, + .get_data = sysinfo_iot2050_get_data, + .get_item_count = sysinfo_iot2050_get_item_count, + .get_data_by_index = sysinfo_iot2050_get_data_by_index, +}; + +/** + * @brief Convert the IOT2050 UUID string to the SMBIOS format + * + * @param uuid_raw The IOT2050 UUID string parsed from the eeprom + * @param uuid_smbios The buffer to hold the SMBIOS formatted UUID + */ +static void sysinfo_iot2050_convert_uuid(const char *uuid_iot2050, + u8 *uuid_smbios) +{ + char uuid_rfc4122_str[IOT2050_UUID_STR_LEN + 4 + 1] = {0}; + char *tmp = uuid_rfc4122_str; + + for (int i = 0; i < 16; i++) { + memcpy(tmp, uuid_iot2050 + i * 2, 2); + tmp += 2; + if (i == 3 || i == 5 || i == 7 || i == 9) + *tmp++ = '-'; + } + uuid_str_to_bin(uuid_rfc4122_str, uuid_smbios, UUID_STR_FORMAT_GUID); +} + +static int sysinfo_iot2050_probe(struct udevice *dev) +{ + struct sysinfo_iot2050_priv *priv = dev_get_priv(dev); + unsigned long offset; + + offset = dev_read_u32_default(dev, "offset", + TI_SRAM_SCRATCH_BOARD_EEPROM_START); + priv->info = (struct iot2050_info *)offset; + + sysinfo_iot2050_convert_uuid(priv->info->uuid, priv->uuid_smbios); + + return 0; +} + +static const struct udevice_id sysinfo_iot2050_ids[] = { + { .compatible = "siemens,sysinfo-iot2050" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sysinfo_iot2050) = { + .name = "sysinfo_iot2050", + .id = UCLASS_SYSINFO, + .of_match = sysinfo_iot2050_ids, + .ops = &sysinfo_iot2050_ops, + .priv_auto = sizeof(struct sysinfo_iot2050_priv), + .probe = sysinfo_iot2050_probe, +}; diff --git a/drivers/sysinfo/iot2050.h b/drivers/sysinfo/iot2050.h new file mode 100644 index 00000000000..657221db096 --- /dev/null +++ b/drivers/sysinfo/iot2050.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Siemens AG, 2025 + */ + +#include <sysinfo.h> + +enum sysinfo_id_iot2050 { + BOARD_MLFB = SYSID_USER, + BOARD_A5E, + BOARD_NAME, + BOARD_UUID, + BOARD_SEBOOT_VER, +}; diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index 3c0cd51273e..f04998ef8bb 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -119,6 +119,35 @@ int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size) return ops->get_data(dev, id, data, size); } +int sysinfo_get_item_count(struct udevice *dev, int id) +{ + struct sysinfo_priv *priv = dev_get_uclass_priv(dev); + struct sysinfo_ops *ops = sysinfo_get_ops(dev); + + if (!priv->detected) + return -EPERM; + + if (!ops->get_item_count) + return -ENOSYS; + + return ops->get_item_count(dev, id); +} + +int sysinfo_get_data_by_index(struct udevice *dev, int id, int index, + void **data, size_t *size) +{ + struct sysinfo_priv *priv = dev_get_uclass_priv(dev); + struct sysinfo_ops *ops = sysinfo_get_ops(dev); + + if (!priv->detected) + return -EPERM; + + if (!ops->get_data_by_index) + return -ENOSYS; + + return ops->get_data_by_index(dev, id, index, data, size); +} + UCLASS_DRIVER(sysinfo) = { .id = UCLASS_SYSINFO, .name = "sysinfo", diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c index e8b54a02965..c1baf3c69ec 100644 --- a/drivers/timer/sandbox_timer.c +++ b/drivers/timer/sandbox_timer.c @@ -18,6 +18,11 @@ void timer_test_add_offset(unsigned long offset) sandbox_timer_offset += offset; } +ulong timer_test_get_offset(void) +{ + return sandbox_timer_offset; +}; + u64 notrace timer_early_get_count(void) { return os_get_nsec() / 1000 + sandbox_timer_offset * 1000; diff --git a/drivers/tpm/tpm2_tis_mmio.c b/drivers/tpm/tpm2_tis_mmio.c index dee5503c055..fc62dcda9ef 100644 --- a/drivers/tpm/tpm2_tis_mmio.c +++ b/drivers/tpm/tpm2_tis_mmio.c @@ -135,7 +135,7 @@ static const struct tpm_ops tpm_tis_ops = { .cleanup = tpm_tis_cleanup, }; -static const struct tpm_tis_chip_data tpm_tis_std_chip_data = { +static struct tpm_tis_chip_data tpm_tis_std_chip_data = { .pcr_count = 24, .pcr_select_min = 3, }; diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 0100723a68b..682a6910655 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -87,6 +87,14 @@ config USB_DWC3_LAYERSCAPE Host and Peripheral operation modes are supported. OTG is not supported. +config USB_DWC3_STI + bool "STi USB wrapper" + depends on DM_USB && USB_DWC3_GENERIC && SYSCON + help + Enables support for the on-chip xHCI controller on STMicroelectronics + STiH407 family SoCs. This is a driver for the dwc3 to provide the + glue logic to configure the controller. + menu "PHY Subsystem" config USB_DWC3_PHY_OMAP diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index a085c9d4628..985206eafe4 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o +obj-$(CONFIG_USB_DWC3_STI) += dwc3-generic-sti.o diff --git a/drivers/usb/dwc3/dwc3-generic-sti.c b/drivers/usb/dwc3/dwc3-generic-sti.c new file mode 100644 index 00000000000..b34f5ceceac --- /dev/null +++ b/drivers/usb/dwc3/dwc3-generic-sti.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * STi specific glue layer for DWC3 + * + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_NOP + +#include <reset.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/read.h> +#include <linux/usb/otg.h> +#include "dwc3-generic.h" + +/* glue registers */ +#define CLKRST_CTRL 0x00 +#define AUX_CLK_EN BIT(0) +#define SW_PIPEW_RESET_N BIT(4) +#define EXT_CFG_RESET_N BIT(8) + +#define XHCI_REVISION BIT(12) + +#define USB2_VBUS_MNGMNT_SEL1 0x2C +#define USB2_VBUS_UTMIOTG 0x1 + +#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0) +#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4) +#define SEL_OVERRIDE_BVALID(n) ((n) << 8) + +/* Static DRD configuration */ +#define USB3_CONTROL_MASK 0xf77 + +#define USB3_DEVICE_NOT_HOST BIT(0) +#define USB3_FORCE_VBUSVALID BIT(1) +#define USB3_DELAY_VBUSVALID BIT(2) +#define USB3_SEL_FORCE_OPMODE BIT(4) +#define USB3_FORCE_OPMODE(n) ((n) << 5) +#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) +#define USB3_FORCE_DPPULLDOWN2 BIT(9) +#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) +#define USB3_FORCE_DMPULLDOWN2 BIT(11) + +static void dwc3_stih407_glue_configure(struct udevice *dev, int index, + enum usb_dr_mode mode) +{ + struct dwc3_glue_data *glue = dev_get_plat(dev); + struct regmap *regmap; + ulong syscfg_base; + ulong syscfg_offset; + ulong glue_base; + int ret; + + /* deassert both powerdown and softreset */ + ret = reset_deassert_bulk(&glue->resets); + if (ret) { + dev_err(dev, "reset_deassert_bulk error: %d\n", ret); + return; + } + + regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg"); + if (IS_ERR(regmap)) { + dev_err(dev, "unable to get st,syscfg, dev %s\n", dev->name); + return; + } + + syscfg_base = regmap->ranges[0].start; + glue_base = dev_read_addr_index(dev, 0); + syscfg_offset = dev_read_addr_index(dev, 1); + + clrbits_le32(syscfg_base + syscfg_offset, USB3_CONTROL_MASK); + + /* glue drd init */ + switch (mode) { + case USB_DR_MODE_PERIPHERAL: + clrbits_le32(syscfg_base + syscfg_offset, + USB3_DELAY_VBUSVALID | USB3_SEL_FORCE_OPMODE | + USB3_FORCE_OPMODE(0x3) | USB3_SEL_FORCE_DPPULLDOWN2 | + USB3_FORCE_DPPULLDOWN2 | USB3_SEL_FORCE_DMPULLDOWN2 | + USB3_FORCE_DMPULLDOWN2); + + setbits_le32(syscfg_base + syscfg_offset, + USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID); + break; + + case USB_DR_MODE_HOST: + clrbits_le32(syscfg_base + syscfg_offset, + USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID | + USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) | + USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 | + USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); + + setbits_le32(syscfg_base + syscfg_offset, USB3_DELAY_VBUSVALID); + break; + + default: + dev_err(dev, "Unsupported mode of operation %d\n", mode); + return; + } + + /* glue init */ + setbits_le32(glue_base + CLKRST_CTRL, AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION); + clrbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); + + /* configure mux for vbus, powerpresent and bvalid signals */ + setbits_le32(glue_base + USB2_VBUS_MNGMNT_SEL1, + SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | + SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | + SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG)); + setbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); +}; + +struct dwc3_glue_ops stih407_ops = { + .glue_configure = dwc3_stih407_glue_configure, +}; + +static const struct udevice_id dwc3_sti_match[] = { + { .compatible = "st,stih407-dwc3", .data = (ulong)&stih407_ops}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(dwc3_sti_wrapper) = { + .name = "dwc3-sti", + .id = UCLASS_NOP, + .of_match = dwc3_sti_match, + .bind = dwc3_glue_bind, + .probe = dwc3_glue_probe, + .remove = dwc3_glue_remove, + .plat_auto = sizeof(struct dwc3_glue_data), +}; diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 55e62b35c61..21452ad1569 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -7,29 +7,17 @@ * Based on dwc3-omap.c. */ -#include <cpu_func.h> -#include <log.h> #include <dm.h> -#include <dm/device-internal.h> +#include <reset.h> +#include <asm/gpio.h> #include <dm/lists.h> -#include <dwc3-uboot.h> -#include <generic-phy.h> -#include <linux/bitops.h> #include <linux/delay.h> -#include <linux/printk.h> -#include <linux/usb/ch9.h> #include <linux/usb/gadget.h> -#include <malloc.h> #include <power/regulator.h> -#include <usb.h> -#include "core.h" -#include "gadget.h" -#include <reset.h> -#include <clk.h> #include <usb/xhci.h> -#include <asm/gpio.h> - +#include "core.h" #include "dwc3-generic.h" +#include "gadget.h" struct dwc3_generic_plat { fdt_addr_t base; diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index ffe1ae6eb73..d3fc4acb401 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -682,6 +682,7 @@ static int sleep_thread(struct fsg_common *common) k = 0; } + schedule(); dm_usb_gadget_handle_interrupts(udcdev); } common->thread_wakeup_needed = 0; diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index 631969b3405..f2540eb6ded 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -207,7 +207,8 @@ void g_dnl_clear_detach(void) static int on_serialno(const char *name, const char *value, enum env_op op, int flags) { - g_dnl_set_serialnumber((char *)value); + if (value) + g_dnl_set_serialnumber((char *)value); return 0; } U_BOOT_ENV_CALLBACK(serialno, on_serialno); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index a656265890e..3dc79770eeb 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -110,15 +110,6 @@ config USB_XHCI_RCAR Choose this option to add support for USB 3.0 driver on Renesas R-Car Gen3 SoCs. -config USB_XHCI_STI - bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" - depends on ARCH_STI - default y - help - Enables support for the on-chip xHCI controller on STMicroelectronics - STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic - to configure the controller. - config USB_XHCI_DRA7XX_INDEX int "DRA7XX xHCI USB index" range 0 1 diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 301bb9fdee1..902d68d0378 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -54,7 +54,6 @@ obj-$(CONFIG_USB_XHCI_GENERIC) += xhci-generic.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o -obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o # designware diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c deleted file mode 100644 index 3e6834e38e3..00000000000 --- a/drivers/usb/host/dwc3-sti-glue.c +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * STiH407 family DWC3 specific Glue layer - * - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. - */ - -#include <log.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <dm.h> -#include <errno.h> -#include <dm/lists.h> -#include <regmap.h> -#include <reset-uclass.h> -#include <syscon.h> -#include <usb.h> -#include <linux/printk.h> - -#include <linux/usb/dwc3.h> -#include <linux/usb/otg.h> -#include <dwc3-sti-glue.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure - * @syscfg_base: addr for the glue syscfg - * @glue_base: addr for the glue registers - * @syscfg_offset: usb syscfg control offset - * @powerdown_ctl: rest controller for powerdown signal - * @softreset_ctl: reset controller for softreset signal - * @mode: drd static host/device config - */ -struct sti_dwc3_glue_plat { - phys_addr_t syscfg_base; - phys_addr_t glue_base; - phys_addr_t syscfg_offset; - struct reset_ctl powerdown_ctl; - struct reset_ctl softreset_ctl; - enum usb_dr_mode mode; -}; - -static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat) -{ - unsigned long val; - - val = readl(plat->syscfg_base + plat->syscfg_offset); - - val &= USB3_CONTROL_MASK; - - switch (plat->mode) { - case USB_DR_MODE_PERIPHERAL: - val &= ~(USB3_DELAY_VBUSVALID - | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) - | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 - | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); - - val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID; - break; - - case USB_DR_MODE_HOST: - val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID - | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) - | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 - | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); - - val |= USB3_DELAY_VBUSVALID; - break; - - default: - pr_err("Unsupported mode of operation %d\n", plat->mode); - return -EINVAL; - } - writel(val, plat->syscfg_base + plat->syscfg_offset); - - return 0; -} - -static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat) -{ - unsigned long reg; - - reg = readl(plat->glue_base + CLKRST_CTRL); - - reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION; - reg &= ~SW_PIPEW_RESET_N; - - writel(reg, plat->glue_base + CLKRST_CTRL); - - /* configure mux for vbus, powerpresent and bvalid signals */ - reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1); - - reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | - SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | - SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG); - - writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1); - - setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); -} - -static int sti_dwc3_glue_of_to_plat(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - struct udevice *syscon; - struct regmap *regmap; - int ret; - u32 reg[4]; - - ret = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg, - ARRAY_SIZE(reg)); - if (ret) { - pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret); - return ret; - } - - plat->glue_base = reg[0]; - plat->syscfg_offset = reg[2]; - - /* get corresponding syscon phandle */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "st,syscfg", - &syscon); - if (ret) { - pr_err("unable to find syscon device (%d)\n", ret); - return ret; - } - - /* get syscfg-reg base address */ - regmap = syscon_get_regmap(syscon); - if (!regmap) { - pr_err("unable to find regmap\n"); - return -ENODEV; - } - plat->syscfg_base = regmap->ranges[0].start; - - /* get powerdown reset */ - ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl); - if (ret) { - pr_err("can't get powerdown reset for %s (%d)", dev->name, ret); - return ret; - } - - /* get softreset reset */ - ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl); - if (ret) - pr_err("can't get soft reset for %s (%d)", dev->name, ret); - - return ret; -}; - -static int sti_dwc3_glue_bind(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - ofnode node, dwc3_node; - - /* Find snps,dwc3 node from subnode */ - ofnode_for_each_subnode(node, dev_ofnode(dev)) { - if (ofnode_device_is_compatible(node, "snps,dwc3")) - dwc3_node = node; - } - - if (!ofnode_valid(dwc3_node)) { - pr_err("Can't find dwc3 subnode for %s\n", dev->name); - return -ENODEV; - } - - /* retrieve the DWC3 dual role mode */ - plat->mode = usb_get_dr_mode(dwc3_node); - if (plat->mode == USB_DR_MODE_UNKNOWN) - /* by default set dual role mode to HOST */ - plat->mode = USB_DR_MODE_HOST; - - return dm_scan_fdt_dev(dev); -} - -static int sti_dwc3_glue_probe(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - int ret; - - /* deassert both powerdown and softreset */ - ret = reset_deassert(&plat->powerdown_ctl); - if (ret < 0) { - pr_err("DWC3 powerdown reset deassert failed: %d", ret); - return ret; - } - - ret = reset_deassert(&plat->softreset_ctl); - if (ret < 0) { - pr_err("DWC3 soft reset deassert failed: %d", ret); - goto softreset_err; - } - - ret = sti_dwc3_glue_drd_init(plat); - if (ret) - goto init_err; - - sti_dwc3_glue_init(plat); - - return 0; - -init_err: - ret = reset_assert(&plat->softreset_ctl); - if (ret < 0) { - pr_err("DWC3 soft reset deassert failed: %d", ret); - return ret; - } - -softreset_err: - ret = reset_assert(&plat->powerdown_ctl); - if (ret < 0) - pr_err("DWC3 powerdown reset deassert failed: %d", ret); - - return ret; -} - -static int sti_dwc3_glue_remove(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - int ret; - - /* assert both powerdown and softreset */ - ret = reset_assert(&plat->powerdown_ctl); - if (ret < 0) { - pr_err("DWC3 powerdown reset deassert failed: %d", ret); - return ret; - } - - ret = reset_assert(&plat->softreset_ctl); - if (ret < 0) - pr_err("DWC3 soft reset deassert failed: %d", ret); - - return ret; -} - -static const struct udevice_id sti_dwc3_glue_ids[] = { - { .compatible = "st,stih407-dwc3" }, - { } -}; - -U_BOOT_DRIVER(dwc3_sti_glue) = { - .name = "dwc3_sti_glue", - .id = UCLASS_NOP, - .of_match = sti_dwc3_glue_ids, - .of_to_plat = sti_dwc3_glue_of_to_plat, - .probe = sti_dwc3_glue_probe, - .remove = sti_dwc3_glue_remove, - .bind = sti_dwc3_glue_bind, - .plat_auto = sizeof(struct sti_dwc3_glue_plat), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; diff --git a/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts index bd6419a5c20..8311af4c868 100644 --- a/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts +++ b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts @@ -74,6 +74,23 @@ vin-supply = <&vcc5v0_sys>; }; + /* + * HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. + * This is modeled as an always-on active low fixed regulator. + */ + vcc_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_2030>; + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + vcc5v0_sys: regulator-5v0-vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -181,6 +198,12 @@ }; }; + sdmmc { + sdmmc_2030: sdmmc-2030 { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wifi { wifi_reg_on: wifi-reg-on { rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -233,7 +256,7 @@ cap-mmc-highspeed; cap-sd-highspeed; disable-wp; - vmmc-supply = <&vcc_io>; + vmmc-supply = <&vcc_sd>; status = "okay"; }; diff --git a/env/fat.c b/env/fat.c index b04b1d9c315..1ad301eaaff 100644 --- a/env/fat.c +++ b/env/fat.c @@ -41,14 +41,12 @@ __weak const char *env_fat_get_intf(void) __weak char *env_fat_get_dev_part(void) { #ifdef CONFIG_MMC - static char *part_str; - - if (!part_str) { - part_str = CONFIG_ENV_FAT_DEVICE_AND_PART; - if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc") && part_str[0] == ':') { - part_str = "0" CONFIG_ENV_FAT_DEVICE_AND_PART; - part_str[0] += mmc_get_env_dev(); - } + /* reserve one more char for the manipulation below */ + static char part_str[] = CONFIG_ENV_FAT_DEVICE_AND_PART "\0"; + + if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc") && part_str[0] == ':') { + part_str[0] = '0' + mmc_get_env_dev(); + strcpy(&part_str[1], CONFIG_ENV_FAT_DEVICE_AND_PART); } return part_str; diff --git a/env/mmc.c b/env/mmc.c index 379f5ec9be7..2ef15fb72e7 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -40,18 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * In case the environment is redundant, stored in eMMC hardware boot - * partition and the environment and redundant environment offsets are - * identical, store the environment and redundant environment in both - * eMMC boot partitions, one copy in each. - * */ -#if (defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) && \ - (CONFIG_SYS_MMC_ENV_PART == 1) && \ - (CONFIG_ENV_OFFSET == CONFIG_ENV_OFFSET_REDUND)) -#define ENV_MMC_HWPART_REDUND 1 -#endif - #if CONFIG_IS_ENABLED(OF_CONTROL) static int mmc_env_partition_by_name(struct blk_desc *desc, const char *str, @@ -217,6 +205,23 @@ static inline s64 mmc_offset(struct mmc *mmc, int copy) } #endif +static bool mmc_env_is_redundant_in_both_boot_hwparts(struct mmc *mmc) +{ + /* + * In case the environment is redundant, stored in eMMC hardware boot + * partition and the environment and redundant environment offsets are + * identical, store the environment and redundant environment in both + * eMMC boot partitions, one copy in each. + */ + if (!IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) + return false; + + if (CONFIG_SYS_MMC_ENV_PART != 1) + return false; + + return mmc_offset(mmc, 0) == mmc_offset(mmc, 1); +} + __weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) { s64 offset = mmc_offset(mmc, copy); @@ -336,7 +341,7 @@ static int env_mmc_save(void) if (gd->env_valid == ENV_VALID) copy = 1; - if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) { + if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) { ret = mmc_set_env_part(mmc, copy + 1); if (ret) goto fini; @@ -409,7 +414,7 @@ static int env_mmc_erase(void) if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) { copy = 1; - if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) { + if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) { ret = mmc_set_env_part(mmc, copy + 1); if (ret) goto fini; @@ -443,13 +448,7 @@ static inline int read_env(struct mmc *mmc, unsigned long size, return (n == blk_cnt) ? 0 : -1; } -#if defined(ENV_IS_EMBEDDED) -static int env_mmc_load(void) -{ - return 0; -} -#elif defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) -static int env_mmc_load(void) +static int env_mmc_load_redundant(void) { struct mmc *mmc; u32 offset1, offset2; @@ -477,7 +476,7 @@ static int env_mmc_load(void) goto fini; } - if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) { + if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) { ret = mmc_set_env_part(mmc, 1); if (ret) goto fini; @@ -485,7 +484,7 @@ static int env_mmc_load(void) read1_fail = read_env(mmc, CONFIG_ENV_SIZE, offset1, tmp_env1); - if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) { + if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) { ret = mmc_set_env_part(mmc, 2); if (ret) goto fini; @@ -505,8 +504,8 @@ err: return ret; } -#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */ -static int env_mmc_load(void) + +static int env_mmc_load_singular(void) { ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); struct mmc *mmc; @@ -551,7 +550,16 @@ err: return ret; } -#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ + +static int env_mmc_load(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_EMBEDDED)) + return 0; + else if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) + return env_mmc_load_redundant(); + else + return env_mmc_load_singular(); +} U_BOOT_ENV_LOCATION(mmc) = { .location = ENVL_MMC, diff --git a/examples/api/Makefile b/examples/api/Makefile index 722c7e45904..be97b8015bd 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -5,26 +5,9 @@ # Provide symbol API_BUILD to signal that the API example is being built. KBUILD_CPPFLAGS += -DAPI_BUILD -ifeq ($(ARCH),powerpc) -LOAD_ADDR = 0x40000 -endif -ifeq ($(ARCH),arm) -ifdef CONFIG_64BIT -LOAD_ADDR = 0x40400000 -else -LOAD_ADDR = 0x1000000 -endif -endif -ifeq ($(ARCH),mips) -ifdef CONFIG_64BIT -LOAD_ADDR = 0xffffffff80200000 -else -LOAD_ADDR = 0x80200000 -endif -endif -ifeq ($(ARCH),riscv) -LOAD_ADDR = 0x84000000 -endif +# Environment variable loadaddr is set from CONFIG_SYS_LOAD_ADDR. +# Run the examples 4 MiB above this address. +LOAD_ADDR:=${shell printf 0x%X $$(( $(CONFIG_SYS_LOAD_ADDR) + 0x400000 ))} # Resulting ELF and binary exectuables will be named demo and demo.bin extra-y = demo diff --git a/examples/api/crt0.S b/examples/api/crt0.S index d2a97557817..6899ebf8ac2 100644 --- a/examples/api/crt0.S +++ b/examples/api/crt0.S @@ -29,15 +29,17 @@ syscall: .text .globl _start _start: - ldr ip, =search_hint - str sp, [ip] + ldr r4, =search_hint + mov r5, sp + str r5, [r4] b main .globl syscall syscall: - ldr ip, =syscall_ptr - ldr pc, [ip] + ldr r4, =syscall_ptr + ldr r4, [r4] + bx r4 #elif defined(CONFIG_ARM64) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 559170dd5c9..9b57f1c0c66 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -7,6 +7,10 @@ extra-y := hello_world extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2 extra-$(CONFIG_PPC) += sched +# Environment variable loadaddr is set from CONFIG_SYS_LOAD_ADDR. +# Run the examples 4 MiB above this address. +LOAD_ADDR:=${shell printf 0x%X $$(( $(CONFIG_SYS_LOAD_ADDR) + 0x400000 ))} + # # Some versions of make do not handle trailing white spaces properly; # leading to build failures. The problem was found with GNU Make 3.80. @@ -46,7 +50,7 @@ endif # source file. ccflags-y += $(call cc-option,-fno-toplevel-reorder) -LDFLAGS_STANDALONE += -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) +LDFLAGS_STANDALONE += -Ttext $(LOAD_ADDR) ######################################################################### diff --git a/fs/erofs/fs.c b/fs/erofs/fs.c index 7bd2e8fcfc5..dcdc883e34c 100644 --- a/fs/erofs/fs.c +++ b/fs/erofs/fs.c @@ -59,16 +59,19 @@ struct erofs_dir_stream { static int erofs_readlink(struct erofs_inode *vi) { - size_t len = vi->i_size; + size_t alloc_size; char *target; int err; - target = malloc(len + 1); + if (__builtin_add_overflow(vi->i_size, 1, &alloc_size)) + return -EFSCORRUPTED; + + target = malloc(alloc_size); if (!target) return -ENOMEM; - target[len] = '\0'; + target[vi->i_size] = '\0'; - err = erofs_pread(vi, target, len, 0); + err = erofs_pread(vi, target, vi->i_size, 0); if (err) goto err_out; diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index b9314019b1b..8fac6c6c5a9 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -719,6 +719,7 @@ static int sqfs_read_inode_table(unsigned char **inode_table) u32 src_len, dest_offset = 0; unsigned long dest_len = 0; bool compressed; + size_t buf_size; table_size = get_unaligned_le64(&sblk->directory_table_start) - get_unaligned_le64(&sblk->inode_table_start); @@ -728,7 +729,10 @@ static int sqfs_read_inode_table(unsigned char **inode_table) sblk->directory_table_start, &table_offset); /* Allocate a proper sized buffer (itb) to store the inode table */ - itb = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); + if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size)) + return -EINVAL; + + itb = malloc_cache_aligned(buf_size); if (!itb) return -ENOMEM; @@ -806,6 +810,7 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) u32 src_len, dest_offset = 0; unsigned long dest_len = 0; bool compressed; + size_t buf_size; *dir_table = NULL; *pos_list = NULL; @@ -818,7 +823,10 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) sblk->fragment_table_start, &table_offset); /* Allocate a proper sized buffer (dtb) to store the directory table */ - dtb = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); + if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size)) + return -EINVAL; + + dtb = malloc_cache_aligned(buf_size); if (!dtb) return -ENOMEM; @@ -1369,6 +1377,7 @@ static int sqfs_read_nest(const char *filename, void *buf, loff_t offset, unsigned long dest_len; struct fs_dirent *dent; unsigned char *ipos; + size_t buf_size; *actread = 0; @@ -1573,7 +1582,10 @@ static int sqfs_read_nest(const char *filename, void *buf, loff_t offset, table_offset = frag_entry.start - (start * ctxt.cur_dev->blksz); n_blks = DIV_ROUND_UP(table_size + table_offset, ctxt.cur_dev->blksz); - fragment = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); + if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size)) + return -EINVAL; + + fragment = malloc_cache_aligned(buf_size); if (!fragment) { ret = -ENOMEM; diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h index b6bca53db10..3fd5c772a1a 100644 --- a/include/asm-generic/sections.h +++ b/include/asm-generic/sections.h @@ -67,6 +67,9 @@ extern char __text_start[]; /* This marks the text region which must be relocated */ extern char __image_copy_start[], __image_copy_end[]; +/* This marks the rcode region used for SPL relocation */ +extern char _rcode_start[], _rcode_end[]; + extern char __bss_end[]; extern char __rel_dyn_start[], __rel_dyn_end[]; extern char _image_binary_end[]; @@ -77,4 +80,17 @@ extern char _image_binary_end[]; */ extern void _start(void); +#ifndef USE_HOSTCC +#if CONFIG_IS_ENABLED(RELOC_LOADER) +#define __rcode __section(".text.rcode") +#define __rdata __section(".text.rdata") +#else +#define __rcode +#define __rdata +#endif +#else +#define __rcode +#define __rdata +#endif + #endif /* _ASM_GENERIC_SECTIONS_H_ */ diff --git a/include/bloblist.h b/include/bloblist.h index 52ba0ddcf84..f32faf78560 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -467,9 +467,8 @@ int bloblist_reloc(void *to, uint to_size); * If CONFIG_BLOBLIST_ALLOC is selected, it allocates memory for a bloblist of * size CONFIG_BLOBLIST_SIZE. * - * If CONFIG_BLOBLIST_PASSAGE is selected, it uses the bloblist in the incoming - * standard passage. The size is detected automatically so CONFIG_BLOBLIST_SIZE - * can be 0. + * If CONFIG_BLOBLIST_PASSAGE_MANDATORY is selected, bloblist in the incoming + * standard passage is mandatorily required. * * Sets GD_FLG_BLOBLIST_READY in global_data flags on success * @@ -481,7 +480,7 @@ int bloblist_init(void); /** * bloblist_maybe_init() - Init the bloblist system if not already done * - * Calls bloblist_init() if the GD_FLG_BLOBLIST_READY flag is not et + * Calls bloblist_init() if the GD_FLG_BLOBLIST_READY flag is not set * * Return: 0 if OK, -ve on error */ @@ -501,19 +500,18 @@ static inline int bloblist_maybe_init(void) * @rfdt: Register that holds the FDT base address. * @rzero: Register that must be zero. * @rsig: Register that holds signature and register conventions version. + * @xlist: Register that holds the transfer list. * Return: 0 if OK, -EIO if the bloblist is not compliant to the register * conventions. */ -int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig); +int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig, ulong xlist); /** - * xferlist_from_boot_arg() - Get bloblist from the boot args and relocate it - * to the specified address. + * xferlist_from_boot_arg() - Get bloblist from the boot args. * - * @addr: Address for the bloblist - * @size: Size of space reserved for the bloblist + * @addr: Address of the bloblist * Return: 0 if OK, else on error */ -int xferlist_from_boot_arg(ulong addr, ulong size); +int xferlist_from_boot_arg(ulong *addr); #endif /* __BLOBLIST_H */ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index 96efd38594a..385dec2ff4f 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -63,11 +63,6 @@ "fi; " \ "setenv extrabootargs $extrabootargs \"swi_attached\"; " \ "fi;" \ - "run bootcmd_ubifs0;\0" \ - "altbootcmd=" \ - "setenv boot_syslinux_conf \"extlinux/extlinux-rollback.conf\"; " \ - "run distro_bootcmd; " \ - "setenv boot_syslinux_conf \"extlinux/extlinux.conf\"; " \ "run bootcmd_ubifs0;\0" #endif /* ! CONFIG_XPL_BUILD */ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 5df8d03c706..6d24c5decd5 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -16,8 +16,6 @@ #define BK4_EXTRA_ENV_SETTINGS \ "bootlimit=3\0" \ "eraseuserdata=false\0" \ - "altbootcmd=led 5 on; " \ - "boot\0" \ "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ "set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \ "set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index d01f0d37316..93559a171ae 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -64,7 +64,6 @@ BUR_COMMON_ENV \ " do echo \"### booting ${target} ###\"; run b_${target};" \ " if test ${b_break} = 1; then; exit; fi; done\0" \ "loaddev=mmc 0\0" \ -"altbootcmd=setenv b_mode 0; run b_default;\0" \ "bootlimit=1\0" \ "net2nor=sf probe && dhcp &&" \ " tftp ${loadaddr} SPL && sf erase 0 +${filesize} &&" \ diff --git a/include/configs/display5.h b/include/configs/display5.h index 51fa2b03a2e..98b1e5af2c0 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -170,7 +170,6 @@ "display=tianma-tm070-800x480\0" \ "board=display5\0" \ "mmcdev=0\0" \ - "altbootcmd=run recovery\0" \ "bootdelay=1\0" \ "baudrate=115200\0" \ "ethact=FEC\0" \ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index f3d85c9c11e..5e3f67124c0 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -82,14 +82,6 @@ "doboot=" \ "echo Booting from mmc:${mmcdev}:${mmcpart} ...; " \ "run helix;\0" \ - "altbootcmd=" \ - "setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \ - "run hasfirstboot || setenv mmcpart 0; " \ - "if test ${mmcpart} != 0; then " \ - "setenv bootcause REVERT; " \ - "run swappartitions loadimage doboot; " \ - "fi; " \ - "run failbootcmd\0" \ "tryboot=" \ "setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \ "run loadimage || run swappartitions && run loadimage || " \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 07b36706e56..c8ef048bd43 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -67,14 +67,6 @@ "Try again, or contact GE Service for support.\"; " \ "bootcount reset; " \ "while true; do sleep 1; done; \0" \ - "altbootcmd=" \ - "run doquiet; " \ - "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ - "run hasfirstboot || setenv partnum 0; " \ - "if test ${partnum} != 0; then " \ - "run swappartitions loadimage doboot; " \ - "fi; " \ - "run failbootcmd\0" \ "loadimage=" \ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ "doboot=" \ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 786b70fe064..3d5701c636c 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -47,7 +47,6 @@ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ "loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \ - "altbootcmd=run recoveryboot\0"\ "fitboot=echo Booting FIT image from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 64ddbf711d3..84da8250684 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -42,8 +42,7 @@ "env_persisted=0\0" \ "env_persist=if test ${env_persisted} != 1; " \ "then env set env_persisted 1; run save_env; fi;\0" \ - "save_env=env save; env save\0" \ - "altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0" + "save_env=env save; env save\0" #define CFG_ENV_FLAGS_LIST_STATIC \ "bootset:bw," \ diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h index 7058d632d67..626ccae7205 100644 --- a/include/configs/imx8mm-mx8menlo.h +++ b/include/configs/imx8mm-mx8menlo.h @@ -18,14 +18,6 @@ "devtype=mmc\0" \ "devnum=1\0" \ "distro_bootpart=1\0" \ - "altbootcmd=" \ - "mmc partconf 0 mmcpart ; " \ - "if test ${mmcpart} -eq 1 ; then " \ - "mmc partconf 0 1 2 0 ; " \ - "else " \ - "mmc partconf 0 1 1 0 ; " \ - "fi ; " \ - "boot\0" \ "boot_file=fitImage\0" \ "console=ttymxc0\0" \ "fdt_addr=0x43000000\0" \ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 57ecb5e2190..5ce4219912f 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -34,7 +34,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h index de5bdd30e18..58a03b35ac4 100644 --- a/include/configs/imx8mp_data_modul_edm_sbc.h +++ b/include/configs/imx8mp_data_modul_edm_sbc.h @@ -24,7 +24,6 @@ #define FEC_QUIRK_ENET_MAC #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index c848fce8bda..f3e239d780f 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -28,7 +28,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=run bootcmd ; reset\0" \ "bootlimit=3\0" \ "dfu_alt_info=" \ /* RAM block at DRAM offset 256..768 MiB */ \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 1ea4fa59fd5..a6aafb51854 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -93,13 +93,6 @@ "splashfile=boot/usplash.bmp.gz\0" \ "splashimage=0x88000000\0" \ "splashpos=m,m\0" \ - "altbootcmd=" \ - "if test ${mmcpart} -eq 1 ; then " \ - "setenv mmcpart 2 ; " \ - "else " \ - "setenv mmcpart 1 ; " \ - "fi ; " \ - "boot\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" \ "addcons=" \ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 5ced45b88b2..0077f6a5f95 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -26,6 +26,7 @@ "scriptaddr=0x88100000\0" \ "pxefile_addr_r=0x88200000\0" \ "ramdisk_addr_r=0x88300000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 6d1f669de50..3707de254e1 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -59,14 +59,6 @@ "Try again, or contact GE Service for support.\"; " \ "bootcount reset; " \ "while true; do sleep 1; done; \0" \ - "altbootcmd=" \ - "run doquiet; " \ - "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ - "run hasfirstboot || setenv partnum 0; " \ - "if test ${partnum} != 0; then " \ - "run swappartitions loadimage doboot; " \ - "fi; " \ - "run failbootcmd\0" \ "loadimage=" \ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ "doboot=" \ diff --git a/include/configs/picasso.h b/include/configs/picasso.h new file mode 100644 index 00000000000..a58c7e5f353 --- /dev/null +++ b/include/configs/picasso.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2024 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/s4sk.h b/include/configs/s4sk.h new file mode 100644 index 00000000000..a1707359a39 --- /dev/null +++ b/include/configs/s4sk.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This file is S4SK board configuration. + * + * Copyright (C) 2024-2025 Renesas Electronics Corp. + */ + +#ifndef __S4SK_H +#define __S4SK_H + +#include "rcar-gen4-common.h" + +#endif /* __S4SK_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 74b7fe85800..a918dc1350c 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -128,7 +128,6 @@ "verify=no \0" \ "project_dir=targetdir\0" \ "upgrade_available=0\0" \ - "altbootcmd=run bootcmd\0" \ "partitionset_active=A\0" \ "loadaddr=0x82000000\0" \ "kloadaddr=0x81000000\0" \ diff --git a/include/configs/siemens-env-common.h b/include/configs/siemens-env-common.h index 36fa5d936f7..c028823e1eb 100644 --- a/include/configs/siemens-env-common.h +++ b/include/configs/siemens-env-common.h @@ -183,7 +183,6 @@ "rootfs_name=/dev/mmcblk0\0" \ "upgrade_available=0\0" \ "bootlimit=3\0" \ - "altbootcmd=run bootcmd\0" \ "optargs=\0" \ /**********************************************************************/ diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index df8ed451a43..8ea708d0e92 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -58,8 +58,7 @@ "boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \ "boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \ "boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \ - "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \ - "altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0" + "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" /* Console settings */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index b7ee1dbf201..5ed17671f79 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 * * Copyright (C) 2017-2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -56,6 +57,11 @@ #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ "bootcmd_qspi=ubi detach; sf probe && " \ + "setenv mtdids 'nor0=nor0,nand0=nand.0' && " \ + "setenv mtdparts 'mtdparts=nor0:66m(u-boot),190m(root); " \ + "nand.0:2m(nand_uboot),500m(nand_root)' && " \ + "env select UBI; saveenv && " \ + "ubi part root && " \ "if ubi part root && ubi readvol ${scriptaddr} script; " \ "then echo QSPI: Running script from UBIFS; " \ "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 26b6c1cd188..39102f15eb9 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -239,20 +239,47 @@ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" +#define GET_OVERLAY_MMC_TI_ARGS \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} &&" \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + #define BOOT_TARGET_DEVICES(func) \ + func(TI_MMC, ti_mmc, na) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) +#define BOOTENV_DEV_TI_MMC(devtypeu, devtypel, instance) \ + "bootcmd_ti_mmc= run get_name_kern; run mmcboot\0" + +#define BOOTENV_DEV_NAME_TI_MMC(devtyeu, devtypel, instance) \ + "ti_mmc " + #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "get_name_kern=" \ + "if test $boot_fit -eq 1; then " \ + "setenv bootfile fitImage; " \ + "else " \ + "setenv bootfile zImage; " \ + "fi\0" \ DEFAULT_FIT_TI_ARGS \ + "get_fit_config=setenv name_fit_config ${fdtfile}\0" \ DEFAULT_COMMON_BOOT_TI_ARGS \ DEFAULT_FDT_TI_ARGS \ + GET_OVERLAY_MMC_TI_ARGS \ DFUARGS \ NETARGS \ NANDARGS \ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index b5a17f93efc..5eee13b3fc0 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -181,12 +181,14 @@ " if load hostfs - ${kernel_addr_r} ${kernel_name}; then" \ " setenv fdt_high 0xffffffffffffffff;" \ " setenv initrd_high 0xffffffffffffffff;" \ - " load hostfs - ${fdt_addr_r} ${fdtfile};" \ + " if test -n load hostfs - ${fdt_addr_r} ${fdtfile}; then" \ + " fdt move $fdtcontroladdr $fdt_addr_r;" \ + " fi;" \ " load hostfs - ${ramdisk_addr_r} ${ramdisk_name};" \ " fdt addr ${fdt_addr_r};" \ " fdt resize;" \ " fdt chosen ${ramdisk_addr_r} ${filesize};" \ - " booti $kernel_addr_r - $fdt_addr_r;" \ + " booti $kernel_addr_r - ${fdt_addr_r};" \ " fi;" \ "fi\0" #define BOOTENV_DEV_NAME_SMH(devtypeu, devtypel, instance) "smh " diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index bb0db7c5ca3..13941ba3589 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -179,6 +179,7 @@ #ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ + "usb_pgood_delay=1000\0" \ BOOTENV #endif diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h deleted file mode 100644 index 2c0552d1a93..00000000000 --- a/include/dt-bindings/clock/rk3036-cru.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_GPLL 3 -#define ARMCLK 4 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI 65 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_NANDC 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_OTGPHY0 93 -#define SCLK_LCDC 100 -#define SCLK_HDMI 109 -#define SCLK_HEVC 111 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_VIDEO 125 -#define SCLK_MAC 151 -#define SCLK_MACREF 152 -#define SCLK_SFC 160 - -#define DCLK_LCDC 190 - -/* aclk gates */ -#define ACLK_DMAC2 194 -#define ACLK_LCDC 197 -#define ACLK_VIO 203 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_SPI 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_HDMI 360 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_WDT 368 - -/* hclk gates */ -#define HCLK_OTG0 449 -#define HCLK_OTG1 450 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_I2S 462 -#define HCLK_LCDC 465 -#define HCLK_ROM 467 -#define HCLK_VIO_BUS 472 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE0_DBG 4 -#define SRST_CORE1_DBG 5 -#define SRST_CORE0_POR 8 -#define SRST_CORE1_POR 9 -#define SRST_L2C 12 -#define SRST_TOPDBG 13 -#define SRST_STRC_SYS_A 14 -#define SRST_PD_CORE_NIU 15 - -#define SRST_TIMER2 16 -#define SRST_CPUSYS_H 17 -#define SRST_AHB2APB_H 19 -#define SRST_TIMER3 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S 24 -#define SRST_DDR_PLL 25 -#define SRST_GPU_DLL 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_CORE_DLL 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_SFC 47 - -#define SRST_PWM0 48 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_GRF 55 -#define SRST_PERIPHSYS_A 57 -#define SRST_PERIPHSYS_H 58 -#define SRST_PERIPHSYS_P 59 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_MAC 66 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_MMC0 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_WDT 86 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 - -#define SRST_HDMI_P 96 -#define SRST_VIO_BUS_H 99 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_LCDC1_A 117 -#define SRST_LCDC1_H 118 -#define SRST_LCDC1_D 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 - -#define SRST_DBG_P 131 - -#endif diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h deleted file mode 100644 index 453f66718c6..00000000000 --- a/include/dt-bindings/clock/rk3288-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_SDIO1 70 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_PS2C 74 -#define SCLK_NANDC0 75 -#define SCLK_NANDC1 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S0 82 -#define SCLK_SPDIF 83 -#define SCLK_SPDIF8CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 -#define SCLK_HSADC 92 -#define SCLK_OTGPHY0 93 -#define SCLK_OTGPHY1 94 -#define SCLK_OTGPHY2 95 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_LCDC_PWM0 100 -#define SCLK_LCDC_PWM1 101 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_ISP_JPE 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S0_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_SDIO1_DRV 116 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_SDIO1_SAMPLE 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M_SRC 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_CRYPTO 125 -#define SCLK_MIPIDSI_24M 126 -#define SCLK_VIP_OUT 127 - -#define SCLK_MAC_PLL 150 -#define SCLK_MAC 151 -#define SCLK_MACREF_OUT 152 - -#define DCLK_VOP0 190 -#define DCLK_VOP1 191 - -/* aclk gates */ -#define ACLK_GPU 192 -#define ACLK_DMAC1 193 -#define ACLK_DMAC2 194 -#define ACLK_MMU 195 -#define ACLK_GMAC 196 -#define ACLK_VOP0 197 -#define ACLK_VOP1 198 -#define ACLK_CRYPTO 199 -#define ACLK_RGA 200 -#define ACLK_RGA_NIU 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NIU 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NIU 206 -#define ACLK_HEVC 207 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_GPIO4 324 -#define PCLK_GPIO5 325 -#define PCLK_GPIO6 326 -#define PCLK_GPIO7 327 -#define PCLK_GPIO8 328 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM 350 -#define PCLK_RKPWM 351 -#define PCLK_PS2C 352 -#define PCLK_TIMER 353 -#define PCLK_TZPC 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_DSI1 357 -#define PCLK_MIPI_CSI 358 -#define PCLK_LVDS_PHY 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO2_H2P 361 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL0 364 -#define PCLK_PUBL0 365 -#define PCLK_DDRUPCTL1 366 -#define PCLK_PUBL1 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 -#define PCLK_EFUSE1024 370 -#define PCLK_ISP_IN 371 - -/* hclk gates */ -#define HCLK_GPS 448 -#define HCLK_OTG0 449 -#define HCLK_USBHOST0 450 -#define HCLK_USBHOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_NANDC1 454 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_SDIO1 458 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S0 462 -#define HCLK_SPDIF 463 -#define HCLK_SPDIF8CH 464 -#define HCLK_VOP0 465 -#define HCLK_VOP1 466 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NIU 472 -#define HCLK_VIP 473 -#define HCLK_VIO2_H2P 474 -#define HCLK_HEVC 475 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE2 2 -#define SRST_CORE3 3 -#define SRST_CORE0_PO 4 -#define SRST_CORE1_PO 5 -#define SRST_CORE2_PO 6 -#define SRST_CORE3_PO 7 -#define SRST_PDCORE_STRSYS 8 -#define SRST_PDBUS_STRSYS 9 -#define SRST_L2C 10 -#define SRST_TOPDBG 11 -#define SRST_CORE0_DBG 12 -#define SRST_CORE1_DBG 13 -#define SRST_CORE2_DBG 14 -#define SRST_CORE3_DBG 15 - -#define SRST_PDBUG_AHB_ARBITOR 16 -#define SRST_EFUSE256 17 -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_TIMER 22 -#define SRST_I2S0 23 -#define SRST_SPDIF 24 -#define SRST_TIMER0 25 -#define SRST_TIMER1 26 -#define SRST_TIMER2 27 -#define SRST_TIMER3 28 -#define SRST_TIMER4 29 -#define SRST_TIMER5 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_GPIO5 37 -#define SRST_GPIO6 38 -#define SRST_GPIO7 39 -#define SRST_GPIO8 40 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_CCP 71 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_NANDC1 78 - -#define SRST_TZPC 80 -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIO1_NIU_AXI 103 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP 111 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO_H2P 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDSI1 116 -#define SRST_MIPICSI 117 -#define SRST_LVDS_PHY 118 -#define SRST_LVDS_CON 119 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_SDIO1 130 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBHOST1_AHB 138 -#define SRST_USBHOST1_PHY 139 -#define SRST_USBHOST1_CON 140 -#define SRST_USB_ADP 141 -#define SRST_ACC_EFUSE 142 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_PD_CORE_MP_AXI 147 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_LCDC_PWM1 150 -#define SRST_VIO0_H2P_BRG 151 -#define SRST_VIO1_H2P_BRG 152 -#define SRST_RGA_H2P_BRG 153 -#define SRST_HEVC 154 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_DDRPHY0_CTRL 164 -#define SRST_DDRPHY1 165 -#define SRST_DDRPHY1_APB 166 -#define SRST_DDRCTRL1 167 -#define SRST_DDRCTRL1_APB 168 -#define SRST_DDRPHY1_CTRL 169 -#define SRST_DDRMSCH0 170 -#define SRST_DDRMSCH1 171 -#define SRST_CRYPTO 174 -#define SRST_C2C_HOST 175 - -#define SRST_LCDC1_AXI 176 -#define SRST_LCDC1_AHB 177 -#define SRST_LCDC1_DCLK 178 -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_PS2C 187 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 -#define SRST_TSP_CLKIN1 190 -#define SRST_TSP_27M 191 - -#endif diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h deleted file mode 100644 index 546ffbaf7b4..00000000000 --- a/include/dwc3-sti-glue.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. - */ - -#ifndef __DWC3_STI_UBOOT_H_ -#define __DWC3_STI_UBOOT_H_ - -/* glue registers */ -#include <linux/bitops.h> -#define CLKRST_CTRL 0x00 -#define AUX_CLK_EN BIT(0) -#define SW_PIPEW_RESET_N BIT(4) -#define EXT_CFG_RESET_N BIT(8) - -#define XHCI_REVISION BIT(12) - -#define USB2_VBUS_MNGMNT_SEL1 0x2C -#define USB2_VBUS_UTMIOTG 0x1 - -#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0) -#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4) -#define SEL_OVERRIDE_BVALID(n) ((n) << 8) - -/* Static DRD configuration */ -#define USB3_CONTROL_MASK 0xf77 - -#define USB3_DEVICE_NOT_HOST BIT(0) -#define USB3_FORCE_VBUSVALID BIT(1) -#define USB3_DELAY_VBUSVALID BIT(2) -#define USB3_SEL_FORCE_OPMODE BIT(4) -#define USB3_FORCE_OPMODE(n) ((n) << 5) -#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) -#define USB3_FORCE_DPPULLDOWN2 BIT(9) -#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) -#define USB3_FORCE_DMPULLDOWN2 BIT(11) - -int sti_dwc3_init(enum usb_dr_mode mode); - -#endif /* __DWC3_STI_UBOOT_H_ */ diff --git a/include/efi_loader.h b/include/efi_loader.h index dcae6a731a0..1d75d97ebbc 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -852,21 +852,6 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, /* Adds a range into the EFI memory map */ efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type); -/** - * efi_add_memory_map_pg() - add pages to the memory map - * - * @start: start address, must be a multiple of - * EFI_PAGE_SIZE - * @pages: number of pages to add - * @memory_type: type of memory added - * @overlap_conventional: region may only overlap free(conventional) - * memory - * Return: status code - */ -efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, - int memory_type, - bool overlap_conventional); - /* Called by board init to initialize the EFI drivers */ efi_status_t efi_driver_init(void); /* Called when a block device is added */ @@ -1264,6 +1249,21 @@ efi_status_t efi_disk_get_device_name(const efi_handle_t handle, char *buf, int void efi_add_known_memory(void); /** + * efi_map_update_notify() - notify EFI of memory map changes + * + * @addr: start of memory area + * @size: size of memory area + * @op: type of change + * Return: 0 if change could be processed + */ +#ifdef CONFIG_EFI_LOADER +int efi_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op); +#else +#define efi_map_update_notify(addr, size, op) (0) +#endif + +/** * efi_load_option_dp_join() - join device-paths for load option * * @dp: in: binary device-path, out: joined device-path diff --git a/include/env/pg-wcom/common.env b/include/env/pg-wcom/common.env index 4b660cebd67..5f2ba1c4090 100644 --- a/include/env/pg-wcom/common.env +++ b/include/env/pg-wcom/common.env @@ -22,7 +22,6 @@ add_default=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${ WCOM_UBI_LINUX_MTD addpanic=setenv bootargs ${bootargs} panic=1 panic_on_oops=1 -altbootcmd=run bootcmd backup_bank=0 boot=bootm ${load_addr_r} - ${fdt_addr_r} diff --git a/include/env/phytec/k3_mmc.env b/include/env/phytec/k3_mmc.env index ad8d3a8b764..3f67e312f65 100644 --- a/include/env/phytec/k3_mmc.env +++ b/include/env/phytec/k3_mmc.env @@ -11,6 +11,7 @@ mmcargs=setenv bootargs console=${console} earlycon=${earlycon} root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw + ${optargs} mmcloadimage=load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} Image mmcloadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} mmcboot=if test ${doraucboot} = 1; then run raucinit; fi; diff --git a/include/env/phytec/k3_net.env b/include/env/phytec/k3_net.env index 377e406688d..8ad1cb7b0c2 100644 --- a/include/env/phytec/k3_net.env +++ b/include/env/phytec/k3_net.env @@ -9,7 +9,7 @@ #include <env/phytec/overlays.env> netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp rw - nfsroot=${serverip}:${nfsroot},vers=4,tcp + nfsroot=${serverip}:${nfsroot},vers=4,tcp ${optargs} netloadimage=${net_fetch_cmd} ${kernel_addr_r} ${serverip}:/Image netloadfdt=${net_fetch_cmd} ${fdt_addr_r} ${serverip}:/${fdtfile} netboot=run netargs; diff --git a/include/env/phytec/k3_spi.env b/include/env/phytec/k3_spi.env index 97d3a157058..8e9cfce3b4c 100644 --- a/include/env/phytec/k3_spi.env +++ b/include/env/phytec/k3_spi.env @@ -6,7 +6,7 @@ /* Logic for TI K3 based SoCs to boot from an OSPI/QSPI NOR flash. */ -spiargs=setenv bootargs console=${console} earlycon=${earlycon} +spiargs=setenv bootargs console=${console} earlycon=${earlycon} ${optargs} spiloadimage=sf read ${kernel_addr_r} ${spi_image_addr} ${size_kern} spiloadfdt=sf read ${fdt_addr_r} ${spi_fdt_addr} ${size_fdt} spiloadramdisk=sf read ${ramdisk_addr_r} ${spi_ramdisk_addr} ${size_fs} diff --git a/include/env/ti/mmc.h b/include/env/ti/mmc.h index d07189baaf4..dbb0e3559ea 100644 --- a/include/env/ti/mmc.h +++ b/include/env/ti/mmc.h @@ -44,6 +44,7 @@ "mmcloados=" \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ + "run get_overlay_mmc;" \ "bootz ${loadaddr} - ${fdtaddr}; " \ "else " \ "if test ${boot_fdt} = try; then " \ diff --git a/include/env_default.h b/include/env_default.h index aa3dd40f3fa..60c39f9853f 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -115,6 +115,9 @@ const char default_environment[] = { #if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0) "bootlimit=" __stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0" #endif +#ifdef CONFIG_BOOTCOUNT_ALTBOOTCMD + "altbootcmd=" CONFIG_BOOTCOUNT_ALTBOOTCMD "\0" +#endif #ifdef CONFIG_MTDIDS_DEFAULT "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" #endif diff --git a/include/fpga.h b/include/fpga.h index 44f2755a3f1..4cc44164b2f 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -58,7 +58,7 @@ typedef enum { void fpga_init(void); int fpga_add(fpga_type devtype, void *desc); int fpga_count(void); -const fpga_desc *const fpga_get_desc(int devnum); +const fpga_desc *fpga_get_desc(int devnum); int fpga_is_partial_data(int devnum, size_t img_len); #if CONFIG_IS_ENABLED(FPGA) int fpga_load(int devnum, const void *buf, size_t bsize, @@ -78,8 +78,8 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype); int fpga_dump(int devnum, const void *buf, size_t bsize); int fpga_info(int devnum); -const fpga_desc *const fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn); +const fpga_desc *fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn); int fpga_compatible2flag(int devnum, const char *compatible); #endif /* _FPGA_H_ */ diff --git a/include/image.h b/include/image.h index 8a9f779d3ff..c1db8383459 100644 --- a/include/image.h +++ b/include/image.h @@ -232,6 +232,7 @@ enum image_type_t { IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */ IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */ IH_TYPE_STARFIVE_SPL, /* StarFive SPL image */ + IH_TYPE_TFA_BL31, /* TFA BL31 image */ IH_TYPE_COUNT, /* Number of image types */ }; @@ -1687,6 +1688,24 @@ struct sig_header_s { */ int image_pre_load(ulong addr); +#if defined(USE_HOSTCC) +/** + * rsa_verify_openssl() - Verify a signature against some data with openssl API + * + * Verify a RSA PKCS1.5/PSS signature against an expected hash. + * + * @info: Specifies the key and algorithms + * @region: Pointer to the input data + * @region_count: Number of region + * @sig: Signature + * @sig_len: Number of bytes in the signature + * Return: 0 if verified, -ve on error + */ +int rsa_verify_openssl(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t *sig, uint sig_len); +#endif + /** * fit_image_verify_required_sigs() - Verify signatures marked as 'required' * diff --git a/include/led.h b/include/led.h index 64247cd3a70..2a7f38bf84b 100644 --- a/include/led.h +++ b/include/led.h @@ -53,6 +53,11 @@ struct udevice; +/* + * value imported from linux:include/linux/uapi/linux/uleds.h + */ +#define LED_MAX_NAME_SIZE 64 + enum led_state_t { LEDST_OFF = 0, LEDST_ON = 1, @@ -81,11 +86,14 @@ struct led_sw_blink { * * @label: LED label * @default_state: LED default state + * @name: LED name, derived from function, color or function-enumerator + * property. * @sw_blink: LED software blink struct */ struct led_uc_plat { const char *label; enum led_state_t default_state; + char name[LED_MAX_NAME_SIZE]; #ifdef CONFIG_LED_SW_BLINK struct led_sw_blink *sw_blink; #endif diff --git a/include/linux/string.h b/include/linux/string.h index 27b2beb9ddb..d943fcce690 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -72,6 +72,9 @@ extern char * strrchr(const char *,int); #ifndef __HAVE_ARCH_STRSTR extern char * strstr(const char *,const char *); #endif +#ifndef __HAVE_ARCH_STRNSTR +extern char *strnstr(const char *, const char *, size_t); +#endif #ifndef __HAVE_ARCH_STRLEN extern __kernel_size_t strlen(const char *); #endif diff --git a/include/lmb.h b/include/lmb.h index d9d7435a431..09297a4f530 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -32,6 +32,18 @@ #define LMB_NONOTIFY BIT(2) /** + * enum lmb_map_op - memory map operation + */ +enum lmb_map_op { + /** @LMB_MAP_OP_RESERVE: reserve memory */ + LMB_MAP_OP_RESERVE = 1, + /** @LMB_MAP_OP_FREE: free memory */ + LMB_MAP_OP_FREE, + /** @LMB_MAP_OP_ADD: add memory */ + LMB_MAP_OP_ADD, +}; + +/** * struct lmb_region - Description of one region * @base: Base address of the region * @size: Size of the region diff --git a/include/miiphy.h b/include/miiphy.h index 1e6c7041fdc..b879fd16ae3 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -44,6 +44,7 @@ struct phy_device *mdio_phydev_for_ethname(const char *devname); void miiphy_listdev(void); +void mdio_init(struct mii_dev *bus); struct mii_dev *mdio_alloc(void); void mdio_free(struct mii_dev *bus); int mdio_register(struct mii_dev *bus); @@ -64,8 +65,6 @@ void mdio_list_devices(void); #define BB_MII_DEVNAME "bb_miiphy" struct bb_miiphy_bus { - char name[MDIO_NAME_LEN]; - int (*init)(struct bb_miiphy_bus *bus); int (*mdio_active)(struct bb_miiphy_bus *bus); int (*mdio_tristate)(struct bb_miiphy_bus *bus); int (*set_mdio)(struct bb_miiphy_bus *bus, int v); @@ -73,19 +72,11 @@ struct bb_miiphy_bus { int (*set_mdc)(struct bb_miiphy_bus *bus, int v); int (*delay)(struct bb_miiphy_bus *bus); void *priv; + struct mii_dev mii; }; -extern struct bb_miiphy_bus bb_miiphy_buses[]; -extern int bb_miiphy_buses_num; - -/** - * bb_miiphy_init() - Initialize bit-banged MII bus driver - * - * It is called during the generic post-relocation init sequence. - * - * Return: 0 if OK - */ -int bb_miiphy_init(void); +struct bb_miiphy_bus *bb_miiphy_alloc(void); +void bb_miiphy_free(struct bb_miiphy_bus *bus); int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg); int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, diff --git a/include/net-lwip.h b/include/net-lwip.h index 4d7f9387d1d..64e5c720560 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -10,6 +10,7 @@ enum proto_t { TFTPGET }; +void net_lwip_set_current(void); struct netif *net_lwip_new_netif(struct udevice *udev); struct netif *net_lwip_new_netif_noip(struct udevice *udev); void net_lwip_remove_netif(struct netif *netif); diff --git a/include/power/tps65941.h b/include/power/tps65941.h index cec85333f0b..a026ec56958 100644 --- a/include/power/tps65941.h +++ b/include/power/tps65941.h @@ -21,10 +21,11 @@ #define TPS65941_BUCK_VOLT_MAX 3340000 #define TPS65941_BUCK_MODE_MASK 0x1 -#define TPS65941_LDO_VOLT_MASK 0x3E +#define TPS65941_LDO_VOLT_MASK 0x7E #define TPS65941_LDO_VOLT_MAX_HEX 0x3A #define TPS65941_LDO_VOLT_MIN_HEX 0x4 #define TPS65941_LDO_VOLT_MAX 3300000 +#define TPS65941_LDO_VOLT_MIN 600000 #define TPS65941_LDO_MODE_MASK 0x1 #define TPS65941_LDO_BYPASS_EN 0x80 #define TP65941_BUCK_CONF_SLEW_MASK 0x7 diff --git a/include/spl.h b/include/spl.h index 7155e9c67aa..850c64d4b19 100644 --- a/include/spl.h +++ b/include/spl.h @@ -345,7 +345,7 @@ typedef ulong (*spl_load_reader)(struct spl_load_info *load, ulong sector, * @priv: Private data for the device * @bl_len: Block length for reading in bytes * @phase: Image phase to load - * @fit_loaded: true if the FIT has been loaded, except for external data + * @no_fdt_update: true to update the FDT with any loadables that are loaded */ struct spl_load_info { spl_load_reader read; @@ -355,7 +355,7 @@ struct spl_load_info { #endif #if CONFIG_IS_ENABLED(BOOTMETH_VBE) u8 phase; - u8 fit_loaded; + u8 fdt_update; #endif }; @@ -395,12 +395,20 @@ static inline enum image_phase_t xpl_get_phase(struct spl_load_info *info) #endif } -static inline bool xpl_get_fit_loaded(struct spl_load_info *info) +static inline void xpl_set_fdt_update(struct spl_load_info *info, + bool fdt_update) { #if CONFIG_IS_ENABLED(BOOTMETH_VBE) - return info->fit_loaded; + info->fdt_update = fdt_update; +#endif +} + +static inline enum image_phase_t xpl_get_fdt_update(struct spl_load_info *info) +{ +#if CONFIG_IS_ENABLED(BOOTMETH_VBE) + return info->fdt_update; #else - return false; + return true; #endif } @@ -415,6 +423,7 @@ static inline void spl_load_init(struct spl_load_info *load, load->priv = priv; spl_set_bl_len(load, bl_len); xpl_set_phase(load, IH_PHASE_NONE); + xpl_set_fdt_update(load, true); } /* diff --git a/include/spl_load.h b/include/spl_load.h index 935f7d336f2..525e0c9e86c 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -20,13 +20,15 @@ static inline int _spl_load(struct spl_image_info *spl_image, ulong base_offset, image_offset, overhead; int read, ret; + log_debug("\nloading hdr from %lx to %p\n", (ulong)offset, header); read = info->read(info, offset, ALIGN(sizeof(*header), spl_get_bl_len(info)), header); if (read < (int)sizeof(*header)) return -EIO; if (image_get_magic(header) == FDT_MAGIC) { - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) { + log_debug("Found FIT\n"); + if (CONFIG_IS_ENABLED(LOAD_FIT_FULL)) { void *buf; /* @@ -48,9 +50,12 @@ static inline int _spl_load(struct spl_image_info *spl_image, return spl_parse_image_header(spl_image, bootdev, buf); } - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) + if (CONFIG_IS_ENABLED(LOAD_FIT)) { + log_debug("Simple loading\n"); return spl_load_simple_fit(spl_image, info, offset, header); + } + log_debug("No FIT support\n"); } if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && diff --git a/include/sysinfo.h b/include/sysinfo.h index ba2ac273e8e..e87cf969fcd 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -57,6 +57,7 @@ enum sysinfo_id { SYSID_SM_SYSTEM_WAKEUP, SYSID_SM_SYSTEM_SKU, SYSID_SM_SYSTEM_FAMILY, + SYSID_SM_SYSTEM_UUID, /* Baseboard (or Module) Information (Type 2) */ SYSID_SM_BASEBOARD_MANUFACTURER, @@ -151,6 +152,8 @@ enum sysinfo_id { /* For show_board_info() */ SYSID_BOARD_MODEL, SYSID_BOARD_MANUFACTURER, + SYSID_BOARD_MAC_ADDR, + SYSID_BOARD_RAM_SIZE_MB, SYSID_PRIOR_STAGE_VERSION, SYSID_PRIOR_STAGE_DATE, @@ -221,6 +224,30 @@ struct sysinfo_ops { int (*get_data)(struct udevice *dev, int id, void **data, size_t *size); /** + * get_item_count() - Get the item count of the specific data area that + * describes the hardware setup. + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * + * Return: non-negative item count if OK, -ve on error. + */ + int (*get_item_count)(struct udevice *dev, int id); + + /** + * get_data_by_index() - Get a data value by index from the platform. + * + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * @index: The item index, starting from 0. + * @data: Pointer to the address of the data area. + * @size: Pointer to the size of the data area. + * + * Return: 0 if OK, -ve on error. + */ + int (*get_data_by_index)(struct udevice *dev, int id, int index, + void **data, size_t *size); + + /** * get_fit_loadable - Get the name of an image to load from FIT * This function can be used to provide the image names based on runtime * detection. A classic use-case would when DTBOs are used to describe @@ -304,6 +331,32 @@ int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val); int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size); /** + * sysinfo_get_item_count() - Get the item count of the specific data area that + * describes the hardware setup. + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * + * Return: non-negative item count if OK, -EPERM if called before + * sysinfo_detect(), else -ve on error. + */ +int sysinfo_get_item_count(struct udevice *dev, int id); + +/** + * sysinfo_get_data_by_index() - Get a data value by index from the platform. + * + * @dev: The sysinfo instance to gather the data. + * @id: A unique identifier for the data area to be get. + * @index: The item index, starting from 0. + * @data: Pointer to the address of the data area. + * @size: Pointer to the size of the data area. + * + * Return: 0 if OK, -EPERM if called before sysinfo_detect(), else -ve on + * error. + */ +int sysinfo_get_data_by_index(struct udevice *dev, int id, int index, + void **data, size_t *size); + +/** * sysinfo_get() - Return the sysinfo device for the sysinfo in question. * @devp: Pointer to structure to receive the sysinfo device. * @@ -364,6 +417,18 @@ static inline int sysinfo_get_data(struct udevice *dev, int id, void **data, return -ENOSYS; } +static inline int sysinfo_get_item_count(struct udevice *dev, int id) +{ + return -ENOSYS; +} + +static inline int sysinfo_get_data_by_index(struct udevice *dev, int id, + int index, void **data, + size_t *size) +{ + return -ENOSYS; +} + static inline int sysinfo_get(struct udevice **devp) { return -ENOSYS; diff --git a/include/test/fdt_overlay.h b/include/test/fdt_overlay.h new file mode 100644 index 00000000000..251ad0ec97a --- /dev/null +++ b/include/test/fdt_overlay.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2016 NextThing Co + * Copyright (c) 2016 Free Electrons + */ + +#ifndef __TEST_OVERLAY_H__ +#define __TEST_OVERLAY_H__ + +#include <test/test.h> + +/* Declare a new FDT-overlay test */ +#define FDT_OVERLAY_TEST(_name, _flags) UNIT_TEST(_name, _flags, fdt_overlay) + +/* Declare init for FDT-overlay test */ +#define FDT_OVERLAY_TEST_INIT(_name, _flags) \ + UNIT_TEST_INIT(_name, _flags, fdt_overlay) + +#endif /* __TEST_OVERLAY_H__ */ diff --git a/include/test/optee.h b/include/test/optee.h index f4255b39ee3..0a548a59e83 100644 --- a/include/test/optee.h +++ b/include/test/optee.h @@ -8,7 +8,9 @@ #include <test/test.h> -/* Declare a new environment test */ +/* Declare a new optee test */ #define OPTEE_TEST(_name, _flags) UNIT_TEST(_name, _flags, optee) +#define OPTEE_TEST_INIT(_name, _flags) UNIT_TEST_INIT(_name, _flags, optee) +#define OPTEE_TEST_UNINIT(_name, _flags) UNIT_TEST_UNINIT(_name, _flags, optee) #endif /* __TEST_OPTEE_H__ */ diff --git a/include/test/overlay.h b/include/test/overlay.h deleted file mode 100644 index 5dc98399ce7..00000000000 --- a/include/test/overlay.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 NextThing Co - * Copyright (c) 2016 Free Electrons - */ - -#ifndef __TEST_OVERLAY_H__ -#define __TEST_OVERLAY_H__ - -#include <test/test.h> - -/* Declare a new environment test */ -#define OVERLAY_TEST(_name, _flags) UNIT_TEST(_name, _flags, overlay) - -#endif /* __TEST_OVERLAY_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h deleted file mode 100644 index 774dd893378..00000000000 --- a/include/test/suites.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2015 - * Joe Hershberger, National Instruments, joe.hershberger@ni.com - */ - -#ifndef __TEST_SUITES_H__ -#define __TEST_SUITES_H__ - -struct cmd_tbl; -struct unit_test; -struct unit_test_state; - -/* 'command' functions normally called do_xxx where xxx is the command name */ -typedef int (*ut_cmd_func)(struct unit_test_state *uts, struct cmd_tbl *cmd, - int flags, int argc, char *const argv[]); - -/** - * cmd_ut_category() - Run a category of unit tests - * - * @uts: Unit-test state, which must be ready for use, i.e. ut_init_state() - * has been called. The caller is responsible for calling - * ut_uninit_state() after this function returns - * @name: Category name - * @prefix: Prefix of test name - * @tests: List of tests to run - * @n_ents: Number of tests in @tests - * @argc: Argument count provided. Must be >= 1. If this is 1 then all - * tests are run, otherwise only the one named @argv[1] is run. - * @argv: Arguments: argv[1] is the test to run (if @argc >= 2) - * Return: 0 if OK, CMD_RET_FAILURE on failure - */ -int cmd_ut_category(struct unit_test_state *uts, const char *name, - const char *prefix, struct unit_test *tests, int n_ents, - int argc, char *const argv[]); - -int do_ut_bootstd(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag, - int argc, char *const argv[]); -int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); -int do_ut_overlay(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag, - int argc, char *const argv[]); - -#endif /* __TEST_SUITES_H__ */ diff --git a/include/test/test.h b/include/test/test.h index bac43c81d63..0f2b68a5dee 100644 --- a/include/test/test.h +++ b/include/test/test.h @@ -16,11 +16,15 @@ * @skip_count: Number of tests that were skipped * @test_count: Number of tests run. If a test is run muiltiple times, only one * is counted + * @start: Timer value when test started + * @duration_ms: Suite duration in milliseconds */ struct ut_stats { int fail_count; int skip_count; int test_count; + ulong start; + ulong duration_ms; }; /* @@ -29,6 +33,8 @@ struct ut_stats { * @cur: Statistics for the current run * @total: Statistics for all test runs * @run_count: Number of times ut_run_list() has been called + * @worst: Sute which had the first per-text run time + * @worst_ms: Time taken by that test * @start: Store the starting mallinfo when doing leak test * @of_live: true to use livetree if available, false to use flattree * @of_root: Record of the livetree root node (used for setting up tests) @@ -52,6 +58,8 @@ struct unit_test_state { struct ut_stats cur; struct ut_stats total; int run_count; + const struct suite *worst; + int worst_ms; struct mallinfo start; struct device_node *of_root; bool of_live; @@ -92,6 +100,8 @@ enum ut_flags { UTF_ETH_BOOTDEV = BIT(9), /* enable Ethernet bootdevs */ UTF_SF_BOOTDEV = BIT(10), /* enable SPI flash bootdevs */ UFT_BLOBLIST = BIT(11), /* test changes gd->bloblist */ + UTF_INIT = BIT(12), /* test inits a suite */ + UTF_UNINIT = BIT(13), /* test uninits a suite */ }; /** @@ -139,6 +149,24 @@ struct unit_test { .func = _name, \ } +/* init function for unit-test suite (the 'A' makes it first) */ +#define UNIT_TEST_INIT(_name, _flags, _suite) \ + ll_entry_declare(struct unit_test, A ## _name, ut_ ## _suite) = { \ + .file = __FILE__, \ + .name = #_name, \ + .flags = (_flags) | UTF_INIT, \ + .func = _name, \ + } + +/* uninit function for unit-test suite (the 'aaa' makes it last) */ +#define UNIT_TEST_UNINIT(_name, _flags, _suite) \ + ll_entry_declare(struct unit_test, zzz ## _name, ut_ ## _suite) = { \ + .file = __FILE__, \ + .name = #_name, \ + .flags = (_flags) | UTF_UNINIT, \ + .func = _name, \ + } + /* Get the start of a list of unit tests for a particular suite */ #define UNIT_TEST_SUITE_START(_suite) \ ll_entry_start(struct unit_test, ut_ ## _suite) diff --git a/include/time.h b/include/time.h index 3b2ba091247..f5b86bf70fe 100644 --- a/include/time.h +++ b/include/time.h @@ -28,7 +28,7 @@ uint64_t get_timer_us(uint64_t base); */ unsigned long get_timer_us_long(unsigned long base); -/* +/** * timer_test_add_offset() * * Allow tests to add to the time reported through lib/time.c functions @@ -36,6 +36,19 @@ unsigned long get_timer_us_long(unsigned long base); */ void timer_test_add_offset(unsigned long offset); +#ifdef CONFIG_SANDBOX +/** + * timer_test_get_offset() + * + * Get the total offset currently being added the time + * + * Return:: number of milliseconds the system time has been advanced + */ +ulong timer_test_get_offset(void); +#else +static inline ulong timer_test_get_offset(void) { return 0; } +#endif + /** * usec_to_tick() - convert microseconds to clock ticks * diff --git a/include/vbe.h b/include/vbe.h index 56bff63362f..61bfa0e557d 100644 --- a/include/vbe.h +++ b/include/vbe.h @@ -10,6 +10,8 @@ #ifndef __VBE_H #define __VBE_H +#include <linux/types.h> + /** * enum vbe_phase_t - current phase of VBE * @@ -26,12 +28,31 @@ enum vbe_phase_t { }; /** + * enum vbe_pick_t - indicates which firmware is picked + * + * @VBEFT_A: Firmware A + * @VBEFT_B: Firmware B + * @VBEFT_RECOVERY: Recovery firmware + */ +enum vbe_pick_t { + VBEP_A, + VBEP_B, + VBEP_RECOVERY, +}; + +/** * struct vbe_handoff - information about VBE progress * + * @offset: Offset of the FIT to use for SPL onwards + * @size: Size of the area containing the FIT * @phases: Indicates which phases used the VBE bootmeth (1 << PHASE_...) + * @pick: Indicates which firmware pick was used (enum vbe_pick_t) */ struct vbe_handoff { + ulong offset; + ulong size; u8 phases; + u8 pick; }; /** diff --git a/lib/Kconfig b/lib/Kconfig index b27965fc480..1a683dea670 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -758,6 +758,16 @@ config VPL_CRC8 checksum with feedback to produce an 8-bit result. The code is small and it does not require a lookup table (unlike CRC32). +config CRC16 + bool "Support CRC16" + default y + help + Enables CRC16 support. This is normally required. Two algorithms are + provided: + + - CCITT, with a polynomical x^16 + x^12 + x^5 + 1 + - standard, with polynomial x^16 + x^15 + x^2 + 1 (0x8005) + config SPL_CRC16 bool "Support CRC16 in SPL" depends on SPL diff --git a/lib/Makefile b/lib/Makefile index fc6e68c901a..a7bc2f3134a 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -35,8 +35,6 @@ obj-$(CONFIG_CIRCBUF) += circbuf.o endif obj-y += crc8.o -obj-y += crc16.o -obj-y += crc16-ccitt.o obj-$(CONFIG_ERRNO_STR) += errno_str.o obj-$(CONFIG_FIT) += fdtdec_common.o obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o @@ -71,6 +69,7 @@ endif obj-$(CONFIG_$(PHASE_)CRC8) += crc8.o obj-$(CONFIG_$(PHASE_)CRC16) += crc16.o +obj-$(CONFIG_$(PHASE_)CRC16) += crc16-ccitt.o obj-y += crypto/ @@ -80,11 +79,11 @@ obj-$(CONFIG_$(XPL_)RSA) += rsa/ obj-$(CONFIG_HASH) += hash-checksum.o obj-$(CONFIG_BLAKE2) += blake2/blake2b.o -obj-$(CONFIG_$(XPL_)MD5_LEGACY) += md5.o -obj-$(CONFIG_$(XPL_)SHA1_LEGACY) += sha1.o -obj-$(CONFIG_$(XPL_)SHA256) += sha256_common.o -obj-$(CONFIG_$(XPL_)SHA256_LEGACY) += sha256.o -obj-$(CONFIG_$(XPL_)SHA512_LEGACY) += sha512.o +obj-$(CONFIG_$(PHASE_)MD5_LEGACY) += md5.o +obj-$(CONFIG_$(PHASE_)SHA1_LEGACY) += sha1.o +obj-$(CONFIG_$(PHASE_)SHA256) += sha256_common.o +obj-$(CONFIG_$(PHASE_)SHA256_LEGACY) += sha256.o +obj-$(CONFIG_$(PHASE_)SHA512_LEGACY) += sha512.o obj-$(CONFIG_CRYPT_PW) += crypt/ obj-$(CONFIG_$(XPL_)ASN1_DECODER_LEGACY) += asn1_decoder.o diff --git a/lib/crc8.c b/lib/crc8.c index 811e19917b4..bbb229c3892 100644 --- a/lib/crc8.c +++ b/lib/crc8.c @@ -6,11 +6,12 @@ #ifdef USE_HOSTCC #include <arpa/inet.h> #endif +#include <asm/sections.h> #include <u-boot/crc.h> #define POLY (0x1070U << 3) -static unsigned char _crc8(unsigned short data) +__rcode static unsigned char _crc8(unsigned short data) { int i; @@ -23,7 +24,7 @@ static unsigned char _crc8(unsigned short data) return (unsigned char)(data >> 8); } -unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len) +__rcode unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len) { int i; diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c index 1c5dde60691..f0095e9dbcf 100644 --- a/lib/ecdsa/ecdsa-libcrypto.c +++ b/lib/ecdsa/ecdsa-libcrypto.c @@ -363,8 +363,10 @@ int ecdsa_add_verify_data(struct image_sign_info *info, void *fdt) ret = prepare_ctx(&ctx, info); if (ret >= 0) { ret = do_add(&ctx, fdt, fdt_key_name, info); - if (ret < 0) - ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO; + if (ret < 0) { + free_ctx(&ctx); + return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO; + } } free_ctx(&ctx); diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c index d3c668dc183..070747de515 100644 --- a/lib/efi_driver/efi_block_device.c +++ b/lib/efi_driver/efi_block_device.c @@ -35,8 +35,10 @@ #include <efi_driver.h> #include <malloc.h> #include <dm/device-internal.h> +#include <dm/lists.h> #include <dm/root.h> #include <dm/tag.h> +#include <dm/uclass-internal.h> /** * struct efi_blk_plat - attributes of a block device @@ -118,13 +120,18 @@ static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, static efi_status_t efi_bl_create_block_device(efi_handle_t handle, void *interface) { - struct udevice *bdev = NULL, *parent = dm_root(); + struct udevice *bdev = NULL, *parent; efi_status_t ret; + int r; int devnum; char *name; struct efi_block_io *io = interface; struct efi_blk_plat *plat; + r = uclass_find_first_device(UCLASS_EFI_LOADER, &parent); + if (r) + return EFI_OUT_OF_RESOURCES; + devnum = blk_next_free_devnum(UCLASS_EFI_LOADER); if (devnum < 0) return EFI_OUT_OF_RESOURCES; @@ -221,6 +228,24 @@ efi_bl_init(struct efi_driver_binding_extended_protocol *this) return EFI_SUCCESS; } +/** + * efi_block_device_create() - create parent for EFI block devices + * + * Create a device that serves as parent for all block devices created via + * ConnectController(). + * + * Return: 0 for success + */ +static int efi_block_device_create(void) +{ + int ret; + struct udevice *dev; + + ret = device_bind_driver(gd->dm_root, "EFI block driver", "efi", &dev); + + return ret; +} + /* Block device driver operators */ static const struct blk_ops efi_blk_ops = { .read = efi_bl_read, @@ -249,3 +274,5 @@ U_BOOT_DRIVER(efi_block) = { .id = UCLASS_EFI_LOADER, .ops = &driver_ops, }; + +EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, efi_block_device_create); diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index 1f3de0a2339..5452640354e 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -531,7 +531,8 @@ static efi_status_t efi_disk_add_dev( /* Store first EFI system partition */ if (part && efi_system_partition.uclass_id == UCLASS_INVALID) { - if (part_info->bootable & PART_EFI_SYSTEM_PARTITION) { + if (part_info && + part_info->bootable & PART_EFI_SYSTEM_PARTITION) { efi_system_partition.uclass_id = desc->uclass_id; efi_system_partition.devnum = desc->devnum; efi_system_partition.part = part; diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 1212772471e..6d00b186250 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -268,6 +268,7 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map, * memory * Return: status code */ +static efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, int memory_type, bool overlap_conventional) @@ -865,3 +866,30 @@ int efi_memory_init(void) return 0; } + +int efi_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op) +{ + u64 efi_addr; + u64 pages; + efi_status_t status; + + efi_addr = (uintptr_t)map_sysmem(addr, 0); + pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK)); + efi_addr &= ~EFI_PAGE_MASK; + + status = efi_add_memory_map_pg(efi_addr, pages, + op == LMB_MAP_OP_RESERVE ? + EFI_BOOT_SERVICES_DATA : + EFI_CONVENTIONAL_MEMORY, + false); + if (status != EFI_SUCCESS) { + log_err("LMB Map notify failure %lu\n", + status & ~EFI_ERROR_MASK); + return -1; + } + unmap_sysmem((void *)(uintptr_t)efi_addr); + + return 0; +} + diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index b265d95dd6b..31180df9e3a 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -19,6 +19,7 @@ */ static struct efi_var_file __efi_runtime_data *efi_var_buf; static struct efi_var_entry __efi_runtime_data *efi_current_var; +static const u16 __efi_runtime_rodata vtf[] = u"VarToFile"; /** * efi_var_mem_compare() - compare GUID and name with a variable @@ -331,7 +332,7 @@ efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor, if (timep) *timep = var->time; - if (!u16_strcmp(variable_name, u"VarToFile")) + if (!u16_strcmp(variable_name, vtf)) return efi_var_collect_mem(data, data_size, EFI_VARIABLE_NON_VOLATILE); old_size = *data_size; diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index 0d090d051dd..6a1fa39bb6f 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -41,6 +41,7 @@ static u16 mm_sp_id; extern struct efi_var_file __efi_runtime_data *efi_var_buf; static efi_uintn_t max_buffer_size; /* comm + var + func + data */ static efi_uintn_t max_payload_size; /* func + data */ +static const u16 __efi_runtime_rodata pk[] = u"PK"; struct mm_connection { struct udevice *tee; @@ -858,7 +859,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, if (alt_ret != EFI_SUCCESS) goto out; - if (!u16_strcmp(variable_name, u"PK")) + if (!u16_strcmp(variable_name, pk)) alt_ret = efi_init_secure_state(); out: free(comm_buf); diff --git a/lib/gunzip.c b/lib/gunzip.c index e71d8d00ccb..52007715bda 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -15,6 +15,7 @@ #include <u-boot/crc.h> #include <watchdog.h> #include <u-boot/zlib.h> +#include <asm/sections.h> #define HEADER0 '\x1f' #define HEADER1 '\x8b' @@ -43,7 +44,7 @@ void gzfree(void *x, void *addr, unsigned nb) free (addr); } -int gzip_parse_header(const unsigned char *src, unsigned long len) +__rcode int gzip_parse_header(const unsigned char *src, unsigned long len) { int i, flags; @@ -71,7 +72,7 @@ int gzip_parse_header(const unsigned char *src, unsigned long len) return i; } -int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) +__rcode int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) { int offset = gzip_parse_header(src, *lenp); @@ -274,8 +275,8 @@ out: /* * Uncompress blocks compressed with zlib without headers */ -int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, - int stoponerr, int offset) +__rcode int zunzip(void *dst, int dstlen, unsigned char *src, + unsigned long *lenp, int stoponerr, int offset) { z_stream s; int err = 0; diff --git a/lib/lmb.c b/lib/lmb.c index 7ca44591e1d..93fc1bea07c 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -23,10 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define MAP_OP_RESERVE (u8)0x1 -#define MAP_OP_FREE (u8)0x2 -#define MAP_OP_ADD (u8)0x3 - /* * The following low level LMB functions must not access the global LMB memory * map since they are also used to manage IOVA memory maps in iommu drivers like @@ -430,42 +426,12 @@ long io_lmb_free(struct lmb *io_lmb, phys_addr_t base, phys_size_t size) static struct lmb lmb; -static bool lmb_should_notify(u32 flags) -{ - return !lmb.test && !(flags & LMB_NONOTIFY) && - CONFIG_IS_ENABLED(EFI_LOADER); -} - -static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op, - u32 flags) +static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op, u32 flags) { - u64 efi_addr; - u64 pages; - efi_status_t status; - - if (op != MAP_OP_RESERVE && op != MAP_OP_FREE && op != MAP_OP_ADD) { - log_err("Invalid map update op received (%d)\n", op); - return -1; - } - - if (!lmb_should_notify(flags)) - return 0; - - efi_addr = (uintptr_t)map_sysmem(addr, 0); - pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK)); - efi_addr &= ~EFI_PAGE_MASK; - - status = efi_add_memory_map_pg(efi_addr, pages, - op == MAP_OP_RESERVE ? - EFI_BOOT_SERVICES_DATA : - EFI_CONVENTIONAL_MEMORY, - false); - if (status != EFI_SUCCESS) { - log_err("%s: LMB Map notify failure %lu\n", __func__, - status & ~EFI_ERROR_MASK); - return -1; - } - unmap_sysmem((void *)(uintptr_t)efi_addr); + if (CONFIG_IS_ENABLED(EFI_LOADER) && + !lmb.test && !(flags & LMB_NONOTIFY)) + return efi_map_update_notify(addr, size, op); return 0; } @@ -642,7 +608,7 @@ long lmb_add(phys_addr_t base, phys_size_t size) if (ret) return ret; - return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE); + return lmb_map_update_notify(base, size, LMB_MAP_OP_ADD, LMB_NONE); } long lmb_free_flags(phys_addr_t base, phys_size_t size, @@ -654,7 +620,7 @@ long lmb_free_flags(phys_addr_t base, phys_size_t size, if (ret < 0) return ret; - return lmb_map_update_notify(base, size, MAP_OP_FREE, flags); + return lmb_map_update_notify(base, size, LMB_MAP_OP_FREE, flags); } long lmb_free(phys_addr_t base, phys_size_t size) @@ -671,7 +637,7 @@ long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags) if (ret) return ret; - return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags); + return lmb_map_update_notify(base, size, LMB_MAP_OP_RESERVE, flags); } static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, @@ -712,7 +678,7 @@ static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, return 0; ret = lmb_map_update_notify(base, size, - MAP_OP_RESERVE, + LMB_MAP_OP_RESERVE, flags); if (ret) return ret; diff --git a/lib/lwip/lwip/src/apps/tftp/tftp.c b/lib/lwip/lwip/src/apps/tftp/tftp.c index 56aeabc4d73..63b1e0e0e20 100644 --- a/lib/lwip/lwip/src/apps/tftp/tftp.c +++ b/lib/lwip/lwip/src/apps/tftp/tftp.c @@ -264,19 +264,55 @@ static u16_t payload_size(void) return TFTP_DEFAULT_BLOCK_SIZE; } +/** + * find_option() - check if OACK message contains option + * + * @p: message buffer + * @option: option key + * Return: option value + */ static const char * find_option(struct pbuf *p, const char *option) { - int i; - u16_t optlen = strlen(option); - const char *b = p->payload; - - for (i = 0; i + optlen + 1 < p->len; i++) { - if (lwip_strnstr(b + i, option, optlen)) - return b + i + optlen + 2; - } + const char *pos = p->payload; + int rem = p->len; + + /* + * According to RFC 2347 the OACK packet has the following format: + * + * +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+ + * | opc | opt1 | 0 | value1 | 0 | optN | 0 | valueN | 0 | + * +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+ + */ + + /* Skip opc */ + pos += 2; + rem -= 2; + if (rem <= 0) + return NULL; + + for (;;) { + int len; + int diff; + + len = strnlen(pos, rem) + 1; + if (rem < len) + break; + diff = strcmp(pos, option); + /* Skip option */ + pos += len; + rem -= len; + len = strnlen(pos, rem) + 1; + if (rem < len) + break; + if (!diff) + return pos; + /* Skip value */ + pos += len; + rem -= len; + } - return NULL; + return NULL; } static void diff --git a/lib/lwip/u-boot/arch/cc.h b/lib/lwip/u-boot/arch/cc.h index de138846358..6104c296f6f 100644 --- a/lib/lwip/u-boot/arch/cc.h +++ b/lib/lwip/u-boot/arch/cc.h @@ -34,7 +34,7 @@ x, __LINE__, __FILE__); } while (0) #define atoi(str) (int)dectoul(str, NULL) -#define lwip_strnstr(a, b, c) strstr(a, b) +#define lwip_strnstr(a, b, c) strnstr(a, b, c) #define LWIP_ERR_T int #define LWIP_CONST_CAST(target_type, val) ((target_type)((uintptr_t)val)) diff --git a/lib/lz4.c b/lib/lz4.c index 63955a0b178..c718659c590 100644 --- a/lib/lz4.c +++ b/lib/lz4.c @@ -33,15 +33,16 @@ #include <linux/bug.h> #include <asm/unaligned.h> #include <u-boot/lz4.h> +#include <asm/sections.h> #define FORCE_INLINE inline __attribute__((always_inline)) -static FORCE_INLINE u16 LZ4_readLE16(const void *src) +__rcode static FORCE_INLINE u16 LZ4_readLE16(const void *src) { return get_unaligned_le16(src); } -static FORCE_INLINE void LZ4_copy8(void *dst, const void *src) +__rcode static FORCE_INLINE void LZ4_copy8(void *dst, const void *src) { put_unaligned(get_unaligned((const u64 *)src), (u64 *)dst); } @@ -53,7 +54,7 @@ typedef int32_t S32; typedef uint64_t U64; typedef uintptr_t uptrval; -static FORCE_INLINE void LZ4_write32(void *memPtr, U32 value) +__rcode static FORCE_INLINE void LZ4_write32(void *memPtr, U32 value) { put_unaligned(value, (U32 *)memPtr); } @@ -63,7 +64,7 @@ static FORCE_INLINE void LZ4_write32(void *memPtr, U32 value) **************************************/ /* customized version of memcpy, which may overwrite up to 7 bytes beyond dstEnd */ -static void LZ4_wildCopy(void* dstPtr, const void* srcPtr, void* dstEnd) +__rcode static void LZ4_wildCopy(void *dstPtr, const void *srcPtr, void *dstEnd) { BYTE* d = (BYTE*)dstPtr; const BYTE* s = (const BYTE*)srcPtr; @@ -112,13 +113,24 @@ typedef enum { decode_full_block = 0, partial_decode = 1 } earlyEnd_directive; #endif /* + * spl_reloc needs all necessary data to be set up within its code, since the + * code is relocated at runtime. Unfortunately this increase code-size slightly + * so only do it if spl_reloc is enabled + */ +#if CONFIG_IS_ENABLED(RELOC_LOADER) +#define STATIC +#else +#define STATIC static +#endif + +/* * LZ4_decompress_generic() : * This generic decompression function covers all use cases. * It shall be instantiated several times, using different sets of directives. * Note that it is important for performance that this function really get inlined, * in order to remove useless branches during compilation optimization. */ -static FORCE_INLINE int LZ4_decompress_generic( +__rcode static FORCE_INLINE int LZ4_decompress_generic( const char * const src, char * const dst, int srcSize, @@ -141,6 +153,8 @@ static FORCE_INLINE int LZ4_decompress_generic( const size_t dictSize ) { + STATIC const unsigned int inc32table[8] = {0, 1, 2, 1, 0, 4, 4, 4}; + STATIC const int dec64table[8] = {0, 0, 0, -1, -4, 1, 2, 3}; const BYTE *ip = (const BYTE *) src; const BYTE * const iend = ip + srcSize; @@ -149,8 +163,6 @@ static FORCE_INLINE int LZ4_decompress_generic( BYTE *cpy; const BYTE * const dictEnd = (const BYTE *)dictStart + dictSize; - static const unsigned int inc32table[8] = {0, 1, 2, 1, 0, 4, 4, 4}; - static const int dec64table[8] = {0, 0, 0, -1, -4, 1, 2, 3}; const int safeDecode = (endOnInput == endOnInputSize); const int checkOffset = ((safeDecode) && (dictSize < (int)(64 * KB))); @@ -514,8 +526,9 @@ _output_error: return (int) (-(((const char *)ip) - src)) - 1; } -int LZ4_decompress_safe(const char *source, char *dest, - int compressedSize, int maxDecompressedSize) +#ifndef CONFIG_SPL_BUILD +__rcode int LZ4_decompress_safe(const char *source, char *dest, + int compressedSize, int maxDecompressedSize) { return LZ4_decompress_generic(source, dest, compressedSize, maxDecompressedSize, @@ -523,11 +536,13 @@ int LZ4_decompress_safe(const char *source, char *dest, noDict, (BYTE *)dest, NULL, 0); } -int LZ4_decompress_safe_partial(const char *src, char *dst, - int compressedSize, int targetOutputSize, int dstCapacity) +__rcode int LZ4_decompress_safe_partial(const char *src, char *dst, + int compressedSize, + int targetOutputSize, int dstCapacity) { dstCapacity = min(targetOutputSize, dstCapacity); return LZ4_decompress_generic(src, dst, compressedSize, dstCapacity, endOnInputSize, partial_decode, noDict, (BYTE *)dst, NULL, 0); } +#endif diff --git a/lib/lz4_wrapper.c b/lib/lz4_wrapper.c index 4d48e7b0e8b..b1204511170 100644 --- a/lib/lz4_wrapper.c +++ b/lib/lz4_wrapper.c @@ -15,7 +15,7 @@ #define LZ4F_BLOCKUNCOMPRESSED_FLAG 0x80000000U -int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn) +__rcode int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn) { const void *end = dst + *dstn; const void *in = src; diff --git a/lib/mbedtls/Kconfig b/lib/mbedtls/Kconfig index aa82336ef14..35d8c507a89 100644 --- a/lib/mbedtls/Kconfig +++ b/lib/mbedtls/Kconfig @@ -112,6 +112,46 @@ config SPL_MD5_LEGACY endif # SPL +if VPL + +config VPL_SHA1_LEGACY + bool "Enable SHA1 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_SHA1 + help + This option enables support of hashing using SHA1 algorithm + with legacy crypto library. + +config VPL_SHA256_LEGACY + bool "Enable SHA256 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_SHA256 + help + This option enables support of hashing using SHA256 algorithm + with legacy crypto library. + +config VPL_SHA512_LEGACY + bool "Enable SHA512 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_SHA512 + help + This option enables support of hashing using SHA512 algorithm + with legacy crypto library. + +config VPL_SHA384_LEGACY + bool "Enable SHA384 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_SHA384 + select VPL_SHA512_LEGACY + help + This option enables support of hashing using SHA384 algorithm + with legacy crypto library. + +config VPL_MD5_LEGACY + bool "Enable MD5 support in VPL with legacy crypto library" + depends on LEGACY_CRYPTO_BASIC && VPL_MD5 + help + This option enables support of hashing using MD5 algorithm + with legacy crypto library. + +endif # VPL + endif # LEGACY_CRYPTO_BASIC config LEGACY_CRYPTO_CERT diff --git a/lib/mbedtls/external/mbedtls/framework b/lib/mbedtls/external/mbedtls/framework deleted file mode 160000 -Subproject 750634d3a51eb9d61b59fd5d801546927c94658 diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index d3b4f71d6be..b74aaf86e6d 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -565,6 +565,11 @@ int rsa_verify(struct image_sign_info *info, uint8_t hash[info->crypto->key_len]; int ret; +#ifdef USE_HOSTCC + if (!info->fdt_blob) + return rsa_verify_openssl(info, region, region_count, sig, sig_len); +#endif + /* * Verify that the checksum-length does not exceed the * rsa-signature-length diff --git a/lib/smbios.c b/lib/smbios.c index 78cee8c0c26..7c9701a57f9 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -429,6 +429,8 @@ static int smbios_write_type1(ulong *current, int handle, struct smbios_type1 *t; int len = sizeof(*t); char *serial_str = env_get("serial#"); + size_t uuid_len; + void *uuid; t = map_sysmem(*current, len); memset(t, 0, len); @@ -450,6 +452,10 @@ static int smbios_write_type1(ulong *current, int handle, SYSID_SM_SYSTEM_SERIAL, NULL); } + if (!sysinfo_get_data(ctx->dev, SYSID_SM_SYSTEM_UUID, &uuid, + &uuid_len) && + uuid_len == sizeof(t->uuid)) + memcpy(t->uuid, uuid, sizeof(t->uuid)); t->wakeup_type = smbios_get_val_si(ctx, "wakeup-type", SYSID_SM_SYSTEM_WAKEUP, SMBIOS_WAKEUP_TYPE_UNKNOWN); diff --git a/lib/string.c b/lib/string.c index feae9519f2f..d56f88d4a84 100644 --- a/lib/string.c +++ b/lib/string.c @@ -15,11 +15,13 @@ * reentrant and should be faster). Use only strsep() in new code, please. */ +#include <asm/sections.h> #include <config.h> +#include <limits.h> #include <linux/compiler.h> -#include <linux/types.h> -#include <linux/string.h> #include <linux/ctype.h> +#include <linux/string.h> +#include <linux/types.h> #include <malloc.h> /** @@ -559,7 +561,7 @@ __used void * memset(void * s,int c,size_t count) * You should not use this function to access IO space, use memcpy_toio() * or memcpy_fromio() instead. */ -__used void * memcpy(void *dest, const void *src, size_t count) +__rcode __used void *memcpy(void *dest, const void *src, size_t count) { unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src; char *d8, *s8; @@ -593,7 +595,7 @@ __used void * memcpy(void *dest, const void *src, size_t count) * * Unlike memcpy(), memmove() copes with overlapping areas. */ -__used void * memmove(void * dest,const void *src,size_t count) +__rcode __used void *memmove(void *dest, const void *src, size_t count) { char *tmp, *s; @@ -678,30 +680,48 @@ char *memdup(const void *src, size_t len) return p; } -#ifndef __HAVE_ARCH_STRSTR +#ifndef __HAVE_ARCH_STRNSTR /** - * strstr - Find the first substring in a %NUL terminated string - * @s1: The string to be searched - * @s2: The string to search for + * strnstr() - find the first substring occurrence in a NUL terminated string + * + * @s1: string to be searched + * @s2: string to search for + * @len: maximum number of characters in s2 to consider + * + * Return: pointer to the first occurrence or NULL */ -char * strstr(const char * s1,const char * s2) +char *strnstr(const char *s1, const char *s2, size_t len) { - int l1, l2; + size_t l1, l2; + l1 = strnlen(s1, len); l2 = strlen(s2); - if (!l2) - return (char *) s1; - l1 = strlen(s1); - while (l1 >= l2) { - l1--; - if (!memcmp(s1,s2,l2)) + + for (; l1 >= l2; --l1, ++s1) { + if (!memcmp(s1, s2, l2)) return (char *) s1; - s1++; } + return NULL; } #endif +#ifndef __HAVE_ARCH_STRSTR +/** + * strstr() - find the first substring occurrence in a NUL terminated string + * + * @s1: string to be searched + * @s2: string to search for + * @len: maximum number of characters in s2 to consider + * + * Return: pointer to the first occurrence or NULL + */ +char *strstr(const char *s1, const char *s2) +{ + return strnstr(s1, s2, SIZE_MAX); +} +#endif + #ifndef __HAVE_ARCH_MEMCHR /** * memchr - Find a character in an area of memory. diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c index 0503c17341f..faf55d7f327 100644 --- a/lib/tiny-printf.c +++ b/lib/tiny-printf.c @@ -211,6 +211,7 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) bool lz = false; int width = 0; bool islong = false; + bool force_char = false; ch = *(fmt++); if (ch == '-') @@ -300,6 +301,8 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) break; case 'c': out(info, (char)(va_arg(va, int))); + /* For the case when it's \0 char */ + force_char = true; break; case 's': p = va_arg(va, char*); @@ -317,8 +320,10 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) while (width-- > 0) info->putc(info, lz ? '0' : ' '); if (p) { - while ((ch = *p++)) + while ((ch = *p++) || force_char) { info->putc(info, ch); + force_char = false; + } } } } diff --git a/lib/uuid.c b/lib/uuid.c index 97388f597a6..75658778044 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -120,6 +120,10 @@ static const struct { EFI_BLOCK_IO_PROTOCOL_GUID, }, { + "Disk IO", + EFI_DISK_IO_PROTOCOL_GUID, + }, + { "Simple File System", EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID, }, @@ -128,6 +132,10 @@ static const struct { EFI_LOADED_IMAGE_PROTOCOL_GUID, }, { + "Loaded Image Device Path", + EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID, + }, + { "Graphics Output", EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID, }, @@ -140,10 +148,18 @@ static const struct { EFI_HII_DATABASE_PROTOCOL_GUID, }, { + "HII Config Access", + EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID, + }, + { "HII Config Routing", EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID, }, { + "Load File", + EFI_LOAD_FILE_PROTOCOL_GUID, + }, + { "Load File2", EFI_LOAD_FILE2_PROTOCOL_GUID, }, diff --git a/lib/zlib/inflate.c b/lib/zlib/inflate.c index f7e81fc8b2a..b4c72cc2c5c 100644 --- a/lib/zlib/inflate.c +++ b/lib/zlib/inflate.c @@ -2,10 +2,12 @@ * Copyright (C) 1995-2005 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h */ +#include <asm/sections.h> + local void fixedtables OF((struct inflate_state FAR *state)); local int updatewindow OF((z_streamp strm, unsigned out)); -int ZEXPORT inflateReset(z_streamp strm) +__rcode int ZEXPORT inflateReset(z_streamp strm) { struct inflate_state FAR *state; @@ -30,8 +32,8 @@ int ZEXPORT inflateReset(z_streamp strm) return Z_OK; } -int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, - int stream_size) +__rcode int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, + int stream_size) { struct inflate_state FAR *state; @@ -67,12 +69,12 @@ int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, return inflateReset(strm); } -int ZEXPORT inflateInit_(z_streamp strm, int stream_size) +__rcode int ZEXPORT inflateInit_(z_streamp strm, int stream_size) { return inflateInit2_(strm, DEF_WBITS, stream_size); } -local void fixedtables(struct inflate_state FAR *state) +__rcode local void fixedtables(struct inflate_state FAR *state) { state->lencode = lenfix; state->lenbits = 9; @@ -94,7 +96,7 @@ local void fixedtables(struct inflate_state FAR *state) output will fall in the output data, making match copies simpler and faster. The advantage may be dependent on the size of the processor's data caches. */ -local int updatewindow(z_streamp strm, unsigned out) +__rcode local int updatewindow(z_streamp strm, unsigned int out) { struct inflate_state FAR *state; unsigned copy, dist; @@ -322,7 +324,7 @@ local int updatewindow(z_streamp strm, unsigned out) when flush is set to Z_FINISH, inflate() cannot return Z_OK. Instead it will return Z_BUF_ERROR if it has not reached the end of the stream. */ -int ZEXPORT inflate(z_streamp strm, int flush) +__rcode int ZEXPORT inflate(z_streamp strm, int flush) { struct inflate_state FAR *state; unsigned char FAR *next; /* next input */ @@ -924,7 +926,7 @@ int ZEXPORT inflate(z_streamp strm, int flush) return ret; } -int ZEXPORT inflateEnd(z_streamp strm) +__rcode int ZEXPORT inflateEnd(z_streamp strm) { struct inflate_state FAR *state; if (strm == Z_NULL || strm->state == Z_NULL || strm->zfree == (free_func)0) diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c index e7d9147455c..3b7e4700c6e 100644 --- a/net/lwip/dhcp.c +++ b/net/lwip/dhcp.c @@ -115,7 +115,7 @@ int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) int ret; struct udevice *dev; - eth_set_current(); + net_lwip_set_current(); dev = eth_get_dev(); if (!dev) { diff --git a/net/lwip/dns.c b/net/lwip/dns.c index 1de63c9998b..149bdb784dc 100644 --- a/net/lwip/dns.c +++ b/net/lwip/dns.c @@ -121,7 +121,7 @@ int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (argc == 3) var = argv[2]; - eth_set_current(); + net_lwip_set_current(); return dns_loop(eth_get_dev(), name, var); } diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c index b863047f598..cab1dd7d483 100644 --- a/net/lwip/net-lwip.c +++ b/net/lwip/net-lwip.c @@ -127,6 +127,20 @@ static int get_udev_ipv4_info(struct udevice *dev, ip4_addr_t *ip, return 0; } +/* Initialize the lwIP stack and the ethernet devices and set current device */ +void net_lwip_set_current(void) +{ + static bool init_done; + + if (!init_done) { + eth_init_rings(); + eth_init(); + lwip_init(); + init_done = true; + } + eth_set_current(); +} + static struct netif *new_netif(struct udevice *udev, bool with_ip) { unsigned char enetaddr[ARP_HLEN]; @@ -134,19 +148,10 @@ static struct netif *new_netif(struct udevice *udev, bool with_ip) ip4_addr_t ip, mask, gw; struct netif *netif; int ret = 0; - static bool first_call = true; if (!udev) return NULL; - if (first_call) { - eth_init_rings(); - /* Pick a valid active device, if any */ - eth_init(); - lwip_init(); - first_call = false; - } - if (eth_start_udev(udev) < 0) { log_err("Could not start %s\n", udev->name); return NULL; diff --git a/net/lwip/ping.c b/net/lwip/ping.c index aa617530749..200a702bbb5 100644 --- a/net/lwip/ping.c +++ b/net/lwip/ping.c @@ -168,7 +168,7 @@ int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (!ipaddr_aton(argv[1], &addr)) return CMD_RET_USAGE; - eth_set_current(); + net_lwip_set_current(); if (ping_loop(eth_get_dev(), &addr) < 0) return CMD_RET_FAILURE; diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c index fc4aff5f2ba..123d66b5dba 100644 --- a/net/lwip/tftp.c +++ b/net/lwip/tftp.c @@ -280,7 +280,7 @@ int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) goto out; } - eth_set_current(); + net_lwip_set_current(); if (tftp_loop(eth_get_dev(), laddr, fname, srvip, port) < 0) ret = CMD_RET_FAILURE; diff --git a/net/lwip/wget.c b/net/lwip/wget.c index b76f6c0f1d9..14f27d42998 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -354,7 +354,7 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) int wget_do_request(ulong dst_addr, char *uri) { - eth_set_current(); + net_lwip_set_current(); if (!wget_info) wget_info = &default_wget_info; @@ -433,10 +433,15 @@ bool wget_validate_uri(char *uri) if (!strncmp(uri, "http://", strlen("http://"))) { prefix_len = strlen("http://"); - } else if (!strncmp(uri, "https://", strlen("https://"))) { - prefix_len = strlen("https://"); + } else if (CONFIG_IS_ENABLED(WGET_HTTPS)) { + if (!strncmp(uri, "https://", strlen("https://"))) { + prefix_len = strlen("https://"); + } else { + log_err("only http(s):// is supported\n"); + return false; + } } else { - log_err("only http(s):// is supported\n"); + log_err("only http:// is supported\n"); return false; } diff --git a/test/Kconfig b/test/Kconfig index 558a9cd49b4..31016eedbf8 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -20,9 +20,18 @@ config SPL_UNIT_TEST of-platdata and SPL handover. To run these tests with the sandbox_spl board, use the -u (unit test) option. +if UNIT_TEST + +config UNIT_TEST_DURATION + bool "Report unit-test duration" + default y + help + Enable this short the time taken by each test suite. This is reported + after the suite runs, alongside the pass/fail results. In addition, + an overall total is reported if multiple suites are run. + config UT_LIB bool "Unit tests for library functions" - depends on UNIT_TEST default y if !SANDBOX_VPL help Enables the 'ut lib' command which tests library functions like @@ -63,16 +72,15 @@ config UT_LIB_RSA Enables rsa_verify() test, currently rsa_verify_with_pkey only() only, at the 'ut lib' command. -endif +endif # UT_LIB config UT_BOOTSTD bool "Unit tests for standard boot" - depends on UNIT_TEST && BOOTSTD && SANDBOX + depends on BOOTSTD && SANDBOX default y config UT_COMPRESSION bool "Unit test for compression" - depends on UNIT_TEST depends on CMDLINE && GZIP_COMPRESSED && BZIP2 && LZMA && LZO && LZ4 && ZSTD default y help @@ -81,7 +89,6 @@ config UT_COMPRESSION config UT_LOG bool "Unit tests for logging functions" - depends on UNIT_TEST default y help Enables the 'ut log' command which tests logging functions like @@ -90,7 +97,6 @@ config UT_LOG config UT_TIME bool "Unit tests for time functions" - depends on UNIT_TEST help Enables the 'ut time' command which tests that the time functions work correctly. The test is fairly simple and will not catch all @@ -99,7 +105,6 @@ config UT_TIME config UT_UNICODE bool "Unit tests for Unicode functions" - depends on UNIT_TEST default y select CHARSET help @@ -111,7 +116,9 @@ source "test/env/Kconfig" source "test/image/Kconfig" source "test/lib/Kconfig" source "test/optee/Kconfig" -source "test/overlay/Kconfig" +source "test/fdt_overlay/Kconfig" + +endif # UNIT_TEST config POST bool "Power On Self Test support" diff --git a/test/Makefile b/test/Makefile index 47a07d653a9..99d4797d968 100644 --- a/test/Makefile +++ b/test/Makefile @@ -14,11 +14,14 @@ endif ifneq ($(CONFIG_HUSH_PARSER),) obj-$(CONFIG_$(XPL_)CMDLINE) += hush/ endif +obj-$(CONFIG_UT_OPTEE) += optee/ obj-y += ut.o ifeq ($(CONFIG_XPL_BUILD),) obj-y += boot/ obj-$(CONFIG_UNIT_TEST) += common/ +obj-$(CONFIG_UT_ENV) += env/ +obj-$(CONFIG_UT_FDT_OVERLAY) += fdt_overlay/ obj-y += log/ else obj-$(CONFIG_SPL_UT_LOAD) += image/ diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c index 8c44afd9297..5f07430714e 100644 --- a/test/boot/bootdev.c +++ b/test/boot/bootdev.c @@ -12,7 +12,6 @@ #include <bootflow.h> #include <mapmem.h> #include <os.h> -#include <test/suites.h> #include <test/ut.h> #include "bootstd_common.h" diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index a8735c1c23d..eb7f00af39a 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -21,7 +21,6 @@ #endif #include <dm/device-internal.h> #include <dm/lists.h> -#include <test/suites.h> #include <test/ut.h> #include "bootstd_common.h" #include "../../boot/bootflow_internal.h" diff --git a/test/boot/bootm.c b/test/boot/bootm.c index 7e0ccb0e23f..1d1efe71ad5 100644 --- a/test/boot/bootm.c +++ b/test/boot/bootm.c @@ -7,7 +7,6 @@ #include <bootm.h> #include <asm/global_data.h> -#include <test/suites.h> #include <test/test.h> #include <test/ut.h> diff --git a/test/boot/bootmeth.c b/test/boot/bootmeth.c index 18ae6d7fe13..577f259fb37 100644 --- a/test/boot/bootmeth.c +++ b/test/boot/bootmeth.c @@ -9,7 +9,6 @@ #include <bootmeth.h> #include <bootstd.h> #include <dm.h> -#include <test/suites.h> #include <test/ut.h> #include "bootstd_common.h" diff --git a/test/boot/bootstd_common.c b/test/boot/bootstd_common.c index 724e3d9bdd2..052c0fe5cc6 100644 --- a/test/boot/bootstd_common.c +++ b/test/boot/bootstd_common.c @@ -13,7 +13,6 @@ #include <mmc.h> #include <usb.h> #include <linux/log2.h> -#include <test/suites.h> #include <test/ut.h> #include <u-boot/crc.h> #include "bootstd_common.h" @@ -21,8 +20,14 @@ /* tracks whether bootstd_setup_for_tests() has been run yet */ bool vbe_setup_done; -/* set up MMC for VBE tests */ -int bootstd_setup_for_tests(void) +/** + * bootstd_setup_for_tests() - Set up MMC data for VBE tests + * + * Some data is needed for VBE tests to work. This function sets that up. + * + * @return 0 if OK, -ve on error + */ +static int bootstd_setup_for_tests(struct unit_test_state *uts) { ALLOC_CACHE_ALIGN_BUFFER(u8, buf, MMC_MAX_BLOCK_LEN); struct udevice *mmc; @@ -55,6 +60,7 @@ int bootstd_setup_for_tests(void) return 0; } +BOOTSTD_TEST_INIT(bootstd_setup_for_tests, 0); int bootstd_test_drop_bootdev_order(struct unit_test_state *uts) { @@ -93,20 +99,3 @@ void bootstd_reset_usb(void) { usb_started = false; } - -int do_ut_bootstd(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag, - int argc, char *const argv[]) -{ - struct unit_test *tests = UNIT_TEST_SUITE_START(bootstd); - const int n_ents = UNIT_TEST_SUITE_COUNT(bootstd); - int ret; - - ret = bootstd_setup_for_tests(); - if (ret) { - printf("Failed to set up for bootstd tests (err=%d)\n", ret); - return CMD_RET_FAILURE; - } - - return cmd_ut_category(uts, "bootstd", "bootstd_", - tests, n_ents, argc, argv); -} diff --git a/test/boot/bootstd_common.h b/test/boot/bootstd_common.h index ea3ecd1166c..c61698adc02 100644 --- a/test/boot/bootstd_common.h +++ b/test/boot/bootstd_common.h @@ -13,6 +13,7 @@ /* Declare a new bootdev test */ #define BOOTSTD_TEST(_name, _flags) UNIT_TEST(_name, _flags, bootstd) +#define BOOTSTD_TEST_INIT(_name, _flags) UNIT_TEST_INIT(_name, _flags, bootstd) #define NVDATA_START_BLK ((0x400 + 0x400) / MMC_MAX_BLOCK_LEN) #define VERSION_START_BLK ((0x400 + 0x800) / MMC_MAX_BLOCK_LEN) @@ -36,15 +37,6 @@ struct unit_test_state; int bootstd_test_drop_bootdev_order(struct unit_test_state *uts); /** - * bootstd_setup_for_tests() - Set up MMC data for VBE tests - * - * Some data is needed for VBE tests to work. This function sets that up. - * - * @return 0 if OK, -ve on error - */ -int bootstd_setup_for_tests(void); - -/** * bootstd_test_check_mmc_hunter() - Check that the mmc bootdev hunter was used * * @uts: Unit test state to use for ut_assert...() functions diff --git a/test/boot/expo.c b/test/boot/expo.c index db14ff86f8b..1d283a2ac95 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -10,7 +10,6 @@ #include <menu.h> #include <video.h> #include <linux/input.h> -#include <test/suites.h> #include <test/ut.h> #include "bootstd_common.h" #include <test/cedit-test.h> diff --git a/test/boot/image.c b/test/boot/image.c index 0894e30587f..4df7b17ce88 100644 --- a/test/boot/image.c +++ b/test/boot/image.c @@ -7,7 +7,6 @@ */ #include <image.h> -#include <test/suites.h> #include <test/ut.h> #include "bootstd_common.h" diff --git a/test/boot/measurement.c b/test/boot/measurement.c index 5a49c7a6b23..1d38663fc0f 100644 --- a/test/boot/measurement.c +++ b/test/boot/measurement.c @@ -8,7 +8,6 @@ #include <bootm.h> #include <malloc.h> -#include <test/suites.h> #include <test/test.h> #include <test/ut.h> #include <asm/io.h> diff --git a/test/boot/upl.c b/test/boot/upl.c index aa58cdf083b..eec89026fc3 100644 --- a/test/boot/upl.c +++ b/test/boot/upl.c @@ -10,7 +10,6 @@ #include <mapmem.h> #include <upl.h> #include <dm/ofnode.h> -#include <test/suites.h> #include <test/test.h> #include <test/ut.h> #include "bootstd_common.h" diff --git a/test/boot/vbe_simple.c b/test/boot/vbe_simple.c index 4fe4323b401..c37de627c52 100644 --- a/test/boot/vbe_simple.c +++ b/test/boot/vbe_simple.c @@ -11,7 +11,6 @@ #include <image.h> #include <of_live.h> #include <vbe.h> -#include <test/suites.h> #include <test/ut.h> #include "bootstd_common.h" @@ -33,9 +32,6 @@ static int vbe_simple_test_base(struct unit_test_state *uts) ofnode node; u32 vernum; - /* Set up the VBE info */ - ut_assertok(bootstd_setup_for_tests()); - /* Read the version back */ ut_assertok(vbe_find_by_any("firmware0", &dev)); ut_assertok(bootmeth_get_state_desc(dev, info, sizeof(info))); diff --git a/test/cmd/addrmap.c b/test/cmd/addrmap.c index 1f2deb15052..72798b96edd 100644 --- a/test/cmd/addrmap.c +++ b/test/cmd/addrmap.c @@ -6,7 +6,6 @@ */ #include <console.h> -#include <test/suites.h> #include <test/ut.h> /* Declare a new addrmap test */ diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c index 7408c271a30..09f44ee41ed 100644 --- a/test/cmd/bdinfo.c +++ b/test/cmd/bdinfo.c @@ -10,7 +10,6 @@ #include <mapmem.h> #include <asm/global_data.h> #include <dm/uclass.h> -#include <test/suites.h> #include <test/ut.h> #include <dm.h> #include <env.h> diff --git a/test/cmd/exit.c b/test/cmd/exit.c index 71c37edcdf6..fdde054b928 100644 --- a/test/cmd/exit.c +++ b/test/cmd/exit.c @@ -8,7 +8,6 @@ #include <console.h> #include <mapmem.h> #include <asm/global_data.h> -#include <test/suites.h> #include <test/ut.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c index ab6dbd45e54..c11c181c807 100644 --- a/test/cmd/fdt.c +++ b/test/cmd/fdt.c @@ -10,7 +10,6 @@ #include <mapmem.h> #include <asm/global_data.h> #include <linux/libfdt.h> -#include <test/suites.h> #include <test/ut.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/test/cmd/font.c b/test/cmd/font.c index af88d1b5459..7ae648d7395 100644 --- a/test/cmd/font.c +++ b/test/cmd/font.c @@ -8,7 +8,6 @@ #include <console.h> #include <dm.h> #include <video_console.h> -#include <test/suites.h> #include <test/ut.h> /* Declare a new fdt test */ diff --git a/test/cmd/loadm.c b/test/cmd/loadm.c index 3c623aa655f..043cd25dfb6 100644 --- a/test/cmd/loadm.c +++ b/test/cmd/loadm.c @@ -13,7 +13,6 @@ #include <mapmem.h> #include <asm/global_data.h> #include <dm/test.h> -#include <test/suites.h> #include <test/test.h> #include <test/ut.h> diff --git a/test/cmd/mbr.c b/test/cmd/mbr.c index 45bab04923a..e651256a4cb 100644 --- a/test/cmd/mbr.c +++ b/test/cmd/mbr.c @@ -15,7 +15,6 @@ #include <dm/device-internal.h> #include <dm/lists.h> #include <linux/sizes.h> -#include <test/suites.h> #include <test/ut.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/test/cmd/pci_mps.c b/test/cmd/pci_mps.c index 8b3ea4a6134..6618c247d13 100644 --- a/test/cmd/pci_mps.c +++ b/test/cmd/pci_mps.c @@ -8,7 +8,6 @@ */ #include <console.h> -#include <test/suites.h> #include <test/ut.h> #define PCI_MPS_TEST(_name, _flags) UNIT_TEST(_name, _flags, pci_mps) diff --git a/test/cmd/seama.c b/test/cmd/seama.c index 1edc3fcac5a..39f85f1c502 100644 --- a/test/cmd/seama.c +++ b/test/cmd/seama.c @@ -7,7 +7,6 @@ #include <command.h> #include <dm.h> -#include <test/suites.h> #include <test/test.h> #include <test/ut.h> diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c index 7f318a42ead..85803eb54b8 100644 --- a/test/cmd/setexpr.c +++ b/test/cmd/setexpr.c @@ -9,7 +9,6 @@ #include <console.h> #include <mapmem.h> #include <dm/test.h> -#include <test/suites.h> #include <test/ut.h> #define BUF_SIZE 0x100 @@ -297,31 +296,19 @@ SETEXPR_TEST(setexpr_test_backref, UTF_CONSOLE); /* Test 'setexpr' command with setting strings */ static int setexpr_test_str(struct unit_test_state *uts) { - ulong start_mem; char *buf; buf = map_sysmem(0, BUF_SIZE); memset(buf, '\xff', BUF_SIZE); - /* - * Set 'fred' to the same length as we expect to get below, to avoid a - * new allocation in 'setexpr'. That way we can check for memory leaks. - */ ut_assertok(env_set("fred", "x")); - start_mem = ut_check_free(); - strcpy(buf, "hello"); - ut_asserteq(1, run_command("setexpr.s fred 0", 0)); - ut_assertok(ut_check_delta(start_mem)); + ut_asserteq(0, run_command("setexpr.s fred 0", 0)); + ut_asserteq_str("0", env_get("fred")); + strcpy(buf, "hello"); ut_assertok(env_set("fred", "12345")); - start_mem = ut_check_free(); ut_assertok(run_command("setexpr.s fred *0", 0)); ut_asserteq_str("hello", env_get("fred")); - /* - * This fails in CI at present. - * - * ut_assertok(ut_check_delta(start_mem)); - */ unmap_sysmem(buf); @@ -332,45 +319,25 @@ SETEXPR_TEST(setexpr_test_str, UTF_CONSOLE); /* Test 'setexpr' command with concatenating strings */ static int setexpr_test_str_oper(struct unit_test_state *uts) { - ulong start_mem; char *buf; + /* Test concatenation of strings */ + ut_assertok(run_command("setexpr.s fred '1' + '3'", 0)); + ut_asserteq_str("13", env_get("fred")); + buf = map_sysmem(0, BUF_SIZE); memset(buf, '\xff', BUF_SIZE); strcpy(buf, "hello"); strcpy(buf + 0x10, " there"); - start_mem = ut_check_free(); ut_asserteq(1, run_command("setexpr.s fred *0 * *10", 0)); - ut_assertok(ut_check_delta(start_mem)); ut_assert_nextline("invalid op"); ut_assert_console_end(); - /* - * Set 'fred' to the same length as we expect to get below, to avoid a - * new allocation in 'setexpr'. That way we can check for memory leaks. - */ ut_assertok(env_set("fred", "12345012345")); - start_mem = ut_check_free(); ut_assertok(run_command("setexpr.s fred *0 + *10", 0)); ut_asserteq_str("hello there", env_get("fred")); - /* - * This check does not work with sandbox_flattree, apparently due to - * memory allocations in env_set(). - * - * The truetype console produces lots of memory allocations even though - * the LCD display is not visible. But even without these, it does not - * work. - * - * A better test would be for dlmalloc to record the allocs and frees - * for a particular caller, but that is not supported. - * - * For now, drop this test. - * - * ut_assertok(ut_check_delta(start_mem)); - */ - unmap_sysmem(buf); return 0; diff --git a/test/cmd_ut.c b/test/cmd_ut.c index fbfdaaae0b5..44e5fdfdaa6 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -7,7 +7,6 @@ #include <command.h> #include <console.h> #include <vsprintf.h> -#include <test/suites.h> #include <test/test.h> #include <test/ut.h> @@ -20,77 +19,31 @@ * @name: Name of suite * @start: First test in suite * @end: End test in suite (points to the first test in the next suite) - * @cmd: Command to use to run the suite * @help: Help-string to show for this suite */ struct suite { const char *name; struct unit_test *start; struct unit_test *end; - ut_cmd_func cmd; const char *help; }; -static int do_ut_all(struct unit_test_state *uts, struct cmd_tbl *cmdtp, - int flag, int argc, char *const argv[]); +static int do_ut_all(struct unit_test_state *uts, const char *select_name, + int runs_per_test, bool force_run, + const char *test_insert); -static int do_ut_info(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]); - -int cmd_ut_category(struct unit_test_state *uts, const char *name, - const char *prefix, struct unit_test *tests, int n_ents, - int argc, char *const argv[]) -{ - const char *test_insert = NULL; - int runs_per_text = 1; - bool force_run = false; - int ret; - - while (argc > 1 && *argv[1] == '-') { - const char *str = argv[1]; - - switch (str[1]) { - case 'r': - runs_per_text = dectoul(str + 2, NULL); - break; - case 'f': - force_run = true; - break; - case 'I': - test_insert = str + 2; - break; - } - argv++; - argc--; - } - - ret = ut_run_list(uts, name, prefix, tests, n_ents, - cmd_arg1(argc, argv), runs_per_text, force_run, - test_insert); - - return ret ? CMD_RET_FAILURE : 0; -} +static int do_ut_info(bool show_suites); /* declare linker-list symbols for the start and end of a suite */ #define SUITE_DECL(_name) \ ll_start_decl(suite_start_ ## _name, struct unit_test, ut_ ## _name); \ ll_end_decl(suite_end_ ## _name, struct unit_test, ut_ ## _name) -/* declare a test suite which uses a subcommand to run */ -#define SUITE_CMD(_name, _cmd_func, _help) { \ - #_name, \ - suite_start_ ## _name, \ - suite_end_ ## _name, \ - _cmd_func, \ - _help, \ - } - /* declare a test suite which can be run directly without a subcommand */ #define SUITE(_name, _help) { \ #_name, \ suite_start_ ## _name, \ suite_end_ ## _name, \ - NULL, \ _help, \ } @@ -105,6 +58,7 @@ SUITE_DECL(dm); SUITE_DECL(env); SUITE_DECL(exit); SUITE_DECL(fdt); +SUITE_DECL(fdt_overlay); SUITE_DECL(font); SUITE_DECL(hush); SUITE_DECL(lib); @@ -114,7 +68,6 @@ SUITE_DECL(mbr); SUITE_DECL(measurement); SUITE_DECL(mem); SUITE_DECL(optee); -SUITE_DECL(overlay); SUITE_DECL(pci_mps); SUITE_DECL(seama); SUITE_DECL(setexpr); @@ -125,15 +78,14 @@ static struct suite suites[] = { SUITE(bdinfo, "bdinfo (board info) command"), SUITE(bloblist, "bloblist implementation"), SUITE(bootm, "bootm command"), -#ifdef CONFIG_UT_BOOTSTD - SUITE_CMD(bootstd, do_ut_bootstd, "standard boot implementation"), -#endif + SUITE(bootstd, "standard boot implementation"), SUITE(cmd, "various commands"), SUITE(common, "tests for common/ directory"), SUITE(dm, "driver model"), SUITE(env, "environment"), SUITE(exit, "shell exit and variables"), SUITE(fdt, "fdt command"), + SUITE(fdt_overlay, "device tree overlays"), SUITE(font, "font command"), SUITE(hush, "hush behaviour"), SUITE(lib, "library functions"), @@ -142,12 +94,7 @@ static struct suite suites[] = { SUITE(mbr, "mbr command"), SUITE(measurement, "TPM-based measured boot"), SUITE(mem, "memory-related commands"), -#ifdef CONFIG_UT_OPTEE - SUITE_CMD(optee, do_ut_optee, "OP-TEE"), -#endif -#ifdef CONFIG_UT_OVERLAY - SUITE_CMD(overlay, do_ut_overlay, "device tree overlays"), -#endif + SUITE(optee, "OP-TEE"), SUITE(pci_mps, "PCI Express Maximum Payload Size"), SUITE(seama, "seama command parameters loading and decoding"), SUITE(setexpr, "setexpr command"), @@ -167,33 +114,59 @@ static bool has_tests(struct suite *ste) { int n_ents = ste->end - ste->start; - return n_ents || ste->cmd; + return n_ents; } /** run_suite() - Run a suite of tests */ static int run_suite(struct unit_test_state *uts, struct suite *ste, - struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) + const char *select_name, int runs_per_test, bool force_run, + const char *test_insert) { + int n_ents = ste->end - ste->start; + char prefix[30]; int ret; - if (ste->cmd) { - ret = ste->cmd(uts, cmdtp, flag, argc, argv); - } else { - int n_ents = ste->end - ste->start; - char prefix[30]; + /* use a standard prefix */ + snprintf(prefix, sizeof(prefix), "%s_test_", ste->name); - /* use a standard prefix */ - snprintf(prefix, sizeof(prefix), "%s_test", ste->name); - ret = cmd_ut_category(uts, ste->name, prefix, ste->start, - n_ents, argc, argv); - } + ret = ut_run_list(uts, ste->name, prefix, ste->start, n_ents, + select_name, runs_per_test, force_run, test_insert); return ret; } -static int do_ut_all(struct unit_test_state *uts, struct cmd_tbl *cmdtp, - int flag, int argc, char *const argv[]) +static void show_stats(struct unit_test_state *uts) +{ + if (uts->run_count < 2) + return; + + ut_report(&uts->total, uts->run_count); + if (CONFIG_IS_ENABLED(UNIT_TEST_DURATION) && + uts->total.test_count && uts->worst) { + ulong avg = uts->total.duration_ms / uts->total.test_count; + + printf("Average test time: %ld ms, worst case '%s' took %d ms\n", + avg, uts->worst->name, uts->worst_ms); + } +} + +static void update_stats(struct unit_test_state *uts, const struct suite *ste) +{ + if (CONFIG_IS_ENABLED(UNIT_TEST_DURATION) && uts->cur.test_count) { + ulong avg; + + avg = uts->cur.duration_ms ? + uts->cur.duration_ms / + uts->cur.test_count : 0; + if (avg > uts->worst_ms) { + uts->worst_ms = avg; + uts->worst = ste; + } + } +} + +static int do_ut_all(struct unit_test_state *uts, const char *select_name, + int runs_per_test, bool force_run, const char *test_insert) { int i; int retval; @@ -201,25 +174,23 @@ static int do_ut_all(struct unit_test_state *uts, struct cmd_tbl *cmdtp, for (i = 0; i < ARRAY_SIZE(suites); i++) { struct suite *ste = &suites[i]; - char *const argv[] = {(char *)ste->name, NULL}; if (has_tests(ste)) { printf("----Running %s tests----\n", ste->name); - retval = run_suite(uts, ste, cmdtp, flag, 1, argv); + retval = run_suite(uts, ste, select_name, runs_per_test, + force_run, test_insert); if (!any_fail) any_fail = retval; + update_stats(uts, ste); } } - ut_report(&uts->total, uts->run_count); return any_fail; } -static int do_ut_info(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) +static int do_ut_info(bool show_suites) { int suite_count, i; - const char *flags; for (suite_count = 0, i = 0; i < ARRAY_SIZE(suites); i++) { struct suite *ste = &suites[i]; @@ -231,24 +202,26 @@ static int do_ut_info(struct cmd_tbl *cmdtp, int flag, int argc, printf("Test suites: %d\n", suite_count); printf("Total tests: %d\n", (int)UNIT_TEST_ALL_COUNT()); - flags = cmd_arg1(argc, argv); - if (flags && !strcmp("-s", flags)) { - int i; + if (show_suites) { + int i, total; puts("\nTests Suite Purpose"); puts("\n----- ------------ -------------------------\n"); - for (i = 0; i < ARRAY_SIZE(suites); i++) { + for (i = 0, total = 0; i < ARRAY_SIZE(suites); i++) { struct suite *ste = &suites[i]; long n_ent = ste->end - ste->start; - if (n_ent) - printf("%5ld", n_ent); - else if (ste->cmd) - printf("%5s", "?"); - else /* suite is not present */ - continue; - printf(" %-13.13s %s\n", ste->name, ste->help); + if (n_ent) { + printf("%5ld %-13.13s %s\n", n_ent, ste->name, + ste->help); + total += n_ent; + } } + puts("----- ------------ -------------------------\n"); + printf("%5d %-13.13s\n", total, "Total"); + + if (UNIT_TEST_ALL_COUNT() != total) + puts("Error: Suite test-count does not match total\n"); } return 0; @@ -269,37 +242,77 @@ static struct suite *find_suite(const char *name) static int do_ut(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + const char *test_insert = NULL, *select_name; struct unit_test_state uts; + bool show_suites = false; + bool force_run = false; + int runs_per_text = 1; struct suite *ste; - const char *name; + char *name; int ret; - if (argc < 2) - return CMD_RET_USAGE; - /* drop initial "ut" arg */ argc--; argv++; + while (argc > 0 && *argv[0] == '-') { + const char *str = argv[0]; + + switch (str[1]) { + case 'r': + runs_per_text = dectoul(str + 2, NULL); + break; + case 'f': + force_run = true; + break; + case 'I': + test_insert = str + 2; + if (!strchr(test_insert, ':')) + return CMD_RET_USAGE; + break; + case 's': + show_suites = true; + break; + } + argv++; + argc--; + } + + if (argc < 1) + return CMD_RET_USAGE; + ut_init_state(&uts); name = argv[0]; + select_name = cmd_arg1(argc, argv); if (!strcmp(name, "all")) { - ret = do_ut_all(&uts, cmdtp, flag, argc, argv); + ret = do_ut_all(&uts, select_name, runs_per_text, force_run, + test_insert); } else if (!strcmp(name, "info")) { - ret = do_ut_info(cmdtp, flag, argc, argv); + ret = do_ut_info(show_suites); } else { - ste = find_suite(argv[0]); - if (!ste) { - printf("Suite '%s' not found\n", argv[0]); - return CMD_RET_FAILURE; - } else if (!has_tests(ste)) { - /* perhaps a Kconfig option needs to be set? */ - printf("Suite '%s' is not enabled\n", argv[0]); - return CMD_RET_FAILURE; + int any_fail = 0; + const char *p; + + for (; p = strsep(&name, ","), p; name = NULL) { + ste = find_suite(p); + if (!ste) { + printf("Suite '%s' not found\n", p); + return CMD_RET_FAILURE; + } else if (!has_tests(ste)) { + /* perhaps a Kconfig option needs to be set? */ + printf("Suite '%s' is not enabled\n", p); + return CMD_RET_FAILURE; + } + + ret = run_suite(&uts, ste, select_name, runs_per_text, + force_run, test_insert); + if (!any_fail) + any_fail = ret; + update_stats(&uts, ste); } - - ret = run_suite(&uts, ste, cmdtp, flag, argc, argv); + ret = any_fail; } + show_stats(&uts); if (ret) return ret; ut_uninit_state(&uts); @@ -308,14 +321,16 @@ static int do_ut(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } U_BOOT_LONGHELP(ut, - "[-r] [-f] [<suite>] - run unit tests\n" + "[-rs] [-f] [-I<n>:<one_test>][<suites>] - run unit tests\n" " -r<runs> Number of times to run each test\n" " -f Force 'manual' tests to run as well\n" - " <suite> Test suite to run, or all\n" + " -I Test to run after <n> other tests have run\n" + " -s Show all suites with ut info\n" + " <suites> Comma-separated list of suites to run\n" "\n" - "\nOptions for <suite>:" - "\nall - execute all enabled tests" - "\ninfo [-s] - show info about tests [and suites]" + "Options for <suite>:\n" + "all - execute all enabled tests\n" + "info - show info about tests [and suites]" ); U_BOOT_CMD( diff --git a/test/common/bloblist.c b/test/common/bloblist.c index ab8f41c6808..797bde27025 100644 --- a/test/common/bloblist.c +++ b/test/common/bloblist.c @@ -6,7 +6,6 @@ #include <bloblist.h> #include <log.h> #include <mapmem.h> -#include <test/suites.h> #include <test/test.h> #include <test/ut.h> diff --git a/test/dm/Kconfig b/test/dm/Kconfig index e5b341e523a..640421c2a79 100644 --- a/test/dm/Kconfig +++ b/test/dm/Kconfig @@ -1,6 +1,6 @@ config UT_DM bool "Enable driver model unit test command" - depends on SANDBOX && UNIT_TEST + depends on SANDBOX help This enables the 'ut dm' command which runs a series of unit tests on the driver model code. Each subsystem (uclass) is tested. diff --git a/test/dm/led.c b/test/dm/led.c index e5b86326c3a..36652c2833a 100644 --- a/test/dm/led.c +++ b/test/dm/led.c @@ -20,7 +20,12 @@ static int dm_test_led_base(struct unit_test_state *uts) ut_assertok(uclass_get_device(UCLASS_LED, 1, &dev)); ut_assertok(uclass_get_device(UCLASS_LED, 2, &dev)); ut_assertok(uclass_get_device(UCLASS_LED, 3, &dev)); - ut_asserteq(-ENODEV, uclass_get_device(UCLASS_LED, 4, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 4, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 5, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 6, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 7, &dev)); + ut_assertok(uclass_get_device(UCLASS_LED, 8, &dev)); + ut_asserteq(-ENODEV, uclass_get_device(UCLASS_LED, 9, &dev)); return 0; } @@ -110,6 +115,21 @@ static int dm_test_led_label(struct unit_test_state *uts) ut_asserteq(-ENODEV, led_get_by_label("sandbox:blue", &dev)); + /* Test if function, color and function-enumerator naming works */ + ut_assertok(led_get_by_label("red:status-20", &dev)); + + /* Test if function, color naming works */ + ut_assertok(led_get_by_label("green:status", &dev)); + + /* Test if function, without color naming works */ + ut_assertok(led_get_by_label(":status", &dev)); + + /* Test if color without function naming works */ + ut_assertok(led_get_by_label("green:", &dev)); + + /* Test if function, color naming is ignored if label is found */ + ut_assertok(led_get_by_label("sandbox:function", &dev)); + return 0; } DM_TEST(dm_test_led_label, UTF_SCAN_PDATA | UTF_SCAN_FDT); diff --git a/test/dm/mux-cmd.c b/test/dm/mux-cmd.c index 6eb3b283161..bd02cda84db 100644 --- a/test/dm/mux-cmd.c +++ b/test/dm/mux-cmd.c @@ -26,8 +26,6 @@ static int dm_test_cmd_mux_list(struct unit_test_state *uts) int i; unsigned long val; - sandbox_set_enable_memio(true); - ut_assertok(uclass_get_device_by_name(UCLASS_MUX, "a-mux-controller", &dev)); chip = dev_get_uclass_priv(dev); @@ -119,8 +117,6 @@ static int dm_test_cmd_mux_select(struct unit_test_state *uts) char cmd[BUF_SIZE]; unsigned int i, state; - sandbox_set_enable_memio(true); - ut_assertok(uclass_get_device_by_name(UCLASS_MUX, "a-mux-controller", &dev)); chip = dev_get_uclass_priv(dev); @@ -153,8 +149,6 @@ static int dm_test_cmd_mux_deselect(struct unit_test_state *uts) char cmd[BUF_SIZE]; unsigned int i, state; - sandbox_set_enable_memio(true); - ut_assertok(uclass_get_device_by_name(UCLASS_MUX, "a-mux-controller", &dev)); chip = dev_get_uclass_priv(dev); diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c index 4a23a3ca38c..cc8b444ff9a 100644 --- a/test/dm/ofnode.c +++ b/test/dm/ofnode.c @@ -1599,7 +1599,7 @@ static int dm_test_ofnode_delete(struct unit_test_state *uts) ut_assert(!ofnode_valid(node)); ut_assert(!ofnode_valid(ofnode_path("/leds/default_on"))); - ut_asserteq(2, ofnode_get_child_count(ofnode_path("/leds"))); + ut_asserteq(7, ofnode_get_child_count(ofnode_path("/leds"))); return 0; } diff --git a/test/env/Kconfig b/test/env/Kconfig index 6cb82337b36..21d88f47a6d 100644 --- a/test/env/Kconfig +++ b/test/env/Kconfig @@ -1,6 +1,5 @@ config UT_ENV bool "Enable env unit tests" - depends on UNIT_TEST default y help This enables the 'ut env' command which runs a series of unit diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c index 81d1bb2f80d..43f1b7d1cef 100644 --- a/test/env/cmd_ut_env.c +++ b/test/env/cmd_ut_env.c @@ -5,7 +5,6 @@ */ #include <test/env.h> -#include <test/suites.h> #include <test/ut.h> static int env_test_env_cmd(struct unit_test_state *uts) diff --git a/test/overlay/Kconfig b/test/fdt_overlay/Kconfig index 881848968bb..c50b8822544 100644 --- a/test/overlay/Kconfig +++ b/test/fdt_overlay/Kconfig @@ -1,6 +1,6 @@ -config UT_OVERLAY +config UT_FDT_OVERLAY bool "Enable Device Tree Overlays Unit Tests" - depends on UNIT_TEST && OF_CONTROL && SANDBOX + depends on OF_CONTROL && SANDBOX default y select OF_LIBFDT_OVERLAY help diff --git a/test/overlay/Makefile b/test/fdt_overlay/Makefile index 47937e3c108..5625c0d8885 100644 --- a/test/overlay/Makefile +++ b/test/fdt_overlay/Makefile @@ -4,7 +4,7 @@ # Copyright (c) 2016 Free Electrons # Test files -obj-y += cmd_ut_overlay.o +obj-y += cmd_ut_fdt_overlay.o DTC_FLAGS += -@ diff --git a/test/overlay/cmd_ut_overlay.c b/test/fdt_overlay/cmd_ut_fdt_overlay.c index aefa147ec04..0084033b6ca 100644 --- a/test/overlay/cmd_ut_overlay.c +++ b/test/fdt_overlay/cmd_ut_fdt_overlay.c @@ -6,6 +6,7 @@ #include <command.h> #include <errno.h> +#include <fdtdec.h> #include <fdt_support.h> #include <image.h> #include <log.h> @@ -13,9 +14,8 @@ #include <linux/sizes.h> +#include <test/fdt_overlay.h> #include <test/ut.h> -#include <test/overlay.h> -#include <test/suites.h> /* 4k ought to be enough for anybody */ #define FDT_COPY_SIZE (4 * SZ_1K) @@ -26,32 +26,61 @@ extern u32 __dtbo_test_fdt_overlay_stacked_begin; static void *fdt; -static int ut_fdt_getprop_u32_by_index(void *fdt, const char *path, - const char *name, int index, - u32 *out) +static int fdt_overlay_init(struct unit_test_state *uts) { - const fdt32_t *val; - int node_off; - int len; + void *fdt_base = &__dtb_test_fdt_base_begin; + void *fdt_overlay = &__dtbo_test_fdt_overlay_begin; + void *fdt_overlay_stacked = &__dtbo_test_fdt_overlay_stacked_begin; + void *fdt_overlay_copy, *fdt_overlay_stacked_copy; - node_off = fdt_path_offset(fdt, path); - if (node_off < 0) - return node_off; + ut_assertok(fdt_check_header(fdt_base)); + ut_assertok(fdt_check_header(fdt_overlay)); - val = fdt_getprop(fdt, node_off, name, &len); - if (!val || (len < (sizeof(uint32_t) * (index + 1)))) - return -FDT_ERR_NOTFOUND; + fdt = malloc(FDT_COPY_SIZE); + fdt_overlay_copy = malloc(FDT_COPY_SIZE); + fdt_overlay_stacked_copy = malloc(FDT_COPY_SIZE); + ut_assertnonnull(fdt); + ut_assertnonnull(fdt_overlay_copy); + ut_assertnonnull(fdt_overlay_stacked_copy); - *out = fdt32_to_cpu(*(val + index)); + /* + * Resize the FDT to 4k so that we have room to operate on + * + * (and relocate it since the memory might be mapped + * read-only) + */ + ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE)); - return 0; -} + /* + * Resize the overlay to 4k so that we have room to operate on + * + * (and relocate it since the memory might be mapped + * read-only) + */ + ut_assertok(fdt_open_into(fdt_overlay, fdt_overlay_copy, + FDT_COPY_SIZE)); -static int ut_fdt_getprop_u32(void *fdt, const char *path, const char *name, - u32 *out) -{ - return ut_fdt_getprop_u32_by_index(fdt, path, name, 0, out); + /* + * Resize the stacked overlay to 4k so that we have room to operate on + * + * (and relocate it since the memory might be mapped + * read-only) + */ + ut_assertok(fdt_open_into(fdt_overlay_stacked, fdt_overlay_stacked_copy, + FDT_COPY_SIZE)); + + /* Apply the overlay */ + ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_copy)); + + /* Apply the stacked overlay */ + ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_stacked_copy)); + + free(fdt_overlay_stacked_copy); + free(fdt_overlay_copy); + + return 0; } +FDT_OVERLAY_TEST_INIT(fdt_overlay_init, 0); static int fdt_getprop_str(void *fdt, const char *path, const char *name, const char **out) @@ -68,19 +97,20 @@ static int fdt_getprop_str(void *fdt, const char *path, const char *name, return len < 0 ? len : 0; } -static int fdt_overlay_change_int_property(struct unit_test_state *uts) +static int fdt_overlay_test_change_int_property(struct unit_test_state *uts) { - u32 val = 0; + int off; - ut_assertok(ut_fdt_getprop_u32(fdt, "/test-node", "test-int-property", - &val)); - ut_asserteq(43, val); + off = fdt_path_offset(fdt, "/test-node"); + ut_assert(off >= 0); + + ut_asserteq(43, fdtdec_get_uint(fdt, off, "test-int-property", 0)); return CMD_RET_SUCCESS; } -OVERLAY_TEST(fdt_overlay_change_int_property, 0); +FDT_OVERLAY_TEST(fdt_overlay_test_change_int_property, 0); -static int fdt_overlay_change_str_property(struct unit_test_state *uts) +static int fdt_overlay_test_change_str_property(struct unit_test_state *uts) { const char *val = NULL; @@ -90,9 +120,9 @@ static int fdt_overlay_change_str_property(struct unit_test_state *uts) return CMD_RET_SUCCESS; } -OVERLAY_TEST(fdt_overlay_change_str_property, 0); +FDT_OVERLAY_TEST(fdt_overlay_test_change_str_property, 0); -static int fdt_overlay_add_str_property(struct unit_test_state *uts) +static int fdt_overlay_test_add_str_property(struct unit_test_state *uts) { const char *val = NULL; @@ -102,9 +132,9 @@ static int fdt_overlay_add_str_property(struct unit_test_state *uts) return CMD_RET_SUCCESS; } -OVERLAY_TEST(fdt_overlay_add_str_property, 0); +FDT_OVERLAY_TEST(fdt_overlay_test_add_str_property, 0); -static int fdt_overlay_add_node_by_phandle(struct unit_test_state *uts) +static int fdt_overlay_test_add_node_by_phandle(struct unit_test_state *uts) { int off; @@ -115,9 +145,9 @@ static int fdt_overlay_add_node_by_phandle(struct unit_test_state *uts) return CMD_RET_SUCCESS; } -OVERLAY_TEST(fdt_overlay_add_node_by_phandle, 0); +FDT_OVERLAY_TEST(fdt_overlay_test_add_node_by_phandle, 0); -static int fdt_overlay_add_node_by_path(struct unit_test_state *uts) +static int fdt_overlay_test_add_node_by_path(struct unit_test_state *uts) { int off; @@ -128,9 +158,9 @@ static int fdt_overlay_add_node_by_path(struct unit_test_state *uts) return CMD_RET_SUCCESS; } -OVERLAY_TEST(fdt_overlay_add_node_by_path, 0); +FDT_OVERLAY_TEST(fdt_overlay_test_add_node_by_path, 0); -static int fdt_overlay_add_subnode_property(struct unit_test_state *uts) +static int fdt_overlay_test_add_subnode_property(struct unit_test_state *uts) { int off; @@ -142,12 +172,12 @@ static int fdt_overlay_add_subnode_property(struct unit_test_state *uts) return CMD_RET_SUCCESS; } -OVERLAY_TEST(fdt_overlay_add_subnode_property, 0); +FDT_OVERLAY_TEST(fdt_overlay_test_add_subnode_property, 0); -static int fdt_overlay_local_phandle(struct unit_test_state *uts) +static int fdt_overlay_test_local_phandle(struct unit_test_state *uts) { uint32_t local_phandle; - u32 val = 0; + u32 val[2]; int off; off = fdt_path_offset(fdt, "/new-local-node"); @@ -156,22 +186,19 @@ static int fdt_overlay_local_phandle(struct unit_test_state *uts) local_phandle = fdt_get_phandle(fdt, off); ut_assert(local_phandle); - ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle", - 0, &val)); - ut_asserteq(local_phandle, val); - - ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle", - 1, &val)); - ut_asserteq(local_phandle, val); + ut_assertok(fdtdec_get_int_array(fdt, 0, "test-several-phandle", val, + ARRAY_SIZE(val))); + ut_asserteq(local_phandle, val[0]); + ut_asserteq(local_phandle, val[1]); return CMD_RET_SUCCESS; } -OVERLAY_TEST(fdt_overlay_local_phandle, 0); +FDT_OVERLAY_TEST(fdt_overlay_test_local_phandle, 0); -static int fdt_overlay_local_phandles(struct unit_test_state *uts) +static int fdt_overlay_test_local_phandles(struct unit_test_state *uts) { uint32_t local_phandle, test_phandle; - u32 val = 0; + u32 val[2]; int off; off = fdt_path_offset(fdt, "/new-local-node"); @@ -186,95 +213,25 @@ static int fdt_overlay_local_phandles(struct unit_test_state *uts) test_phandle = fdt_get_phandle(fdt, off); ut_assert(test_phandle); - ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 0, - &val)); - ut_asserteq(test_phandle, val); - - ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 1, - &val)); - ut_asserteq(local_phandle, val); - - return CMD_RET_SUCCESS; -} -OVERLAY_TEST(fdt_overlay_local_phandles, 0); - -static int fdt_overlay_stacked(struct unit_test_state *uts) -{ - u32 val = 0; - - ut_assertok(ut_fdt_getprop_u32(fdt, "/new-local-node", - "stacked-test-int-property", &val)); - ut_asserteq(43, val); + ut_assertok(fdtdec_get_int_array(fdt, 0, "test-phandle", val, + ARRAY_SIZE(val))); + ut_asserteq(test_phandle, val[0]); + ut_asserteq(local_phandle, val[1]); return CMD_RET_SUCCESS; } -OVERLAY_TEST(fdt_overlay_stacked, 0); +FDT_OVERLAY_TEST(fdt_overlay_test_local_phandles, 0); -int do_ut_overlay(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag, - int argc, char *const argv[]) +static int fdt_overlay_test_stacked(struct unit_test_state *uts) { - struct unit_test *tests = UNIT_TEST_SUITE_START(overlay); - const int n_ents = UNIT_TEST_SUITE_COUNT(overlay); - void *fdt_base = &__dtb_test_fdt_base_begin; - void *fdt_overlay = &__dtbo_test_fdt_overlay_begin; - void *fdt_overlay_stacked = &__dtbo_test_fdt_overlay_stacked_begin; - void *fdt_overlay_copy, *fdt_overlay_stacked_copy; - int ret = -ENOMEM; - - ut_assertok(fdt_check_header(fdt_base)); - ut_assertok(fdt_check_header(fdt_overlay)); - - fdt = malloc(FDT_COPY_SIZE); - if (!fdt) - goto err1; - - fdt_overlay_copy = malloc(FDT_COPY_SIZE); - if (!fdt_overlay_copy) - goto err2; - - fdt_overlay_stacked_copy = malloc(FDT_COPY_SIZE); - if (!fdt_overlay_stacked_copy) - goto err3; - - /* - * Resize the FDT to 4k so that we have room to operate on - * - * (and relocate it since the memory might be mapped - * read-only) - */ - ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE)); - - /* - * Resize the overlay to 4k so that we have room to operate on - * - * (and relocate it since the memory might be mapped - * read-only) - */ - ut_assertok(fdt_open_into(fdt_overlay, fdt_overlay_copy, - FDT_COPY_SIZE)); - - /* - * Resize the stacked overlay to 4k so that we have room to operate on - * - * (and relocate it since the memory might be mapped - * read-only) - */ - ut_assertok(fdt_open_into(fdt_overlay_stacked, fdt_overlay_stacked_copy, - FDT_COPY_SIZE)); - - /* Apply the overlay */ - ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_copy)); + int off; - /* Apply the stacked overlay */ - ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_stacked_copy)); + off = fdt_path_offset(fdt, "/new-local-node"); + ut_assert(off > 0); - ret = cmd_ut_category(uts, "overlay", "", tests, n_ents, argc, argv); + ut_asserteq(43, + fdtdec_get_uint(fdt, off, "stacked-test-int-property", 0)); - free(fdt_overlay_stacked_copy); -err3: - free(fdt_overlay_copy); -err2: - free(fdt); -err1: - return ret; + return CMD_RET_SUCCESS; } +FDT_OVERLAY_TEST(fdt_overlay_test_stacked, 0); diff --git a/test/overlay/test-fdt-base.dts b/test/fdt_overlay/test-fdt-base.dts index 38278334e4d..38278334e4d 100644 --- a/test/overlay/test-fdt-base.dts +++ b/test/fdt_overlay/test-fdt-base.dts diff --git a/test/overlay/test-fdt-overlay-stacked.dtso b/test/fdt_overlay/test-fdt-overlay-stacked.dtso index 6411adec539..6411adec539 100644 --- a/test/overlay/test-fdt-overlay-stacked.dtso +++ b/test/fdt_overlay/test-fdt-overlay-stacked.dtso diff --git a/test/overlay/test-fdt-overlay.dtso b/test/fdt_overlay/test-fdt-overlay.dtso index 5a21b346d07..5a21b346d07 100644 --- a/test/overlay/test-fdt-overlay.dtso +++ b/test/fdt_overlay/test-fdt-overlay.dtso diff --git a/test/lib/string.c b/test/lib/string.c index 8d22f3fd68f..31391a387b9 100644 --- a/test/lib/string.c +++ b/test/lib/string.c @@ -11,6 +11,7 @@ #include <command.h> #include <log.h> +#include <string.h> #include <test/lib.h> #include <test/test.h> #include <test/ut.h> @@ -221,3 +222,42 @@ static int lib_memdup(struct unit_test_state *uts) return 0; } LIB_TEST(lib_memdup, 0); + +/** lib_strnstr() - unit test for strnstr() */ +static int lib_strnstr(struct unit_test_state *uts) +{ + const char *s1 = "Itsy Bitsy Teenie Weenie"; + const char *s2 = "eenie"; + const char *s3 = "eery"; + + ut_asserteq_ptr(&s1[12], strnstr(s1, s2, SIZE_MAX)); + ut_asserteq_ptr(&s1[12], strnstr(s1, s2, 17)); + ut_assertnull(strnstr(s1, s2, 16)); + ut_assertnull(strnstr(s1, s2, 0)); + ut_asserteq_ptr(&s1[13], strnstr(&s1[3], &s2[1], SIZE_MAX)); + ut_asserteq_ptr(&s1[13], strnstr(&s1[3], &s2[1], 14)); + ut_assertnull(strnstr(&s1[3], &s2[1], 13)); + ut_assertnull(strnstr(&s1[3], &s2[1], 0)); + ut_assertnull(strnstr(s1, s3, SIZE_MAX)); + ut_assertnull(strnstr(s1, s3, 0)); + + return 0; +} +LIB_TEST(lib_strnstr, 0); + +/** lib_strstr() - unit test for strstr() */ +static int lib_strstr(struct unit_test_state *uts) +{ + const char *s1 = "Itsy Bitsy Teenie Weenie"; + const char *s2 = "eenie"; + const char *s3 = "easy"; + + ut_asserteq_ptr(&s1[12], strstr(s1, s2)); + ut_asserteq_ptr(&s1[13], strstr(&s1[3], &s2[1])); + ut_assertnull(strstr(s1, s3)); + ut_asserteq_ptr(&s1[2], strstr(s1, &s3[2])); + ut_asserteq_ptr(&s1[8], strstr(&s1[5], &s3[2])); + + return 0; +} +LIB_TEST(lib_strstr, 0); diff --git a/test/log/cont_test.c b/test/log/cont_test.c index 32b1c792367..3b3b791f025 100644 --- a/test/log/cont_test.c +++ b/test/log/cont_test.c @@ -9,7 +9,6 @@ #include <asm/global_data.h> #include <test/log.h> #include <test/test.h> -#include <test/suites.h> #include <test/ut.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c index 341dbfc9310..1913e6817a7 100644 --- a/test/log/nolog_test.c +++ b/test/log/nolog_test.c @@ -13,7 +13,6 @@ #include <asm/global_data.h> #include <test/log.h> #include <test/test.h> -#include <test/suites.h> #include <test/ut.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/test/log/pr_cont_test.c b/test/log/pr_cont_test.c index 7734e927f98..67d8ac59db9 100644 --- a/test/log/pr_cont_test.c +++ b/test/log/pr_cont_test.c @@ -8,7 +8,6 @@ #include <console.h> #include <test/log.h> #include <test/test.h> -#include <test/suites.h> #include <test/ut.h> #include <asm/global_data.h> #include <linux/printk.h> diff --git a/test/log/syslog_test.c b/test/log/syslog_test.c index c4180f775b9..98b91436580 100644 --- a/test/log/syslog_test.c +++ b/test/log/syslog_test.c @@ -15,7 +15,6 @@ #include <hexdump.h> #include <test/log.h> #include <test/test.h> -#include <test/suites.h> #include <test/ut.h> #include <asm/eth.h> #include "syslog_test.h" diff --git a/test/log/syslog_test_ndebug.c b/test/log/syslog_test_ndebug.c index b10e636812b..dfd0217c1e4 100644 --- a/test/log/syslog_test_ndebug.c +++ b/test/log/syslog_test_ndebug.c @@ -12,7 +12,6 @@ #include <hexdump.h> #include <test/log.h> #include <test/test.h> -#include <test/suites.h> #include <test/ut.h> #include <asm/eth.h> #include "syslog_test.h" diff --git a/test/optee/Kconfig b/test/optee/Kconfig index 2f6834aa3b4..63e2cbf79c7 100644 --- a/test/optee/Kconfig +++ b/test/optee/Kconfig @@ -1,6 +1,6 @@ config UT_OPTEE bool "Enable OP-TEE Unit Tests" - depends on UNIT_TEST && OF_CONTROL && OPTEE + depends on OF_CONTROL && OPTEE default y help This enables the 'ut optee' command which runs a series of unit diff --git a/test/optee/Makefile b/test/optee/Makefile index 8793fd7ad61..ec56750fa80 100644 --- a/test/optee/Makefile +++ b/test/optee/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH # Test files -obj-y += cmd_ut_optee.o +obj-y += optee.o DTC_FLAGS += -@ diff --git a/test/optee/cmd_ut_optee.c b/test/optee/optee.c index fc6674764f9..658621fa2fa 100644 --- a/test/optee/cmd_ut_optee.c +++ b/test/optee/optee.c @@ -14,7 +14,6 @@ #include <test/ut.h> #include <test/optee.h> -#include <test/suites.h> /* 4k ought to be enough for anybody */ #define FDT_COPY_SIZE (4 * SZ_1K) @@ -26,6 +25,41 @@ extern u32 __dtb_test_optee_no_optee_begin; static void *fdt; static bool expect_success; +static int optee_test_init(struct unit_test_state *uts) +{ + void *fdt_optee = &__dtb_test_optee_optee_begin; + void *fdt_no_optee = &__dtb_test_optee_no_optee_begin; + void *fdt_base = &__dtb_test_optee_base_begin; + int ret = -ENOMEM; + + ut_assertok(fdt_check_header(fdt_base)); + ut_assertok(fdt_check_header(fdt_optee)); + ut_assertok(fdt_check_header(fdt_no_optee)); + + fdt = malloc(FDT_COPY_SIZE); + if (!fdt) + return ret; + + /* + * Resize the FDT to 4k so that we have room to operate on + * + * (and relocate it since the memory might be mapped + * read-only) + */ + ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE)); + + return 0; +} +OPTEE_TEST_INIT(optee_test_init, 0); + +static int optee_test_uninit(struct unit_test_state *uts) +{ + free(fdt); + + return 0; +} +OPTEE_TEST_UNINIT(optee_test_uninit, 0); + static int optee_fdt_firmware(struct unit_test_state *uts) { const void *prop; @@ -46,7 +80,6 @@ static int optee_fdt_firmware(struct unit_test_state *uts) return CMD_RET_SUCCESS; } -OPTEE_TEST(optee_fdt_firmware, 0); static int optee_fdt_protected_memory(struct unit_test_state *uts) { @@ -89,60 +122,50 @@ static int optee_fdt_protected_memory(struct unit_test_state *uts) return CMD_RET_SUCCESS; } -OPTEE_TEST(optee_fdt_protected_memory, 0); -int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +/* (1) Try to copy optee nodes from empty dt */ +static int optee_fdt_copy_empty(struct unit_test_state *uts) { - struct unit_test *tests = UNIT_TEST_SUITE_START(optee); - const int n_ents = UNIT_TEST_SUITE_COUNT(optee); - struct unit_test_state *uts; - void *fdt_optee = &__dtb_test_optee_optee_begin; void *fdt_no_optee = &__dtb_test_optee_no_optee_begin; - void *fdt_base = &__dtb_test_optee_base_begin; - int ret = -ENOMEM; - - uts = calloc(1, sizeof(*uts)); - if (!uts) - return -ENOMEM; - - ut_assertok(fdt_check_header(fdt_base)); - ut_assertok(fdt_check_header(fdt_optee)); - ut_assertok(fdt_check_header(fdt_no_optee)); - - fdt = malloc(FDT_COPY_SIZE); - if (!fdt) - return ret; - /* - * Resize the FDT to 4k so that we have room to operate on - * - * (and relocate it since the memory might be mapped - * read-only) - */ - ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE)); - - /* - * (1) Try to copy optee nodes from empty dt. - * This should still run successfully. - */ + /* This should still run successfully */ ut_assertok(optee_copy_fdt_nodes(fdt_no_optee, fdt)); expect_success = false; - ret = cmd_ut_category("optee", "", tests, n_ents, argc, argv); + ut_assertok(optee_fdt_firmware(uts)); + ut_assertok(optee_fdt_protected_memory(uts)); + + return 0; +} +OPTEE_TEST(optee_fdt_copy_empty, 0); + +/* (2) Try to copy optee nodes from prefilled dt */ +static int optee_fdt_copy_prefilled(struct unit_test_state *uts) +{ + void *fdt_optee = &__dtb_test_optee_optee_begin; - /* (2) Try to copy optee nodes from prefilled dt */ ut_assertok(optee_copy_fdt_nodes(fdt_optee, fdt)); expect_success = true; - ret = cmd_ut_category("optee", "", tests, n_ents, argc, argv); + ut_assertok(optee_fdt_firmware(uts)); + ut_assertok(optee_fdt_protected_memory(uts)); + + return 0; +} +OPTEE_TEST(optee_fdt_copy_prefilled, 0); + +/* (3) Try to copy OP-TEE nodes into a already filled DT */ +static int optee_fdt_copy_already_filled(struct unit_test_state *uts) +{ + void *fdt_optee = &__dtb_test_optee_optee_begin; - /* (3) Try to copy OP-TEE nodes into a already filled DT */ ut_assertok(fdt_open_into(fdt_optee, fdt, FDT_COPY_SIZE)); ut_assertok(optee_copy_fdt_nodes(fdt_optee, fdt)); expect_success = true; - ret = cmd_ut_category("optee", "", tests, n_ents, argc, argv); + ut_assertok(optee_fdt_firmware(uts)); + ut_assertok(optee_fdt_protected_memory(uts)); - free(fdt); - return ret; + return 0; } +OPTEE_TEST(optee_fdt_copy_already_filled, 0); diff --git a/test/py/requirements.txt b/test/py/requirements.txt index 75760f96e56..acfe17dce9f 100644 --- a/test/py/requirements.txt +++ b/test/py/requirements.txt @@ -1,30 +1,4 @@ -atomicwrites==1.4.1 -attrs==19.3.0 -concurrencytest==0.1.2 -coverage==6.2 -extras==1.0.0 filelock==3.0.12 -fixtures==3.0.0 -importlib-metadata==0.23 -linecache2==1.0.0 -more-itertools==7.2.0 -packaging==24.1 -pbr==5.4.3 -pluggy==0.13.0 -py==1.11.0 -pycryptodomex==3.19.1 -pyelftools==0.27 -pygit2==1.13.3 -pyparsing==3.0.7 +pycryptodomex==3.21.0 pytest==6.2.5 pytest-xdist==2.5.0 -python-mimeparse==1.6.0 -python-subunit==1.3.0 -requests==2.32.3 -setuptools==70.3.0 -six==1.16.0 -testtools==2.3.0 -traceback2==1.4.0 -unittest2==1.1.0 -wcwidth==0.1.7 -zipp==3.19.2 diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py index 45143c1c7d9..177b982e891 100644 --- a/test/py/tests/test_event_dump.py +++ b/test/py/tests/test_event_dump.py @@ -19,6 +19,7 @@ def test_event_dump(u_boot_console): EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.* EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple_os.c:.* EVT_LAST_STAGE_INIT alloc_write_acpi_tables .*lib/acpi/acpi_table.c:.* +EVT_LAST_STAGE_INIT efi_block_device_create .*lib/efi_driver/efi_block_device.c:.* EVT_LAST_STAGE_INIT install_smbios_table .*lib/efi_loader/efi_smbios.c:.* EVT_MISC_INIT_F sandbox_early_getopt_check .*arch/sandbox/cpu/start.c:.* EVT_TEST h_adder_simple .*test/common/event.c:''' diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py index 0abdfa78b76..d57db9178e9 100644 --- a/test/py/tests/test_spi.py +++ b/test/py/tests/test_spi.py @@ -119,37 +119,35 @@ def spi_pre_commands(u_boot_console, freq): pytest.fail('Not recognized the SPI flash part name') m = re.search('page size (.+?) Bytes', output) - if m: - try: - page_size = int(m.group(1)) - except ValueError: - pytest.fail('Not recognized the SPI page size') + assert m + try: + page_size = int(m.group(1)) + except ValueError: + pytest.fail('Not recognized the SPI page size') m = re.search('erase size (.+?) KiB', output) - if m: - try: - erase_size = int(m.group(1)) - except ValueError: - pytest.fail('Not recognized the SPI erase size') - + assert m + try: + erase_size = int(m.group(1)) erase_size *= 1024 + except ValueError: + pytest.fail('Not recognized the SPI erase size') m = re.search('total (.+?) MiB', output) - if m: - try: - total_size = int(m.group(1)) - except ValueError: - pytest.fail('Not recognized the SPI total size') - + assert m + try: + total_size = int(m.group(1)) total_size *= 1024 * 1024 + except ValueError: + pytest.fail('Not recognized the SPI total size') m = re.search('Detected (.+?) with', output) - if m: - try: - flash_part = m.group(1) - assert flash_part == part_name - except ValueError: - pytest.fail('Not recognized the SPI flash part') + assert m + try: + flash_part = m.group(1) + assert flash_part == part_name + except ValueError: + pytest.fail('Not recognized the SPI flash part') global SPI_DATA SPI_DATA = { diff --git a/test/py/tests/test_suite.py b/test/py/tests/test_suite.py index 73c185349b4..9ddc883394b 100644 --- a/test/py/tests/test_suite.py +++ b/test/py/tests/test_suite.py @@ -7,10 +7,10 @@ import re # List of test suites we expect to find with 'ut info' and 'ut all' EXPECTED_SUITES = [ 'addrmap', 'bdinfo', 'bloblist', 'bootm', 'bootstd', - 'cmd', 'common', 'dm', 'env', 'exit', + 'cmd', 'common', 'dm', 'env', 'exit', 'fdt_overlay', 'fdt', 'font', 'hush', 'lib', 'loadm', 'log', 'mbr', 'measurement', 'mem', - 'overlay', 'pci_mps', 'setexpr', 'upl', + 'pci_mps', 'setexpr', 'upl', ] @@ -66,11 +66,12 @@ def collect_info(cons, output): msg = m.group(3) if DEBUG_ME: cons.log.info(f"test_name {test_name} msg '{msg}'") - if msg == ' (flat tree)' and test_name not in tests: - tests.add(test_name) + full_name = f'{cur_suite}.{test_name}' + if msg == ' (flat tree)' and full_name not in tests: + tests.add(full_name) test_count += 1 if not msg or 'skipped as it is manual' in msg: - tests.add(test_name) + tests.add(full_name) test_count += 1 if DEBUG_ME: cons.log.info(f'test_count {test_count}') @@ -134,7 +135,7 @@ def xtest_suite(u_boot_console, u_boot_config): - The number of suites matches that reported by the 'ut info' - Where available, the number of tests is each suite matches that - reported by 'ut info -s' + reported by 'ut -s info' - The total number of tests adds up to the total that are actually run with 'ut all' - All suites are run with 'ut all' @@ -166,7 +167,7 @@ def xtest_suite(u_boot_console, u_boot_config): # Run 'ut info' and compare with the log results with cons.log.section('Check suite test-counts'): - output = cons.run_command('ut info -s') + output = cons.run_command('ut -s info') suite_count, total_test_count, test_count = process_ut_info(cons, output) @@ -186,3 +187,22 @@ def xtest_suite(u_boot_console, u_boot_config): assert suite_count == len(EXPECTED_SUITES) assert total_test_count == len(all_tests) + + # Run three suites + with cons.log.section('Check multiple suites'): + output = cons.run_command('ut bloblist,setexpr,mem') + assert 'Suites run: 3' in output + + # Run a particular test + with cons.log.section('Check single test'): + output = cons.run_command('ut bloblist reloc') + assert 'Test: reloc: bloblist.c' in output + + # Run tests multiple times + with cons.log.section('Check multiple runs'): + output = cons.run_command('ut -r2 bloblist') + lines = output.splitlines() + run = len([line for line in lines if 'Test:' in line]) + count = re.search(r'Tests run: (\d*)', lines[-1]).group(1) + + assert run == 2 * int(count) diff --git a/test/py/tests/test_ums.py b/test/py/tests/test_ums.py index 749b1606235..387571c5140 100644 --- a/test/py/tests/test_ums.py +++ b/test/py/tests/test_ums.py @@ -113,14 +113,12 @@ def test_ums(u_boot_console, env__usb_dev_port, env__block_devs): mount_subdir = env__block_devs[0]['writable_fs_subdir'] part_num = env__block_devs[0]['writable_fs_partition'] host_ums_part_node = '%s-part%d' % (host_ums_dev_node, part_num) + test_f = u_boot_utils.PersistentRandomFile(u_boot_console, 'ums.bin', + 1024 * 1024); + mounted_test_fn = mount_point + '/' + mount_subdir + test_f.fn else: host_ums_part_node = host_ums_dev_node - test_f = u_boot_utils.PersistentRandomFile(u_boot_console, 'ums.bin', - 1024 * 1024); - if have_writable_fs_partition: - mounted_test_fn = mount_point + '/' + mount_subdir + test_f.fn - def start_ums(): """Start U-Boot's ums shell command. @@ -197,25 +195,23 @@ def test_ums(u_boot_console, env__usb_dev_port, env__block_devs): ignore_errors) ignore_cleanup_errors = True - try: - start_ums() - if not have_writable_fs_partition: - # Skip filesystem-based testing if not configured - return + if have_writable_fs_partition: try: - mount() - u_boot_console.log.action('Writing test file via UMS') - cmd = ('rm', '-f', mounted_test_fn) - u_boot_utils.run_and_log(u_boot_console, cmd) - if os.path.exists(mounted_test_fn): - raise Exception('Could not rm target UMS test file') - cmd = ('cp', test_f.abs_fn, mounted_test_fn) - u_boot_utils.run_and_log(u_boot_console, cmd) - ignore_cleanup_errors = False + start_ums() + try: + mount() + u_boot_console.log.action('Writing test file via UMS') + cmd = ('rm', '-f', mounted_test_fn) + u_boot_utils.run_and_log(u_boot_console, cmd) + if os.path.exists(mounted_test_fn): + raise Exception('Could not rm target UMS test file') + cmd = ('cp', test_f.abs_fn, mounted_test_fn) + u_boot_utils.run_and_log(u_boot_console, cmd) + ignore_cleanup_errors = False + finally: + umount(ignore_errors=ignore_cleanup_errors) finally: - umount(ignore_errors=ignore_cleanup_errors) - finally: - stop_ums(ignore_errors=ignore_cleanup_errors) + stop_ums(ignore_errors=ignore_cleanup_errors) ignore_cleanup_errors = True try: diff --git a/test/py/tests/test_usb.py b/test/py/tests/test_usb.py index e1f203b5cbc..9bef883325f 100644 --- a/test/py/tests/test_usb.py +++ b/test/py/tests/test_usb.py @@ -242,7 +242,7 @@ def test_usb_part(u_boot_console): elif part_type == '83': print('ext(2/4) detected') output = u_boot_console.run_command( - 'fstype usb %d:%d' % i, part_id + 'fstype usb %d:%d' % (i, part_id) ) if 'ext2' in output: part_ext2.append(part_id) @@ -580,6 +580,8 @@ def test_usb_load(u_boot_console): elif fs in ['ext4', 'ext2']: file, size, expected_crc32 = \ usb_ext4load_ext4write(u_boot_console, fs, x, part) + else: + raise Exception('Unsupported filesystem type %s' % fs) offset = random.randrange(128, 1024, 128) output = u_boot_console.run_command( diff --git a/test/test-main.c b/test/test-main.c index 22b9b46d9cd..cabc736a524 100644 --- a/test/test-main.c +++ b/test/test-main.c @@ -14,6 +14,7 @@ #include <net.h> #include <of_live.h> #include <os.h> +#include <spl.h> #include <usb.h> #include <dm/ofnode.h> #include <dm/root.h> @@ -513,11 +514,12 @@ static int ut_run_test(struct unit_test_state *uts, struct unit_test *test, * the first call to this function. On exit, @uts->cur.fail_count is * incremented by the number of failures (0, one hopes) * @test: Test to run + * @leaf: Part of the name to show, or NULL to use test->name * Return: 0 if all tests passed, -EAGAIN if the test should be skipped, -1 if * any failed */ static int ut_run_test_live_flat(struct unit_test_state *uts, - struct unit_test *test) + struct unit_test *test, const char *leaf) { int runs, ret; @@ -529,7 +531,7 @@ static int ut_run_test_live_flat(struct unit_test_state *uts, if (CONFIG_IS_ENABLED(OF_LIVE)) { if (!(test->flags & UTF_FLAT_TREE)) { uts->of_live = true; - ret = ut_run_test(uts, test, test->name); + ret = ut_run_test(uts, test, leaf ?: test->name); if (ret != -EAGAIN) { ut_assertok(ret); runs++; @@ -557,7 +559,7 @@ static int ut_run_test_live_flat(struct unit_test_state *uts, (!runs || ut_test_run_on_flattree(test)) && !(gd->flags & GD_FLG_FDT_CHANGED)) { uts->of_live = false; - ret = ut_run_test(uts, test, test->name); + ret = ut_run_test(uts, test, leaf ?: test->name); if (ret != -EAGAIN) { ut_assertok(ret); runs++; @@ -593,6 +595,7 @@ static int ut_run_tests(struct unit_test_state *uts, const char *prefix, struct unit_test *tests, int count, const char *select_name, const char *test_insert) { + int prefix_len = prefix ? strlen(prefix) : 0; struct unit_test *test, *one; int found = 0; int pos = 0; @@ -617,7 +620,8 @@ static int ut_run_tests(struct unit_test_state *uts, const char *prefix, const char *test_name = test->name; int ret, i, old_fail_count; - if (!test_matches(prefix, test_name, select_name)) + if (!(test->flags & (UTF_INIT | UTF_UNINIT)) && + !test_matches(prefix, test_name, select_name)) continue; if (test->flags & UTF_MANUAL) { @@ -645,7 +649,7 @@ static int ut_run_tests(struct unit_test_state *uts, const char *prefix, uts->cur.test_count++; if (one && upto == pos) { - ret = ut_run_test_live_flat(uts, one); + ret = ut_run_test_live_flat(uts, one, NULL); if (uts->cur.fail_count != old_fail_count) { printf("Test '%s' failed %d times (position %d)\n", one->name, @@ -655,8 +659,11 @@ static int ut_run_tests(struct unit_test_state *uts, const char *prefix, return -EBADF; } + if (prefix_len && !strncmp(test_name, prefix, prefix_len)) + test_name = test_name + prefix_len; + for (i = 0; i < uts->runs_per_test; i++) - ret = ut_run_test_live_flat(uts, test); + ret = ut_run_test_live_flat(uts, test, test_name); if (uts->cur.fail_count != old_fail_count) { printf("Test '%s' failed %d times\n", test_name, uts->cur.fail_count - old_fail_count); @@ -680,6 +687,12 @@ void ut_report(struct ut_stats *stats, int run_count) else printf("Tests"); printf(" run: %d, ", stats->test_count); + if (stats && stats->test_count) { + ulong dur = stats->duration_ms; + + printf("%ld ms, average: %ld ms, ", dur, + dur ? dur / stats->test_count : 0); + } if (stats->skip_count) printf("skipped: %d, ", stats->skip_count); printf("failures: %d\n", stats->fail_count); @@ -692,16 +705,22 @@ int ut_run_list(struct unit_test_state *uts, const char *category, { ; bool has_dm_tests = false; + ulong start_offset = 0; + ulong test_offset = 0; int ret; memset(&uts->cur, '\0', sizeof(struct ut_stats)); + if (CONFIG_IS_ENABLED(UNIT_TEST_DURATION)) { + uts->cur.start = get_timer(0); + start_offset = timer_test_get_offset(); + } if (!CONFIG_IS_ENABLED(OF_PLATDATA) && ut_list_has_dm_tests(tests, count, prefix, select_name)) { has_dm_tests = true; /* * If we have no device tree, or it only has a root node, then - * these * tests clearly aren't going to work... + * these tests clearly aren't going to work... */ if (!gd->fdt_blob || fdt_next_node(gd->fdt_blob, 0, NULL) < 0) { puts("Please run with test device tree:\n" @@ -732,13 +751,19 @@ int ut_run_list(struct unit_test_state *uts, const char *category, if (has_dm_tests) dm_test_restore(uts->of_root); - ut_report(&uts->cur, 1); if (ret == -ENOENT) printf("Test '%s' not found\n", select_name); + if (CONFIG_IS_ENABLED(UNIT_TEST_DURATION)) { + test_offset = timer_test_get_offset() - start_offset; + + uts->cur.duration_ms = get_timer(uts->cur.start) - test_offset; + } + ut_report(&uts->cur, 1); uts->total.skip_count += uts->cur.skip_count; uts->total.fail_count += uts->cur.fail_count; uts->total.test_count += uts->cur.test_count; + uts->total.duration_ms += uts->cur.duration_ms; uts->run_count++; return ret; diff --git a/tools/.gitignore b/tools/.gitignore index 0108c567309..6a5c613f772 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -29,6 +29,7 @@ /mxsboot /ncb /prelink-riscv +/preload_check_sign /printinitialenv /proftool /relocate-rela diff --git a/tools/Kconfig b/tools/Kconfig index 5c75af48fe3..8e272ee99a8 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -9,6 +9,16 @@ config MKIMAGE_DTC_PATH some cases the system dtc may not support all required features and the path to a different version should be given here. +config TOOLS_IMAGE_PRE_LOAD + def_bool y + help + Enable pre-load signature support in the tools builds. + +config TOOLS_CRC16 + def_bool y + help + Enable CRC32 support in the tools builds + config TOOLS_CRC32 def_bool y help diff --git a/tools/Makefile b/tools/Makefile index 237fa900a24..e5f5eea47c7 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -66,6 +66,7 @@ mkenvimage-objs := mkenvimage.o os_support.o generated/lib/crc32.o hostprogs-y += dumpimage mkimage hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fit_info fit_check_sign hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fdt_add_pubkey +hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += preload_check_sign ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_FWU_MDATA_GPT_BLK),) hostprogs-y += file2include @@ -89,6 +90,8 @@ ECDSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/ecdsa/, ecdsa- AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/aes/, \ aes-encrypt.o aes-decrypt.o) +PRELOAD_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := generated/boot/image-pre-load.o + # Cryptographic helpers and image types that depend on openssl/libcrypto LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := \ generated/lib/fdt-libcrypto.o \ @@ -158,6 +161,7 @@ fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o fdt_add_pubkey-objs := $(dumpimage-mkimage-objs) fdt_add_pubkey.o file2include-objs := file2include.o +preload_check_sign-objs := $(dumpimage-mkimage-objs) $(PRELOAD_OBJS-y) preload_check_sign.o ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_TOOLS_LIBCRYPTO),) # Add CFG_MXS into host CFLAGS, so we can check whether or not register @@ -195,6 +199,7 @@ HOSTLDLIBS_dumpimage := $(HOSTLDLIBS_mkimage) HOSTLDLIBS_fit_info := $(HOSTLDLIBS_mkimage) HOSTLDLIBS_fit_check_sign := $(HOSTLDLIBS_mkimage) HOSTLDLIBS_fdt_add_pubkey := $(HOSTLDLIBS_mkimage) +HOSTLDLIBS_preload_check_sign := $(HOSTLDLIBS_mkimage) hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl diff --git a/tools/binman/etype/fdtmap.py b/tools/binman/etype/fdtmap.py index f1f6217940f..2259404180c 100644 --- a/tools/binman/etype/fdtmap.py +++ b/tools/binman/etype/fdtmap.py @@ -106,6 +106,9 @@ class Entry_fdtmap(Entry): Returns: FDT map binary data """ + fsw = libfdt.FdtSw() + fsw.finish_reservemap() + def _AddNode(node): """Add a node to the FDT map""" for pname, prop in node.props.items(): @@ -134,8 +137,6 @@ class Entry_fdtmap(Entry): # Build a new tree with all nodes and properties starting from that # node - fsw = libfdt.FdtSw() - fsw.finish_reservemap() with fsw.add_node(''): fsw.property_string('image-node', node.name) _AddNode(node) diff --git a/tools/binman/etype/image_header.py b/tools/binman/etype/image_header.py index 24011884958..2114df8159f 100644 --- a/tools/binman/etype/image_header.py +++ b/tools/binman/etype/image_header.py @@ -62,6 +62,7 @@ class Entry_image_header(Entry): def _GetHeader(self): image_pos = self.GetSiblingImagePos('fdtmap') + offset = None if image_pos == False: self.Raise("'image_header' section must have an 'fdtmap' sibling") elif image_pos is None: diff --git a/tools/binman/etype/pre_load.py b/tools/binman/etype/pre_load.py index 2e4c72359ff..00f1a896767 100644 --- a/tools/binman/etype/pre_load.py +++ b/tools/binman/etype/pre_load.py @@ -112,6 +112,8 @@ class Entry_pre_load(Entry_collection): # Compute the signature if padding_name is None: padding_name = "pkcs-1.5" + padding = None + padding_args = None if padding_name == "pss": salt_len = key.size_in_bytes() - hash_image.digest_size - 2 padding = pss diff --git a/tools/binman/etype/ti_board_config.py b/tools/binman/etype/ti_board_config.py index c10d66edcb1..7c6773ac7bc 100644 --- a/tools/binman/etype/ti_board_config.py +++ b/tools/binman/etype/ti_board_config.py @@ -119,12 +119,14 @@ class Entry_ti_board_config(Entry_section): array of bytes representing value """ size = 0 + br = bytearray() if (data_type == '#/definitions/u8'): size = 1 elif (data_type == '#/definitions/u16'): size = 2 else: size = 4 + br = None if type(val) == int: br = val.to_bytes(size, byteorder='little') return br diff --git a/tools/binman/etype/x509_cert.py b/tools/binman/etype/x509_cert.py index 29630d1b86c..25e6808b7f9 100644 --- a/tools/binman/etype/x509_cert.py +++ b/tools/binman/etype/x509_cert.py @@ -84,6 +84,7 @@ class Entry_x509_cert(Entry_collection): input_fname = tools.get_output_filename('input.%s' % uniq) config_fname = tools.get_output_filename('config.%s' % uniq) tools.write_file(input_fname, input_data) + stdout = None if type == 'generic': stdout = self.openssl.x509_cert( cert_fname=output_fname, diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 9f6688ee7a4..1bc2fca26ea 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -763,6 +763,16 @@ class TestFunctional(unittest.TestCase): return False return True + def _CheckPreload(self, image, key, algo="sha256,rsa2048", + padding="pkcs-1.5"): + try: + tools.run('preload_check_sign', '-k', key, '-a', algo, '-p', + padding, '-f', image) + except: + self.fail('Expected image signed with a pre-load') + return False + return True + def testRun(self): """Test a basic run with valid args""" result = self._RunBinman('-h') @@ -5782,9 +5792,14 @@ fdt fdtmap Extract the devicetree blob from the fdtmap data = self._DoReadFileDtb( '230_pre_load.dts', entry_args=entry_args, extra_indirs=[os.path.join(self._binman_dir, 'test')])[0] + + image_fname = tools.get_output_filename('image.bin') + is_signed = self._CheckPreload(image_fname, self.TestFile("dev.key")) + self.assertEqual(PRE_LOAD_MAGIC, data[:len(PRE_LOAD_MAGIC)]) self.assertEqual(PRE_LOAD_VERSION, data[4:4 + len(PRE_LOAD_VERSION)]) self.assertEqual(PRE_LOAD_HDR_SIZE, data[8:8 + len(PRE_LOAD_HDR_SIZE)]) + self.assertEqual(is_signed, True) def testPreLoadNoKey(self): """Test an image with a pre-load heade0r with missing key""" @@ -6382,6 +6397,7 @@ fdt fdtmap Extract the devicetree blob from the fdtmap ename, prop = entry_m.group(1), entry_m.group(3) entry, entry_name, prop_name = image.LookupEntry(entries, name, msg) + expect_val = None if prop_name == 'offset': expect_val = entry.offset elif prop_name == 'image_pos': diff --git a/tools/binman/requirements.txt b/tools/binman/requirements.txt new file mode 100644 index 00000000000..f068ef75a30 --- /dev/null +++ b/tools/binman/requirements.txt @@ -0,0 +1,5 @@ +importlib_resources==6.5.2 +jsonschema==4.23.0 +pycryptodomex==3.21.0 +pyelftools==0.31 +yamllint==1.35.1 diff --git a/tools/binman/setup.py b/tools/binman/setup.py index 9a9206eb044..bec078a3d9b 100644 --- a/tools/binman/setup.py +++ b/tools/binman/setup.py @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -from distutils.core import setup +from setuptools import setup setup(name='binman', version='1.0', license='GPL-2.0+', diff --git a/tools/binman/state.py b/tools/binman/state.py index 45bae40c525..6772d3678fe 100644 --- a/tools/binman/state.py +++ b/tools/binman/state.py @@ -406,10 +406,13 @@ def CheckSetHashValue(node, get_data_func): hash_node = node.FindNode('hash') if hash_node: algo = hash_node.props.get('algo').value + data = None if algo == 'sha256': m = hashlib.sha256() m.update(get_data_func()) data = m.digest() + if data is None: + raise ValueError(f"Node '{node.path}': Unknown hash algorithm '{algo}'") for n in GetUpdateNodes(hash_node): n.SetData('value', data) diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index 3eac17ac212..4bea0a02b78 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -19,8 +19,8 @@ import time from buildman import builderthread from buildman import toolchain -from patman import gitutil from u_boot_pylib import command +from u_boot_pylib import gitutil from u_boot_pylib import terminal from u_boot_pylib import tools from u_boot_pylib.terminal import tprint @@ -1096,14 +1096,13 @@ class Builder: diff = result[name] if name.startswith('_'): continue - if diff != 0: - color = self.col.RED if diff > 0 else self.col.GREEN + colour = self.col.RED if diff > 0 else self.col.GREEN msg = ' %s %+d' % (name, diff) if not printed_target: tprint('%10s %-15s:' % ('', result['_target']), newline=False) printed_target = True - tprint(msg, colour=color, newline=False) + tprint(msg, colour=colour, newline=False) if printed_target: tprint() if show_bloat: @@ -1354,6 +1353,7 @@ class Builder: for line in lines: if not line: continue + col = None if line[0] == '+': col = self.col.GREEN elif line[0] == '-': diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py index 7646f2e3e27..b8578d5b97b 100644 --- a/tools/buildman/builderthread.py +++ b/tools/buildman/builderthread.py @@ -17,8 +17,8 @@ import sys import threading from buildman import cfgutil -from patman import gitutil from u_boot_pylib import command +from u_boot_pylib import gitutil from u_boot_pylib import tools RETURN_CODE_RETRY = -1 diff --git a/tools/buildman/control.py b/tools/buildman/control.py index 55d4d770c5c..5109b1cd5ce 100644 --- a/tools/buildman/control.py +++ b/tools/buildman/control.py @@ -20,9 +20,9 @@ from buildman import bsettings from buildman import cfgutil from buildman import toolchain from buildman.builder import Builder -from patman import gitutil from patman import patchstream from u_boot_pylib import command +from u_boot_pylib import gitutil from u_boot_pylib import terminal from u_boot_pylib import tools from u_boot_pylib.terminal import print_clear, tprint diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py index 1afc2fb1594..d779040c74e 100644 --- a/tools/buildman/func_test.py +++ b/tools/buildman/func_test.py @@ -18,8 +18,8 @@ from buildman import bsettings from buildman import cmdline from buildman import control from buildman import toolchain -from patman import gitutil from u_boot_pylib import command +from u_boot_pylib import gitutil from u_boot_pylib import terminal from u_boot_pylib import test_util from u_boot_pylib import tools diff --git a/tools/buildman/main.py b/tools/buildman/main.py index a948f36d9c0..72571b226d9 100755 --- a/tools/buildman/main.py +++ b/tools/buildman/main.py @@ -50,8 +50,7 @@ def run_tests(skip_net_tests, debug, verbose, args): # 'entry' module. result = test_util.run_test_suites( 'buildman', debug, verbose, False, args.threads, test_name, [], - [test.TestBuild, func_test.TestFunctional, - 'buildman.toolchain', 'patman.gitutil']) + [test.TestBuild, func_test.TestFunctional, 'buildman.toolchain']) return (0 if result.wasSuccessful() else 1) diff --git a/tools/buildman/requirements.txt b/tools/buildman/requirements.txt index 052d0ed5c6f..d48650cd1e5 100644 --- a/tools/buildman/requirements.txt +++ b/tools/buildman/requirements.txt @@ -1,5 +1,2 @@ -coverage==6.2 -jsonschema==4.17.3 -pycryptodome==3.20 -pyyaml==6.0 -yamllint==1.26.3 +filelock==3.0.12 +importlib_resources==6.5.2 diff --git a/tools/buildman/test.py b/tools/buildman/test.py index 385a34e5254..c5feb74a105 100644 --- a/tools/buildman/test.py +++ b/tools/buildman/test.py @@ -836,6 +836,7 @@ class TestBuild(unittest.TestCase): tmpdir = self.base_dir with (patch('time.time', side_effect=self.get_time), + patch('time.perf_counter', side_effect=self.get_time), patch('time.monotonic', side_effect=self.get_time), patch('time.sleep', side_effect=self.inc_time), patch('os.kill', side_effect=self.kill)): diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index d2848ab85f3..85d67848327 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -122,7 +122,6 @@ RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \ python3 \ python3-dev \ python3-pip \ - python3-pyelftools \ python3-sphinx \ python3-virtualenv \ rpm2cpio \ @@ -308,12 +307,18 @@ USER uboot:uboot # COPY / ADD directives don't work as we need them to. RUN wget -O /tmp/pytest-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/test/py/requirements.txt RUN wget -O /tmp/sphinx-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/doc/sphinx/requirements.txt +RUN wget -O /tmp/binman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/binman/requirements.txt RUN wget -O /tmp/buildman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/buildman/requirements.txt +RUN wget -O /tmp/patman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/patman/requirements.txt +RUN wget -O /tmp/u_boot_pylib-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/u_boot_pylib/requirements.txt RUN virtualenv -p /usr/bin/python3 /tmp/venv && \ . /tmp/venv/bin/activate && \ pip install -r /tmp/pytest-requirements.txt \ -r /tmp/sphinx-requirements.txt \ - -r /tmp/buildman-requirements.txt && \ + -r /tmp/binman-requirements.txt \ + -r /tmp/buildman-requirements.txt \ + -r /tmp/patman-requirements.txt \ + -r /tmp/u_boot_pylib-requirements.txt && \ deactivate && \ rm -rf /tmp/venv /tmp/*-requirements.txt diff --git a/tools/dtoc/setup.py b/tools/dtoc/setup.py index 5e092fe0872..ae9ad043b01 100644 --- a/tools/dtoc/setup.py +++ b/tools/dtoc/setup.py @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -from distutils.core import setup +from setuptools import setup setup(name='dtoc', version='1.0', license='GPL-2.0+', diff --git a/tools/image-host.c b/tools/image-host.c index 84095d760c1..a9b86902763 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -19,6 +19,11 @@ #include <openssl/evp.h> #endif +#if CONFIG_IS_ENABLED(IMAGE_PRE_LOAD) +#include <openssl/rsa.h> +#include <openssl/err.h> +#endif + /** * fit_set_hash_value - set hash value in requested has node * @fit: pointer to the FIT format image header @@ -364,33 +369,46 @@ static int fit_image_read_key_iv_data(const char *keydir, const char *key_iv_nam return ret; } -static int get_random_data(void *data, int size) +/** + * get_random_data() - fill buffer with random data + * + * There is no common cryptographically safe function in Linux and BSD. + * Hence directly access the /dev/urandom PRNG. + * + * @data: buffer to fill + * @size: buffer size + */ +static int get_random_data(void *data, size_t size) { - unsigned char *tmp = data; - struct timespec date; - int i, ret; - - if (!tmp) { - fprintf(stderr, "%s: pointer data is NULL\n", __func__); - ret = -1; - goto out; - } + int fd; + int ret; - ret = clock_gettime(CLOCK_MONOTONIC, &date); - if (ret) { - fprintf(stderr, "%s: clock_gettime has failed (%s)\n", __func__, - strerror(errno)); - goto out; + fd = open("/dev/urandom", O_RDONLY); + if (fd < 0) { + perror("Failed to open /dev/urandom"); + return -1; } - srandom(date.tv_nsec); + while (size) { + ssize_t count; - for (i = 0; i < size; i++) { - *tmp = random() & 0xff; - tmp++; + count = read(fd, data, size); + if (count < 0) { + if (errno == EINTR) { + continue; + } else { + perror("Failed to read from /dev/urandom"); + ret = -1; + goto out; + } + } + data += count; + size -= count; } + ret = 0; +out: + close(fd); - out: return ret; } @@ -716,11 +734,20 @@ static int strlist_add(struct strlist *list, const char *str) { char *dup; + if (!list || !str) + return -1; + dup = strdup(str); + if(!dup) + return -1; + list->strings = realloc(list->strings, (list->count + 1) * sizeof(char *)); - if (!list || !str) + if (!list->strings) { + free(dup); return -1; + } + list->strings[list->count++] = dup; return 0; @@ -1388,3 +1415,139 @@ int fit_check_sign(const void *fit, const void *key, return ret; } #endif + +#if CONFIG_IS_ENABLED(IMAGE_PRE_LOAD) +/** + * rsa_verify_openssl() - Verify a signature against some data with openssl API + * + * Verify a RSA PKCS1.5/PSS signature against an expected hash. + * + * @info: Specifies the key and algorithms + * @region: Pointer to the input data + * @region_count: Number of region + * @sig: Signature + * @sig_len: Number of bytes in the signature + * Return: 0 if verified, -ve on error + */ +int rsa_verify_openssl(struct image_sign_info *info, + const struct image_region region[], int region_count, + uint8_t *sig, uint sig_len) +{ + EVP_PKEY *pkey = NULL; + EVP_PKEY_CTX *ckey = NULL; + EVP_MD_CTX *ctx = NULL; + int pad; + int size; + int i; + int ret = 0; + + if (!info) { + fprintf(stderr, "No info provided\n"); + ret = -EINVAL; + goto out; + } + + if (!info->key) { + fprintf(stderr, "No key provided\n"); + ret = -EINVAL; + goto out; + } + + if (!info->checksum) { + fprintf(stderr, "No checksum information\n"); + ret = -EINVAL; + goto out; + } + + if (!info->padding) { + fprintf(stderr, "No padding information\n"); + ret = -EINVAL; + goto out; + } + + if (region_count < 1) { + fprintf(stderr, "Invalid value for region_count: %d\n", region_count); + ret = -EINVAL; + goto out; + } + + pkey = (EVP_PKEY *)info->key; + + ckey = EVP_PKEY_CTX_new(pkey, NULL); + if (!ckey) { + ret = -ENOMEM; + fprintf(stderr, "EVK key context setup failed: %s\n", + ERR_error_string(ERR_get_error(), NULL)); + goto out; + } + + size = EVP_PKEY_size(pkey); + if (size > sig_len) { + fprintf(stderr, "Invalid signature size (%d bytes)\n", + size); + ret = -EINVAL; + goto out; + } + + ctx = EVP_MD_CTX_new(); + if (!ctx) { + ret = -ENOMEM; + fprintf(stderr, "EVP context creation failed: %s\n", + ERR_error_string(ERR_get_error(), NULL)); + goto out; + } + EVP_MD_CTX_init(ctx); + + if (EVP_DigestVerifyInit(ctx, &ckey, + EVP_get_digestbyname(info->checksum->name), + NULL, pkey) <= 0) { + ret = -EINVAL; + fprintf(stderr, "Verifier setup failed: %s\n", + ERR_error_string(ERR_get_error(), NULL)); + goto out; + } + + if (!strcmp(info->padding->name, "pkcs-1.5")) { + pad = RSA_PKCS1_PADDING; + } else if (!strcmp(info->padding->name, "pss")) { + pad = RSA_PKCS1_PSS_PADDING; + } else { + ret = -ENOMSG; + fprintf(stderr, "Unsupported padding: %s\n", + info->padding->name); + goto out; + } + + if (EVP_PKEY_CTX_set_rsa_padding(ckey, pad) <= 0) { + ret = -EINVAL; + fprintf(stderr, "padding setup has failed: %s\n", + ERR_error_string(ERR_get_error(), NULL)); + goto out; + } + + for (i=0 ; i < region_count ; ++i) { + if (EVP_DigestVerifyUpdate(ctx, region[i].data, + region[i].size) <= 0) { + ret = -EINVAL; + fprintf(stderr, "Hashing data failed: %s\n", + ERR_error_string(ERR_get_error(), NULL)); + goto out; + } + } + + if (EVP_DigestVerifyFinal(ctx, sig, sig_len) <= 0) { + ret = -EINVAL; + fprintf(stderr, "Verifying digest failed: %s\n", + ERR_error_string(ERR_get_error(), NULL)); + goto out; + } +out: + if (ctx) + EVP_MD_CTX_free(ctx); + + if (ret) + fprintf(stderr, "Failed to verify signature\n"); + + return ret; +} +#endif diff --git a/tools/imx8image.c b/tools/imx8image.c index 15510d3e712..0135b190951 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -290,6 +290,7 @@ static uint32_t parse_cfg_file(image_t *param_stack, char *name) } } + free(line); fclose(fd); return 0; } diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c index d60d293e649..0f24ba75c0f 100644 --- a/tools/imx8mimage.c +++ b/tools/imx8mimage.c @@ -206,6 +206,7 @@ static uint32_t parse_cfg_file(char *name) } } + free(line); fclose(fd); return 0; } diff --git a/tools/imximage.c b/tools/imximage.c index 467d9f27d2a..55231caf8f3 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -783,6 +783,7 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name) } (*set_dcd_rst)(imxhdr, dcd_len, name, lineno); + free(line); fclose(fd); /* Exit if there is no BOOT_FROM field specifying the flash_offset */ diff --git a/tools/kwbimage.c b/tools/kwbimage.c index d1cbced28fc..3dcf5ba66b9 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -1653,6 +1653,12 @@ static int image_create_config_parse_oneline(char *line, char *unknown_msg = "Ignoring unknown line '%s'\n"; keyword = strtok_r(line, delimiters, &saveptr); + + if (!keyword) { + fprintf(stderr, "Parameter missing in line '%s'\n", line); + return -1; + } + keyword_id = recognize_keyword(keyword); if (!keyword_id) { diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py index 24c02c4fca1..b726794751a 100755 --- a/tools/microcode-tool.py +++ b/tools/microcode-tool.py @@ -279,6 +279,9 @@ def MicrocodeTool(): if (not not options.mcfile) != (not not options.mcfile): parser.error("You must specify either header files or a microcode file, not both") + date = None + microcodes = None + license_text = None if options.headerfile: date, license_text, microcodes = ParseHeaderFiles(options.headerfile) elif options.mcfile: diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index a8eebab6c33..885cdb1390e 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -28,7 +28,7 @@ static void usage(const char *exec_name) { - fprintf(stderr, "%s [-h] [-r] [-b] [-p <byte>] -s <environment partition size> -o <output> <input file>\n" + fprintf(stderr, "%s [-h] [-V] [-r] [-b] [-p <byte>] -s <environment partition size> -o <output> <input file>\n" "\n" "This tool takes a key=value input file (same as would a `printenv' show) and generates the corresponding environment image, ready to be flashed.\n" "\n" diff --git a/tools/mkimage.h b/tools/mkimage.h index 15741f250fd..5d6bcc9301a 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -37,6 +37,10 @@ static inline void *map_sysmem(ulong paddr, unsigned long len) return (void *)(uintptr_t)paddr; } +static inline void unmap_sysmem(const void *vaddr) +{ +} + static inline ulong map_to_sysmem(const void *ptr) { return (ulong)(uintptr_t)ptr; diff --git a/tools/patman/__init__.py b/tools/patman/__init__.py index 08eeffdf6d2..6de0e9fba10 100644 --- a/tools/patman/__init__.py +++ b/tools/patman/__init__.py @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ __all__ = ['checkpatch', 'commit', 'control', 'func_test', 'get_maintainer', - 'gitutil', '__main__', 'patchstream', 'project', 'series', - 'settings','setup', 'status', 'test_checkpatch', 'test_settings'] + '__main__', 'patchstream', 'project', 'series', + 'settings', 'setup', 'status', 'test_checkpatch', 'test_settings'] diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py index f645b38b647..36f1c08507c 100755 --- a/tools/patman/__main__.py +++ b/tools/patman/__main__.py @@ -49,7 +49,7 @@ def run_patman(): result = test_util.run_test_suites( 'patman', False, False, False, None, None, None, [test_checkpatch.TestPatch, func_test.TestFunctional, - 'gitutil', 'settings']) + 'settings']) sys.exit(0 if result.wasSuccessful() else 1) diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py index e03cac115e4..2975881705c 100644 --- a/tools/patman/checkpatch.py +++ b/tools/patman/checkpatch.py @@ -8,8 +8,8 @@ import os import re import sys -from patman import gitutil from u_boot_pylib import command +from u_boot_pylib import gitutil from u_boot_pylib import terminal EMACS_PREFIX = r'(?:[0-9]{4}.*\.patch:[0-9]+: )?' diff --git a/tools/patman/cmdline.py b/tools/patman/cmdline.py index d6496c0cb78..562bc823f60 100644 --- a/tools/patman/cmdline.py +++ b/tools/patman/cmdline.py @@ -13,8 +13,8 @@ import os import pathlib import sys -from patman import gitutil from patman import project +from u_boot_pylib import gitutil from patman import settings PATMAN_DIR = pathlib.Path(__file__).parent diff --git a/tools/patman/control.py b/tools/patman/control.py index b292da9dc27..fb5a4246ced 100644 --- a/tools/patman/control.py +++ b/tools/patman/control.py @@ -12,8 +12,8 @@ import os import sys from patman import checkpatch -from patman import gitutil from patman import patchstream +from u_boot_pylib import gitutil from u_boot_pylib import terminal diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py index af6c025a441..bf333dc557b 100644 --- a/tools/patman/func_test.py +++ b/tools/patman/func_test.py @@ -18,11 +18,11 @@ import unittest from patman.commit import Commit from patman import control -from patman import gitutil from patman import patchstream from patman.patchstream import PatchStream from patman.series import Series from patman import settings +from u_boot_pylib import gitutil from u_boot_pylib import terminal from u_boot_pylib import tools from u_boot_pylib.test_util import capture_sys_output diff --git a/tools/patman/get_maintainer.py b/tools/patman/get_maintainer.py index 8df3d124bac..200ee96551d 100644 --- a/tools/patman/get_maintainer.py +++ b/tools/patman/get_maintainer.py @@ -7,8 +7,8 @@ import os import shlex import shutil -from patman import gitutil from u_boot_pylib import command +from u_boot_pylib import gitutil def find_get_maintainer(script_file_name): diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index 940b50ca8d4..490d382045b 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -15,9 +15,9 @@ import shutil import tempfile from patman import commit -from patman import gitutil from patman.series import Series from u_boot_pylib import command +from u_boot_pylib import gitutil # Tags that we detect and remove RE_REMOVE = re.compile(r'^BUG=|^TEST=|^BRANCH=|^Review URL:' diff --git a/tools/patman/project.py b/tools/patman/project.py index 4459042b5d4..d6143a67066 100644 --- a/tools/patman/project.py +++ b/tools/patman/project.py @@ -4,7 +4,7 @@ import os.path -from patman import gitutil +from u_boot_pylib import gitutil def detect_project(): """Autodetect the name of the current project. diff --git a/tools/patman/requirements.txt b/tools/patman/requirements.txt new file mode 100644 index 00000000000..e8cbc6cf0c3 --- /dev/null +++ b/tools/patman/requirements.txt @@ -0,0 +1,5 @@ +ConfigParser==7.1.0 +importlib_resources==6.5.2 +pygit2==1.13.3 +Requests==2.32.3 +setuptools==75.8.0 diff --git a/tools/patman/series.py b/tools/patman/series.py index 6866e1dbd08..d7f2f010f5d 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -12,8 +12,8 @@ import sys import time from patman import get_maintainer -from patman import gitutil from patman import settings +from u_boot_pylib import gitutil from u_boot_pylib import terminal from u_boot_pylib import tools diff --git a/tools/patman/settings.py b/tools/patman/settings.py index 68c93e313b3..d66b22be1df 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -12,7 +12,7 @@ import argparse import os import re -from patman import gitutil +from u_boot_pylib import gitutil """Default settings per-project. diff --git a/tools/patman/test_checkpatch.py b/tools/patman/test_checkpatch.py index db7860f551d..3bf16febbf6 100644 --- a/tools/patman/test_checkpatch.py +++ b/tools/patman/test_checkpatch.py @@ -11,10 +11,10 @@ import tempfile import unittest from patman import checkpatch -from patman import gitutil from patman import patchstream from patman import series from patman import commit +from u_boot_pylib import gitutil class Line: @@ -530,4 +530,3 @@ index 0000000..2234c87 if __name__ == "__main__": unittest.main() - gitutil.RunTests() diff --git a/tools/preload_check_sign.c b/tools/preload_check_sign.c new file mode 100644 index 00000000000..ebead459273 --- /dev/null +++ b/tools/preload_check_sign.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Check a file including a preload header including a signature + * + * Copyright (c) 2025 Paul HENRYS <paul.henrys_ext@softathome.com> + * + * Binman makes it possible to generate a preload header signing part or the + * complete file. The tool preload_check_sign allows to verify and authenticate + * a file starting with a preload header. + */ +#include <stdio.h> +#include <unistd.h> +#include <openssl/pem.h> +#include <openssl/evp.h> +#include <openssl/err.h> +#include <image.h> + +extern void image_pre_load_sig_set_info(struct image_sig_info *info); +extern int image_pre_load_sig(ulong addr); + +static void usage(char *cmdname) +{ + fprintf(stderr, "Usage: %s -f file -k PEM key file\n" + " -f ==> set file which should be checked\n" + " -k ==> PEM key file\n" + " -a ==> algo (default: sha256,rsa2048)\n" + " -p ==> padding (default: pkcs-1.5)\n" + " -h ==> help\n", + cmdname); + exit(EXIT_FAILURE); +} + +int main(int argc, char **argv) +{ + int ret = 0; + char cmdname[256]; + char *file = NULL; + char *keyfile = NULL; + int c; + FILE *fp = NULL; + FILE *fp_key = NULL; + size_t bytes; + long filesize; + void *buffer = NULL; + EVP_PKEY *pkey = NULL; + char *algo = "sha256,rsa2048"; + char *padding = "pkcs-1.5"; + struct image_sig_info info = {0}; + + strncpy(cmdname, *argv, sizeof(cmdname) - 1); + cmdname[sizeof(cmdname) - 1] = '\0'; + while ((c = getopt(argc, argv, "f:k:a:p:h")) != -1) + switch (c) { + case 'f': + file = optarg; + break; + case 'k': + keyfile = optarg; + break; + case 'a': + algo = optarg; + break; + case 'p': + padding = optarg; + break; + default: + usage(cmdname); + break; + } + + if (!file) { + fprintf(stderr, "%s: Missing file\n", *argv); + usage(*argv); + } + + if (!keyfile) { + fprintf(stderr, "%s: Missing key file\n", *argv); + usage(*argv); + } + + fp = fopen(file, "r"); + if (!fp) { + fprintf(stderr, "Error opening file: %s\n", file); + ret = EXIT_FAILURE; + goto out; + } + + fseek(fp, 0, SEEK_END); + filesize = ftell(fp); + rewind(fp); + + buffer = malloc(filesize); + if (!buffer) { + fprintf(stderr, "Memory allocation failed"); + ret = EXIT_FAILURE; + goto out; + } + + bytes = fread(buffer, 1, filesize, fp); + if (bytes != filesize) { + fprintf(stderr, "Error reading file\n"); + ret = EXIT_FAILURE; + goto out; + } + + fp_key = fopen(keyfile, "r"); + if (!fp_key) { + fprintf(stderr, "Error opening file: %s\n", keyfile); + ret = EXIT_FAILURE; + goto out; + } + + /* Attempt to read the private key */ + pkey = PEM_read_PrivateKey(fp_key, NULL, NULL, NULL); + if (!pkey) { + /* If private key reading fails, try reading as a public key */ + fseek(fp_key, 0, SEEK_SET); + pkey = PEM_read_PUBKEY(fp_key, NULL, NULL, NULL); + } + if (!pkey) { + fprintf(stderr, "Unable to retrieve the public key: %s\n", + ERR_error_string(ERR_get_error(), NULL)); + ret = EXIT_FAILURE; + goto out; + } + + info.algo_name = algo; + info.padding_name = padding; + info.key = (uint8_t *)pkey; + info.mandatory = 1; + info.sig_size = EVP_PKEY_size(pkey); + if (info.sig_size < 0) { + fprintf(stderr, "Fail to retrieve the signature size: %s\n", + ERR_error_string(ERR_get_error(), NULL)); + ret = EXIT_FAILURE; + goto out; + } + + /* Compute signature information */ + info.sig_info.name = info.algo_name; + info.sig_info.padding = image_get_padding_algo(info.padding_name); + info.sig_info.checksum = image_get_checksum_algo(info.sig_info.name); + info.sig_info.crypto = image_get_crypto_algo(info.sig_info.name); + info.sig_info.key = info.key; + info.sig_info.keylen = info.key_len; + + /* Check the signature */ + image_pre_load_sig_set_info(&info); + ret = image_pre_load_sig((ulong)buffer); +out: + if (fp) + fclose(fp); + if (fp_key) + fclose(fp_key); + if (info.key) + EVP_PKEY_free(pkey); + free(buffer); + + exit(ret); +} diff --git a/tools/proftool.c b/tools/proftool.c index af2cdb6d584..c7b427f3078 100644 --- a/tools/proftool.c +++ b/tools/proftool.c @@ -676,6 +676,7 @@ static int read_trace_config(FILE *fin) if (!tok) { error("Invalid trace config data on line %d\n", linenum); + free(line); return -1; } if (0 == strcmp(tok, "include-func")) { @@ -685,6 +686,7 @@ static int read_trace_config(FILE *fin) } else { error("Unknown command in trace config data line %d\n", linenum); + free(line); return -1; } @@ -692,6 +694,7 @@ static int read_trace_config(FILE *fin) if (!tok) { error("Missing pattern in trace config data line %d\n", linenum); + free(line); return -1; } diff --git a/tools/u_boot_pylib/__init__.py b/tools/u_boot_pylib/__init__.py index 63c88e85ec0..807a62e0743 100644 --- a/tools/u_boot_pylib/__init__.py +++ b/tools/u_boot_pylib/__init__.py @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -__all__ = ['command', 'cros_subprocess','terminal', 'test_util', 'tools', - 'tout'] +__all__ = ['command', 'cros_subprocess', 'gitutil', 'terminal', 'test_util', + 'tools', 'tout'] diff --git a/tools/u_boot_pylib/__main__.py b/tools/u_boot_pylib/__main__.py index 8f98d7bd9f8..c0762bca733 100755 --- a/tools/u_boot_pylib/__main__.py +++ b/tools/u_boot_pylib/__main__.py @@ -13,7 +13,6 @@ if __name__ == "__main__": sys.path.append(os.path.join(our_path, '..')) # Run tests - from u_boot_pylib import terminal from u_boot_pylib import test_util result = test_util.run_test_suites( diff --git a/tools/patman/gitutil.py b/tools/u_boot_pylib/gitutil.py index 6d6a7eedecc..6d6a7eedecc 100644 --- a/tools/patman/gitutil.py +++ b/tools/u_boot_pylib/gitutil.py diff --git a/tools/u_boot_pylib/requirements.txt b/tools/u_boot_pylib/requirements.txt new file mode 100644 index 00000000000..1087e6f2857 --- /dev/null +++ b/tools/u_boot_pylib/requirements.txt @@ -0,0 +1 @@ +concurrencytest==0.1.2 diff --git a/tools/ublimage.c b/tools/ublimage.c index 8f9b58c7983..a1bd807bfa0 100644 --- a/tools/ublimage.c +++ b/tools/ublimage.c @@ -178,6 +178,7 @@ static uint32_t parse_cfg_file(struct ubl_header *ublhdr, char *name) lineno, fld, &dcd_len); } } + free(line); fclose(fd); return dcd_len; |