diff options
1040 files changed, 18099 insertions, 3811 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index eb9353fc3dc..d6f3fa423c6 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -203,12 +203,12 @@ stages: grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then - wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi # the below corresponds to .gitlab-ci.yml "script" cd \${WORK_DIR} diff --git a/.gitignore b/.gitignore index 84051b7bfde..33014811926 100644 --- a/.gitignore +++ b/.gitignore @@ -44,8 +44,10 @@ fit-dtb.blob* /MLO* /SPL* /System.map -/u-boot* /boards.cfg +/mkimage-in-simple-bin* +/simple-bin* +/u-boot* /*.log # @@ -65,6 +67,8 @@ fit-dtb.blob* # # Generated include files # +/include/autoconf.mk* +/include/config.h /include/config/ /include/generated/ diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 1e11b5a6fea..fee165198ae 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -32,12 +32,12 @@ stages: - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then - wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi after_script: @@ -80,6 +80,8 @@ Nava kishore Manne <nava.kishore.manne@amd.com> <nava.manne@xilinx.com> Neal Frager <neal.frager@amd.com> <neal.frager@xilinx.com> Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com> Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de> +This contributor prefers not to receive mails <noreply@example.com> <pali@kernel.org> +This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@gmail.com> Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com> Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com> Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com> diff --git a/MAINTAINERS b/MAINTAINERS index cde778bc4d3..7c1cb2dc4dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -58,7 +58,7 @@ F: lib/acpi/ ANDROID AB M: Igor Opaniuk <igor.opaniuk@gmail.com> -R: Sam Protsenko <joe.skb7@gmail.com> +R: Sam Protsenko <semen.protsenko@linaro.org> S: Maintained F: cmd/ab_select.c F: common/android_ab.c @@ -567,7 +567,9 @@ S: Supported F: arch/arm/dts/am335x-sancloud* ARM SNAPDRAGON -M: Ramon Fried <rfried.dev@gmail.com> +M: Caleb Connolly <caleb.connolly@linaro.org> +M: Neil Armstrong <neil.armstrong@linaro.org> +R: Sumit Garg <sumit.garg@linaro.org> S: Maintained F: arch/arm/mach-snapdragon/ F: drivers/gpio/msm_gpio.c @@ -948,6 +950,7 @@ F: include/cyclic.h DFU M: Lukasz Majewski <lukma@denx.de> +M: Mattijs Korpershoek <mkorpershoek@baylibre.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git F: cmd/dfu.c @@ -1054,7 +1057,8 @@ F: test/common/event.c F: test/py/tests/test_event_dump.py FASTBOOT -S: Orphaned +M: Mattijs Korpershoek <mkorpershoek@baylibre.com> +S: Maintained F: cmd/fastboot.c F: doc/android/fastboot*.rst F: include/fastboot.h @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -VERSION = 2023 -PATCHLEVEL = 10 +VERSION = 2024 +PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc2 NAME = # *DOCUMENTATION* @@ -2156,15 +2156,15 @@ CLEAN_DIRS += $(MODVERDIR) \ $(foreach d, spl tpl vpl, $(patsubst %,$d/%, \ $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) -CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ - include/generated/env.* drivers/video/u_boot_logo.S \ +CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \ + include/config.h include/generated/env.* drivers/video/u_boot_logo.S \ tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \ u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \ lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \ idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \ mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \ itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \ - mkimage.rom.mkimage rom.map simple-bin.map simple-bin-spi.map \ + mkimage.rom.mkimage mkimage-in-simple-bin* rom.map simple-bin* \ idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb # Directories & files removed with 'make mrproper' diff --git a/arch/Kconfig b/arch/Kconfig index 19f2891ba1c..4f5b75129f3 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -208,6 +208,8 @@ config SANDBOX imply PHYSMEM imply GENERATE_ACPI_TABLE imply BINMAN + imply CMD_MBR + imply CMD_MMC config SH bool "SuperH architecture" diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 2dd003445f8..44ec5864a1c 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. */ -#include <common.h> #include <bootstage.h> #include <env.h> #include <image.h> diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index d97a5787424..22e748868a7 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -4,7 +4,6 @@ */ #include <config.h> -#include <common.h> #include <cpu_func.h> #include <asm/global_data.h> #include <linux/bitops.h> diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 15678579618..803dfd42558 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2014, 2018 Synopsys, Inc. All rights reserved. */ -#include <common.h> #include <clock_legacy.h> #include <init.h> #include <malloc.h> diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c index 023eae19075..858b388cc0b 100644 --- a/arch/arc/lib/init_helpers.c +++ b/arch/arc/lib/init_helpers.c @@ -5,7 +5,6 @@ #include <init.h> #include <asm/cache.h> -#include <common.h> int init_cache_f_r(void) { diff --git a/arch/arc/lib/interrupts.c b/arch/arc/lib/interrupts.c index db21fbb1142..523b44cb95a 100644 --- a/arch/arc/lib/interrupts.c +++ b/arch/arc/lib/interrupts.c @@ -3,8 +3,8 @@ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. */ -#include <common.h> #include <irq_func.h> +#include <vsprintf.h> #include <asm/arcregs.h> #include <asm/ptrace.h> diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c index fd6f4fbc930..95b6d5150c7 100644 --- a/arch/arc/lib/relocate.c +++ b/arch/arc/lib/relocate.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. */ -#include <common.h> #include <elf.h> #include <log.h> #include <asm/sections.h> diff --git a/arch/arc/lib/reset.c b/arch/arc/lib/reset.c index b8589d0f0a4..fa60fa96338 100644 --- a/arch/arc/lib/reset.c +++ b/arch/arc/lib/reset.c @@ -4,7 +4,6 @@ */ #include <command.h> -#include <common.h> #include <cpu_func.h> __weak void reset_cpu(void) diff --git a/arch/arm/cpu/armv7/mpu_v7r.c b/arch/arm/cpu/armv7/mpu_v7r.c index 57ab640e263..1d31c63e5fd 100644 --- a/arch/arm/cpu/armv7/mpu_v7r.c +++ b/arch/arm/cpu/armv7/mpu_v7r.c @@ -2,7 +2,7 @@ /* * Cortex-R Memory Protection Unit specific code * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 96066a2b6b8..3200a5f01eb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -191,6 +191,10 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6b-io.dtb \ rk3588-evb1-v10.dtb \ + rk3588-nanopc-t6.dtb \ + rk3588s-orangepi-5.dtb \ + rk3588-orangepi-5-plus.dtb \ + rk3588-quartzpro64.dtb \ rk3588s-rock-5a.dtb \ rk3588-rock-5b.dtb @@ -319,6 +323,7 @@ else dtb-$(CONFIG_ARCH_MVEBU) += \ armada-3720-db.dtb \ armada-3720-espressobin.dtb \ + armada-3720-ripe-atlas.dtb \ armada-3720-turris-mox.dtb \ armada-3720-eDPU.dtb \ armada-3720-uDPU.dtb \ @@ -372,6 +377,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cse-nand.dtb \ zynq-cse-nor.dtb \ zynq-cse-qspi-single.dtb \ + zynq-cse-qspi-parallel.dtb \ + zynq-cse-qspi-stacked.dtb \ + zynq-cse-qspi-x1-single.dtb \ + zynq-cse-qspi-x1-stacked.dtb \ + zynq-cse-qspi-x2-single.dtb \ + zynq-cse-qspi-x2-stacked.dtb \ zynq-dlc20-rev1.0.dtb \ zynq-microzed.dtb \ zynq-minized.dtb \ @@ -413,6 +424,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-emmc1.dtb \ zynqmp-mini-nand.dtb \ zynqmp-mini-qspi.dtb \ + zynqmp-mini-qspi-parallel.dtb \ + zynqmp-mini-qspi-single.dtb \ + zynqmp-mini-qspi-stacked.dtb \ + zynqmp-mini-qspi-x1-single.dtb \ + zynqmp-mini-qspi-x1-stacked.dtb \ + zynqmp-mini-qspi-x2-single.dtb \ + zynqmp-mini-qspi-x2-stacked.dtb \ zynqmp-sc-revB.dtb \ zynqmp-sc-revC.dtb \ zynqmp-sc-vek280-revA.dtbo \ @@ -463,13 +481,27 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini-emmc0.dtb \ versal-mini-emmc1.dtb \ versal-mini-ospi-single.dtb \ + versal-mini-ospi-stacked.dtb \ + versal-mini-qspi-parallel.dtb \ versal-mini-qspi-single.dtb \ + versal-mini-qspi-stacked.dtb \ + versal-mini-qspi-x1-single.dtb \ + versal-mini-qspi-x1-stacked.dtb \ + versal-mini-qspi-x2-single.dtb \ + versal-mini-qspi-x2-stacked.dtb \ xilinx-versal-virt.dtb dtb-$(CONFIG_ARCH_VERSAL_NET) += \ versal-net-mini.dtb \ versal-net-mini-emmc.dtb \ versal-net-mini-ospi-single.dtb \ + versal-net-mini-ospi-stacked.dtb \ versal-net-mini-qspi-single.dtb \ + versal-net-mini-qspi-parallel.dtb \ + versal-net-mini-qspi-stacked.dtb \ + versal-net-mini-qspi-x1-single.dtb \ + versal-net-mini-qspi-x1-stacked.dtb \ + versal-net-mini-qspi-x2-single.dtb \ + versal-net-mini-qspi-x2-stacked.dtb \ xilinx-versal-net-virt.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb diff --git a/arch/arm/dts/am335x-baltos.dts b/arch/arm/dts/am335x-baltos.dts index b3c13c9a9d1..34b87d47a79 100644 --- a/arch/arm/dts/am335x-baltos.dts +++ b/arch/arm/dts/am335x-baltos.dts @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi b/arch/arm/dts/am335x-evm-u-boot.dtsi index 82a483ae3e2..72402c82928 100644 --- a/arch/arm/dts/am335x-evm-u-boot.dtsi +++ b/arch/arm/dts/am335x-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am33xx-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts index 5d962252b7d..e0267657f90 100644 --- a/arch/arm/dts/am335x-evmsk.dts +++ b/arch/arm/dts/am335x-evmsk.dts @@ -5,7 +5,7 @@ /* * AM335x Starter Kit - * http://www.ti.com/tool/tmdssk3358 + * https://www.ti.com/tool/tmdssk3358 */ /dts-v1/; diff --git a/arch/arm/dts/am335x-icev2-u-boot.dtsi b/arch/arm/dts/am335x-icev2-u-boot.dtsi index 67bfac916ee..ac1feaa9d9f 100644 --- a/arch/arm/dts/am335x-icev2-u-boot.dtsi +++ b/arch/arm/dts/am335x-icev2-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am33xx-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts index a54272421cc..bcfdbb772c1 100644 --- a/arch/arm/dts/am335x-icev2.dts +++ b/arch/arm/dts/am335x-icev2.dts @@ -5,7 +5,7 @@ /* * AM335x ICE V2 board - * http://www.ti.com/tool/tmdsice3359 + * https://www.ti.com/tool/tmdsice3359 */ /dts-v1/; diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi index a51d6aceb96..a49560924b3 100644 --- a/arch/arm/dts/am335x-pxm2.dtsi +++ b/arch/arm/dts/am335x-pxm2.dtsi @@ -3,7 +3,7 @@ * Heiko Schocher <hs@denx.de> * * Based on: - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/dts/am335x-pxm50.dts b/arch/arm/dts/am335x-pxm50.dts index f4e66d29d59..69ed32c44cc 100644 --- a/arch/arm/dts/am335x-pxm50.dts +++ b/arch/arm/dts/am335x-pxm50.dts @@ -2,7 +2,7 @@ * Copyright (C) 2014 DENX Software Engineering GmbH * Heiko Schocher <hs@denx.de> * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts index 7760b9709a8..0dcd561d990 100644 --- a/arch/arm/dts/am335x-rut.dts +++ b/arch/arm/dts/am335x-rut.dts @@ -3,7 +3,7 @@ * Heiko Schocher <hs@denx.de> * * Based on: - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts index a2676d10c24..271d1ab356c 100644 --- a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts +++ b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2021 Sancloud Ltd - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi b/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi index fd47bc23a2e..db0288820d9 100644 --- a/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi +++ b/arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2021 SanCloud Ltd */ diff --git a/arch/arm/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/dts/am335x-sancloud-bbe-lite.dts index 8ffbc72dc57..daa90f64a8a 100644 --- a/arch/arm/dts/am335x-sancloud-bbe-lite.dts +++ b/arch/arm/dts/am335x-sancloud-bbe-lite.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Copyright (C) 2021 SanCloud Ltd */ /dts-v1/; diff --git a/arch/arm/dts/am4372-generic-u-boot.dtsi b/arch/arm/dts/am4372-generic-u-boot.dtsi index 1dd0a5dac1e..40f3756eb3f 100644 --- a/arch/arm/dts/am4372-generic-u-boot.dtsi +++ b/arch/arm/dts/am4372-generic-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am4372-u-boot.dtsi" diff --git a/arch/arm/dts/am4372-generic.dts b/arch/arm/dts/am4372-generic.dts index b8a2bb82ef5..2524e0405cd 100644 --- a/arch/arm/dts/am4372-generic.dts +++ b/arch/arm/dts/am4372-generic.dts @@ -2,7 +2,7 @@ /* * Device Tree Source for Generic AM4372 EVM * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/am4372-u-boot.dtsi b/arch/arm/dts/am4372-u-boot.dtsi index 2fac2fcdf9b..0c498bcf085 100644 --- a/arch/arm/dts/am4372-u-boot.dtsi +++ b/arch/arm/dts/am4372-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ /{ diff --git a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi index da0b1365ffe..6393170ad22 100644 --- a/arch/arm/dts/am437x-gp-evm-u-boot.dtsi +++ b/arch/arm/dts/am437x-gp-evm-u-boot.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi index 4e6ad9445b3..7c9f80e7ba2 100644 --- a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi +++ b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am4372-u-boot.dtsi" diff --git a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi index 43e519c4e58..580ba3512bd 100644 --- a/arch/arm/dts/am437x-sk-evm-u-boot.dtsi +++ b/arch/arm/dts/am437x-sk-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am4372-u-boot.dtsi" diff --git a/arch/arm/dts/am571x-idk-u-boot.dtsi b/arch/arm/dts/am571x-idk-u-boot.dtsi index 65199200ed5..98a7a7eeb39 100644 --- a/arch/arm/dts/am571x-idk-u-boot.dtsi +++ b/arch/arm/dts/am571x-idk-u-boot.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-idk-common-u-boot.dtsi" diff --git a/arch/arm/dts/am5729-beagleboneai.dts b/arch/arm/dts/am5729-beagleboneai.dts index f772aefb8f3..75a29e65e10 100644 --- a/arch/arm/dts/am5729-beagleboneai.dts +++ b/arch/arm/dts/am5729-beagleboneai.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/am572x-idk-u-boot.dtsi b/arch/arm/dts/am572x-idk-u-boot.dtsi index 65199200ed5..98a7a7eeb39 100644 --- a/arch/arm/dts/am572x-idk-u-boot.dtsi +++ b/arch/arm/dts/am572x-idk-u-boot.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-idk-common-u-boot.dtsi" diff --git a/arch/arm/dts/am574x-idk-u-boot.dtsi b/arch/arm/dts/am574x-idk-u-boot.dtsi index 65199200ed5..98a7a7eeb39 100644 --- a/arch/arm/dts/am574x-idk-u-boot.dtsi +++ b/arch/arm/dts/am574x-idk-u-boot.dtsi @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "am57xx-idk-common-u-boot.dtsi" diff --git a/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi b/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi index 49b16215e52..2af4e60cda8 100644 --- a/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi +++ b/arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi b/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi index 49b16215e52..2af4e60cda8 100644 --- a/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi +++ b/arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi b/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi index 49b16215e52..2af4e60cda8 100644 --- a/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi +++ b/arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi b/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi index 49b16215e52..2af4e60cda8 100644 --- a/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi +++ b/arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi index b07aea0048d..31faec4afe6 100644 --- a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi +++ b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi b/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi index 49b16215e52..2af4e60cda8 100644 --- a/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi +++ b/arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/armada-3720-ripe-atlas.dts b/arch/arm/dts/armada-3720-ripe-atlas.dts new file mode 100644 index 00000000000..4457845266f --- /dev/null +++ b/arch/arm/dts/armada-3720-ripe-atlas.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Device Tree file for CZ.NIC' RIPE Atlas Probe + * 2021 by Marek Behún <marek.behun@nic.cz> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "armada-372x.dtsi" + +/ { + model = "CZ.NIC's RIPE Atlas Probe"; + compatible = "cznic,ripe-atlas", "marvell,armada3720", + "marvell,armada3710"; + + aliases { + ethernet0 = ð0; + mmc0 = &sdhci0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + led { + gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_ACTIVITY; + }; + }; + + vsdc_reg: vsdc-reg { + compatible = "regulator-gpio"; + regulator-name = "vsdc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1 + 3300000 0x0>; + enable-active-high; + }; +}; + +&comphy { + status = "disabled"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&smi_pins>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + status = "okay"; +}; + +&sdhci0 { + bus-width = <8>; + non-removable; + vqmmc-supply = <&vsdc_reg>; + marvell,pad-type = "sd"; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/bitmain-antminer-s9.dts b/arch/arm/dts/bitmain-antminer-s9.dts index 0228b4b30e5..f5ad95a276b 100644 --- a/arch/arm/dts/bitmain-antminer-s9.dts +++ b/arch/arm/dts/bitmain-antminer-s9.dts @@ -52,6 +52,8 @@ &nfc0 { status = "okay"; + #address-cells = <1>; + #size-cells = <0>; nand@0 { reg = <0>; }; diff --git a/arch/arm/dts/da850-lcdk-u-boot.dtsi b/arch/arm/dts/da850-lcdk-u-boot.dtsi index bbaebcb67a0..9ab48bca088 100644 --- a/arch/arm/dts/da850-lcdk-u-boot.dtsi +++ b/arch/arm/dts/da850-lcdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * da850-lcdk U-Boot Additions * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ / { diff --git a/arch/arm/dts/dra7-evm-u-boot.dtsi b/arch/arm/dts/dra7-evm-u-boot.dtsi index 87b2451a8e8..3fe1fb4552d 100644 --- a/arch/arm/dts/dra7-evm-u-boot.dtsi +++ b/arch/arm/dts/dra7-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/dra7-ipu-common-early-boot.dtsi b/arch/arm/dts/dra7-ipu-common-early-boot.dtsi index 90fc4cb36d5..afa4595195b 100644 --- a/arch/arm/dts/dra7-ipu-common-early-boot.dtsi +++ b/arch/arm/dts/dra7-ipu-common-early-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ / { diff --git a/arch/arm/dts/dra71-evm-u-boot.dtsi b/arch/arm/dts/dra71-evm-u-boot.dtsi index 8e7dc719bf8..339b05f54a0 100644 --- a/arch/arm/dts/dra71-evm-u-boot.dtsi +++ b/arch/arm/dts/dra71-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi index 8e7dc719bf8..339b05f54a0 100644 --- a/arch/arm/dts/dra72-evm-revc-u-boot.dtsi +++ b/arch/arm/dts/dra72-evm-revc-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/dra72-evm-u-boot.dtsi b/arch/arm/dts/dra72-evm-u-boot.dtsi index 91a3b6b742a..dfdd5c57ad1 100644 --- a/arch/arm/dts/dra72-evm-u-boot.dtsi +++ b/arch/arm/dts/dra72-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/dra76-evm-u-boot.dtsi b/arch/arm/dts/dra76-evm-u-boot.dtsi index 1216d93bdcd..c8da3e48389 100644 --- a/arch/arm/dts/dra76-evm-u-boot.dtsi +++ b/arch/arm/dts/dra76-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include "omap5-u-boot.dtsi" diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts index 5d9a00c9429..0e5d329b149 100644 --- a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts +++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts @@ -24,6 +24,14 @@ pagesize = <16>; }; +&eeprom0wl { + status = "disabled"; +}; + +&eeprom1wl { + status = "disabled"; +}; + ðphy0f { /* SMSC LAN8740Ai */ pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>; reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi index ea2a567447a..b504d36818b 100644 --- a/arch/arm/dts/imx8mp-dhcom-som.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -392,6 +392,18 @@ reg = <0x53>; }; + eeprom0wl: eeprom@58 { + compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x50 */ + pagesize = <32>; + reg = <0x58>; + }; + + eeprom1wl: eeprom@5b { + compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x53 */ + pagesize = <32>; + reg = <0x5b>; + }; + ioexp: gpio@74 { compatible = "nxp,pca9539"; reg = <0x74>; diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi index 93b4d91e4c3..a9dffa5a71e 100644 --- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -8,6 +8,7 @@ compatible = "wdt-reboot"; wdt = <&wdog3>; bootph-pre-ram; + bootph-some-ram; }; firmware { @@ -30,19 +31,23 @@ &aips2 { bootph-pre-ram; + bootph-some-ram; }; &aips3 { bootph-pre-ram; + bootph-some-ram; }; &iomuxc { bootph-pre-ram; + bootph-some-ram; }; ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; bootph-pre-ram; + bootph-some-ram; }; &pinctrl_reg_usdhc2_vmmc { @@ -51,59 +56,73 @@ &pinctrl_uart1 { bootph-pre-ram; + bootph-some-ram; }; &pinctrl_usdhc2_gpio { bootph-pre-ram; + bootph-some-ram; }; &pinctrl_usdhc2 { bootph-pre-ram; + bootph-some-ram; }; &gpio1 { bootph-pre-ram; + bootph-some-ram; }; &gpio2 { bootph-pre-ram; + bootph-some-ram; }; &gpio3 { bootph-pre-ram; + bootph-some-ram; }; &gpio4 { bootph-pre-ram; + bootph-some-ram; }; &lpuart1 { bootph-pre-ram; + bootph-some-ram; }; &usdhc1 { bootph-pre-ram; + bootph-some-ram; }; &usdhc2 { bootph-pre-ram; + bootph-some-ram; fsl,signal-voltage-switch-extra-delay-ms = <8>; }; &lpi2c2 { bootph-pre-ram; + bootph-some-ram; }; &{/soc@0/bus@44000000/i2c@44350000/pmic@25} { bootph-pre-ram; + bootph-some-ram; }; &{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { bootph-pre-ram; + bootph-some-ram; }; &pinctrl_lpi2c2 { bootph-pre-ram; + bootph-some-ram; }; &fec { @@ -124,6 +143,7 @@ &s4muap { bootph-pre-ram; + bootph-some-ram; status = "okay"; }; diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi index 5638321903a..cfea21b3c9d 100644 --- a/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm - * http://www.ti.com/lit/pdf/spracj0 + * https://www.ti.com/lit/pdf/spracj0 * Configuration Parameters * Memory Type: DDR4 * Data Rate: 1600 MT/s diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index e4cbc47c2a7..11d83927ac5 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-am654-r5-base-board-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi index 48698cdddc7..9f0586ed1a4 100644 --- a/arch/arm/dts/k3-am654-ddr.dtsi +++ b/arch/arm/dts/k3-am654-ddr.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ / { diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi index 949320c91d0..286604576e0 100644 --- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/pinctrl/k3.h> diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 7671875a55c..637a5cc85e0 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi index 9ec8dff44be..f0683088cf6 100644 --- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi +++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0 * This file was generated on 06/01/2021 */ diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index cd95907b981..b77f8d92de3 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-j721e-binman.dtsi" diff --git a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi index 5a6f9b11b8e..66e15811519 100644 --- a/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1 * This file was generated on 07/17/2022 */ diff --git a/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi index 6c7328e8db0..18f1944474b 100644 --- a/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721e-ddr-sk-lp4-4266.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.1 * This file was generated on 07/19/2021 */ diff --git a/arch/arm/dts/k3-j721e-ddr.dtsi b/arch/arm/dts/k3-j721e-ddr.dtsi index 3a9ea42fe54..7d2ccd9547c 100644 --- a/arch/arm/dts/k3-j721e-ddr.dtsi +++ b/arch/arm/dts/k3-j721e-ddr.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ / { diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index fcd9c716a50..9655ca21d02 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi index 457515b0736..33742d81971 100644 --- a/arch/arm/dts/keystone-clocks.dtsi +++ b/arch/arm/dts/keystone-clocks.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 clock tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/arch/arm/dts/keystone-k2e-clocks.dtsi b/arch/arm/dts/keystone-k2e-clocks.dtsi index f7592155a74..46f8ab3a11d 100644 --- a/arch/arm/dts/keystone-k2e-clocks.dtsi +++ b/arch/arm/dts/keystone-k2e-clocks.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Edison SoC specific device tree * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi index 970d452f080..953c7502260 100644 --- a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /{ diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts index ed76e56369f..bf884442617 100644 --- a/arch/arm/dts/keystone-k2e-evm.dts +++ b/arch/arm/dts/keystone-k2e-evm.dts @@ -2,7 +2,7 @@ /* * Keystone 2 Edison EVM device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/keystone-k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi index 45ebb0ac4f5..dd61503db39 100644 --- a/arch/arm/dts/keystone-k2e-netcp.dtsi +++ b/arch/arm/dts/keystone-k2e-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 Edison Netcp driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/arch/arm/dts/keystone-k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi index 496bb310c7d..449cddcb814 100644 --- a/arch/arm/dts/keystone-k2e.dtsi +++ b/arch/arm/dts/keystone-k2e.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Edison soc device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ / { diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi index 05653afc7e9..72b67b232dd 100644 --- a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /{ diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts index 6376c62b6d0..491fdc4b046 100644 --- a/arch/arm/dts/keystone-k2g-evm.dts +++ b/arch/arm/dts/keystone-k2g-evm.dts @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G EVM * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi index 8e4b36c2de3..3634ed7268c 100644 --- a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /{ diff --git a/arch/arm/dts/keystone-k2g-generic.dts b/arch/arm/dts/keystone-k2g-generic.dts index fc938a4baa8..dc6c31a31b4 100644 --- a/arch/arm/dts/keystone-k2g-generic.dts +++ b/arch/arm/dts/keystone-k2g-generic.dts @@ -2,7 +2,7 @@ /* * Device Tree Source for Generic 66AK2G0X EVM * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi index 8e4b36c2de3..3634ed7268c 100644 --- a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /{ diff --git a/arch/arm/dts/keystone-k2g-ice.dts b/arch/arm/dts/keystone-k2g-ice.dts index cbdb6bfca8c..b898ae668a9 100644 --- a/arch/arm/dts/keystone-k2g-ice.dts +++ b/arch/arm/dts/keystone-k2g-ice.dts @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G Industrial Communication Engine EVM * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi b/arch/arm/dts/keystone-k2g-netcp.dtsi index 136cd20b76e..2afb48823c1 100644 --- a/arch/arm/dts/keystone-k2g-netcp.dtsi +++ b/arch/arm/dts/keystone-k2g-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G Netcp driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@4020000 { diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi index f12af433bb1..5c3ff127218 100644 --- a/arch/arm/dts/keystone-k2g.dtsi +++ b/arch/arm/dts/keystone-k2g.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for K2G SOC * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm/dts/keystone-k2hk-clocks.dtsi b/arch/arm/dts/keystone-k2hk-clocks.dtsi index 4ba6912176e..3ca4722087c 100644 --- a/arch/arm/dts/keystone-k2hk-clocks.dtsi +++ b/arch/arm/dts/keystone-k2hk-clocks.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Kepler/Hawking SoC clock nodes * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi index 22df84ba93b..3e38f228a6a 100644 --- a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ */ /{ diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts index ea53f3f6b86..6222876f277 100644 --- a/arch/arm/dts/keystone-k2hk-evm.dts +++ b/arch/arm/dts/keystone-k2hk-evm.dts @@ -2,7 +2,7 @@ /* * Keystone 2 Kepler/Hawking EVM device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/keystone-k2hk-netcp.dtsi b/arch/arm/dts/keystone-k2hk-netcp.dtsi index 580af633df1..3f8c4c263a2 100644 --- a/arch/arm/dts/keystone-k2hk-netcp.dtsi +++ b/arch/arm/dts/keystone-k2hk-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 Hawking Netcp driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/arch/arm/dts/keystone-k2hk.dtsi b/arch/arm/dts/keystone-k2hk.dtsi index ef02f23c320..e5ab1fbb559 100644 --- a/arch/arm/dts/keystone-k2hk.dtsi +++ b/arch/arm/dts/keystone-k2hk.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Kepler/Hawking soc specific device tree * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ / { diff --git a/arch/arm/dts/keystone-k2l-clocks.dtsi b/arch/arm/dts/keystone-k2l-clocks.dtsi index 635528064de..fcfc2fb6cc2 100644 --- a/arch/arm/dts/keystone-k2l-clocks.dtsi +++ b/arch/arm/dts/keystone-k2l-clocks.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 lamarr SoC clock nodes * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ clocks { diff --git a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi index 0a507d0210b..f1aed14b0b5 100644 --- a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ &usb_phy { diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts index 187f2caa6d3..9d2b4542e81 100644 --- a/arch/arm/dts/keystone-k2l-evm.dts +++ b/arch/arm/dts/keystone-k2l-evm.dts @@ -2,7 +2,7 @@ /* * Keystone 2 Lamarr EVM device tree * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; diff --git a/arch/arm/dts/keystone-k2l-netcp.dtsi b/arch/arm/dts/keystone-k2l-netcp.dtsi index 54c11288191..2caa0583fc8 100644 --- a/arch/arm/dts/keystone-k2l-netcp.dtsi +++ b/arch/arm/dts/keystone-k2l-netcp.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for Keystone 2 Lamarr Netcp driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ */ qmss: qmss@2a40000 { diff --git a/arch/arm/dts/keystone-k2l.dtsi b/arch/arm/dts/keystone-k2l.dtsi index dcc83a7ee44..c8893e284f2 100644 --- a/arch/arm/dts/keystone-k2l.dtsi +++ b/arch/arm/dts/keystone-k2l.dtsi @@ -2,7 +2,7 @@ /* * Keystone 2 Lamarr SoC specific device tree * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ */ / { diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi index 2afcab76d22..1538ccef81a 100644 --- a/arch/arm/dts/keystone.dtsi +++ b/arch/arm/dts/keystone.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ */ #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm/dts/omap3-u-boot.dtsi b/arch/arm/dts/omap3-u-boot.dtsi index 7366ff56932..bc2793757b7 100644 --- a/arch/arm/dts/omap3-u-boot.dtsi +++ b/arch/arm/dts/omap3-u-boot.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi index 720e79b3a55..d1de2e7c85f 100644 --- a/arch/arm/dts/omap5-u-boot.dtsi +++ b/arch/arm/dts/omap5-u-boot.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts index f69a38f42d2..0a27fa5271f 100644 --- a/arch/arm/dts/rk3328-rock64.dts +++ b/arch/arm/dts/rk3328-rock64.dts @@ -37,7 +37,8 @@ vin-supply = <&vcc_io>; }; - vcc_host_5v: vcc-host-5v-regulator { + /* Common enable line for all of the rails mentioned in the labels */ + vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator { compatible = "regulator-fixed"; gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -48,17 +49,6 @@ vin-supply = <&vcc_sys>; }; - vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&usb20_host_drv>; - regulator-name = "vcc_host1_5v"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - vcc_sys: vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi index 572bdc5665b..1136f0bb3b8 100644 --- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -8,9 +8,16 @@ }; }; -/* PCIe PHY driver in U-Boot does not support bifurcation */ &pcie3x1 { - status = "disabled"; + pinctrl-0 = <&pcie30x1_reset_h>; +}; + +&pinctrl { + pcie { + pcie30x1_reset_h: pcie30x1-reset-h { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &sdhci { diff --git a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi index bd2e2594863..e8566785e96 100644 --- a/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi +++ b/arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi @@ -6,16 +6,7 @@ #include "rk3588-u-boot.dtsi" / { - aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; - }; - chosen { - u-boot,spl-boot-order = &sdhci; + u-boot,spl-boot-order = "same-as-spl", &sdhci; }; }; - -&sdhci { - bootph-all; -}; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts index 229a9111f5e..b9d789d5786 100644 --- a/arch/arm/dts/rk3588-evb1-v10.dts +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -7,6 +7,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/rockchip.h> #include "rk3588.dtsi" @@ -23,12 +24,84 @@ stdout-path = "serial2:1500000n8"; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "Escape"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1235000>; + }; + }; + backlight: backlight { compatible = "pwm-backlight"; power-supply = <&vcc12v_dcin>; pwms = <&pwm2 0 25000 0>; }; + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&avdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -38,6 +111,19 @@ regulator-max-microvolt = <12000000>; }; + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + }; + vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_host"; @@ -87,6 +173,10 @@ status = "okay"; }; +&combphy2_psu { + status = "okay"; +}; + &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; }; @@ -163,7 +253,32 @@ }; }; +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + &pinctrl { + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + rtl8211f { rtl8211f_rst: rtl8211f-rst { rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; @@ -177,6 +292,22 @@ }; }; + pcie2 { + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_pcie30_en: vcc3v3-pcie30-en { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -188,6 +319,11 @@ status = "okay"; }; +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; diff --git a/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi new file mode 100644 index 00000000000..87831c9d432 --- /dev/null +++ b/arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 John Clark <inindev@gmail.com> + * + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; +}; + +&fspim1_pins { + bootph-all; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + pinctrl-names = "default"; + pinctrl-0 = <&fspim1_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/rk3588-nanopc-t6.dts b/arch/arm/dts/rk3588-nanopc-t6.dts new file mode 100644 index 00000000000..97af4f91282 --- /dev/null +++ b/arch/arm/dts/rk3588-nanopc-t6.dts @@ -0,0 +1,916 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Thomas McKahan + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "FriendlyElec NanoPC-T6"; + compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "system-led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + usr_led: led-1 { + gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + label = "user-led"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pin>; + }; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-pin-name = "Headphones"; + + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* vcc5v0_sys powers peripherals */ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* vcc4v0_sys powers the RK806, RK860's */ + vcc4v0_sys: vcc4v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-1v1-nldo-s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc4v0_sys>; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_1_pwren>; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_0_pwren>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&gpio0 { + gpio-line-names = /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "HEADER_10", "HEADER_08", "HEADER_32", "", + /* GPIO0 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = /* GPIO1 A0-A7 */ + "HEADER_27", "HEADER_28", "", "", + "", "", "", "HEADER_15", + /* GPIO1 B0-B7 */ + "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", + "HEADER_24", "HEADER_22", "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "HEADER_05", "HEADER_03"; +}; + +&gpio2 { + gpio-line-names = /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 C0-C7 */ + "", "CSI1_11", "CSI1_12", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = /* GPIO3 A0-A7 */ + "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", + "HEADER_37", "", "DSI0_12", "", + /* GPIO3 B0-B7 */ + "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", + "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", + /* GPIO3 C0-C7 */ + "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", + "", "", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "DSI1_10", "", ""; +}; + +&gpio4 { + gpio-line-names = /* GPIO4 A0-A7 */ + "DSI1_08", "DSI1_14", "", "DSI1_12", + "", "", "", "", + /* GPIO4 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "CSI0_11", "CSI0_12", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + rockchip,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&usbc0_int>; + pinctrl-names = "default"; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <1000000>; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + + port { + rt5616_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; + + /* connected with MIPI-CSI1 */ +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&rt5616_p0_0>; + }; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usr_led_pin: usr-led-pin { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_m2_0_pwren: pcie-m20-pwren { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_m2_1_pwren: pcie-m21-pwren { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc4v0_sys>; + vcc2-supply = <&vcc4v0_sys>; + vcc3-supply = <&vcc4v0_sys>; + vcc4-supply = <&vcc4v0_sys>; + vcc5-supply = <&vcc4v0_sys>; + vcc6-supply = <&vcc4v0_sys>; + vcc7-supply = <&vcc4v0_sys>; + vcc8-supply = <&vcc4v0_sys>; + vcc9-supply = <&vcc4v0_sys>; + vcc10-supply = <&vcc4v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc4v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc4v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi new file mode 100644 index 00000000000..b0f5c667197 --- /dev/null +++ b/arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; +}; + +&fspim1_pins { + bootph-all; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; diff --git a/arch/arm/dts/rk3588-orangepi-5-plus.dts b/arch/arm/dts/rk3588-orangepi-5-plus.dts new file mode 100644 index 00000000000..298c183d6f4 --- /dev/null +++ b/arch/arm/dts/rk3588-orangepi-5-plus.dts @@ -0,0 +1,848 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Ondřej Jirman <megi@xff.cz> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "Xunlong Orange Pi 5 Plus"; + compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Mask Rom"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <2000>; + }; + }; + + adc-keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <2000>; + }; + }; + + speaker_amp: speaker-audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Speaker Amp"; + }; + + headphone_amp: headphones-audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Headphones Amp"; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_receiver_pin>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&blue_led_pin>; + + led { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 70 75 80 100>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm3 0 50000 0>; + #cooling-cells = <2>; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + max-brightness = <255>; + pwms = <&pwm2 0 25000 0>; + }; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + simple-audio-card,name = "Analog"; + simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + simple-audio-card,bitclock-master = <&daicpu>; + simple-audio-card,frame-master = <&daicpu>; + /*TODO: SARADC_IN3 is used as MIC detection / key input */ + + simple-audio-card,widgets = + "Microphone", "Onboard Microphone", + "Microphone", "Microphone Jack", + "Speaker", "Speaker", + "Headphone", "Headphones"; + + simple-audio-card,routing = + "Headphones", "LOUT1", + "Headphones", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + + "Headphones", "Headphones Amp OUTL", + "Headphones", "Headphones Amp OUTR", + "Headphones Amp INL", "LOUT1", + "Headphones Amp INR", "ROUT1", + + "Speaker", "Speaker Amp OUTL", + "Speaker", "Speaker Amp OUTR", + "Speaker Amp INL", "LOUT2", + "Speaker Amp INR", "ROUT2", + + /* single ended signal to LINPUT1 */ + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + /* differential signal */ + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + + daicpu: simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + system-clock-frequency = <12288000>; + }; + + daicodec: simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator { + compatible = "regulator-fixed"; + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + regulator-name = "vcc3v3_pcie_eth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_wf: vcc3v3-wf-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_wf"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb20: vcc5v0-usb20-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb20_en>; + regulator-name = "vcc5v0_usb20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + + /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ + es8388: audio-codec@11 { + compatible = "everest,es8388"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + AVDD-supply = <&vcc_1v8_s0>; + DVDD-supply = <&vcc_1v8_s0>; + HPVDD-supply = <&vcc_3v3_s0>; + PVDD-supply = <&vcc_3v3_s0>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&i2s2_2ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m0_lrck + &i2s2m0_sclk + &i2s2m0_sdi + &i2s2m0_sdo>; + status = "okay"; +}; + +/* phy1 - M.KEY socket */ +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_wf>; + status = "okay"; +}; + +/* phy2 - right ethernet port */ +&pcie2x1l1 { + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_eth>; + status = "okay"; +}; + +/* phy0 - left ethernet port */ +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_eth>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + blue_led_pin: blue-led { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb20_en: vcc5v0-usb20-en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm3 { + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim1_pins>; + status = "okay"; + + spi_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vdd2_ddr_s3>; + vcc14-supply = <&vdd2_ddr_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <825000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <825000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* shorted to avcc_1v8_s0 on the board */ + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + /* + * The schematic mentions that actual setting + * should be 0.8375V. RK3588 datasheet specifies + * maximum as 0.825V. So we set datasheet max + * here. + */ + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <825000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&uart9 { + pinctrl-0 = <&uart9m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi new file mode 100644 index 00000000000..191ec988c45 --- /dev/null +++ b/arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Google, Inc + */ + +#include "rk3588-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + }; +}; diff --git a/arch/arm/dts/rk3588-quartzpro64.dts b/arch/arm/dts/rk3588-quartzpro64.dts new file mode 100644 index 00000000000..5c59f9571dc --- /dev/null +++ b/arch/arm/dts/rk3588-quartzpro64.dts @@ -0,0 +1,1137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Ondřej Jirman <megi@xff.cz> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "PINE64 QuartzPro64"; + compatible = "pine64,quartzpro64", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Mask Rom"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <393>; + }; + }; + + adc-keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-volume-up { + label = "V+/REC"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17821>; + }; + + button-volume-down { + label = "V-"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <415384>; + }; + + button-menu { + label = "MENU"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890909>; + }; + + button-esc { + label = "ESC"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1233962>; + }; + }; + + headphone_amp: audio-amplifier-headphone { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Headphones Amp"; + }; + + speaker_amp: audio-amplifier-speaker { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Speaker Amp"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-1 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + simple-audio-card,name = "Analog"; + simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + simple-audio-card,bitclock-master = <&daicpu>; + simple-audio-card,frame-master = <&daicpu>; + /* SARADC_IN3 is used as MIC detection / key input */ + + simple-audio-card,widgets = + "Microphone", "Onboard Microphone", + "Microphone", "Microphone Jack", + "Speaker", "Speaker", + "Headphone", "Headphones"; + + simple-audio-card,routing = + "Headphones", "LOUT1", + "Headphones", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + + "Headphones", "Headphones Amp OUTL", + "Headphones", "Headphones Amp OUTR", + "Headphones Amp INL", "LOUT1", + "Headphones Amp INR", "ROUT1", + + "Speaker", "Speaker Amp OUTL", + "Speaker", "Speaker Amp OUTR", + "Speaker Amp INL", "LOUT2", + "Speaker Amp INR", "ROUT2", + + /* single ended signal to LINPUT1 */ + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + /* differential signal */ + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + + daicpu: simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + system-clock-frequency = <12288000>; + }; + + daicodec: simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_bt: vcc3v3-bt-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_bt"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc_3v3_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_wf: vcc3v3-wf-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_wf"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc_3v3_s0>; + }; + + vcc4v0_sys: vcc4v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + AVDD-supply = <&avcc_1v8_codec_s0>; + DVDD-supply = <&avcc_1v8_codec_s0>; + HPVDD-supply = <&vcc_3v3_s0>; + PVDD-supply = <&vcc_3v3_s0>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_pins: led-pins { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* WIFI */ +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_wf>; + status = "okay"; +}; + +/* GMAC1 */ +&pcie2x1l1 { + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <150000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc4v0_sys>; + vcc2-supply = <&vcc4v0_sys>; + vcc3-supply = <&vcc4v0_sys>; + vcc4-supply = <&vcc4v0_sys>; + vcc5-supply = <&vcc4v0_sys>; + vcc6-supply = <&vcc4v0_sys>; + vcc7-supply = <&vcc4v0_sys>; + vcc8-supply = <&vcc4v0_sys>; + vcc9-supply = <&vcc4v0_sys>; + vcc10-supply = <&vcc4v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc4v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc4v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_gpu_mem_s0: dcdc-reg5 { + regulator-name = "vdd_gpu_mem_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_npu_mem_s0: dcdc-reg6 { + regulator-name = "vdd_npu_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vdd_vdenc_mem_s0: dcdc-reg8 { + regulator-name = "vdd_vdenc_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: dcdc-reg10 { + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: pldo-reg2 { + regulator-name = "vdd1_1v8_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_codec_s0: pldo-reg3 { + regulator-name = "avcc_1v8_codec_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: pldo-reg4 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: pldo-reg6 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + /* reserved for LPDDR5, unused? */ + vdd2l_0v9_ddr_s3: nldo-reg2 { + regulator-name = "vdd2l_0v9_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: nldo-reg3 { + regulator-name = "vdd_0v75_hdmi_edp_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg4 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg5 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pmic@1 { + compatible = "rockchip,rk806"; + reg = <0x01>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, + <&rk806_slave_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc4v0_sys>; + vcc2-supply = <&vcc4v0_sys>; + vcc3-supply = <&vcc4v0_sys>; + vcc4-supply = <&vcc4v0_sys>; + vcc5-supply = <&vcc4v0_sys>; + vcc6-supply = <&vcc4v0_sys>; + vcc7-supply = <&vcc4v0_sys>; + vcc8-supply = <&vcc4v0_sys>; + vcc9-supply = <&vcc4v0_sys>; + vcc10-supply = <&vcc4v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc4v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc4v0_sys>; + + rk806_slave_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_slave_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: dcdc-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: dcdc-reg7 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* reserved, unused? */ + vcc_1v8_cam_s0: pldo-reg1 { + regulator-name = "vcc_1v8_cam_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: pldo-reg2 { + regulator-name = "avdd1v8_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: pldo-reg3 { + regulator-name = "vdd_1v8_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* reserved, unused? */ + vcc_3v3_sd_s0: pldo-reg4 { + regulator-name = "vcc_3v3_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* reserved, unused? */ + vcc_2v8_cam_s0: pldo-reg5 { + regulator-name = "vcc_2v8_cam_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* unused */ + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_pll_s0: nldo-reg1 { + regulator-name = "vdd_0v75_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg3 { + regulator-name = "avdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* reserved, unused */ + avdd_1v2_cam_s0: nldo-reg4 { + regulator-name = "avdd_1v2_cam_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: nldo-reg5 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 96cc84e5aac..b595ddef702 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -4,9 +4,6 @@ */ #include "rk3588-u-boot.dtsi" -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/usb/pd.h> / { @@ -22,54 +19,9 @@ regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; - - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie30"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_vcc3v3_en>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; - - vbus5v0_typec: vbus5v0-typec { - compatible = "regulator-fixed"; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; - vin-supply = <&vcc5v0_usb>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - }; }; -&combphy0_ps { +&combphy2_psu { status = "okay"; }; @@ -77,52 +29,10 @@ bootph-all; }; -&pcie2x1l2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>; - reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie30phy { - status = "okay"; -}; - -&pcie3x4 { - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; - status = "okay"; -}; - &pinctrl { - pcie { - pcie_reset_h: pcie-reset-h { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie2x1l2_pins: pcie2x1l2-pins { - rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>, - <3 RK_PD0 4 &pcfg_pull_none>; - }; - - pcie3_rst: pcie3-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie3_vcc3v3_en: pcie3-vcc3v3-en { - rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb-typec { + usb { usbc0_int: usbc0-int { - rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; @@ -138,8 +48,6 @@ u-boot,spl-sfc-no-dma; pinctrl-names = "default"; pinctrl-0 = <&fspim2_pins>; - #address-cells = <1>; - #size-cells = <0>; status = "okay"; flash@0 { @@ -157,7 +65,6 @@ }; &u2phy0_otg { - rockchip,typec-vbus-det; status = "okay"; }; @@ -169,25 +76,17 @@ status = "okay"; }; -&usb2phy2_grf { +&usbdp_phy1 { status = "okay"; }; -&usb2phy3_grf { +&usbdp_phy1_u3 { status = "okay"; }; -&usb_host0_ehci { - companion = <&usb_host0_ohci>; -}; - -&usb_host1_ehci { - companion = <&usb_host1_ohci>; -}; - &usbdp_phy0 { orientation-switch; - svid = <0xff01>; + mode-switch; sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -195,14 +94,15 @@ port { #address-cells = <1>; #size-cells = <0>; - usbdp_phy0_orientation_switch: endpoint@0 { + + usbdp_phy0_typec_ss: endpoint@0 { reg = <0>; - remote-endpoint = <&usbc0_orien_sw>; + remote-endpoint = <&usbc0_ss>; }; - usbdp_phy0_dp_altmode_mux: endpoint@1 { + usbdp_phy0_typec_sbu: endpoint@1 { reg = <1>; - remote-endpoint = <&dp_altmode_mux>; + remote-endpoint = <&usbc0_sbu>; }; }; }; @@ -211,84 +111,53 @@ status = "okay"; }; -&usbdp_phy1 { - rockchip,dp-lane-mux = <2 3>; +&usb_host0_xhci { + usb-role-switch; status = "okay"; -}; -&usbdp_phy1_u3 { - status = "okay"; -}; + port { + #address-cells = <1>; + #size-cells = <0>; -&usbdrd3_0 { - status = "okay"; + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; }; -&usbdrd3_1 { +&usb_host1_xhci { status = "okay"; }; -&usbdrd_dwc3_0 { - usb-role-switch; - - port { - #address-cells = <1>; - #size-cells = <0>; - dwc3_0_role_switch: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_role_sw>; - }; - }; +&usb_host2_xhci { + status = "okay"; }; &i2c4 { + pinctrl-names = "default"; pinctrl-0 = <&i2c4m1_xfer>; status = "okay"; - usbc0: fusb302@22 { + usbc0: usb-typec@22 { compatible = "fcs,fusb302"; reg = <0x22>; interrupt-parent = <&gpio3>; interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus5v0_typec>; + vbus-supply = <&vcc12v_dcin>; status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_role_sw: endpoint@0 { - remote-endpoint = <&dwc3_0_role_switch>; - }; - }; - }; - usb_con: connector { compatible = "usb-c-connector"; label = "USB-C"; data-role = "dual"; - power-role = "dual"; + power-role = "sink"; try-power-role = "sink"; op-sink-microwatt = <1000000>; sink-pdos = - <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; - source-pdos = - <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - - altmodes { - #address-cells = <1>; - #size-cells = <0>; - - altmode@0 { - reg = <0>; - svid = <0xff01>; - vdo = <0xffffffff>; - }; - }; + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>, + <PDO_VAR(5000, 20000, 5000)>; ports { #address-cells = <1>; @@ -296,15 +165,22 @@ port@0 { reg = <0>; - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdp_phy0_orientation_switch>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; }; }; port@1 { reg = <1>; - dp_altmode_mux: endpoint { - remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; }; }; }; diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 8ab60968f27..741f631db34 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -3,6 +3,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include "rk3588.dtsi" / { @@ -12,6 +13,7 @@ aliases { mmc0 = &sdhci; mmc1 = &sdmmc; + mmc2 = &sdio; serial2 = &uart2; }; @@ -36,6 +38,19 @@ pinctrl-0 = <&hp_detect>; }; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_b>; + + led_rgb_b { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + fan: pwm-fan { compatible = "pwm-fan"; cooling-levels = <0 95 145 195 255>; @@ -44,6 +59,43 @@ #cooling-cells = <2>; }; + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_vcc3v3_en>; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_vcc3v3_en>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_host"; @@ -78,6 +130,14 @@ }; }; +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + &cpu_b0 { cpu-supply = <&vdd_cpu_big0_s0>; }; @@ -204,6 +264,34 @@ }; }; +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -211,12 +299,42 @@ }; }; + leds { + led_rgb_b: led-rgb-b { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sound { hp_detect: hp-detect { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_0_vcc3v3_en: pcie2-0-vcc-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_rst: pcie3-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3_vcc3v3_en: pcie3-vcc3v3-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -258,6 +376,33 @@ status = "okay"; }; +&sdio { + max-frequency = <200000000>; + no-sd; + no-mmc; + non-removable; + bus-width = <4>; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + wakeup-source; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_pcie2x1l0>; + vqmmc-supply = <&vcc_1v8_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status = "okay"; +}; + &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi index 68b419f3abd..31046fc7feb 100644 --- a/arch/arm/dts/rk3588-u-boot.dtsi +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -3,36 +3,27 @@ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. */ -#include "rockchip-u-boot.dtsi" #include "rk3588s-u-boot.dtsi" / { - usbdrd3_1: usbdrd3_1 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, <&cru ACLK_USB3OTG1>; - clock-names = "ref", "suspend", "bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; status = "disabled"; - - usbdrd_dwc3_1: usb@fc400000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG1>; - reset-names = "usb3-otg"; - dr_mode = "host"; - phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - }; }; usbdpphy1_grf: syscon@fd5cc000 { @@ -57,7 +48,6 @@ clock-names = "phyclk"; clock-output-names = "usb480m_phy1"; #clock-cells = <0>; - rockchip,usbctrl-grf = <&usb_grf>; status = "disabled"; u2phy1_otg: otg-port { diff --git a/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi new file mode 100644 index 00000000000..888d1b9c12d --- /dev/null +++ b/arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-u-boot.dtsi" + +/ { + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc; + }; +}; + +&fspim0_pins { + bootph-all; +}; + +&sfc { + bootph-pre-ram; + u-boot,spl-sfc-no-dma; + + flash@0 { + bootph-pre-ram; + }; +}; diff --git a/arch/arm/dts/rk3588s-orangepi-5.dts b/arch/arm/dts/rk3588s-orangepi-5.dts new file mode 100644 index 00000000000..8f399c4317b --- /dev/null +++ b/arch/arm/dts/rk3588s-orangepi-5.dts @@ -0,0 +1,662 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588s.dtsi" + +/ { + model = "Xunlong Orange Pi 5"; + compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <1800>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + + led-1 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-low; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_pcie20"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + tx_delay = <0x42>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + gpio-func { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi index 48181671eac..63151d9d237 100644 --- a/arch/arm/dts/rk3588s-pinctrl.dtsi +++ b/arch/arm/dts/rk3588s-pinctrl.dtsi @@ -1350,6 +1350,41 @@ i2s2 { /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2m0_lrck */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2m0_sclk */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ i2s2m1_lrck: i2s2m1-lrck { rockchip,pins = /* i2s2m1_lrck */ @@ -3308,6 +3343,15 @@ uart9 { /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <2 RK_PC4 10 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <2 RK_PC2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ uart9m1_xfer: uart9m1-xfer { rockchip,pins = /* uart9_rx_m1 */ diff --git a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi index c47b0a7112c..584476f77b1 100644 --- a/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi @@ -4,10 +4,6 @@ */ #include "rk3588s-u-boot.dtsi" -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/usb/pd.h> / { chosen { diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 27b2d7eff87..c0fd16c4022 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -4,7 +4,6 @@ */ #include "rockchip-u-boot.dtsi" -#include <dt-bindings/phy/phy.h> / { aliases { @@ -22,35 +21,47 @@ status = "okay"; }; - usbdrd3_0: usbdrd3_0 { - compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, <&cru ACLK_USB3OTG0>; - clock-names = "ref", "suspend", "bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; status = "disabled"; + }; - usbdrd_dwc3_0: usb@fc000000 { - compatible = "snps,dwc3"; - reg = <0x0 0xfc000000 0x0 0x400000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG0>; - reset-names = "usb3-otg"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - quirk-skip-phy-init; - }; + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; }; pmu1_grf: syscon@fd58a000 { @@ -59,6 +70,11 @@ reg = <0x0 0xfd58a000 0x0 0x2000>; }; + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + usb2phy0_grf: syscon@fd5d0000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; @@ -76,7 +92,6 @@ clock-names = "phyclk"; clock-output-names = "usb480m_phy0"; #clock-cells = <0>; - rockchip,usbctrl-grf = <&usb_grf>; status = "disabled"; u2phy0_otg: otg-port { @@ -102,15 +117,6 @@ reg = <0x0 0xfd5c8000 0x0 0x4000>; }; - sfc: spi@fe2b0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - status = "disabled"; - }; - rng: rng@fe378000 { compatible = "rockchip,trngv1"; reg = <0x0 0xfe378000 0x0 0x200>; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index 5544f66c6ff..61a9a11c3bb 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -1424,6 +1424,17 @@ }; }; + sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>; @@ -2304,6 +2315,19 @@ #interrupt-cells = <2>; }; }; + + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3588_PD_AV1>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; + }; }; #include "rk3588s-pinctrl.dtsi" diff --git a/arch/arm/dts/rv1126-u-boot.dtsi b/arch/arm/dts/rv1126-u-boot.dtsi index 5e348278f2a..44859801357 100644 --- a/arch/arm/dts/rv1126-u-boot.dtsi +++ b/arch/arm/dts/rv1126-u-boot.dtsi @@ -15,6 +15,18 @@ compatible = "rockchip,rv1126-dmc"; bootph-all; }; + + otp: otp@ff5c0000 { + compatible = "rockchip,rv1126-otp"; + reg = <0xff5c0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + cpu_id: id@7 { + reg = <0x07 0x10>; + }; + }; }; &gpio0 { @@ -26,15 +38,15 @@ }; &grf { - bootph-pre-ram; + bootph-all; }; &pmu { - bootph-pre-ram; + bootph-all; }; &pmugrf { - bootph-pre-ram; + bootph-all; }; &xin24m { diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 1f7fdbce530..eb283cacd27 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -135,20 +135,28 @@ &qspi_bk1_pins_a { bootph-pre-ram; - pins1 { + pins { bootph-pre-ram; }; - pins2 { +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { bootph-pre-ram; }; }; &qspi_bk2_pins_a { bootph-pre-ram; - pins1 { + pins { bootph-pre-ram; }; - pins2 { +}; + +&qspi_cs2_pins_a { + bootph-pre-ram; + pins { bootph-pre-ram; }; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index f12941b05f6..2f70b0690d2 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -134,20 +134,14 @@ &qspi_bk1_pins_a { bootph-pre-ram; - pins1 { - bootph-pre-ram; - }; - pins2 { + pins { bootph-pre-ram; }; }; -&qspi_bk2_pins_a { +&qspi_cs1_pins_a { bootph-pre-ram; - pins1 { - bootph-pre-ram; - }; - pins2 { + pins { bootph-pre-ram; }; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index eb905ad2820..552b35db3c7 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -98,10 +98,14 @@ &qspi_bk1_pins_a { bootph-pre-ram; - pins1 { + pins { bootph-pre-ram; }; - pins2 { +}; + +&qspi_cs1_pins_a { + bootph-pre-ram; + pins { bootph-pre-ram; }; }; diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index a521a43d6cf..28ecd2b467a 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -704,6 +704,8 @@ clock-names = "sdhci"; resets = <&tegra_car 14>; reset-names = "sdhci"; + nvidia,default-tap = <0x2>; + nvidia,default-trim = <0x4>; status = "disabled"; }; @@ -715,6 +717,8 @@ clock-names = "sdhci"; resets = <&tegra_car 9>; reset-names = "sdhci"; + nvidia,default-tap = <0x8>; + nvidia,default-trim = <0x0>; status = "disabled"; }; @@ -726,6 +730,8 @@ clock-names = "sdhci"; resets = <&tegra_car 69>; reset-names = "sdhci"; + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; status = "disabled"; }; @@ -737,6 +743,8 @@ clock-names = "sdhci"; resets = <&tegra_car 15>; reset-names = "sdhci"; + nvidia,default-tap = <0x8>; + nvidia,default-trim = <0x0>; status = "disabled"; }; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index 4fa980f24f9..fcf31e2dd09 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include <dt-bindings/input/input.h> - #include "tegra30.dtsi" / { @@ -62,6 +61,9 @@ status = "okay"; bus-width = <8>; non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; }; usb1: usb@7d000000 { @@ -150,7 +152,6 @@ regulator-name = "vdd_5v0_bl"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-boot-on; gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; enable-active-high; }; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts index a98d3e21455..945ae404acc 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts @@ -22,7 +22,7 @@ gpio-controller; regulators { - vdd_1v8: sd2 { + vdd_1v8_vio: sd2 { regulator-name = "vdd_1v8_gen"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -34,8 +34,7 @@ vcore_emmc: ldo3 { regulator-name = "vcore_emmc"; regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; + regulator-max-microvolt = <2850000>; }; }; }; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts index 44ea218a472..4363bfc87d8 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts @@ -23,12 +23,19 @@ gpio-controller; regulators { + vdd_1v8_vio: vddio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + /* eMMC VDD */ vcore_emmc: ldo1 { regulator-name = "vdd_emmc_core"; - regulator-min-microvolt = <1000000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; }; }; diff --git a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts index 812d5a1ba70..89348fde134 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts @@ -22,7 +22,7 @@ gpio-controller; regulators { - vdd_1v8: sd2 { + vdd_1v8_vio: sd2 { regulator-name = "vdd_1v8_gen"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -34,8 +34,7 @@ vcore_emmc: ldo3 { regulator-name = "vcore_emmc"; regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <3100000>; - regulator-always-on; + regulator-max-microvolt = <2850000>; }; }; }; diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 4b2dc61713c..39f7caf8d0b 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -1,18 +1,209 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include "tegra30-asus-transformer.dtsi" +#include <dt-bindings/input/input.h> +#include "tegra30.dtsi" / { model = "ASUS Portable AiO P1801-T"; compatible = "asus,p1801-t", "nvidia,tegra30"; - /delete-node/ host1x@50000000; - /delete-node/ pwm@7000a000; + chosen { + stdout-path = &uarta; + }; - /delete-node/ backlight; - /delete-node/ panel; + aliases { + i2c0 = &pwr_i2c; + i2c1 = &hdmi_ddc; - /delete-node/ regulator-pnl; - /delete-node/ regulator-bl; + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + usb1 = &usb2; /* Mini USB */ + usb2 = &usb3; /* Dock USB */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + nvidia,panel = <&hdmi>; + }; + }; + + hdmi: hdmi@54280000 { + clocks = <&tegra_car TEGRA30_CLK_HDMI>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + status = "okay"; + + hdmi-supply = <&hdmi_5v0_sys>; + pll-supply = <&vdd_1v8_vio>; + vdd-supply = <&hdmi_3v3_vdd>; + + /* low: tablet, high: dock */ + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_LOW>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <33000>; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS659110 PMIC */ + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + vdd_1v8_vio: vddio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + sdmmc1: sdhci@78000000 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* USB via ASUS connector */ + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* Mini USB port */ + usb2: usb@7d004000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; + }; + + /* Dock's USB port */ + usb3: usb@7d008000 { + status = "okay"; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + hdmi_3v3_vdd: regulator-vdd { + compatible = "regulator-fixed"; + regulator-name = "hdmi_3v3_vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + hdmi_5v0_sys: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "hdmi_5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; diff --git a/arch/arm/dts/tegra30-asus-tf201.dts b/arch/arm/dts/tegra30-asus-tf201.dts index 54f359ef960..59e19f97667 100644 --- a/arch/arm/dts/tegra30-asus-tf201.dts +++ b/arch/arm/dts/tegra30-asus-tf201.dts @@ -6,4 +6,9 @@ / { model = "ASUS Transformer Prime TF201"; compatible = "asus,tf201", "nvidia,tegra30"; + + usb-phy@7d008000 { + /delete-property/ nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ + }; }; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index c9b8f4fa140..fd9d11ca19c 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -1,38 +1,116 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include "tegra30-asus-transformer.dtsi" +#include <dt-bindings/input/input.h> +#include "tegra30.dtsi" / { model = "ASUS VivoTab RT TF600T"; compatible = "asus,tf600t", "nvidia,tegra30"; + chosen { + stdout-path = &uarta; + }; + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + spi0 = &spi4; + + usb0 = &usb1; + usb1 = &usb3; /* Dock USB */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + dc@54200000 { + clocks = <&tegra_car TEGRA30_CLK_DISP1>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + + rgb { + status = "okay"; + + nvidia,panel = <&dsia>; + }; + }; + + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel = <&panel>; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; }; - /delete-node/ host1x@50000000; + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; - pmic_i2c: i2c@7000d000 { /* Texas Instruments TPS659110 PMIC */ pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + regulators { vdd_1v2_bl: vdd1 { regulator-name = "vdd_1v2_backlight"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + }; + + vcore_lcd: vdd2 { + regulator-name = "vcore_lcd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + vdd_1v8_vio: vddio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; - ti,regulator-ext-sleep-control = <8>; }; - /delete-node/ ldo2; - /delete-node/ ldo3; + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; /* uSD slot VDDIO */ vddio_usd: ldo5 { regulator-name = "vddio_sdmmc"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -57,11 +135,65 @@ }; }; - backlight { + sdmmc1: sdhci@78000000 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* USB via ASUS connector */ + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* Dock's USB port */ + usb3: usb@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; power-supply = <&vdd_1v2_bl>; + pwms = <&pwm 0 71428>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; }; gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; @@ -75,7 +207,14 @@ }; }; - /delete-node/ panel; + panel: panel { + compatible = "hydis,hv101hd1"; + + vdd-supply = <&vcore_lcd>; + enable-gpios = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; vdd_usd: regulator-usd { compatible = "regulator-fixed"; @@ -83,7 +222,4 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - - /delete-node/ regulator-pnl; - /delete-node/ regulator-bl; }; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index 4eee1df084c..888f9ca74e6 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include <dt-bindings/input/input.h> - #include "tegra30.dtsi" / { @@ -70,12 +69,19 @@ gpio-controller; regulators { + vdd_1v8_vio: vddio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + /* eMMC VDD */ vcore_emmc: ldo1 { regulator-name = "vdd_emmc_core"; - regulator-min-microvolt = <1000000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; /* uSD slot VDD */ @@ -88,8 +94,10 @@ /* uSD slot VDDIO */ vddio_usd: ldo3 { regulator-name = "vddio_usd"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <3100000>; regulator-max-microvolt = <3100000>; + regulator-always-on; + regulator-boot-on; }; }; }; @@ -110,6 +118,9 @@ status = "okay"; bus-width = <8>; non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; }; /* USB via ASUS connector */ @@ -123,6 +134,10 @@ status = "okay"; }; + usb-phy@7d008000 { + status = "okay"; + }; + backlight: backlight { compatible = "pwm-backlight"; @@ -204,7 +219,6 @@ regulator-name = "vdd_5v0_bl"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-boot-on; gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; enable-active-high; }; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index c55e193d1d7..5c7b2deae5d 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -5,7 +5,6 @@ /* CPU Speedo ID 4, Soc Speedo ID 1, CPU Process: 1, Core Process: 0 */ #include <dt-bindings/input/input.h> - #include "tegra30.dtsi" / { @@ -66,13 +65,22 @@ compatible = "ti,tps80032"; reg = <0x48>; + ti,system-power-controller; + regulators { + vdd_1v8_vio: smps5 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + /* DSI VDD */ avdd_dsi_csi: ldo1 { regulator-name = "avdd_dsi_csi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-always-on; }; }; }; @@ -82,6 +90,9 @@ status = "okay"; bus-width = <8>; non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; }; micro_usb: usb@7d000000 { diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi index 922e39915e5..6e52fc5a53e 100644 --- a/arch/arm/dts/tegra30-lg-x3.dtsi +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include <dt-bindings/input/input.h> - #include "tegra30.dtsi" / { @@ -91,6 +90,14 @@ regulator-boot-on; }; + avdd_3v3_periph: ldo2 { + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + vdd_usd: ldo3 { regulator-name = "vdd_sdmmc3"; regulator-min-microvolt = <3000000>; @@ -103,8 +110,6 @@ regulator-name = "vdd_ddr_rx"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; }; }; }; diff --git a/arch/arm/dts/tps6507x.dtsi b/arch/arm/dts/tps6507x.dtsi index db4809d308f..6749d3f3d58 100644 --- a/arch/arm/dts/tps6507x.dtsi +++ b/arch/arm/dts/tps6507x.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ /* * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65070.pdf + * https://www.ti.com/lit/ds/symlink/tps65070.pdf */ &tps { diff --git a/arch/arm/dts/tps65217.dtsi b/arch/arm/dts/tps65217.dtsi index 0d463de5650..262e0bb3eaa 100644 --- a/arch/arm/dts/tps65217.dtsi +++ b/arch/arm/dts/tps65217.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65217.pdf + * https://www.ti.com/lit/ds/symlink/tps65217.pdf */ &tps { diff --git a/arch/arm/dts/tps65910.dtsi b/arch/arm/dts/tps65910.dtsi index a941d1e6232..ab3a4ffd129 100644 --- a/arch/arm/dts/tps65910.dtsi +++ b/arch/arm/dts/tps65910.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ */ /* * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/tps65910.pdf + * https://www.ti.com/lit/ds/symlink/tps65910.pdf */ &tps { diff --git a/arch/arm/dts/twl4030.dtsi b/arch/arm/dts/twl4030.dtsi index 6cb0a01e77e..f87cea1ac4b 100644 --- a/arch/arm/dts/twl4030.dtsi +++ b/arch/arm/dts/twl4030.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/dts/twl6030.dtsi b/arch/arm/dts/twl6030.dtsi index 9d588cfaa5c..8da969035c4 100644 --- a/arch/arm/dts/twl6030.dtsi +++ b/arch/arm/dts/twl6030.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /* * Integrated Power Management Chip - * http://www.ti.com/lit/ds/symlink/twl6030.pdf + * https://www.ti.com/lit/ds/symlink/twl6030.pdf */ &twl { compatible = "ti,twl6030"; diff --git a/arch/arm/dts/twl6030_omap4.dtsi b/arch/arm/dts/twl6030_omap4.dtsi index fc498d0bde8..5730e46b006 100644 --- a/arch/arm/dts/twl6030_omap4.dtsi +++ b/arch/arm/dts/twl6030_omap4.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ &twl { diff --git a/arch/arm/dts/versal-mini-ospi-stacked.dts b/arch/arm/dts/versal-mini-ospi-stacked.dts new file mode 100644 index 00000000000..f46125da716 --- /dev/null +++ b/arch/arm/dts/versal-mini-ospi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI Quad Stacked DTS + * + * Copyright (C) 2018-2020 Xilinx, Inc. + */ + +#include "versal-mini-ospi.dtsi" + +/ { + model = "Xilinx Versal MINI OSPI STACKED"; +}; + +&ospi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <8>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-parallel.dts b/arch/arm/dts/versal-mini-qspi-parallel.dts new file mode 100644 index 00000000000..8485cda3529 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-parallel.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI Quad Parallel DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI PARALLEL"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-stacked.dts b/arch/arm/dts/versal-mini-qspi-stacked.dts new file mode 100644 index 00000000000..54d42775e08 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI Quad Stacked DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-x1-single.dts b/arch/arm/dts/versal-mini-qspi-x1-single.dts new file mode 100644 index 00000000000..4d459a19789 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-x1-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI x1 Single DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI X1 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-x1-stacked.dts b/arch/arm/dts/versal-mini-qspi-x1-stacked.dts new file mode 100644 index 00000000000..905dc773405 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-x1-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI x1 Stacked DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI X1 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-x2-single.dts b/arch/arm/dts/versal-mini-qspi-x2-single.dts new file mode 100644 index 00000000000..d25ad7c7780 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-x2-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI x2 Single DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI X2 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/versal-mini-qspi-x2-stacked.dts b/arch/arm/dts/versal-mini-qspi-x2-stacked.dts new file mode 100644 index 00000000000..0c9e740c728 --- /dev/null +++ b/arch/arm/dts/versal-mini-qspi-x2-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal QSPI x2 Stacked DTS + * + * Copyright (C) 2018-2019 Xilinx, Inc. + */ + +#include "versal-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal MINI QSPI X2 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/versal-net-mini-ospi-stacked.dts b/arch/arm/dts/versal-net-mini-ospi-stacked.dts new file mode 100644 index 00000000000..4bc954a1833 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-ospi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET OSPI Quad Stacked DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-ospi.dtsi" + +/ { + model = "Xilinx Versal NET MINI OSPI STACKED"; +}; + +&ospi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <8>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-parallel.dts b/arch/arm/dts/versal-net-mini-qspi-parallel.dts new file mode 100644 index 00000000000..edc23116094 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-parallel.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI Quad Parallel DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI PARALLEL"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-stacked.dts new file mode 100644 index 00000000000..920eed2f8c5 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI Quad Stacked DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-x1-single.dts b/arch/arm/dts/versal-net-mini-qspi-x1-single.dts new file mode 100644 index 00000000000..856c79c3c00 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-x1-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI x1 Single DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI X1 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts new file mode 100644 index 00000000000..5f74d98ad61 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-x1-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI x1 Stacked DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI X1 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-x2-single.dts b/arch/arm/dts/versal-net-mini-qspi-x2-single.dts new file mode 100644 index 00000000000..6ceaa244e68 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-x2-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI x2 Single DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI X2 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts b/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts new file mode 100644 index 00000000000..5f4d0b55059 --- /dev/null +++ b/arch/arm/dts/versal-net-mini-qspi-x2-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Versal NET QSPI x2 Stacked DTS + * + * (C) Copyright 2023, Advanced Micro Devices, Inc. + */ + +#include "versal-net-mini-qspi.dtsi" + +/ { + model = "Xilinx Versal NET MINI QSPI X2 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index fb61fe98e3d..f8c786ab0b7 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -306,15 +306,11 @@ compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; nor0: flash@1,0 { status = "disabled"; compatible = "cfi-flash"; reg = <1 0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm/dts/zynq-cse-qspi-parallel.dts b/arch/arm/dts/zynq-cse-qspi-parallel.dts new file mode 100644 index 00000000000..afa6348cf59 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-parallel.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI Quad Parallel DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI PARALLEL Board"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-stacked.dts b/arch/arm/dts/zynq-cse-qspi-stacked.dts new file mode 100644 index 00000000000..47859f7ea84 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI Quad Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI STACKED Board"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-rx-bus-width = <4>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-x1-single.dts b/arch/arm/dts/zynq-cse-qspi-x1-single.dts new file mode 100644 index 00000000000..c14fb422b7f --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-x1-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x1 Single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI X1 SINGLE Board"; +}; + +&flash0 { + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts new file mode 100644 index 00000000000..0f4d414a253 --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-x1-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x1 Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI X1 STACKED Board"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-x2-single.dts b/arch/arm/dts/zynq-cse-qspi-x2-single.dts new file mode 100644 index 00000000000..11be06385da --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-x2-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x2 Single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI X2 SINGLE Board"; +}; + +&flash0 { + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts new file mode 100644 index 00000000000..d1b42e9269b --- /dev/null +++ b/arch/arm/dts/zynq-cse-qspi-x2-stacked.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x2 Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynq-cse-qspi.dtsi" + +/ { + model = "Zynq CSE QSPI X2 STACKED Board"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 8d47f24b757..0106d7bb177 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -406,6 +406,31 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 03eb016ed68..ceea982546e 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -309,13 +309,39 @@ &qspi { bootph-all; status = "okay"; - num-cs = <1>; + num-cs = <2>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 17680d7f8ec..199384bec96 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -69,6 +69,31 @@ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index d1e971254e5..f9a086fe66d 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -49,8 +49,27 @@ &nfc0 { status = "okay"; + #address-cells = <1>; + #size-cells = <0>; nand@0 { reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nand-fsbl-uboot"; + reg = <0x0 0x1000000>; + }; + partition@1000000 { + label = "nand-linux"; + reg = <0x1000000 0x2000000>; + }; + partition@3000000 { + label = "nand-rootfs"; + reg = <0x3000000 0x200000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 6e36634e3d4..24520e7d396 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -56,6 +56,31 @@ &nor0 { status = "okay"; bank-width = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nor-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "nor-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "nor-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "nor-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "nor-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; &smcc { diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 21902fbb0cc..add75999f47 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -61,13 +61,39 @@ &qspi { status = "okay"; - num-cs = <1>; + num-cs = <2>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; - reg = <0x0>; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 5320b4b233a..70bc41822e3 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -55,8 +55,35 @@ flash@0 { compatible = "spansion,s25fl256s1", "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <30000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; m25p,fast-read; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 5f1b0b23c12..dd4569e7bd9 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -10,12 +10,6 @@ #include <dt-bindings/clock/xlnx-zynqmp-clk.h> / { - fclk0: fclk0 { - status = "okay"; - compatible = "xlnx,fclk"; - clocks = <&zynqmp_clk PL0_REF>; - }; - pss_ref_clk: pss_ref_clk { bootph-all; compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 25ef646c846..83b8a98d80c 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -71,11 +71,13 @@ &qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index ece9e691454..dd37b726d3d 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -67,11 +67,13 @@ &qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 7372968e573..811cebafe9e 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -67,11 +67,13 @@ &qspi { status = "okay"; + num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; - reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; diff --git a/arch/arm/dts/zynqmp-mini-qspi-parallel.dts b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts new file mode 100644 index 00000000000..728e8223de4 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-parallel.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI Quad Parallel DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI PARALLEL"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-single.dts b/arch/arm/dts/zynqmp-mini-qspi-single.dts new file mode 100644 index 00000000000..0f9306e988c --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-single.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI SINGLE"; +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts new file mode 100644 index 00000000000..9a9541b0b61 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-stacked.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI Quad Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts new file mode 100644 index 00000000000..5af875cc719 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-x1-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI x1 Single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI X1 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts new file mode 100644 index 00000000000..ebf890e0ae9 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-x1-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI x1 Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI X1 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts new file mode 100644 index 00000000000..a5ab31583ec --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-x2-single.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx CSE QSPI x2 Single DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI X2 SINGLE"; +}; + +&flash0 { + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts new file mode 100644 index 00000000000..e234b76f252 --- /dev/null +++ b/arch/arm/dts/zynqmp-mini-qspi-x2-stacked.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx ZynqMP QSPI x2 Stacked DTS + * + * Copyright (C) 2015 - 2017 Xilinx, Inc. + */ + +#include "zynqmp-mini-qspi.dts" + +/ { + model = "ZynqMP MINI QSPI X2 STACKED"; +}; + +&qspi { + num-cs = <2>; +}; + +&flash0 { + reg = <0>, <1>; + stacked-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; +}; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 22e7d68d02b..c4f1da92186 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -190,6 +190,25 @@ &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -345,6 +364,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index eadc2563064..6c5e0e56606 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -178,6 +178,25 @@ &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -333,6 +352,12 @@ }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index 2f88aa4a0d2..9ab8f5bfffe 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -119,9 +119,13 @@ phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { /* u131 - M88e1512 */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { /* u131 - M88e1512 */ + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index 66919f578e0..ce76e0b3db3 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -120,9 +120,13 @@ phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 23a3ff2fed9..160c6c58b36 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -141,8 +141,7 @@ reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; @@ -178,8 +177,7 @@ reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "bch"; + nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index f03c201caee..58a56bc1bd8 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -214,16 +214,61 @@ soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; + /* efuse access */ + efuse_dna: efuse-dna@c { + reg = <0xc 0xc>; + }; + efuse_usr0: efuse-usr0@20 { + reg = <0x20 0x4>; + }; + efuse_usr1: efuse-usr1@24 { + reg = <0x24 0x4>; + }; + efuse_usr2: efuse-usr2@28 { + reg = <0x28 0x4>; + }; + efuse_usr3: efuse-usr3@2c { + reg = <0x2c 0x4>; + }; + efuse_usr4: efuse-usr4@30 { + reg = <0x30 0x4>; + }; + efuse_usr5: efuse-usr5@34 { + reg = <0x34 0x4>; + }; + efuse_usr6: efuse-usr6@38 { + reg = <0x38 0x4>; + }; + efuse_usr7: efuse-usr7@3c { + reg = <0x3c 0x4>; + }; + efuse_miscusr: efuse-miscusr@40 { + reg = <0x40 0x4>; + }; + efuse_chash: efuse-chash@50 { + reg = <0x50 0x4>; + }; + efuse_pufmisc: efuse-pufmisc@54 { + reg = <0x54 0x4>; + }; + efuse_sec: efuse-sec@58 { + reg = <0x58 0x4>; + }; + efuse_spkid: efuse-spkid@5c { + reg = <0x5c 0x4>; + }; + efuse_ppk0hash: efuse-ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + efuse_ppk1hash: efuse-ppk1hash@d0 { + reg = <0xd0 0x30>; + }; }; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; - xlnx_aes: zynqmp-aes { - compatible = "xlnx,zynqmp-aes"; - }; - zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; @@ -261,7 +306,6 @@ #address-cells = <2>; #size-cells = <2>; ranges; - power-domains = <&zynqmp_firmware PD_PL>; }; remoteproc { @@ -344,7 +388,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e8>; + /* iommus = <&smmu 0x14e8>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -357,7 +401,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14e9>; + /* iommus = <&smmu 0x14e9>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -370,7 +414,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ea>; + /* iommus = <&smmu 0x14ea>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -383,7 +427,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14eb>; + /* iommus = <&smmu 0x14eb>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -396,7 +440,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ec>; + /* iommus = <&smmu 0x14ec>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -409,7 +453,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ed>; + /* iommus = <&smmu 0x14ed>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -422,7 +466,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ee>; + /* iommus = <&smmu 0x14ee>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -435,7 +479,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; - iommus = <&smmu 0x14ef>; + /* iommus = <&smmu 0x14ef>; */ power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -480,7 +524,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x868>; + /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -493,7 +537,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x869>; + /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -506,7 +550,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86a>; + /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -519,7 +563,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86b>; + /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -532,7 +576,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86c>; + /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -545,7 +589,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86d>; + /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -558,7 +602,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86e>; + /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -571,7 +615,7 @@ clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; - iommus = <&smmu 0x86f>; + /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -591,7 +635,7 @@ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x872>; + /* iommus = <&smmu 0x872>; */ power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -603,7 +647,7 @@ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x874>; + /* iommus = <&smmu 0x874>; */ power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; @@ -617,7 +661,7 @@ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x875>; + /* iommus = <&smmu 0x875>; */ power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; @@ -631,7 +675,7 @@ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x876>; + /* iommus = <&smmu 0x876>; */ power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; @@ -645,7 +689,7 @@ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; - iommus = <&smmu 0x877>; + /* iommus = <&smmu 0x877>; */ power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; @@ -724,7 +768,7 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - iommus = <&smmu 0x4d0>; + /* iommus = <&smmu 0x4d0>; */ power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; @@ -745,7 +789,7 @@ <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; - iommus = <&smmu 0x873>; + /* iommus = <&smmu 0x873>; */ power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -777,8 +821,7 @@ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, - <&smmu 0x4c2>, <&smmu 0x4c3>; + /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */ /* dma-coherent; */ }; @@ -790,7 +833,7 @@ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x870>; + /* iommus = <&smmu 0x870>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; power-domains = <&zynqmp_firmware PD_SD_0>; @@ -805,7 +848,7 @@ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - iommus = <&smmu 0x871>; + /* iommus = <&smmu 0x871>; */ #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; power-domains = <&zynqmp_firmware PD_SD_1>; @@ -956,11 +999,10 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&smmu 0x860>; + /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; - snps,xhci-stream-quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -989,11 +1031,10 @@ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&smmu 0x861>; + /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; - snps,xhci-stream-quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1039,8 +1080,6 @@ compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; - #address-cells = <1>; - #size-cells = <0>; }; }; @@ -1052,6 +1091,7 @@ interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; + /* iommus = <&smmu 0xce4>; */ #dma-cells = <1>; }; @@ -1066,6 +1106,7 @@ reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; + /* iommus = <&smmu 0xce3>; */ clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h index 7bcafba6f0b..8e3d55f3e76 100644 --- a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h +++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h @@ -4,7 +4,7 @@ * * Clock synthesizer header * - * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef __CLK_SYNTHESIZER_H diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 67400c2c63a..13960db2fbd 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -4,7 +4,7 @@ * * clock header * - * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _CLOCKS_H_ diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index e5ad50754e7..adb574e8f13 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -4,7 +4,7 @@ * * AM33xx clock define * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _CLOCKS_AM33XX_H_ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index b33e6f7fd1b..8ec25854f3f 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -4,7 +4,7 @@ * * AM33xx specific header file * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _AM33XX_CPU_H diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 1a031071073..6e7a62bc227 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -4,7 +4,7 @@ * * ddr specific header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _DDR_DEFS_H diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 387f053ce68..33ee915098f 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -4,7 +4,7 @@ * * hardware specific header * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef __AM33XX_HARDWARE_H diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index 878ef3e5d22..de597c2775f 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -4,7 +4,7 @@ * * AM33xx hardware specific header * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef __AM33XX_HARDWARE_AM33XX_H diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 0b73ebdbb4d..8786d8c923e 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -4,7 +4,7 @@ * * AM43xx hardware specific header * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef __AM43XX_HARDWARE_AM43XX_H diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index b1b189631af..ed60abf2e71 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -1,7 +1,7 @@ /* * mmc_host_def.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index ebb2d303dfe..f704afaca12 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -1,7 +1,7 @@ /* * mux.h * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h index 26bd4b46ffb..c702e4adc41 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h @@ -1,7 +1,7 @@ /* * mux_am33xx.h * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h index f74ae74ff16..24f0041c94b 100644 --- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h @@ -2,7 +2,7 @@ /* * mux_am43xx.h * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _MUX_AM43XX_H_ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 53046deed56..71a84fef35e 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -2,7 +2,7 @@ /* * omap.h * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * * Author: * Chandan Nath <chandan.nath@ti.com> diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index be17aad29ee..513cdaca859 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -4,7 +4,7 @@ * * System information header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _SYS_PROTO_H_ diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h index bac43b231f8..397bb47edfb 100644 --- a/arch/arm/include/asm/arch-omap3/emif4.h +++ b/arch/arm/include/asm/arch-omap3/emif4.h @@ -4,7 +4,7 @@ * Vaibhav Hiremath <hvaibhav@ti.com> * * Copyright (C) 2010 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _EMIF_H_ diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h index 30bdaad64e3..e8fe88f2afc 100644 --- a/arch/arm/include/asm/arch-omap4/ehci.h +++ b/arch/arm/include/asm/arch-omap4/ehci.h @@ -4,7 +4,7 @@ * Based on LINUX KERNEL * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com * Author: Govindraj R <govindraj.raja@ti.com> */ diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h index 48dc8092492..67e3dae7bce 100644 --- a/arch/arm/include/asm/arch-omap4/hardware.h +++ b/arch/arm/include/asm/arch-omap4/hardware.h @@ -4,7 +4,7 @@ * * hardware specific header * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef __OMAP_HARDWARE_H diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h index 1790b92a245..3c52a76d48b 100644 --- a/arch/arm/include/asm/arch-omap5/ehci.h +++ b/arch/arm/include/asm/arch-omap5/ehci.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com* + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com* * Author: Govindraj R <govindraj.raja@ti.com> */ diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h index b6d26e9f0e5..c948c0ef114 100644 --- a/arch/arm/include/asm/arch-omap5/hardware.h +++ b/arch/arm/include/asm/arch-omap5/hardware.h @@ -4,7 +4,7 @@ * * hardware specific header * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef __OMAP_HARDWARE_H diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h index 28c0fb9a4c6..6bf3828c84e 100644 --- a/arch/arm/include/asm/arch-rk3066/boot0.h +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -3,6 +3,81 @@ #ifndef __ASM_ARCH_BOOT0_H__ #define __ASM_ARCH_BOOT0_H__ -#include <asm/arch-rockchip/boot0.h> +#include <asm/arch-rockchip/boot_mode.h> +/* + * Execution starts on the instruction following this 4-byte header + * (containing the magic 'RK30'). This magic constant will be written into + * the final image by the rkimage tool, but we need to reserve space for it here. + */ +#ifdef CONFIG_SPL_BUILD + b 1f /* if overwritten, entry-address is at the next word */ +1: +#endif + +#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM) +/* + * Keep track of the re-entries with help of the lr register. + * This binary can be re-used and called from various BROM functions. + * Only when it's called from the part that handles SPI, NAND or EMMC + * hardware it needs to early return to BROM ones. + * In download mode when it handles data on USB OTG and UART0 + * this section must be skipped. + */ + ldr r3, =CONFIG_ROCKCHIP_BOOT_LR_REG + cmp lr, r3 /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG) */ + bne reset /* goto reset; */ +/* + * Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in + * support to enter download mode on return to BROM. This binary must check + * the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set. + * It then returns to BROM to the end of the function that reads boot blocks. + * From there the BROM code goes into a download mode and waits for data + * on USB OTG and UART0. + */ + ldr r2, =BOOT_BROM_DOWNLOAD + ldr r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG + ldr r0, [r3] /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != */ + cmp r0, r2 /* BOOT_BROM_DOWNLOAD) { */ + bne early_return /* goto early_return; */ + /* } else { */ + mov r0, #0 + str r0, [r3] /* writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */ + + ldr r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG + bx r3 /* return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/ + /* } */ +early_return: + bx lr /* return to LR in BROM */ + +SAVE_SP_ADDR: + .word 0 + + .globl save_boot_params +save_boot_params: + push {r1-r12, lr} + ldr r0, =SAVE_SP_ADDR + str sp, [r0] + b save_boot_params_ret + + .globl back_to_bootrom +back_to_bootrom: + ldr r0, =SAVE_SP_ADDR + ldr sp, [r0] + mov r0, #0 + pop {r1-r12, pc} +#endif + +#if (defined(CONFIG_SPL_BUILD)) +/* U-Boot proper of armv7 does not need this */ + b reset +#endif + +/* + * For armv7, the addr '_start' will be used as vector start address + * and is written to the VBAR register, which needs to aligned to 0x20. + */ + .align(5), 0x0 +_start: + ARM_VECTORS #endif diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index d6a55764ba3..750c7d809e7 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -128,21 +128,22 @@ struct tegra_mmc { /* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */ #define MEMCOMP_PADCTRL_VREF 7 -#define AUTO_CAL_ENABLE (1 << 29) -#define AUTO_CAL_ACTIVE (1 << 31) -#define AUTO_CAL_START (1 << 31) +#define AUTO_CAL_ENABLE BIT(29) +#define AUTO_CAL_ACTIVE BIT(31) +#define AUTO_CAL_START BIT(31) + #if defined(CONFIG_TEGRA210) #define AUTO_CAL_PD_OFFSET (0x7D << 8) #define AUTO_CAL_PU_OFFSET (0 << 0) -#define IO_TRIM_BYPASS_MASK (1 << 2) -#define TRIM_VAL_SHIFT 24 -#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT) -#define TAP_VAL_SHIFT 16 -#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT) #else #define AUTO_CAL_PD_OFFSET (0x70 << 8) #define AUTO_CAL_PU_OFFSET (0x62 << 0) #endif +#define TRIM_VAL_SHIFT 24 +#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT) +#define TAP_VAL_SHIFT 16 +#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT) + #endif /* __ASSEMBLY__ */ #endif /* __TEGRA_MMC_H_ */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 19a9e112a43..4f0adb07325 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -118,6 +118,8 @@ #define HCR_EL2_E2H_BIT 34 #ifndef __ASSEMBLY__ +#include <linux/types.h> + static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index 2b51b5eb997..662b62cbb28 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -4,7 +4,7 @@ * Based on LINUX KERNEL * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com* + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com* * Author: Govindraj R <govindraj.raja@ti.com> */ diff --git a/arch/arm/include/asm/ti-common/omap_wdt.h b/arch/arm/include/asm/ti-common/omap_wdt.h index 42d7e4c989e..855f8892257 100644 --- a/arch/arm/include/asm/ti-common/omap_wdt.h +++ b/arch/arm/include/asm/ti-common/omap_wdt.h @@ -4,7 +4,7 @@ * * OMAP Watchdog header file * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef __OMAP_WDT_H__ diff --git a/arch/arm/mach-davinci/config.mk b/arch/arm/mach-davinci/config.mk index 4674cae43b1..edbac8e8e21 100644 --- a/arch/arm/mach-davinci/config.mk +++ b/arch/arm/mach-davinci/config.mk @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/ +# Copyright (C) 2012, Texas Instruments, Incorporated - https://www.ti.com/ ifndef CONFIG_SPL_BUILD INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 08ab7069187..abd48d42583 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -71,7 +71,7 @@ config CSF_SIZE config CMD_BMODE bool "Support the 'bmode' command" default y - depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 + depends on ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5 help This enables the 'bmode' (bootmode) command for forcing a boot from specific media. diff --git a/arch/arm/mach-imx/cmd_bmode.c b/arch/arm/mach-imx/cmd_bmode.c index cb317499d54..5b2f4686230 100644 --- a/arch/arm/mach-imx/cmd_bmode.c +++ b/arch/arm/mach-imx/cmd_bmode.c @@ -83,7 +83,11 @@ static int do_boot_mode(struct cmd_tbl *cmdtp, int flag, int argc, reset_requested = 0; } +/* No longer applicable to i.MX8M */ +#if IS_ENABLED(CONFIG_MX53) || IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7) boot_mode_apply(p->cfg_val); +#endif + if (reset_requested && p->cfg_val) do_reset(NULL, 0, 0, NULL); return 0; diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index ebc8021d7cc..c9455fe222a 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -276,8 +276,8 @@ unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash) #endif #ifdef CONFIG_SPL_MMC -unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, - unsigned long raw_sect) +unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect) { int end; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5de4d11a761..39802d6a796 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -28,8 +28,10 @@ #include <errno.h> #include <fdt_support.h> #include <fsl_wdog.h> +#include <fuse.h> #include <imx_sip.h> #include <linux/bitops.h> +#include <linux/bitfield.h> DECLARE_GLOBAL_DATA_PTR; @@ -648,19 +650,17 @@ struct rom_api *g_rom_api = (struct rom_api *)0x980; #if defined(CONFIG_IMX8M) #include <spl.h> -int spl_mmc_emmc_boot_partition(struct mmc *mmc) +int imx8m_detect_secondary_image_boot(void) { u32 *rom_log_addr = (u32 *)0x9e0; u32 *rom_log; u8 event_id; - int i, part; - - part = default_spl_mmc_emmc_boot_partition(mmc); + int i, boot_secondary = 0; /* If the ROM event log pointer is not valid. */ if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 || *rom_log_addr & 0x3) - return part; + return -EINVAL; /* Parse the ROM event ID version 2 log */ rom_log = (u32 *)(uintptr_t)(*rom_log_addr); @@ -668,7 +668,7 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc) event_id = rom_log[i] >> 24; switch (event_id) { case 0x00: /* End of list */ - return part; + return boot_secondary; /* Log entries with 1 parameter, skip 1 */ case 0x80: /* Start to perform the device initialization */ case 0x81: /* The boot device initialization completes */ @@ -686,26 +686,89 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc) continue; /* Boot from the secondary boot image */ case 0x51: - /* - * Swap the eMMC boot partitions in case there was a - * fallback event (i.e. primary image was corrupted - * and that corruption was recognized by the BootROM), - * so the SPL loads the rest of the U-Boot from the - * correct eMMC boot partition, since the BootROM - * leaves the boot partition set to the corrupted one. - */ - if (part == 1) - part = 2; - else if (part == 2) - part = 1; + boot_secondary = 1; continue; default: continue; } } + return boot_secondary; +} + +int spl_mmc_emmc_boot_partition(struct mmc *mmc) +{ + int part, ret; + + part = default_spl_mmc_emmc_boot_partition(mmc); + if (part == 0) + return part; + + ret = imx8m_detect_secondary_image_boot(); + if (ret < 0) { + printf("Could not get boot partition! Using %d\n", part); + return part; + } + + if (ret == 1) { + /* + * Swap the eMMC boot partitions in case there was a + * fallback event (i.e. primary image was corrupted + * and that corruption was recognized by the BootROM), + * so the SPL loads the rest of the U-Boot from the + * correct eMMC boot partition, since the BootROM + * leaves the boot partition set to the corrupted one. + */ + if (part == 1) + part = 2; + else if (part == 2) + part = 1; + } + return part; } + +int boot_mode_getprisec(void) +{ + return !!imx8m_detect_secondary_image_boot(); +} +#endif + +#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#define IMG_CNTN_SET1_OFFSET GENMASK(22, 19) +unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect) +{ + u32 val, offset; + + if (fuse_read(2, 1, &val)) { + debug("Error reading fuse!\n"); + return raw_sect; + } + + val = FIELD_GET(IMG_CNTN_SET1_OFFSET, val); + if (val > 10) { + debug("Secondary image boot disabled!\n"); + return raw_sect; + } + + if (val == 0) + offset = SZ_4M; + else if (val == 1) + offset = SZ_2M; + else if (val == 2) + offset = SZ_1M; + else /* flash.bin offset = 1 MiB * 2^n */ + offset = SZ_1M << val; + + offset /= 512; + offset -= CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET; + + if (imx8m_detect_secondary_image_boot()) + raw_sect += offset; + + return raw_sect; +} #endif bool is_usb_boot(void) diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index ccce6a78caa..d2e4205c5ce 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -54,7 +54,6 @@ config SYS_SOC config SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT bool "Force minimal current draw from VDD5V by MX28 PMU" - default n help After setting this option, the current drawn from VDD5V by the PMU is reduced to zero - the DCDC_BATT is used as @@ -62,7 +61,6 @@ config SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT config SPL_MXS_PMU_DISABLE_BATT_CHARGE bool "Disable Battery Charging in MX28 PMU" - default n config SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR bool "Enable the 4P2 linear regulator in MX28 PMU" diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index fd77b8bbba5..c7ca0fdce56 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla <lokeshvutla@ti.com> obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/ diff --git a/arch/arm/mach-k3/am654_init.c b/arch/arm/mach-k3/am654_init.c index 0d3889cde2b..9353a475a49 100644 --- a/arch/arm/mach-k3/am654_init.c +++ b/arch/arm/mach-k3/am654_init.c @@ -2,7 +2,7 @@ /* * AM6: SoC specific initialization * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/arch/arm/mach-k3/cache.S b/arch/arm/mach-k3/cache.S index a5717ea203a..17cfb12f108 100644 --- a/arch/arm/mach-k3/cache.S +++ b/arch/arm/mach-k3/cache.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * Andrew F. Davis <afd@ti.com> */ diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index c3006ba387e..d8974d6c388 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -2,7 +2,7 @@ /* * K3: Common Architecture initialization * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index eabb44f6204..04f3c0b85bd 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -2,7 +2,7 @@ /* * K3: Architecture common definitions * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index 029041f415c..9913964c46b 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -2,7 +2,7 @@ /* * K3: AM6 SoC definitions, structures etc. * - * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * (C) Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __ASM_ARCH_AM6_HARDWARE_H #define __ASM_ARCH_AM6_HARDWARE_H diff --git a/arch/arm/mach-k3/include/mach/am6_spl.h b/arch/arm/mach-k3/include/mach/am6_spl.h index 61e03809276..4c6950ff2b7 100644 --- a/arch/arm/mach-k3/include/mach/am6_spl.h +++ b/arch/arm/mach-k3/include/mach/am6_spl.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ #ifndef _ASM_ARCH_AM6_SPL_H_ diff --git a/arch/arm/mach-k3/include/mach/clock.h b/arch/arm/mach-k3/include/mach/clock.h index e3adbcd9ded..32368ce0ede 100644 --- a/arch/arm/mach-k3/include/mach/clock.h +++ b/arch/arm/mach-k3/include/mach/clock.h @@ -2,7 +2,7 @@ /* * K3: Common SoC clock definitions. * - * (C) Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * (C) Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 65742c4b7c8..a1a9dfbde66 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ #ifndef _ASM_ARCH_HARDWARE_H_ diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h index 376db389ba1..780341124a8 100644 --- a/arch/arm/mach-k3/include/mach/j721e_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -2,7 +2,7 @@ /* * K3: J721E SoC definitions, structures etc. * - * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __ASM_ARCH_J721E_HARDWARE_H #define __ASM_ARCH_J721E_HARDWARE_H diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h index e8947917a6b..ed3d7333bd4 100644 --- a/arch/arm/mach-k3/include/mach/j721e_spl.h +++ b/arch/arm/mach-k3/include/mach/j721e_spl.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ #ifndef _ASM_ARCH_J721E_SPL_H_ diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h index 7948bcf4789..ad4fcdd4a97 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_hardware.h +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -2,7 +2,7 @@ /* * K3: J721S2 SoC definitions, structures etc. * - * (C) Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * (C) Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __ASM_ARCH_J721S2_HARDWARE_H #define __ASM_ARCH_J721S2_HARDWARE_H diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h index 94b6c1337f7..d8fae2c8b45 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_spl.h +++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ * David Huang <d-huang@ti.com> */ #ifndef _ASM_ARCH_J721S2_SPL_H_ diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index 356cd892109..3ddc7eb6b63 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ #ifndef _ASM_ARCH_SPL_H_ diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile index ff9abd78ea6..0f91cf4daea 100644 --- a/arch/arm/mach-k3/j7200/Makefile +++ b/arch/arm/mach-k3/j7200/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile index ff9abd78ea6..0f91cf4daea 100644 --- a/arch/arm/mach-k3/j721e/Makefile +++ b/arch/arm/mach-k3/j721e/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index b1f7e25ed09..18814c39ec3 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -2,7 +2,7 @@ /* * J721E: SoC specific initialization * - * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/arch/arm/mach-k3/j721s2/Makefile b/arch/arm/mach-k3/j721s2/Makefile index 7bcd4901cd9..e794bffb3af 100644 --- a/arch/arm/mach-k3/j721s2/Makefile +++ b/arch/arm/mach-k3/j721s2/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ obj-y += clk-data.o obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c index a5be84b147c..7170a808c4b 100644 --- a/arch/arm/mach-k3/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2_init.c @@ -2,7 +2,7 @@ /* * J721E: SoC specific initialization * - * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ * David Huang <d-huang@ti.com> */ diff --git a/arch/arm/mach-k3/lowlevel_init.S b/arch/arm/mach-k3/lowlevel_init.S index 70c5d1cade4..463ab0de1bd 100644 --- a/arch/arm/mach-k3/lowlevel_init.S +++ b/arch/arm/mach-k3/lowlevel_init.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c index 2aec96277e6..605f7931518 100644 --- a/arch/arm/mach-k3/r5_mpu.c +++ b/arch/arm/mach-k3/r5_mpu.c @@ -2,7 +2,7 @@ /* * K3: R5 MPU region definitions * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c index 89659f479ee..ebc9704a33b 100644 --- a/arch/arm/mach-k3/security.c +++ b/arch/arm/mach-k3/security.c @@ -2,7 +2,7 @@ /* * K3: Security functions * - * Copyright (C) 2018-2022 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ * Andrew F. Davis <afd@ti.com> */ diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index ef245fef9c4..73a17276e12 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -2,7 +2,7 @@ /* * K3: System Firmware Loader * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Andreas Dannenberg <dannenberg@ti.com> */ diff --git a/arch/arm/mach-k3/sysfw-loader.h b/arch/arm/mach-k3/sysfw-loader.h index b23a9e821ed..e48c834227d 100644 --- a/arch/arm/mach-k3/sysfw-loader.h +++ b/arch/arm/mach-k3/sysfw-loader.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Andreas Dannenberg <dannenberg@ti.com> */ diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index b863bab1969..e91b0d68f4d 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -2,7 +2,7 @@ /* * K2x: Secure commands file * - * Copyright (C) 2012-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012-2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include <hang.h> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 5c7f4bf964a..c80d8587b14 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -144,8 +144,12 @@ config TARGET_TURRIS_OMNIA select ATSHA204A config TARGET_TURRIS_MOX - bool "Support Turris Mox" + bool "Support CZ.NIC's Turris Mox / RIPE Atlas Probe" select ARMADA_3700 + select BOARD_TYPES + select ENV_IS_IN_MMC + select ENV_IS_IN_SPI_FLASH + select MULTI_DTB_FIT config TARGET_MVEBU_ARMADA_8K bool "Support Armada 7k/8k platforms" diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 379daa88a4d..79f8877745b 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -71,8 +71,9 @@ #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR must be set to 0 #endif #if !defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET) || \ - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0 -#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET must be set to 0 + (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0 && \ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 4096) +#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET must be set to either 0 or 4096 #endif #endif @@ -123,8 +124,8 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { return IS_SD(mmc) ? MMCSD_MODE_RAW : MMCSD_MODE_EMMCBOOT; } -unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, - unsigned long raw_sect) +unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect) { return IS_SD(mmc) ? 1 : 0; } diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 2aa8013527e..3f1af7f1633 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ obj-$(CONFIG_AM33XX) += clock_am33xx.o obj-$(CONFIG_AM43XX) += clock_am43xx.o diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 06b41297730..09659da5867 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -4,7 +4,7 @@ * * Common board functions for AM33XX based boards * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c index 459bac13e05..d4f2abe17a9 100644 --- a/arch/arm/mach-omap2/am33xx/chilisom.c +++ b/arch/arm/mach-omap2/am33xx/chilisom.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * Copyright (C) 2017, Grinn - http://grinn-global.com/ */ diff --git a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c index c9b9502aef6..0969a404bf6 100644 --- a/arch/arm/mach-omap2/am33xx/clk_synthesizer.c +++ b/arch/arm/mach-omap2/am33xx/clk_synthesizer.c @@ -4,7 +4,7 @@ * * Clock synthesizer apis * - * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/ */ diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c index 130ee6c6e3e..3273632c648 100644 --- a/arch/arm/mach-omap2/am33xx/clock.c +++ b/arch/arm/mach-omap2/am33xx/clock.c @@ -5,7 +5,7 @@ * Clock initialization for AM33XX boards. * Derived from OMAP4 boards * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> #include <hang.h> diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index cd3b34bf56b..d39e7e4fed1 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -4,7 +4,7 @@ * * clocks for AM33XX based boards * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/arch/arm/mach-omap2/am33xx/clock_am43xx.c b/arch/arm/mach-omap2/am33xx/clock_am43xx.c index b98bb9989c0..8039bc2fe75 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am43xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am43xx.c @@ -5,7 +5,7 @@ * clocks for AM43XX based boards * Derived from AM33XX based boards * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 5f970d93f0a..61b95c93733 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -2,7 +2,7 @@ /* * DDR Configuration for AM33xx devices. * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index bf3da43ed98..b29250b8d20 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -4,7 +4,7 @@ * * AM33XX emif4 configuration file * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/arch/arm/mach-omap2/am33xx/mux.c b/arch/arm/mach-omap2/am33xx/mux.c index aad3ec85569..49605593979 100644 --- a/arch/arm/mach-omap2/am33xx/mux.c +++ b/arch/arm/mach-omap2/am33xx/mux.c @@ -1,7 +1,7 @@ /* * mux.c * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index 338f6afcae3..390d540e85a 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -4,7 +4,7 @@ * * System information functions * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * * Derived from Beagle Board and 3430 SDP code by * Richard Woodruff <r-woodruff2@ti.com> diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index a2dd5f6df01..a68b21aeacc 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -4,7 +4,7 @@ * * Common bootmode functions for omap based boards * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/arch/arm/mach-omap2/config.mk b/arch/arm/mach-omap2/config.mk index 4f0d2598fa8..30d8fb1b1d9 100644 --- a/arch/arm/mach-omap2/config.mk +++ b/arch/arm/mach-omap2/config.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ # # SPDX-License-Identifier: GPL-2.0+ diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index f76262bb0ce..40db1aec142 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ +# Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/ quiet_cmd_mkomapsecimg = SECURE $@ ifneq ($(TI_SECURE_DEV_PKG),) ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),) diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index 491e7c23dbc..7e5a2819220 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -6,7 +6,7 @@ * Based on mem.c and sdrc.c * * Copyright (C) 2010 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 07f534a60b2..5d43e7c9cf4 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -7,7 +7,7 @@ * generic init function (mem_init). * * Copyright (C) 2004-2010 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ * * Copyright (C) 2011 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index b7f79800de5..054782efbdb 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -1,7 +1,7 @@ /* * Voltage Controller implementation for OMAP * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * Nishanth Menon * * This program is free software; you can redistribute it and/or modify diff --git a/arch/arm/mach-rmobile/board.c b/arch/arm/mach-rmobile/board.c index a10371f74e0..79c7e02671f 100644 --- a/arch/arm/mach-rmobile/board.c +++ b/arch/arm/mach-rmobile/board.c @@ -3,7 +3,7 @@ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> * (C) Copyright 2012 Renesas Solutions Corp. */ -#include <common.h> + #include <init.h> #include <asm/io.h> diff --git a/arch/arm/mach-rmobile/cpu_info-r8a7740.c b/arch/arm/mach-rmobile/cpu_info-r8a7740.c index dcbe25f37ab..5a94235c4b9 100644 --- a/arch/arm/mach-rmobile/cpu_info-r8a7740.c +++ b/arch/arm/mach-rmobile/cpu_info-r8a7740.c @@ -3,7 +3,7 @@ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> * (C) Copyright 2012 Renesas Solutions Corp. */ -#include <common.h> + #include <asm/io.h> u32 rmobile_get_cpu_type(void) diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c index 8fc4cd7f9de..b9d8b5e57b5 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c @@ -4,7 +4,7 @@ * * Copyright (C) 2013,2014 Renesas Electronics Corporation */ -#include <common.h> + #include <asm/io.h> #define PRR_MASK 0x7fff diff --git a/arch/arm/mach-rmobile/cpu_info-rzg.c b/arch/arm/mach-rmobile/cpu_info-rzg.c index 1c18fd06f0b..4ade4bc0219 100644 --- a/arch/arm/mach-rmobile/cpu_info-rzg.c +++ b/arch/arm/mach-rmobile/cpu_info-rzg.c @@ -3,7 +3,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation * */ -#include <common.h> + #include <linux/libfdt.h> /* If the firmware passed a device tree, use it for soc identification. */ diff --git a/arch/arm/mach-rmobile/cpu_info-rzg2l.c b/arch/arm/mach-rmobile/cpu_info-rzg2l.c index de4892ee901..f69649dc7ea 100644 --- a/arch/arm/mach-rmobile/cpu_info-rzg2l.c +++ b/arch/arm/mach-rmobile/cpu_info-rzg2l.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <asm/io.h> #include <linux/libfdt.h> diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 6804b1da2cd..895c0f5336b 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -3,7 +3,7 @@ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> * (C) Copyright 2012-2021 Renesas Solutions Corp. */ -#include <common.h> + #include <cpu_func.h> #include <asm/cache.h> #include <init.h> diff --git a/arch/arm/mach-rmobile/emac.c b/arch/arm/mach-rmobile/emac.c index cb9bce0cf23..95651626da4 100644 --- a/arch/arm/mach-rmobile/emac.c +++ b/arch/arm/mach-rmobile/emac.c @@ -6,7 +6,6 @@ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> */ -#include <common.h> #include <net.h> #include <linux/errno.h> #include <netdev.h> diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c index a68eb806b35..4dff9e07629 100644 --- a/arch/arm/mach-rmobile/memmap-gen3.c +++ b/arch/arm/mach-rmobile/memmap-gen3.c @@ -5,10 +5,10 @@ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> */ -#include <common.h> -#include <cpu_func.h> #include <asm/armv8/mmu.h> #include <asm/global_data.h> +#include <asm/u-boot.h> +#include <cpu_func.h> #define GEN3_NR_REGIONS 16 diff --git a/arch/arm/mach-rmobile/memmap-rzg2l.c b/arch/arm/mach-rmobile/memmap-rzg2l.c index a08d0ea08fc..9934a775220 100644 --- a/arch/arm/mach-rmobile/memmap-rzg2l.c +++ b/arch/arm/mach-rmobile/memmap-rzg2l.c @@ -6,9 +6,9 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ -#include <common.h> #include <asm/armv8/mmu.h> #include <asm/global_data.h> +#include <asm/u-boot.h> #include <cpu_func.h> #define RZG2L_NR_REGIONS 16 diff --git a/arch/arm/mach-rmobile/pfc-r8a7740.c b/arch/arm/mach-rmobile/pfc-r8a7740.c index 5d42a68266b..4f4847699b0 100644 --- a/arch/arm/mach-rmobile/pfc-r8a7740.c +++ b/arch/arm/mach-rmobile/pfc-r8a7740.c @@ -18,7 +18,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <common.h> + #include <sh_pfc.h> #include <asm/gpio.h> #include <asm/arch/irqs.h> diff --git a/arch/arm/mach-rmobile/psci-r8a779a0.c b/arch/arm/mach-rmobile/psci-r8a779a0.c index 6a85eb22cac..b6c49e731f9 100644 --- a/arch/arm/mach-rmobile/psci-r8a779a0.c +++ b/arch/arm/mach-rmobile/psci-r8a779a0.c @@ -6,7 +6,6 @@ * */ -#include <common.h> #include <asm/io.h> #include <asm/psci.h> #include <asm/secure.h> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c43c185c17c..b577a911e78 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -359,6 +359,8 @@ config ROCKCHIP_RV1126 select BOARD_LATE_INIT imply ROCKCHIP_COMMON_BOARD imply OF_LIBFDT_OVERLAY + imply ROCKCHIP_OTP + imply MISC_INIT_R imply TPL_DM imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT @@ -401,7 +403,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" default y - select ROCKCHIP_BROM_HELPER + select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066 select TPL_BOOTROM_SUPPORT depends on TPL help @@ -450,7 +452,6 @@ config ROCKCHIP_BOOT_MODE_REG config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on PMIC_RK8XX - default n ---help--- Say Y here to prevent the device from booting up because of a plug-in event. When set, the device will boot briefly to determine why it was diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig index 95d7fc8a291..4a79a829ade 100644 --- a/arch/arm/mach-rockchip/rk3066/Kconfig +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -10,6 +10,14 @@ config TARGET_MK808 config ROCKCHIP_BOOT_MODE_REG default 0x20004040 +config ROCKCHIP_BOOT_LR_REG + hex + default 0x00001058 + +config ROCKCHIP_BOOT_RETURN_REG + hex + default 0x00001100 + config SYS_SOC default "rk3066" diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 79fcc99b898..e5282dd1125 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -6,6 +6,51 @@ config TARGET_EVB_RK3588 help RK3588 EVB is a evaluation board for Rockchp RK3588. +config TARGET_NANOPCT6_RK3588 + bool "FriendlyElec NanoPC-T6 RK3588 board" + select BOARD_LATE_INIT + help + The NanoPC-T6 is a Rockchip RK3588 based SBC by FriendlyElec. + + There are four variants depending on the DRAM size: 4G/32GB eMMC, + 8G/64GB eMMC, 16G/16MB SPI NOR, and 16G/256GB eMMC/16MB SPI NOR + + Specifications: + + CPU: Rockchip RK3588, 4x Cortex-A76 (up to 2.4GHz) + + 4x Cortex-A55 (up to 1.8GHz) + GPU: Mali-G610 MP4 + VPU: 8K@60fps H.265 and VP9 decoder, 8K@30fps H.264 decoder, + 4K@60fps AV1 decoder, 8K@30fps H.264 and H.265 encoder + NPU: 6TOPs, supports INT4/INT8/INT16/FP16 + RAM: 64-bit 4GB/8GB/16GB LPDDR4X at 2133MHz + eMMC: 0GB/32GB/64GB/256GB HS400 + MicroSD Slot: MicroSD SDR104 + PCIe 3.0: M.2 M-Key x1, PCIe 3.0 x4 for NVMe SSDs up to 2,500 MB/s + Ethernet: PCIe 2.5G 2x Ethernet (RTL8125BG) + PCIe 2.1: M.2 E-Key x1, PCIe 2.1 x1 and USB2.0 Host, + supports M.2 WiFi and Bluetooth + 4G Module: MiniPCIe x1, MicroSIM Card Slot x1 + Audio Out: 3.5mm jack for stereo headphone output + Audio In: 2.0mm PH-2A connector for analog microphone input + Video Input: standard HDMI input port, up to 4Kp60 + 2x 4-lane MIPI-CSI, compatible with MIPI V1.2 + Video Output: 2x standard HDMI output ports compatible with HDMI2.1, + HDMI2.0, and HDMI1.4 + 2x 4-lane MIPI-DSI, compatible with MIPI DPHY 2.0 or CPHY 1.1 + USB-A: USB 3.0, Type A + USB-C: Full function USB Type‑C port, DP display up to 4Kp60, USB 3.0 + 40-pin 2.54mm header connector: up to 2x SPIs, 6x UARTs, 1x I2Cs, + 8x PWMs, 2x I2Ss, 28x GPIOs + Debug UART: 3 Pin 2.54mm header, 3V level, 1500000bps + Onboard IR receiver: 38KHz carrier frequency + RTC Battery: 2 Pin 1.27/1.25mm RTC battery connector for low power + RTC IC HYM8563TS + 5V Fan connector + Working Temperature: 0C to 70C + Power: 5.5*2.1mm DC Jack, 12VDC input + Dimensions: 110x80x1.6mm (without case) / 86x114.5x30mm (with case) + config TARGET_RK3588_NEU6 bool "Edgeble Neural Compute Module 6(Neu6) SoM" select BOARD_LATE_INIT @@ -80,6 +125,13 @@ config TARGET_ROCK5B_RK3588 USB PD over USB Type-C Size: 100mm x 72mm (Pico-ITX form factor) +config TARGET_QUARTZPRO64_RK3588 + bool "Pine64 QuartzPro64 RK3588 board" + select BOARD_LATE_INIT + help + Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board + Computer) by Pine64. + config ROCKCHIP_BOOT_MODE_REG default 0xfd588080 @@ -93,6 +145,8 @@ config SYS_MALLOC_F_LEN default 0x80000 source board/edgeble/neural-compute-module-6/Kconfig +source board/friendlyelec/nanopc-t6-rk3588/Kconfig +source board/pine64/quartzpro64-rk3588/Kconfig source board/rockchip/evb_rk3588/Kconfig source board/radxa/rock5a-rk3588s/Kconfig source board/radxa/rock5b-rk3588/Kconfig diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 0e073045be5..2fc1521e2d3 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -14,7 +14,6 @@ config SPL_SYS_MALLOC_F_LEN config SDM845 bool "Qualcomm Snapdragon 845 SoC" - default n select LINUX_KERNEL_IMAGE_HEADER config LNX_KRNL_IMG_TEXT_OFFSET_BASE diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index e07abbe21c1..55574fd4beb 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -40,6 +40,13 @@ u32 get_bootmode(void) TAMP_BOOT_MODE_SHIFT; } +u32 get_bootauth(void) +{ + /* read boot auth status and partition from TAMP backup register */ + return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_AUTH_MASK) >> + TAMP_BOOT_AUTH_SHIFT; +} + /* * weak function overidde: set the DDR/SYSRAM executable before to enable the * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc) @@ -91,10 +98,10 @@ static void early_enable_caches(void) if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) return; - if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) gd->arch.tlb_size = PGTABLE_SIZE; gd->arch.tlb_addr = (unsigned long)&early_tlb; - } +#endif /* enable MMU (default configuration) */ dcache_enable(); @@ -371,8 +378,24 @@ __weak void stm32mp_misc_init(void) { } +static int setup_boot_auth_info(void) +{ + char buf[10]; + u32 bootauth = get_bootauth(); + + snprintf(buf, sizeof(buf), "%d", bootauth >> 4); + env_set("boot_auth", buf); + + snprintf(buf, sizeof(buf), "%d", bootauth & + (u32)TAMP_BOOT_PARTITION_MASK); + env_set("boot_part", buf); + + return 0; +} + int arch_misc_init(void) { + setup_boot_auth_info(); setup_boot_mode(); setup_mac_address(); setup_serial_number(); diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 1cdc5e3b186..ac0deced67e 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -139,8 +139,12 @@ enum boot_device { #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) #define TAMP_BOOT_MODE_SHIFT 8 +#define TAMP_BOOT_AUTH_MASK GENMASK(23, 16) +#define TAMP_BOOT_AUTH_SHIFT 16 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) +#define TAMP_BOOT_AUTH_ST_MASK GENMASK(7, 4) +#define TAMP_BOOT_PARTITION_MASK GENMASK(3, 0) #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) enum forced_boot_mode { diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 83fb32a45fc..52aca1e23e1 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -66,6 +66,9 @@ void get_soc_name(char name[SOC_NAME_SIZE]); /* return boot mode */ u32 get_bootmode(void); +/* return auth status and partition */ +u32 get_bootauth(void); + int get_eth_nb(void); int setup_mac_address(void); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 40ca7d7b3a9..a10e4c06b6a 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -811,7 +811,6 @@ config AXP_GPIO config AXP_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER - default n ---help--- Say Y here to prevent the device from booting up because of a plug-in event. When set, the device will boot into the SPL briefly to diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index c2fadf75367..11a49418225 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -338,8 +338,8 @@ uint32_t sunxi_get_spl_size(void) * Also U-Boot proper is located at least 32KB after the SPL, but will * immediately follow the SPL if that is bigger than that. */ -unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, - unsigned long raw_sect) +unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect) { unsigned long spl_size = sunxi_get_spl_size(); unsigned long sector; diff --git a/arch/arm/mach-sunxi/dram_sun8i_a23.c b/arch/arm/mach-sunxi/dram_sun8i_a23.c index 3ed97b59a32..056cb03efb1 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a23.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a23.c @@ -14,7 +14,7 @@ * * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one * found in the TI Keystone2 documentation: - * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf + * https://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf * "Table4-2 DDR3 PHY Registers" * This may be used as a (possible) reference for future work / cleanups. */ diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 464bd0798f6..f2737781287 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -18,7 +18,6 @@ config TEGRA_CLKRST config TEGRA_CRYPTO bool "Tegra AES128 crypto module" select AES - default n config TEGRA_GP_PADCTRL bool @@ -61,6 +60,9 @@ config TEGRA_COMMON select MISC select OF_CONTROL select SPI + select SYSRESET + select SPL_SYSRESET if SPL + select SYSRESET_TEGRA imply CMD_DM imply CRC32_VERIFY diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 981768bb0e1..cd405874d36 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -26,6 +26,10 @@ #include <asm/arch-tegra/gpu.h> #include <asm/arch-tegra/usb.h> #include <asm/arch-tegra/xusb-padctl.h> +#ifndef CONFIG_TEGRA186 +#include <asm/arch-tegra/fuse.h> +#include <asm/arch/gp_padctrl.h> +#endif #if IS_ENABLED(CONFIG_TEGRA_CLKRST) #include <asm/arch/clock.h> #endif @@ -256,6 +260,37 @@ int board_early_init_f(void) } #endif /* EARLY_INIT */ +#ifndef CONFIG_TEGRA186 +static void nvidia_board_late_init_generic(void) +{ + char serialno_str[17]; + + /* Set chip id as serialno */ + sprintf(serialno_str, "%016llx", tegra_chip_uid()); + env_set("serial#", serialno_str); + + switch (tegra_get_chip()) { + case CHIPID_TEGRA20: + env_set("platform", "tegra20"); + break; + case CHIPID_TEGRA30: + env_set("platform", "tegra30"); + break; + case CHIPID_TEGRA114: + env_set("platform", "tegra114"); + break; + case CHIPID_TEGRA124: + env_set("platform", "tegra124"); + break; + case CHIPID_TEGRA210: + env_set("platform", "tegra210"); + break; + default: + return; + } +} +#endif + int board_late_init(void) { #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) @@ -268,6 +303,14 @@ int board_late_init(void) #endif start_cpu_fan(); cboot_late_init(); + + /* + * Perform generic env setup in case + * vendor does not provide it. + */ +#ifndef CONFIG_TEGRA186 + nvidia_board_late_init_generic(); +#endif nvidia_board_late_init(); return 0; diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index 8d617bee63c..c4f5106750b 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -84,12 +84,3 @@ void tegra_pmc_writel(u32 value, unsigned long offset) writel(value, NV_PA_PMC_BASE + offset); } - -void reset_cpu(void) -{ - u32 value; - - value = tegra_pmc_readl(PMC_CNTRL); - value |= PMC_CNTRL_MAIN_RST; - tegra_pmc_writel(value, PMC_CNTRL); -} diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c index 62c10536306..7d8f080c310 100644 --- a/arch/arm/mach-tegra/tegra114/cpu.c +++ b/arch/arm/mach-tegra/tegra114/cpu.c @@ -13,9 +13,13 @@ #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> +#include <asm/arch-tegra/tegra_i2c.h> #include <linux/delay.h> #include "../cpu.h" +/* In case this function is not defined */ +__weak void pmic_enable_cpu_vdd(void) {} + /* Tegra114-specific CPU init code */ static void enable_cpu_power_rail(void) { @@ -254,6 +258,7 @@ void start_cpu(u32 reset_vector) /* Enable VDD_CPU */ enable_cpu_power_rail(); + pmic_enable_cpu_vdd(); /* Get the CPU(s) running */ enable_cpu_clocks(); diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c index 5eb48990b6c..b2c44f3d237 100644 --- a/arch/arm/mach-tegra/tegra20/bct.c +++ b/arch/arm/mach-tegra/tegra20/bct.c @@ -11,6 +11,9 @@ #include "bct.h" #include "uboot_aes.h" +/* Device with "sbk burned: false" will expose zero key */ +const u8 nosbk[AES128_KEY_LENGTH] = { 0 }; + /* * @param bct boot config table start in RAM * @param ect bootloader start in RAM @@ -23,22 +26,27 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) u8 ebt_hash[AES128_KEY_LENGTH] = { 0 }; u8 sbk[AES128_KEY_LENGTH] = { 0 }; u8 *bct_hash = bct; + bool encrypted; int ret; bct += BCT_HASH; + ebt_size = roundup(ebt_size, EBT_ALIGNMENT); + memcpy(sbk, (u8 *)(bct + BCT_LENGTH), NVBOOT_CMAC_AES_HASH_LENGTH * 4); - ret = decrypt_data_block(bct, BCT_LENGTH, sbk); - if (ret) - return 1; + encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH); - ebt_size = roundup(ebt_size, EBT_ALIGNMENT); + if (encrypted) { + ret = decrypt_data_block(bct, BCT_LENGTH, sbk); + if (ret) + return 1; - ret = encrypt_data_block(ebt, ebt_size, sbk); - if (ret) - return 1; + ret = encrypt_data_block(ebt, ebt_size, sbk); + if (ret) + return 1; + } ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk); if (ret) @@ -52,9 +60,11 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) bct_tbl->bootloader[0].load_addr = CONFIG_SPL_TEXT_BASE; bct_tbl->bootloader[0].length = ebt_size; - ret = encrypt_data_block(bct, BCT_LENGTH, sbk); - if (ret) - return 1; + if (encrypted) { + ret = encrypt_data_block(bct, BCT_LENGTH, sbk); + if (ret) + return 1; + } ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk); if (ret) diff --git a/arch/arm/mach-tegra/tegra30/bct.c b/arch/arm/mach-tegra/tegra30/bct.c index c56958da691..cff1a3e98d2 100644 --- a/arch/arm/mach-tegra/tegra30/bct.c +++ b/arch/arm/mach-tegra/tegra30/bct.c @@ -11,6 +11,9 @@ #include "bct.h" #include "uboot_aes.h" +/* Device with "sbk burned: false" will expose zero key */ +const u8 nosbk[AES128_KEY_LENGTH] = { 0 }; + /* * @param bct boot config table start in RAM * @param ect bootloader start in RAM @@ -23,22 +26,27 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) u8 ebt_hash[AES128_KEY_LENGTH] = { 0 }; u8 sbk[AES128_KEY_LENGTH] = { 0 }; u8 *bct_hash = bct; + bool encrypted; int ret; bct += BCT_HASH; + ebt_size = roundup(ebt_size, EBT_ALIGNMENT); + memcpy(sbk, (u8 *)(bct + BCT_LENGTH), NVBOOT_CMAC_AES_HASH_LENGTH * 4); - ret = decrypt_data_block(bct, BCT_LENGTH, sbk); - if (ret) - return 1; + encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH); - ebt_size = roundup(ebt_size, EBT_ALIGNMENT); + if (encrypted) { + ret = decrypt_data_block(bct, BCT_LENGTH, sbk); + if (ret) + return 1; - ret = encrypt_data_block(ebt, ebt_size, sbk); - if (ret) - return 1; + ret = encrypt_data_block(ebt, ebt_size, sbk); + if (ret) + return 1; + } ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk); if (ret) @@ -52,9 +60,11 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) bct_tbl->bootloader[0].load_addr = CONFIG_SPL_TEXT_BASE; bct_tbl->bootloader[0].length = ebt_size; - ret = encrypt_data_block(bct, BCT_LENGTH, sbk); - if (ret) - return 1; + if (encrypted) { + ret = encrypt_data_block(bct, BCT_LENGTH, sbk); + if (ret) + return 1; + } ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk); if (ret) diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 26b80b7882c..7e7c87d16fa 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -100,30 +100,30 @@ config SPL_ZYNQMP_DRAM_ECC_INIT config SPL_ZYNQMP_DRAM_BANK1_BASE depends on SPL_ZYNQMP_DRAM_ECC_INIT hex "DRAM Bank1 address" - default 0x00000000 - help - Start address of DRAM ECC bank1 + default 0x00000000 + help + Start address of DRAM ECC bank1 config SPL_ZYNQMP_DRAM_BANK1_LEN depends on SPL_ZYNQMP_DRAM_ECC_INIT hex "DRAM Bank1 size" - default 0x80000000 - help - Size in bytes of the DRAM ECC bank1 + default 0x80000000 + help + Size in bytes of the DRAM ECC bank1 config SPL_ZYNQMP_DRAM_BANK2_BASE depends on SPL_ZYNQMP_DRAM_ECC_INIT hex "DRAM Bank2 address" - default 0x800000000 - help - Start address of DRAM ECC bank2 + default 0x800000000 + help + Start address of DRAM ECC bank2 config SPL_ZYNQMP_DRAM_BANK2_LEN depends on SPL_ZYNQMP_DRAM_ECC_INIT hex "DRAM Bank2 size" - default 0x0 - help - Size in bytes of the DRAM ECC bank2. A null size takes no action. + default 0x0 + help + Size in bytes of the DRAM ECC bank2. A null size takes no action. config SYS_MALLOC_F_LEN default 0x600 diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 587edd50d7e..b288c65e7fd 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -200,7 +200,6 @@ source "board/sysam/stmark2/Kconfig" config M68K_QEMU bool "Build with workarounds for incomplete QEMU emulation" - default n help QEMU 8.x currently does not implement RAMBAR accesses and DMA timers. Enable this option for U-Boot CI purposes only diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index bef67767b42..c843a381ea1 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -8,7 +8,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <init.h> #include <net.h> #include <vsprintf.h> diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 10be73822fa..a05cbdcb385 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -8,7 +8,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <watchdog.h> diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c index 09c7f9e67cc..46c9207a93b 100644 --- a/arch/m68k/cpu/mcf523x/interrupts.c +++ b/arch/m68k/cpu/mcf523x/interrupts.c @@ -6,7 +6,6 @@ */ /* CPU specific interrupt routine */ -#include <common.h> #include <irq_func.h> #include <asm/immap.h> #include <asm/io.h> diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c index 6b08a12af0b..2eb43cc7eb9 100644 --- a/arch/m68k/cpu/mcf523x/speed.c +++ b/arch/m68k/cpu/mcf523x/speed.c @@ -8,7 +8,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <clock_legacy.h> #include <asm/global_data.h> #include <asm/processor.h> diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index 5042a38b3e9..6bfde5e9bd7 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -13,7 +13,6 @@ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. */ -#include <common.h> #include <init.h> #include <net.h> #include <vsprintf.h> diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index 99eb61f1675..4506eb39edf 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -17,7 +17,7 @@ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <init.h> #include <watchdog.h> @@ -25,7 +25,6 @@ #include <asm/io.h> #if defined(CONFIG_CMD_NET) -#include <config.h> #include <net.h> #include <asm/fec.h> #endif diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c index c5ed0600736..264bdc7d6c7 100644 --- a/arch/m68k/cpu/mcf52x2/interrupts.c +++ b/arch/m68k/cpu/mcf52x2/interrupts.c @@ -7,7 +7,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <irq_func.h> #include <watchdog.h> #include <asm/processor.h> diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c index 6c7628252b5..538e4c623d4 100644 --- a/arch/m68k/cpu/mcf52x2/speed.c +++ b/arch/m68k/cpu/mcf52x2/speed.c @@ -7,7 +7,6 @@ * Hayden Fraser (Hayden.Fraser@freescale.com) */ -#include <common.h> #include <clock_legacy.h> #include <asm/global_data.h> #include <asm/processor.h> diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c index 53a25d8362c..92a0ef76895 100644 --- a/arch/m68k/cpu/mcf530x/cpu.c +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <command.h> #include <init.h> #include <vsprintf.h> diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c index dad47d87ab3..8f6e668d103 100644 --- a/arch/m68k/cpu/mcf530x/cpu_init.c +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <watchdog.h> diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c index 11686202dc7..99cf8638503 100644 --- a/arch/m68k/cpu/mcf530x/interrupts.c +++ b/arch/m68k/cpu/mcf530x/interrupts.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <irq_func.h> #include <asm/immap.h> #include <asm/io.h> diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c index c8d079016f2..6542fc43ab1 100644 --- a/arch/m68k/cpu/mcf530x/speed.c +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <clock_legacy.h> #include <asm/global_data.h> #include <asm/processor.h> diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 18d20a89265..6973af9d045 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -8,7 +8,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <init.h> #include <net.h> #include <vsprintf.h> diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index 844d2cd7600..62a45f96314 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -8,7 +8,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <watchdog.h> diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c index 4f72fa88e58..e37893c3e53 100644 --- a/arch/m68k/cpu/mcf532x/interrupts.c +++ b/arch/m68k/cpu/mcf532x/interrupts.c @@ -6,7 +6,6 @@ */ /* CPU specific interrupt routine */ -#include <common.h> #include <irq_func.h> #include <asm/immap.h> #include <asm/io.h> diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index 32ffac08135..166916526eb 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -8,7 +8,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <clock_legacy.h> #include <asm/global_data.h> #include <asm/processor.h> diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c index d9a71c6b920..b811ac355e4 100644 --- a/arch/m68k/cpu/mcf5445x/cpu.c +++ b/arch/m68k/cpu/mcf5445x/cpu.c @@ -8,7 +8,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <init.h> #include <net.h> #include <vsprintf.h> diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index bc3a2f3aed6..3277617120c 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -8,7 +8,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <watchdog.h> diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c index 456af171a4e..13eb6ecee10 100644 --- a/arch/m68k/cpu/mcf5445x/dspi.c +++ b/arch/m68k/cpu/mcf5445x/dspi.c @@ -6,7 +6,6 @@ * CPU specific dspi routines */ -#include <common.h> #include <asm/immap.h> #include <asm/io.h> diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c index 400f3dee879..913290086dc 100644 --- a/arch/m68k/cpu/mcf5445x/interrupts.c +++ b/arch/m68k/cpu/mcf5445x/interrupts.c @@ -9,7 +9,6 @@ */ /* CPU specific interrupt routine */ -#include <common.h> #include <irq_func.h> #include <asm/immap.h> #include <asm/io.h> diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 5c78eb98349..41cb9e999ad 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -5,7 +5,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <clock_legacy.h> #include <asm/global_data.h> #include <asm/processor.h> diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 5c3bfff7918..f0264671d38 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -7,7 +7,6 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> #include <asm-offsets.h> #include <config.h> #include <asm/cache.h> diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index aafa4f40cb3..411b00899c2 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -9,6 +9,7 @@ #ifndef __IMMAP_H #define __IMMAP_H +#include <config.h> #if defined(CONFIG_MCF520x) #include <asm/immap_520x.h> #include <asm/m520x.h> diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h index 7c7443b9688..d3c2f4a4091 100644 --- a/arch/m68k/include/asm/immap_520x.h +++ b/arch/m68k/include/asm/immap_520x.h @@ -36,6 +36,7 @@ #define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000) #define MMAP_SDRAM (CFG_SYS_MBAR + 0x000A8000) +#include <linux/types.h> #include <asm/coldfire/crossbar.h> #include <asm/coldfire/edma.h> #include <asm/coldfire/eport.h> diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h index a1825c2a944..d9b0be1d7d4 100644 --- a/arch/m68k/include/asm/immap_5235.h +++ b/arch/m68k/include/asm/immap_5235.h @@ -46,6 +46,7 @@ #define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000) #define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000) +#include <linux/types.h> #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> #include <asm/coldfire/flexcan.h> diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h index c5c3cc75125..5378ed1aac1 100644 --- a/arch/m68k/include/asm/immap_5272.h +++ b/arch/m68k/include/asm/immap_5272.h @@ -27,6 +27,7 @@ #define MMAP_FEC (CFG_SYS_MBAR + 0x00000840) #define MMAP_USB (CFG_SYS_MBAR + 0x00001000) +#include <linux/types.h> #include <asm/coldfire/pwm.h> /* System configuration registers */ diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h index 9b8d71d30d4..c4cce3f94f1 100644 --- a/arch/m68k/include/asm/immap_5275.h +++ b/arch/m68k/include/asm/immap_5275.h @@ -49,6 +49,7 @@ #define MMAP_USB (CFG_SYS_MBAR + 0x001C0000) #define MMAP_PWM0 (CFG_SYS_MBAR + 0x001D0000) +#include <linux/types.h> #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> #include <asm/coldfire/intctrl.h> diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h index f810a4dd5cb..e5f400e6ae3 100644 --- a/arch/m68k/include/asm/immap_5282.h +++ b/arch/m68k/include/asm/immap_5282.h @@ -45,6 +45,7 @@ #define MMAP_CFMC (CFG_SYS_MBAR + 0x001D0000) #define MMAP_CFMMEM (CFG_SYS_MBAR + 0x04000000) +#include <linux/types.h> #include <asm/coldfire/eport.h> #include <asm/coldfire/flexbus.h> #include <asm/coldfire/flexcan.h> diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h index e1f7858b100..3ade4f04756 100644 --- a/arch/m68k/include/asm/immap_5301x.h +++ b/arch/m68k/include/asm/immap_5301x.h @@ -50,6 +50,7 @@ #define MMAP_IIM (CFG_SYS_MBAR + 0x000C8000) #define MMAP_ESDHC (CFG_SYS_MBAR + 0x000CC000) +#include <linux/types.h> #include <asm/coldfire/crossbar.h> #include <asm/coldfire/dspi.h> #include <asm/coldfire/edma.h> diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h index d6442d95b4b..d96dd146efb 100644 --- a/arch/m68k/include/asm/immap_5307.h +++ b/arch/m68k/include/asm/immap_5307.h @@ -17,6 +17,8 @@ #define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) #define MMAP_GPIO (CFG_SYS_MBAR + 0x00000244) +#include <linux/types.h> + typedef struct sim { u8 rsr; u8 sypcr; diff --git a/arch/m68k/include/asm/immap_5329.h b/arch/m68k/include/asm/immap_5329.h index dbf3a2260ee..6f1795a207a 100644 --- a/arch/m68k/include/asm/immap_5329.h +++ b/arch/m68k/include/asm/immap_5329.h @@ -51,6 +51,7 @@ #define MMAP_SSI 0xFC0BC000 #define MMAP_PLL 0xFC0C0000 +#include <linux/types.h> #include <asm/coldfire/crossbar.h> #include <asm/coldfire/edma.h> #include <asm/coldfire/eport.h> diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h index 708d0db755a..c8f3effe240 100644 --- a/arch/m68k/include/asm/immap_5441x.h +++ b/arch/m68k/include/asm/immap_5441x.h @@ -76,6 +76,7 @@ #define MMAP_CCM 0xEC090000 #define MMAP_GPIO 0xEC094000 +#include <linux/types.h> #include <asm/coldfire/crossbar.h> #include <asm/coldfire/dspi.h> #include <asm/coldfire/edma.h> diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index 0b4629f1c8a..3719f11c03c 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -6,8 +6,9 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> +#include <config.h> #include <init.h> +#include <asm/u-boot.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index f18bed235d4..79d8b34c0d5 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <bootstage.h> #include <command.h> #include <env.h> diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index 57e5632fdb5..de04124404c 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -4,7 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <asm/immap.h> #include <asm/cache.h> diff --git a/arch/m68k/lib/fec.c b/arch/m68k/lib/fec.c index eecea7a0235..d6f238e4b34 100644 --- a/arch/m68k/lib/fec.c +++ b/arch/m68k/lib/fec.c @@ -3,8 +3,8 @@ * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com> */ -#include <common.h> #include <asm/global_data.h> +#include <linux/errno.h> #include <linux/libfdt.h> #include <fdt_support.h> diff --git a/arch/m68k/lib/interrupts.c b/arch/m68k/lib/interrupts.c index 799daab5612..175ec689533 100644 --- a/arch/m68k/lib/interrupts.c +++ b/arch/m68k/lib/interrupts.c @@ -7,7 +7,7 @@ * TsiChung Liew (Tsi-Chung.Liew@freescale.com) */ -#include <common.h> +#include <stdio.h> #include <irq_func.h> #include <watchdog.h> #include <asm/processor.h> diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c index 61db1e6c500..4249488c01d 100644 --- a/arch/m68k/lib/time.c +++ b/arch/m68k/lib/time.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <init.h> #include <irq_func.h> #include <time.h> diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c index 28fe803928e..c283351181d 100644 --- a/arch/m68k/lib/traps.c +++ b/arch/m68k/lib/traps.c @@ -7,7 +7,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <init.h> #include <watchdog.h> #include <command.h> diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index 829e6c7ae60..75ec0a8fd24 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -5,7 +5,6 @@ * Michal SIMEK <monstr@monstr.eu> */ -#include <common.h> #include <cpu_func.h> #include <asm/asm.h> #include <asm/cache.h> diff --git a/arch/microblaze/cpu/cpuinfo.c b/arch/microblaze/cpu/cpuinfo.c index 6b15d6ca41c..2bfdf767f3a 100644 --- a/arch/microblaze/cpu/cpuinfo.c +++ b/arch/microblaze/cpu/cpuinfo.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com> */ -#include <common.h> #include <asm/cpuinfo.h> #include <asm/global_data.h> diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c index 9414776afa7..6b329fc7b3a 100644 --- a/arch/microblaze/cpu/exception.c +++ b/arch/microblaze/cpu/exception.c @@ -5,8 +5,8 @@ * Michal SIMEK <monstr@monstr.eu> */ -#include <common.h> #include <hang.h> +#include <stdio.h> #include <asm/asm.h> void _hw_exception_handler (void) diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c index ac53208bda6..244f7fd15eb 100644 --- a/arch/microblaze/cpu/interrupts.c +++ b/arch/microblaze/cpu/interrupts.c @@ -7,7 +7,8 @@ * Yasushi SHOJI <yashi@atmark-techno.com> */ -#include <common.h> +#include <log.h> +#include <vsprintf.h> #include <asm/asm.h> void enable_interrupts(void) diff --git a/arch/microblaze/cpu/pvr.c b/arch/microblaze/cpu/pvr.c index 23c0f912d43..71aea0b9380 100644 --- a/arch/microblaze/cpu/pvr.c +++ b/arch/microblaze/cpu/pvr.c @@ -2,7 +2,6 @@ /* * Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com> */ -#include <common.h> #include <asm/asm.h> #include <asm/pvr.h> diff --git a/arch/microblaze/cpu/relocate.c b/arch/microblaze/cpu/relocate.c index 7a15fb2ec39..e46fe5bdd5d 100644 --- a/arch/microblaze/cpu/relocate.c +++ b/arch/microblaze/cpu/relocate.c @@ -4,8 +4,9 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <elf.h> +#include <log.h> +#include <linux/types.h> #define R_MICROBLAZE_NONE 0 #define R_MICROBLAZE_32 1 diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index c21beafdb81..cb224bd2542 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -5,7 +5,6 @@ * Michal Simek <michal.simek@amd.com> */ -#include <common.h> #include <command.h> #include <image.h> #include <log.h> diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h index 3c58e52217c..fbd9418a2f8 100644 --- a/arch/microblaze/include/asm/cpuinfo.h +++ b/arch/microblaze/include/asm/cpuinfo.h @@ -6,6 +6,8 @@ #ifndef __ASM_MICROBLAZE_CPUINFO_H #define __ASM_MICROBLAZE_CPUINFO_H +#include <linux/types.h> + /** * struct microblaze_cpuinfo - CPU info for microblaze processor core. * diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 930384f4015..f3ec4b741b8 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -7,7 +7,6 @@ * Yasushi SHOJI <yashi@atmark-techno.com> */ -#include <common.h> #include <bootstage.h> #include <command.h> #include <cpu_func.h> diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c index f0e20da28f7..acfc9dc43f1 100644 --- a/arch/mips/cpu/cpu.c +++ b/arch/mips/cpu/cpu.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> */ -#include <common.h> #include <command.h> #include <init.h> #include <linux/compiler.h> diff --git a/arch/mips/cpu/interrupts.c b/arch/mips/cpu/interrupts.c index b3ba9aaeae1..f7f9a185ed4 100644 --- a/arch/mips/cpu/interrupts.c +++ b/arch/mips/cpu/interrupts.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> */ -#include <common.h> #include <irq_func.h> int interrupt_init(void) diff --git a/arch/mips/cpu/time.c b/arch/mips/cpu/time.c index 5e7a7144d02..210709d3b81 100644 --- a/arch/mips/cpu/time.c +++ b/arch/mips/cpu/time.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <time.h> #include <asm/mipsregs.h> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 1b179116c9b..14fbce597b9 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb +dtb-$(CONFIG_BOARD_INTENO_XG6846) += inteno,xg6846.dtb dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb dtb-$(CONFIG_BOARD_MT7621_RFB) += mediatek,mt7621-rfb.dtb diff --git a/arch/mips/dts/inteno,xg6846.dts b/arch/mips/dts/inteno,xg6846.dts new file mode 100644 index 00000000000..180cfdcac9d --- /dev/null +++ b/arch/mips/dts/inteno,xg6846.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Linus Walleij <linusw@kernel.org> + * + * This is a diet version of the device tree from Linux, + * suitable for U-Boot. + */ + +/dts-v1/; + +#include "brcm,bcm6328.dtsi" + +/ { + model = "Inteno XG6846"; + compatible = "inteno,xg6846", "brcm,bcm6328"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&leds { + status = "okay"; + + led@18 { + reg = <18>; + active-low; + label = "red:pwr"; + }; + + led@20 { + reg = <20>; + active-low; + label = "green:pwr"; + }; +}; + +&spi { + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <33333334>; + }; +}; + +&uart0 { + bootph-all; + status = "okay"; +}; diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 641e2ad58de..c1015c885e1 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -11,6 +11,7 @@ #include <asm/cache.h> #ifndef __ASSEMBLY__ +#include <linux/types.h> static inline void mips_cache(int op, const volatile void *addr) { diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c index 1b29d637ce9..749625aa974 100644 --- a/arch/mips/lib/boot.c +++ b/arch/mips/lib/boot.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Stefan Roese <sr@denx.de> */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <asm/global_data.h> diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index ab92bd06b0e..d6d2f7d9d03 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <bootstage.h> #include <env.h> #include <image.h> diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index d23b38d6b93..d365578b926 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> */ -#include <common.h> #include <cpu_func.h> #include <malloc.h> #include <asm/cache.h> diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c index 9cf6809f406..69dd63a31d2 100644 --- a/arch/mips/lib/reloc.c +++ b/arch/mips/lib/reloc.c @@ -26,7 +26,6 @@ * terminating R_MIPS_NONE reloc includes no offset. */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <asm/relocs.h> diff --git a/arch/mips/lib/spl.c b/arch/mips/lib/spl.c index f96fda5b2de..b4087546dd1 100644 --- a/arch/mips/lib/spl.c +++ b/arch/mips/lib/spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Stefan Roese <sr@denx.de> */ -#include <common.h> #include <cpu_func.h> #include <log.h> #include <spl.h> diff --git a/arch/mips/lib/stack.c b/arch/mips/lib/stack.c index 930d21856d9..5797271ae94 100644 --- a/arch/mips/lib/stack.c +++ b/arch/mips/lib/stack.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0+ -#include <common.h> #include <init.h> #include <log.h> #include <asm/global_data.h> diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 7a682f256a6..40469d1be09 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -10,9 +10,9 @@ * Copyright (C) 2014, Imagination Technologies Ltd. */ -#include <common.h> #include <asm/global_data.h> #include <asm/ptrace.h> +#include <config.h> #include <cpu_func.h> #include <hang.h> #include <init.h> @@ -20,6 +20,7 @@ #include <asm/mipsregs.h> #include <asm/addrspace.h> #include <asm/system.h> +#include <asm/u-boot.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c index 68d48939d7d..86fc40a657e 100644 --- a/arch/mips/mach-ath79/ar933x/clk.c +++ b/arch/mips/mach-ath79/ar933x/clk.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> */ -#include <common.h> #include <clock_legacy.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c index 09166ecf8f0..a932efbfbd7 100644 --- a/arch/mips/mach-ath79/ar933x/ddr.c +++ b/arch/mips/mach-ath79/ar933x/ddr.c @@ -4,7 +4,6 @@ * Based on Atheros LSDK/QSDK */ -#include <common.h> #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c index 6ed4057353a..bdaa6839a2b 100644 --- a/arch/mips/mach-ath79/ar934x/clk.c +++ b/arch/mips/mach-ath79/ar934x/clk.c @@ -3,7 +3,6 @@ * Copyright (C) 2016 Marek Vasut <marex@denx.de> */ -#include <common.h> #include <clock_legacy.h> #include <command.h> #include <hang.h> diff --git a/arch/mips/mach-ath79/ar934x/cpu.c b/arch/mips/mach-ath79/ar934x/cpu.c index 7daac036714..f2e4ef191eb 100644 --- a/arch/mips/mach-ath79/ar934x/cpu.c +++ b/arch/mips/mach-ath79/ar934x/cpu.c @@ -3,7 +3,5 @@ * Copyright (C) 2016 Marek Vasut <marex@denx.de> */ -#include <common.h> - /* The lowlevel_init() is not needed on AR934x */ void lowlevel_init(void) {} diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c index 9df48b97ef4..e260783d959 100644 --- a/arch/mips/mach-ath79/ar934x/ddr.c +++ b/arch/mips/mach-ath79/ar934x/ddr.c @@ -5,7 +5,6 @@ * Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com> */ -#include <common.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/addrspace.h> diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c index 79f419088a9..24160ef1152 100644 --- a/arch/mips/mach-ath79/cpu.c +++ b/arch/mips/mach-ath79/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> */ -#include <common.h> #include <init.h> #include <asm/io.h> #include <asm/addrspace.h> diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c index 545b1199e10..247691d3378 100644 --- a/arch/mips/mach-ath79/dram.c +++ b/arch/mips/mach-ath79/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <linux/sizes.h> diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c index f5438ef1c8d..379085f1ff7 100644 --- a/arch/mips/mach-ath79/qca953x/clk.c +++ b/arch/mips/mach-ath79/qca953x/clk.c @@ -3,7 +3,6 @@ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> */ -#include <common.h> #include <clock_legacy.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c index 78f2370e09c..0eb69d3a0fb 100644 --- a/arch/mips/mach-ath79/qca953x/ddr.c +++ b/arch/mips/mach-ath79/qca953x/ddr.c @@ -4,7 +4,6 @@ * Based on Atheros LSDK/QSDK */ -#include <common.h> #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> diff --git a/arch/mips/mach-ath79/qca956x/clk.c b/arch/mips/mach-ath79/qca956x/clk.c index 6a58dba91f3..6138a915efc 100644 --- a/arch/mips/mach-ath79/qca956x/clk.c +++ b/arch/mips/mach-ath79/qca956x/clk.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com> */ -#include <common.h> #include <clock_legacy.h> #include <log.h> #include <asm/global_data.h> diff --git a/arch/mips/mach-ath79/qca956x/cpu.c b/arch/mips/mach-ath79/qca956x/cpu.c index 08a8c84e72d..7da8d0e60f1 100644 --- a/arch/mips/mach-ath79/qca956x/cpu.c +++ b/arch/mips/mach-ath79/qca956x/cpu.c @@ -3,7 +3,5 @@ * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com> */ -#include <common.h> - /* The lowlevel_init() is not needed on QCA956X */ void lowlevel_init(void) {} diff --git a/arch/mips/mach-ath79/qca956x/ddr.c b/arch/mips/mach-ath79/qca956x/ddr.c index f9cf8daa224..2e46e24f483 100644 --- a/arch/mips/mach-ath79/qca956x/ddr.c +++ b/arch/mips/mach-ath79/qca956x/ddr.c @@ -5,7 +5,6 @@ * Based on QSDK */ -#include <common.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/addrspace.h> diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index 6cd5e77fd15..62da8b92a7d 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -4,7 +4,6 @@ * Copyright (C) 2018-2019 Rosy Song <rosysong@rosinson.com> */ -#include <common.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/errno.h> diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index 01d919f2dbe..eb9ea34c52f 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -203,6 +203,17 @@ config BOARD_HUAWEI_HG556A ethernet ports, 3 USB ports, 1 UART, GPIO buttons and LEDs, and a RT3062F/AR9223 (PCI). +config BOARD_INTENO_XG6846 + bool "Inteno XG6846" + depends on SOC_BMIPS_BCM6328 + select BMIPS_SUPPORTS_BOOT_RAM + help + Inteno XG6846 boards have a BCM6328 SoC with 64 MB of RAM and 16 + MB of flash (SPI). + Between its different peripherals there's an integrated switch with 4 + ethernet ports, 1 UART, GPIO buttons and LEDs, and a Marvell + DSA switch connected to a fiber SFP. + config BOARD_NETGEAR_CG3100D bool "Netgear CG3100D" depends on SOC_BMIPS_BCM3380 @@ -272,6 +283,7 @@ source "board/comtrend/ct5361/Kconfig" source "board/comtrend/vr3032u/Kconfig" source "board/comtrend/wap5813n/Kconfig" source "board/huawei/hg556a/Kconfig" +source "board/inteno/xg6846/Kconfig" source "board/netgear/cg3100d/Kconfig" source "board/netgear/dgnd3700v2/Kconfig" source "board/sagem/f@st1704/Kconfig" diff --git a/arch/mips/mach-bmips/dram.c b/arch/mips/mach-bmips/dram.c index bba6cd6f4aa..eec8b44e47e 100644 --- a/arch/mips/mach-bmips/dram.c +++ b/arch/mips/mach-bmips/dram.c @@ -4,7 +4,6 @@ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> */ -#include <common.h> #include <init.h> #include <log.h> #include <ram.h> diff --git a/arch/mips/mach-jz47xx/jz4780/gpio.c b/arch/mips/mach-jz47xx/jz4780/gpio.c index d4884e7fa9f..7f6717efc16 100644 --- a/arch/mips/mach-jz47xx/jz4780/gpio.c +++ b/arch/mips/mach-jz47xx/jz4780/gpio.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ #include <config.h> -#include <common.h> #include <asm/io.h> #include <linux/bitops.h> #include <mach/jz4780.h> diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index 56fdf04bca9..1d6fb6a4e27 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -7,7 +7,6 @@ */ #include <config.h> -#include <common.h> #include <cpu_func.h> #include <hang.h> #include <image.h> diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c b/arch/mips/mach-jz47xx/jz4780/pll.c index 4519b478ccb..8ef00f99a10 100644 --- a/arch/mips/mach-jz47xx/jz4780/pll.c +++ b/arch/mips/mach-jz47xx/jz4780/pll.c @@ -7,7 +7,6 @@ */ #include <config.h> -#include <common.h> #include <asm/io.h> #include <linux/bitops.h> #include <linux/delay.h> diff --git a/arch/mips/mach-jz47xx/jz4780/reset.c b/arch/mips/mach-jz47xx/jz4780/reset.c index bf6addccb5d..d2e9eb79e6d 100644 --- a/arch/mips/mach-jz47xx/jz4780/reset.c +++ b/arch/mips/mach-jz47xx/jz4780/reset.c @@ -7,7 +7,6 @@ */ #include <config.h> -#include <common.h> #include <asm/io.h> #include <linux/bitops.h> #include <mach/jz4780.h> diff --git a/arch/mips/mach-jz47xx/jz4780/sdram.c b/arch/mips/mach-jz47xx/jz4780/sdram.c index 690f3c5601d..09296ee21ad 100644 --- a/arch/mips/mach-jz47xx/jz4780/sdram.c +++ b/arch/mips/mach-jz47xx/jz4780/sdram.c @@ -9,7 +9,6 @@ * Copyright (c) 2006-2013 Ingenic Semiconductor */ -#include <common.h> #include <hang.h> #include <init.h> #include <asm/io.h> diff --git a/arch/mips/mach-jz47xx/jz4780/timer.c b/arch/mips/mach-jz47xx/jz4780/timer.c index 82bb9e8c3bf..94ef505f18f 100644 --- a/arch/mips/mach-jz47xx/jz4780/timer.c +++ b/arch/mips/mach-jz47xx/jz4780/timer.c @@ -7,7 +7,6 @@ */ #include <config.h> -#include <common.h> #include <div64.h> #include <init.h> #include <irq_func.h> diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index d484eb92c41..22b1b98e0ef 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include <common.h> #include <init.h> #include <asm/global_data.h> #include <linux/bitops.h> diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c index f7fbd33cc4b..c7c2040a11a 100644 --- a/arch/mips/mach-mscc/dram.c +++ b/arch/mips/mach-mscc/dram.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include <common.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/mips/mach-mscc/gpio.c b/arch/mips/mach-mscc/gpio.c index d6b4c5d7684..6cd0e2436e7 100644 --- a/arch/mips/mach-mscc/gpio.c +++ b/arch/mips/mach-mscc/gpio.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include <common.h> #include <asm/io.h> #include <linux/bitops.h> diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index 75fb3ca00d2..3ba33d27c17 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -6,6 +6,7 @@ #ifndef __ASM_MACH_DDR_H #define __ASM_MACH_DDR_H +#include <config.h> #include <asm/cacheops.h> #include <asm/io.h> #include <asm/reboot.h> diff --git a/arch/mips/mach-mscc/phy.c b/arch/mips/mach-mscc/phy.c index 83d3e5bdd28..444d1f5315d 100644 --- a/arch/mips/mach-mscc/phy.c +++ b/arch/mips/mach-mscc/phy.c @@ -3,7 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include <common.h> #include <log.h> #include <asm/io.h> diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c index a1214573b51..ca9a7c679d9 100644 --- a/arch/mips/mach-mscc/reset.c +++ b/arch/mips/mach-mscc/reset.c @@ -3,8 +3,6 @@ * Copyright (c) 2018 Microsemi Corporation */ -#include <common.h> - #include <asm/sections.h> #include <asm/io.h> diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c index e88dab10c76..243938a0ebb 100644 --- a/arch/mips/mach-mtmips/cpu.c +++ b/arch/mips/mach-mtmips/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Stefan Roese <sr@denx.de> */ -#include <common.h> #include <event.h> #include <init.h> #include <malloc.h> diff --git a/arch/mips/mach-mtmips/ddr_cal.c b/arch/mips/mach-mtmips/ddr_cal.c index 762619a960f..e2e1760a646 100644 --- a/arch/mips/mach-mtmips/ddr_cal.c +++ b/arch/mips/mach-mtmips/ddr_cal.c @@ -5,7 +5,6 @@ * Author: Weijie Gao <weijie.gao@mediatek.com> */ -#include <common.h> #include <asm/addrspace.h> #include <asm/cacheops.h> #include <asm/global_data.h> diff --git a/arch/mips/mach-mtmips/ddr_init.c b/arch/mips/mach-mtmips/ddr_init.c index 9c986daea6f..cab53561e42 100644 --- a/arch/mips/mach-mtmips/ddr_init.c +++ b/arch/mips/mach-mtmips/ddr_init.c @@ -5,7 +5,6 @@ * Author: Weijie Gao <weijie.gao@mediatek.com> */ -#include <common.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/io.h> diff --git a/arch/mips/mach-mtmips/mt7628/ddr.c b/arch/mips/mach-mtmips/mt7628/ddr.c index 4e72459906e..198bf262f92 100644 --- a/arch/mips/mach-mtmips/mt7628/ddr.c +++ b/arch/mips/mach-mtmips/mt7628/ddr.c @@ -5,7 +5,6 @@ * Author: Weijie Gao <weijie.gao@mediatek.com> */ -#include <common.h> #include <asm/addrspace.h> #include <asm/global_data.h> #include <linux/bitops.h> diff --git a/arch/mips/mach-mtmips/mt7628/init.c b/arch/mips/mach-mtmips/mt7628/init.c index 6b535129df1..2996fd9ef4e 100644 --- a/arch/mips/mach-mtmips/mt7628/init.c +++ b/arch/mips/mach-mtmips/mt7628/init.c @@ -5,7 +5,6 @@ * Author: Weijie Gao <weijie.gao@mediatek.com> */ -#include <common.h> #include <clk.h> #include <dm.h> #include <asm/global_data.h> diff --git a/arch/mips/mach-mtmips/mt7628/serial.c b/arch/mips/mach-mtmips/mt7628/serial.c index e5f3f87a673..11a2149e127 100644 --- a/arch/mips/mach-mtmips/mt7628/serial.c +++ b/arch/mips/mach-mtmips/mt7628/serial.c @@ -5,7 +5,6 @@ * Author: Weijie Gao <weijie.gao@mediatek.com> */ -#include <common.h> #include <asm/io.h> #include "mt7628.h" diff --git a/arch/mips/mach-mtmips/spl.c b/arch/mips/mach-mtmips/spl.c index fe5b49e702f..0208bc423df 100644 --- a/arch/mips/mach-mtmips/spl.c +++ b/arch/mips/mach-mtmips/spl.c @@ -5,7 +5,6 @@ * Author: Weijie Gao <weijie.gao@mediatek.com> */ -#include <common.h> #include <init.h> #include <spl.h> #include <asm/sections.h> diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c index 7ed306e045e..dbf8c9cd221 100644 --- a/arch/mips/mach-pic32/cpu.c +++ b/arch/mips/mach-pic32/cpu.c @@ -4,7 +4,6 @@ * Purna Chandra Mandal <purna.mandal@microchip.com> * */ -#include <common.h> #include <clk.h> #include <dm.h> #include <event.h> diff --git a/arch/mips/mach-pic32/reset.c b/arch/mips/mach-pic32/reset.c index 8071b13f7b4..efd6985b44a 100644 --- a/arch/mips/mach-pic32/reset.c +++ b/arch/mips/mach-pic32/reset.c @@ -4,7 +4,6 @@ * */ -#include <common.h> #include <asm/io.h> #include <mach/pic32.h> diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index e9c30427734..b737d5d12f1 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1617,7 +1617,7 @@ relocate_code: mr r10,r5 /* Save copy of Destination Address */ GET_GOT -#ifndef CONFIG_SPL_SKIP_RELOCATE +#if !defined(CONFIG_SPL_SKIP_RELOCATE) || !defined(CONFIG_SPL_BUILD) mr r3,r5 /* Destination Address */ lis r4,CONFIG_VAL(SYS_MONITOR_BASE)@h /* Source Address */ ori r4,r4,CONFIG_VAL(SYS_MONITOR_BASE)@l diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e291456530b..6d0d812ddb5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -14,6 +14,9 @@ config TARGET_ANDES_AE350 config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" +config TARGET_OPENPITON_RISCV64 + bool "Support RISC-V cores on OpenPiton SoC" + config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" @@ -24,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED bool "Support SiFive Unmatched Board" select SYS_CACHE_SHIFT_6 +config TARGET_SIPEED_MAIX + bool "Support Sipeed Maix Board" + select SYS_CACHE_SHIFT_6 + config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board" select BOARD_LATE_INIT @@ -32,13 +39,6 @@ config TARGET_TH1520_LPI4A bool "Support Sipeed's TH1520 Lichee PI 4A Board" select SYS_CACHE_SHIFT_6 -config TARGET_SIPEED_MAIX - bool "Support Sipeed Maix Board" - select SYS_CACHE_SHIFT_6 - -config TARGET_OPENPITON_RISCV64 - bool "Support RISC-V cores on OpenPiton SoC" - endchoice config SYS_ICACHE_OFF @@ -68,7 +68,6 @@ config SPL_SYS_DCACHE_OFF config SPL_ZERO_MEM_BEFORE_USE bool "Zero memory before use" depends on SPL - default n help Zero stack/GD/malloc area in SPL before using them, this is needed for Sifive core devices that uses L2 cache to store SPL. @@ -77,12 +76,12 @@ config SPL_ZERO_MEM_BEFORE_USE source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" +source "board/openpiton/riscv64/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" -source "board/thead/th1520_lpi4a/Kconfig" -source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" +source "board/thead/th1520_lpi4a/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andesv5/cache.c index 40d77f671c8..269bb27f75a 100644 --- a/arch/riscv/cpu/andesv5/cache.c +++ b/arch/riscv/cpu/andesv5/cache.c @@ -6,7 +6,6 @@ #include <asm/csr.h> #include <asm/asm.h> -#include <common.h> #include <cache.h> #include <cpu_func.h> #include <dm.h> diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index 06e379bcb1f..63bc24cdfc7 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -5,7 +5,6 @@ */ /* CPU specific code */ -#include <common.h> #include <cpu_func.h> #include <irq_func.h> #include <asm/cache.h> diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andesv5/spl.c index 413849043b1..a13dc4095a4 100644 --- a/arch/riscv/cpu/andesv5/spl.c +++ b/arch/riscv/cpu/andesv5/spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2023 Andes Technology Corporation * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> #include <cpu_func.h> #include <hang.h> #include <init.h> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c1a9638c1ab..ebd39cb41a6 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <dm/lists.h> diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c index 94d8018407e..7b5a3471ac8 100644 --- a/arch/riscv/cpu/fu540/dram.c +++ b/arch/riscv/cpu/fu540/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <fdtdec.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c index 8657fcd165c..61f551763f1 100644 --- a/arch/riscv/cpu/fu740/dram.c +++ b/arch/riscv/cpu/fu740/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <fdtdec.h> #include <init.h> #include <linux/sizes.h> diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c index d78e1a3453a..f13c18942f3 100644 --- a/arch/riscv/cpu/generic/cpu.c +++ b/arch/riscv/cpu/generic/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <irq_func.h> #include <asm/cache.h> diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 1b51bae9b66..91007c0a3d3 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <fdtdec.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index 1a9fa46d14b..664b9b93eb6 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -4,7 +4,6 @@ * Author: Yanhong Wang <yanhong.wang@starfivetech.com> */ -#include <common.h> #include <fdtdec.h> #include <init.h> #include <linux/sizes.h> diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 4047b10efe8..6bdf8b9c72f 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 StarFive Technology Co., Ltd. * Author: Yanhong Wang<yanhong.wang@starfivetech.com> */ -#include <common.h> #include <asm/arch/eeprom.h> #include <asm/csr.h> #include <asm/sections.h> diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index e40c7bd3f4f..5cad7b41ff7 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -11,7 +11,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <asm/encoding.h> #ifdef CONFIG_32BIT @@ -27,7 +26,7 @@ .text /* trap entry */ - .align 2 + .align 6 .global trap_entry trap_entry: addi sp, sp, -32 * REGBYTES diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 30cf6743701..6cecadfac56 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -11,7 +11,6 @@ #include <asm-offsets.h> #include <config.h> -#include <common.h> #include <elf.h> #include <system-constants.h> #include <asm/encoding.h> diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index ec237a46ffb..13c47f7caa3 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -627,6 +627,16 @@ status = "disabled"; }; + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x0 0x1600C000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, + <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; + interrupts = <30>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>; diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index c7ed920cde5..393d51c6dde 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -7,6 +7,7 @@ #define _ASM_ANDES_CSR_H #include <asm/asm.h> +#include <linux/bitops.h> #include <linux/const.h> #define CSR_MCACHE_CTL 0x7ca diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h index f354d5c60cd..d2776d5b6cb 100644 --- a/arch/riscv/include/asm/arch-jh7110/eeprom.h +++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h @@ -7,6 +7,8 @@ #ifndef _ASM_RISCV_EEPROM_H #define _ASM_RISCV_EEPROM_H +#include <linux/types.h> + u8 get_pcb_revision_from_eeprom(void); u32 get_ddr_size_from_eeprom(void); diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h new file mode 100644 index 00000000000..90aa2f8a9ed --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/gpio.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#ifndef _GPIO_STARFIVE_H_ +#define _GPIO_STARFIVE_H_ + +#include <asm/arch/regs.h> + +#define GPIO_NUM_SHIFT 2 /*one dword include 4 gpios*/ +#define GPIO_BYTE_SHIFT 3 + +#define GPIO_INDEX_MASK 0x3 + +#define GPIO_DOEN_MASK 0x3f +#define GPIO_DOUT_MASK 0x7f +#define GPIO_DIN_MASK 0x7f +#define GPIO_DS_MASK 0x06 +#define GPIO_DS_SHIFT 1 +#define GPIO_SLEW_MASK BIT(5) +#define GPIO_SLEW_SHIFT 5 +#define GPIO_PULL_MASK 0x18 +#define GPIO_PULL_SHIFT 3 +#define GPIO_PULL_UP 1 +#define GPIO_PULL_DOWN 2 + +#define NR_GPIOS 64 + +#define GPIO_OFFSET(gpio) \ + (((gpio) >> GPIO_NUM_SHIFT) << GPIO_NUM_SHIFT) + +#define GPIO_SHIFT(gpio) \ + (((gpio) & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT) + +enum gpio_state { + LOW, + HIGH +}; + +#define GPIO_DOEN 0x0 +#define GPIO_DOUT 0x40 +#define GPIO_DIN 0x80 +#define GPIO_EN 0xdc +#define GPIO_LOW_IE 0x100 +#define GPIO_HIGH_IE 0x104 +#define GPIO_CONFIG 0x120 + +#define SYS_IOMUX_DOEN(gpio, oen) \ + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_OFFSET(gpio), \ + GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \ + (oen) << GPIO_SHIFT(gpio)) + +#define SYS_IOMUX_DOUT(gpio, gpo) \ + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DOUT + GPIO_OFFSET(gpio), \ + GPIO_DOUT_MASK << GPIO_SHIFT(gpio), \ + ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio)) + +#define SYS_IOMUX_DIN(gpio, gpi)\ + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \ + GPIO_DIN_MASK << GPIO_SHIFT(gpi), \ + ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) + +#define SYS_IOMUX_SET_DS(gpio, ds) \ + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \ + GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT) + +#define SYS_IOMUX_SET_SLEW(gpio, slew) \ + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \ + GPIO_SLEW_MASK, (slew) << GPIO_SLEW_SHIFT) + +#define SYS_IOMUX_SET_PULL(gpio, pull) \ + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \ + GPIO_PULL_MASK, (pull) << GPIO_PULL_SHIFT) + +#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) \ + do { \ + SYS_IOMUX_DOEN(gpio, oen); \ + SYS_IOMUX_DOUT(gpio, gpo); \ + SYS_IOMUX_DIN(gpio, gpi); \ + } while (0) + +#endif /* _GPIO_STARFIVE_H_ */ diff --git a/arch/riscv/include/asm/dma-mapping.h b/arch/riscv/include/asm/dma-mapping.h index 6ecadab41cd..d0cc5d7c775 100644 --- a/arch/riscv/include/asm/dma-mapping.h +++ b/arch/riscv/include/asm/dma-mapping.h @@ -9,7 +9,6 @@ #ifndef __ASM_RISCV_DMA_MAPPING_H #define __ASM_RISCV_DMA_MAPPING_H -#include <common.h> #include <linux/types.h> #include <asm/cache.h> #include <cpu_func.h> diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index b16e6dfa376..4170877a1ae 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -323,6 +323,51 @@ static inline void writesl(unsigned int *addr, const void *data, int longlen) #define insw_p(port, to, len) insw(port, to, len) #define insl_p(port, to, len) insl(port, to, len) +/* + * Unordered I/O memory access primitives. These are even more relaxed than + * the relaxed versions, as they don't even order accesses between successive + * operations to the I/O regions. + */ +#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) +#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) +#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) + +#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c))) +#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c))) +#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c))) + +#ifdef CONFIG_64BIT +#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) +#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c))) +#endif + +/* + * Relaxed I/O memory access primitives. These follow the Device memory + * ordering rules but do not guarantee any ordering relative to Normal memory + * accesses. These are defined to order the indicated access (either a read or + * write) with all other I/O memory accesses to the same peripheral. Since the + * platform specification defines that all I/O regions are strongly ordered on + * channel 0, no explicit fences are required to enforce this ordering. + */ +/* FIXME: These are now the same as asm-generic */ +#define __io_rbr() do {} while (0) +#define __io_rar() do {} while (0) +#define __io_rbw() do {} while (0) +#define __io_raw() do {} while (0) + +#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; }) +#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; }) +#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; }) + +#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); }) +#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); }) +#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); }) + +#ifdef CONFIG_64BIT +#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; }) +#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) +#endif + #include <asm-generic/io.h> #endif /* __ASM_RISCV_IO_H */ diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 4284a332e98..ee749dd1195 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -7,6 +7,8 @@ #ifndef _ASM_RISCV_SMP_H #define _ASM_RISCV_SMP_H +#include <linux/types.h> + /** * struct ipi_data - Inter-processor interrupt (IPI) data structure * diff --git a/arch/riscv/lib/aclint_ipi.c b/arch/riscv/lib/aclint_ipi.c index 90b8e128cb1..dcd7e5e6b34 100644 --- a/arch/riscv/lib/aclint_ipi.c +++ b/arch/riscv/lib/aclint_ipi.c @@ -8,7 +8,6 @@ * associated with software and timer interrupts. */ -#include <common.h> #include <dm.h> #include <regmap.h> #include <syscon.h> diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c index 6fd49e873b1..6a63661312a 100644 --- a/arch/riscv/lib/andes_plicsw.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -8,7 +8,6 @@ * similar to RISC-V PLIC. */ -#include <common.h> #include <dm.h> #include <asm/global_data.h> #include <dm/device-internal.h> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index 452dfcea97f..875bb9a6d98 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -8,7 +8,6 @@ * assembly language modules. */ -#include <common.h> #include <asm/global_data.h> #include <linux/kbuild.h> diff --git a/arch/riscv/lib/boot.c b/arch/riscv/lib/boot.c index 778d011f7ce..03014c56dce 100644 --- a/arch/riscv/lib/boot.c +++ b/arch/riscv/lib/boot.c @@ -4,8 +4,7 @@ * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> -#include <command.h> +#include <asm/u-boot.h> unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, char *const argv[]) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index cc30efc9049..f9e1e18ae02 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -6,7 +6,6 @@ * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> #include <bootstage.h> #include <command.h> #include <dm.h> diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 686e699efbc..afad7e117f3 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -4,7 +4,6 @@ * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> #include <cpu_func.h> void invalidate_icache_all(void) @@ -20,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end) { } -void invalidate_icache_range(unsigned long start, unsigned long end) +__weak void invalidate_icache_range(unsigned long start, unsigned long end) { /* * RISC-V does not have an instruction for invalidating parts of the diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 36c16e9be2a..c658e72bd39 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> #include <fdt_support.h> #include <log.h> #include <mapmem.h> diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c index a65a5b8d17c..a82f48e9a50 100644 --- a/arch/riscv/lib/image.c +++ b/arch/riscv/lib/image.c @@ -6,7 +6,6 @@ * Based on arm/lib/image.c */ -#include <common.h> #include <image.h> #include <mapmem.h> #include <errno.h> diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index e966afa7e3e..a26ccc721fd 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -10,9 +10,9 @@ */ #include <linux/compat.h> -#include <common.h> #include <efi_loader.h> #include <hang.h> +#include <interrupt.h> #include <irq_func.h> #include <asm/global_data.h> #include <asm/ptrace.h> @@ -22,6 +22,13 @@ DECLARE_GLOBAL_DATA_PTR; +static struct resume_data *resume; + +void set_resume(struct resume_data *data) +{ + resume = data; +} + static void show_efi_loaded_images(uintptr_t epc) { efi_print_image_infos((void *)epc); @@ -106,6 +113,11 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) "Store/AMO page fault", }; + if (resume) { + resume->code = code; + longjmp(resume->jump, 1); + } + if (code < ARRAY_SIZE(exception_code)) printf("Unhandled exception: %s\n", exception_code[code]); else diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c index 8779c619cc5..712e1bdb8e1 100644 --- a/arch/riscv/lib/reset.c +++ b/arch/riscv/lib/reset.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <command.h> #include <hang.h> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 55a3bc3b5c9..35a7d3b12f5 100644 --- a/arch/riscv/lib/sbi.c +++ b/arch/riscv/lib/sbi.c @@ -7,7 +7,7 @@ * Taken from Linux arch/riscv/kernel/sbi.c */ -#include <common.h> +#include <errno.h> #include <asm/encoding.h> #include <asm/sbi.h> diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c index d02e2b4c488..511d3816da8 100644 --- a/arch/riscv/lib/sbi_ipi.c +++ b/arch/riscv/lib/sbi_ipi.c @@ -4,7 +4,6 @@ * Lukas Auer <lukas.auer@aisec.fraunhofer.de> */ -#include <common.h> #include <asm/encoding.h> #include <asm/sbi.h> diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c index 28154878fcc..39b0248c323 100644 --- a/arch/riscv/lib/sifive_cache.c +++ b/arch/riscv/lib/sifive_cache.c @@ -3,9 +3,9 @@ * Copyright (C) 2021 SiFive, Inc */ -#include <common.h> #include <cache.h> #include <cpu_func.h> +#include <log.h> #include <dm.h> void enable_caches(void) diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index f3cd8b9044a..a692f065edd 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -4,7 +4,6 @@ * Lukas Auer <lukas.auer@aisec.fraunhofer.de> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <asm/barrier.h> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index 9b242ed8212..9a7a4f6ac8d 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Fraunhofer AISEC, * Lukas Auer <lukas.auer@aisec.fraunhofer.de> */ -#include <common.h> #include <cpu_func.h> #include <hang.h> #include <init.h> diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 2d184c5f652..1d50991f8d2 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -2,7 +2,7 @@ # Copyright (c) 2011 The Chromium OS Authors. PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE -PLATFORM_CPPFLAGS += -fPIC +PLATFORM_CPPFLAGS += -fPIC -ffunction-sections -fdata-sections PLATFORM_LIBS += -lrt SDL_CONFIG ?= sdl2-config @@ -30,7 +30,7 @@ cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \ $(u-boot-main) \ $(u-boot-keep-syms-lto) \ -Wl,--no-whole-archive \ - $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map + $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -Wl,--gc-sections cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \ $(KBUILD_LDFLAGS:%=-Wl,%) \ diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds index ba8dee50c7b..52f13af3742 100644 --- a/arch/sandbox/cpu/u-boot.lds +++ b/arch/sandbox/cpu/u-boot.lds @@ -15,7 +15,7 @@ SECTIONS _u_boot_sandbox_getopt : { *(_u_boot_sandbox_getopt_start) - *(_u_boot_sandbox_getopt) + KEEP(*(_u_boot_sandbox_getopt)) *(_u_boot_sandbox_getopt_end) } diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index ff7e5584c55..241f397ba6e 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -4,11 +4,23 @@ * and sandbox64 builds. */ +#include <config.h> #include <dt-bindings/input/input.h> #define USB_CLASS_HUB 9 / { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + event_log: tcg_event_log { + no-map; + reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>; + }; + }; + binman { }; @@ -342,6 +354,7 @@ tpm2 { compatible = "sandbox,tpm2"; + memory-region = <&event_log>; }; triangle { diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index e4303473563..c7197795efb 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -9,6 +9,7 @@ /dts-v1/; +#include <config.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/sandbox-gpio.h> #include <dt-bindings/input/input.h> @@ -41,6 +42,7 @@ mmc3 = "/mmc3"; mmc4 = "/mmc4"; mmc5 = "/mmc5"; + mmc6 = "/mmc6"; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; @@ -68,6 +70,17 @@ osd0 = "/osd"; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + event_log: tcg_event_log { + no-map; + reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>; + }; + }; + binman: binman { }; @@ -732,6 +745,11 @@ #address-cells = <1>; #size-cells = <0>; + pwrdom_scmi: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + clk_scmi: protocol@14 { reg = <0x14>; #clock-cells = <1>; @@ -1102,6 +1120,13 @@ filename = "mmc5.img"; }; + /* This is used for mbr tests */ + mmc6 { + status = "disabled"; + compatible = "sandbox,mmc"; + filename = "mmc6.img"; + }; + pch { compatible = "sandbox,pch"; }; @@ -1423,6 +1448,7 @@ tpm2 { compatible = "sandbox,tpm2"; + memory-region = <&event_log>; }; tpm { @@ -1546,6 +1572,7 @@ other-node = "/some-bus/c-test@5"; int-values = <0x1937 72993>; u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>; + stdout-path = "serial0:115200n8"; chosen-test { compatible = "denx,u-boot-fdt-test"; reg = <9 1>; @@ -1639,6 +1666,7 @@ sandbox_scmi { compatible = "sandbox,scmi-devices"; + power-domains = <&pwrdom_scmi 2>; clocks = <&clk_scmi 2>, <&clk_scmi 0>; resets = <&reset_scmi 3>; regul0-supply = <®ul0_scmi>; diff --git a/arch/sandbox/include/asm/scmi_test.h b/arch/sandbox/include/asm/scmi_test.h index ccb0df6c148..619f8f5098c 100644 --- a/arch/sandbox/include/asm/scmi_test.h +++ b/arch/sandbox/include/asm/scmi_test.h @@ -6,11 +6,23 @@ #ifndef __SANDBOX_SCMI_TEST_H #define __SANDBOX_SCMI_TEST_H +#include <power-domain.h> + struct udevice; struct sandbox_scmi_agent; struct sandbox_scmi_service; /** + * struct sandbox_scmi_pwd + * @id: Identifier of the power domain used in the SCMI protocol + * @pstate:: Power state of the domain + */ +struct sandbox_scmi_pwd { + uint id; + u32 pstate; +}; + +/** * struct sandbox_scmi_clk - Simulated clock exposed by SCMI * @id: Identifier of the clock used in the SCMI protocol * @enabled: Clock state: true if enabled, false if disabled @@ -45,6 +57,8 @@ struct sandbox_scmi_voltd { /** * struct sandbox_scmi_agent - Simulated SCMI service seen by SCMI agent + * @pwdom_version: Implemented power domain protocol version + * @pwdom_count: Simulated power domains array size * @clk: Simulated clocks * @clk_count: Simulated clocks array size * @reset: Simulated reset domains @@ -53,6 +67,9 @@ struct sandbox_scmi_voltd { * @voltd_count: Simulated voltage domains array size */ struct sandbox_scmi_agent { + int pwdom_version; + struct sandbox_scmi_pwd *pwdom; + size_t pwdom_count; struct sandbox_scmi_clk *clk; size_t clk_count; struct sandbox_scmi_reset *reset; @@ -71,6 +88,8 @@ struct sandbox_scmi_service { /** * struct sandbox_scmi_devices - Reference to devices probed through SCMI + * @pwdom: Array of power domains + * @pwdom_count: Number of power domains probed * @clk: Array the clock devices * @clk_count: Number of clock devices probed * @reset: Array the reset controller devices @@ -79,6 +98,8 @@ struct sandbox_scmi_service { * @regul_count: Number of regulator devices probed */ struct sandbox_scmi_devices { + struct power_domain *pwdom; + size_t pwdom_count; struct clk *clk; size_t clk_count; struct reset_ctl *reset; diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c index d78ee403e6c..772c6bf1ee3 100644 --- a/board/AndesTech/ae350/ae350.c +++ b/board/AndesTech/ae350/ae350.c @@ -4,7 +4,7 @@ * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <flash.h> #include <image.h> diff --git a/board/CZ.NIC/turris_mox/mox_sp.c b/board/CZ.NIC/turris_mox/mox_sp.c index 87f67512fba..11d87564717 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.c +++ b/board/CZ.NIC/turris_mox/mox_sp.c @@ -10,6 +10,8 @@ #include <linux/delay.h> #include <mach/mbox.h> +#include "mox_sp.h" + const char *mox_sp_get_ecdsa_public_key(void) { static char public_key[135]; @@ -42,12 +44,13 @@ static inline void res_to_mac(u8 *mac, u32 t1, u32 t2) mac[5] = t2; } -int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram) +int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram, + enum cznic_a3720_board *board) { - u32 out[8]; + u32 out[9]; int res; - res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, NULL, 0, out, 8); + res = mbox_do_cmd(MBOX_CMD_BOARD_INFO, NULL, 0, out, 9); if (res < 0) return res; @@ -69,5 +72,8 @@ int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, int *ram) if (mac2) res_to_mac(mac2, out[6], out[7]); + if (board) + *board = out[8] + 1; + return 0; } diff --git a/board/CZ.NIC/turris_mox/mox_sp.h b/board/CZ.NIC/turris_mox/mox_sp.h index 83b60374585..720880d5df3 100644 --- a/board/CZ.NIC/turris_mox/mox_sp.h +++ b/board/CZ.NIC/turris_mox/mox_sp.h @@ -8,8 +8,14 @@ #include <common.h> +enum cznic_a3720_board { + BOARD_UNDEFINED = 0x0, + BOARD_TURRIS_MOX = 0x1, + BOARD_RIPE_ATLAS = 0x3, +}; + const char *mox_sp_get_ecdsa_public_key(void); int mbox_sp_get_board_info(u64 *sn, u8 *mac1, u8 *mac2, int *bv, - int *ram); + int *ram, enum cznic_a3720_board *board); #endif /* _BOARD_CZNIC_TURRIS_MOX_MOX_SP_H_ */ diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 370c2668b08..63b86992194 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -15,6 +15,7 @@ #include <dm.h> #include <dm/of_extra.h> #include <env.h> +#include <env_internal.h> #include <event.h> #include <fdt_support.h> #include <init.h> @@ -45,6 +46,26 @@ DECLARE_GLOBAL_DATA_PTR; +int board_fit_config_name_match(const char *name) +{ + if (!gd->board_type) { + enum cznic_a3720_board board; + + if (mbox_sp_get_board_info(NULL, NULL, NULL, NULL, NULL, + &board) < 0) { + printf("Cannot determine board, defaulting to Turris MOX!\n"); + board = BOARD_TURRIS_MOX; + } + + gd->board_type = board; + } + + return !((gd->board_type == BOARD_TURRIS_MOX && + !strcmp(name, "armada-3720-turris-mox")) || + (gd->board_type == BOARD_RIPE_ATLAS && + !strcmp(name, "armada-3720-ripe-atlas"))); +} + #if defined(CONFIG_OF_BOARD_FIXUP) int board_fix_fdt(void *blob) { @@ -53,6 +74,9 @@ int board_fix_fdt(void *blob) int i, size, ret; bool eth1_sgmii; + if (gd->board_type != BOARD_TURRIS_MOX) + return 0; + /* * SPI driver is not loaded in driver model yet, but we have to find out * if pcie should be enabled in U-Boot's device tree. Therefore we have @@ -388,16 +412,23 @@ static void load_spi_dtb(void) int misc_init_r(void) { + int i, ret, addrcnt; u8 mac[2][6]; - int i, ret; - ret = mbox_sp_get_board_info(NULL, mac[0], mac[1], NULL, NULL); + ret = mbox_sp_get_board_info(NULL, mac[0], mac[1], NULL, NULL, NULL); if (ret < 0) { printf("Cannot read data from OTP!\n"); return 0; } - for (i = 0; i < 2; ++i) { + if (gd->board_type == BOARD_TURRIS_MOX) + addrcnt = 2; + else if (gd->board_type == BOARD_RIPE_ATLAS) + addrcnt = 1; + else + addrcnt = 0; + + for (i = 0; i < addrcnt; ++i) { u8 oldmac[6]; if (is_valid_ethaddr(mac[i]) && @@ -405,7 +436,13 @@ int misc_init_r(void) eth_env_set_enetaddr_by_index("eth", i, mac[i]); } - load_spi_dtb(); + if (gd->board_type == BOARD_RIPE_ATLAS) { + env_set("board", "ripe_atlas"); + env_set("board_name", "ripe_atlas"); + env_set("fdtfile", "marvell/armada-3720-ripe-atlas.dtb"); + } else { + load_spi_dtb(); + } return 0; } @@ -528,14 +565,15 @@ static void handle_reset_button(void) int show_board_info(void) { int i, ret, board_version, ram_size, is_sd; - const char *pub_key; + const char *pub_key, *model; const u8 *topology; u64 serial_number; - printf("Model: CZ.NIC Turris Mox Board\n"); + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + printf("Model: %s\n", model); ret = mbox_sp_get_board_info(&serial_number, NULL, NULL, &board_version, - &ram_size); + &ram_size, NULL); if (ret < 0) { printf(" Cannot read board info: %i\n", ret); } else { @@ -550,6 +588,9 @@ int show_board_info(void) else printf(" Cannot read ECDSA Public Key\n"); + if (gd->board_type != BOARD_TURRIS_MOX) + return 0; + ret = mox_get_topology(&topology, &module_count, &is_sd); if (ret) printf("Cannot read module topology!\n"); @@ -668,10 +709,24 @@ err: return NULL; } +enum env_location env_get_location(enum env_operation op, int prio) +{ + if (prio > 0) + return ENVL_UNKNOWN; + + if (gd->board_type == BOARD_RIPE_ATLAS) + return ENVL_MMC; + + return ENVL_SPI_FLASH; +} + static int last_stage_init(void) { struct gpio_desc reset_gpio = {}; + if (gd->board_type != BOARD_TURRIS_MOX) + return 0; + /* configure modules */ if (get_reset_gpio(&reset_gpio) < 0) goto handle_reset_btn; @@ -801,6 +856,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) { int res; + if (gd->board_type != BOARD_TURRIS_MOX) + return 0; + /* * If MOX B (PCI), MOX F (USB) or MOX G (Passthrough PCI) modules are * connected, enable the PCIe node. diff --git a/board/abilis/tb100/tb100.c b/board/abilis/tb100/tb100.c index 89e73225a7d..3dc9e14ef8c 100644 --- a/board/abilis/tb100/tb100.c +++ b/board/abilis/tb100/tb100.c @@ -3,7 +3,6 @@ * (C) Copyright 2014 Pierrick Hascoet, Abilis Systems */ -#include <common.h> #include <cpu_func.h> #include <net.h> #include <netdev.h> diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index b79a2380aa5..d87fe3606f6 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -193,7 +193,7 @@ int board_late_init(void) #ifdef CONFIG_SPL_MMC #define UBOOT_RAW_SECTOR_OFFSET 0x40 -unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, +unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sector) { u32 boot_dev = spl_boot_device(); diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig index 912c6c5fbae..47d9bae9468 100644 --- a/board/asus/grouper/Kconfig +++ b/board/asus/grouper/Kconfig @@ -12,11 +12,9 @@ config SYS_CONFIG_NAME config GROUPER_TPS65911 bool "Enable support TI TPS65911 PMIC" select CMD_POWEROFF - default n config GROUPER_MAX77663 bool "Enable support MAXIM MAX77663 PMIC" select CMD_POWEROFF - default n endif diff --git a/board/asus/grouper/MAINTAINERS b/board/asus/grouper/MAINTAINERS index 18b4f0641f4..f4068d85623 100644 --- a/board/asus/grouper/MAINTAINERS +++ b/board/asus/grouper/MAINTAINERS @@ -2,9 +2,6 @@ GROUPER BOARD M: Svyatoslav Ryhel <clamor95@gmail.com> S: Maintained F: board/asus/grouper/ -F: configs/grouper_E1565.config -F: configs/grouper_PM269.config -F: configs/tilapia.config F: configs/grouper_common_defconfig F: doc/board/asus/grouper_common.rst F: include/configs/grouper.h diff --git a/configs/grouper_E1565.config b/board/asus/grouper/configs/grouper_E1565.config index 4d8d5263fa9..4d8d5263fa9 100644 --- a/configs/grouper_E1565.config +++ b/board/asus/grouper/configs/grouper_E1565.config diff --git a/configs/grouper_PM269.config b/board/asus/grouper/configs/grouper_PM269.config index fc768b20517..fc768b20517 100644 --- a/configs/grouper_PM269.config +++ b/board/asus/grouper/configs/grouper_PM269.config diff --git a/configs/tilapia.config b/board/asus/grouper/configs/tilapia.config index 1fb0633e3a7..1fb0633e3a7 100644 --- a/configs/tilapia.config +++ b/board/asus/grouper/configs/tilapia.config diff --git a/board/asus/grouper/grouper.c b/board/asus/grouper/grouper.c index 2769313e681..5398ec8b9f8 100644 --- a/board/asus/grouper/grouper.c +++ b/board/asus/grouper/grouper.c @@ -9,14 +9,12 @@ #include <common.h> #include <dm.h> -#include <env.h> #include <fdt_support.h> #include <i2c.h> #include <log.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/gpio.h> -#include <asm/arch-tegra/fuse.h> #include <asm/gpio.h> #include <linux/delay.h> #include "pinmux-config-grouper.h" @@ -190,13 +188,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif - -void nvidia_board_late_init(void) -{ - char serialno_str[17]; - - /* Set chip id as serialno */ - sprintf(serialno_str, "%016llx", tegra_chip_uid()); - env_set("serial#", serialno_str); - env_set("platform", "Tegra 3 T30"); -} diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig index 3c36f4ada20..accc999c435 100644 --- a/board/asus/transformer-t30/Kconfig +++ b/board/asus/transformer-t30/Kconfig @@ -14,7 +14,6 @@ config TRANSFORMER_SPI_BOOT select TEGRA20_SLINK select DM_SPI_FLASH select SPI_FLASH_WINBOND - default n help Tegra 3 based Transformers with Windows RT have core boot sequence (BCT and EBT) on separate SPI FLASH diff --git a/board/asus/transformer-t30/MAINTAINERS b/board/asus/transformer-t30/MAINTAINERS index c6c15323b28..071a9c04b86 100644 --- a/board/asus/transformer-t30/MAINTAINERS +++ b/board/asus/transformer-t30/MAINTAINERS @@ -2,13 +2,6 @@ TRANSFORMER BOARD M: Svyatoslav Ryhel <clamor95@gmail.com> S: Maintained F: board/asus/transformer-t30/ -F: configs/p1801-t.config -F: configs/tf201.config -F: configs/tf300t.config -F: configs/tf300tg.config -F: configs/tf300tl.config -F: configs/tf600t.config -F: configs/tf700t.config F: configs/transformer_t30_defconfig F: doc/board/asus/transformer_t30.rst F: include/configs/transformer-common.h diff --git a/configs/p1801-t.config b/board/asus/transformer-t30/configs/p1801-t.config index fab2912132c..fab2912132c 100644 --- a/configs/p1801-t.config +++ b/board/asus/transformer-t30/configs/p1801-t.config diff --git a/configs/tf201.config b/board/asus/transformer-t30/configs/tf201.config index 296743b7748..296743b7748 100644 --- a/configs/tf201.config +++ b/board/asus/transformer-t30/configs/tf201.config diff --git a/configs/tf300t.config b/board/asus/transformer-t30/configs/tf300t.config index 32a92fe76fa..32a92fe76fa 100644 --- a/configs/tf300t.config +++ b/board/asus/transformer-t30/configs/tf300t.config diff --git a/configs/tf300tg.config b/board/asus/transformer-t30/configs/tf300tg.config index 1396294f6de..1396294f6de 100644 --- a/configs/tf300tg.config +++ b/board/asus/transformer-t30/configs/tf300tg.config diff --git a/configs/tf300tl.config b/board/asus/transformer-t30/configs/tf300tl.config index 3db033c8df4..3db033c8df4 100644 --- a/configs/tf300tl.config +++ b/board/asus/transformer-t30/configs/tf300tl.config diff --git a/configs/tf600t.config b/board/asus/transformer-t30/configs/tf600t.config index 89d8db4eb1c..18ab4fbd878 100644 --- a/configs/tf600t.config +++ b/board/asus/transformer-t30/configs/tf600t.config @@ -1,4 +1,4 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf600t" CONFIG_TRANSFORMER_SPI_BOOT=y -CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" +CONFIG_BOOTCOMMAND="setenv gpio_button 222; if run check_button; then poweroff; fi; setenv gpio_button 132; if run check_button; then echo Starting SPI flash update ...; run update_spi; fi; run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" CONFIG_USB_GADGET_PRODUCT_NUM=0x4d00 diff --git a/configs/tf700t.config b/board/asus/transformer-t30/configs/tf700t.config index 066c884d082..066c884d082 100644 --- a/configs/tf700t.config +++ b/board/asus/transformer-t30/configs/tf700t.config diff --git a/board/asus/transformer-t30/transformer-t30.c b/board/asus/transformer-t30/transformer-t30.c index b6fd19d28e4..ba795a802eb 100644 --- a/board/asus/transformer-t30/transformer-t30.c +++ b/board/asus/transformer-t30/transformer-t30.c @@ -11,14 +11,12 @@ #include <common.h> #include <dm.h> -#include <env.h> #include <fdt_support.h> #include <i2c.h> #include <log.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/gpio.h> -#include <asm/arch-tegra/fuse.h> #include <asm/gpio.h> #include <linux/delay.h> #include "pinmux-config-transformer.h" @@ -33,11 +31,6 @@ #define TPS65911_LDO5 0x32 #define TPS65911_LDO6 0x35 -#define TPS65911_GPIO0 0x60 -#define TPS65911_GPIO6 0x66 -#define TPS65911_GPIO7 0x67 -#define TPS65911_GPIO8 0x68 - #define TPS65911_DEVCTRL 0x3F #define DEVCTRL_PWR_OFF_MASK BIT(7) #define DEVCTRL_DEV_ON_MASK BIT(2) @@ -146,26 +139,6 @@ static void tps65911_voltage_init(void) if (ret) log_debug("vddio_usd set failed: %d\n", ret); } - - /* TPS659110: GPIO0_REG output high to VDD_5V0_SBY */ - ret = dm_i2c_reg_write(dev, TPS65911_GPIO0, 0x07); - if (ret) - log_debug("vdd_5v0_sby set failed: %d\n", ret); - - /* TPS659110: GPIO6_REG output high to VDD_3V3_SYS */ - ret = dm_i2c_reg_write(dev, TPS65911_GPIO6, 0x07); - if (ret) - log_debug("vdd_3v3_sys set failed: %d\n", ret); - - /* TPS659110: GPIO7_REG output high to VDD_1V5_DDR */ - ret = dm_i2c_reg_write(dev, TPS65911_GPIO7, 0x07); - if (ret) - log_debug("vdd_1v5_ddr set failed: %d\n", ret); - - /* TPS659110: GPIO8_REG pull_down output high to VDD_5V0_SYS */ - ret = dm_i2c_reg_write(dev, TPS65911_GPIO8, 0x0f); - if (ret) - log_debug("vdd_5v0_sys set failed: %d\n", ret); } /* @@ -189,13 +162,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif - -void nvidia_board_late_init(void) -{ - char serialno_str[17]; - - /* Set chip id as serialno */ - sprintf(serialno_str, "%016llx", tegra_chip_uid()); - env_set("serial#", serialno_str); - env_set("platform", "Tegra 3 T30"); -} diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index c31e2c86a2d..ee9e6d632ed 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -4,7 +4,7 @@ * * Board functions for Bosch Guardian * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ diff --git a/board/bosch/guardian/board.h b/board/bosch/guardian/board.h index b301caf47f5..e1e8c0cb0eb 100644 --- a/board/bosch/guardian/board.h +++ b/board/bosch/guardian/board.h @@ -4,7 +4,7 @@ * * Board header for Bosch Guardian * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c index 12c3eb666fb..53850ffb8f7 100644 --- a/board/bosch/guardian/mux.c +++ b/board/bosch/guardian/mux.c @@ -2,7 +2,7 @@ /* * mux.c * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * Copyright (C) 2018 Robert Bosch Power Tools GmbH */ diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile index 93f2df3773e..bac12edc1d0 100644 --- a/board/bosch/shc/Makefile +++ b/board/bosch/shc/Makefile @@ -2,7 +2,7 @@ # # Makefile # -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ obj-y := mux.o obj-y += board.o diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index e3a9c00e809..962a485acd2 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -8,7 +8,7 @@ * Based on: * Board functions for TI AM335X based boards * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h index 997595bf42b..4cc02f93c64 100644 --- a/board/bosch/shc/board.h +++ b/board/bosch/shc/board.h @@ -8,7 +8,7 @@ * Based on: * TI AM335x boards information header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _BOARD_H_ diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c index 0a97eafea6c..f19d1866c72 100644 --- a/board/bosch/shc/mux.c +++ b/board/bosch/shc/mux.c @@ -6,7 +6,7 @@ * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * Based on: - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index 2fdd95a730c..cfc4b65e0f9 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -107,7 +107,7 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[4] = BOOT_DEVICE_NONE; } -unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect) +unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect) { const u32 boot_dev = spl_boot_device(); int part; diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 474dca72929..05053a87a5a 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * * Based on da830evm.c. Original Copyrights follow: * diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index 5ffd420fff3..9738e2bd9c7 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ * * Based on da850evm.c. Original Copyrights follow: * diff --git a/board/eets/pdu001/README b/board/eets/pdu001/README index 50e715446b6..ab10cf99f45 100644 --- a/board/eets/pdu001/README +++ b/board/eets/pdu001/README @@ -14,7 +14,7 @@ Hardware The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2 SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on -AM3352 SOC from TI (http://www.ti.com). +AM3352 SOC from TI (https://www.ti.com). Customization ============= diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index de224d4d283..3a52e4ae675 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -6,7 +6,7 @@ * * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/ * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/eets/pdu001/board.h b/board/eets/pdu001/board.h index bfea96e5f02..6ad0fea33b4 100644 --- a/board/eets/pdu001/board.h +++ b/board/eets/pdu001/board.h @@ -6,7 +6,7 @@ * * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _BOARD_H_ diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c index 886fef60b0a..c97927e5cfe 100644 --- a/board/eets/pdu001/mux.c +++ b/board/eets/pdu001/mux.c @@ -4,7 +4,7 @@ * * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/friendlyelec/nanopc-t6-rk3588/Kconfig b/board/friendlyelec/nanopc-t6-rk3588/Kconfig new file mode 100644 index 00000000000..032ef486108 --- /dev/null +++ b/board/friendlyelec/nanopc-t6-rk3588/Kconfig @@ -0,0 +1,15 @@ +if TARGET_NANOPCT6_RK3588 + +config SYS_BOARD + default "nanopc-t6-rk3588" + +config SYS_VENDOR + default "friendlyelec" + +config SYS_CONFIG_NAME + default "nanopc-t6-rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS b/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS new file mode 100644 index 00000000000..63ff6fafc8d --- /dev/null +++ b/board/friendlyelec/nanopc-t6-rk3588/MAINTAINERS @@ -0,0 +1,9 @@ +NANOPCT6-RK3588 +M: John Clark <inindev@gmail.com> +R: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: board/friendlyelec/nanopc-t6-rk3588 +F: include/configs/nanopc-t6-rk3588.h +F: configs/nanopc-t6-rk3588_defconfig +F: arch/arm/dts/rk3588-nanopc-t6.dts +F: arch/arm/dts/rk3588-nanopc-t6-u-boot.dtsi diff --git a/board/friendlyelec/nanopc-t6-rk3588/Makefile b/board/friendlyelec/nanopc-t6-rk3588/Makefile new file mode 100644 index 00000000000..c1c49b19708 --- /dev/null +++ b/board/friendlyelec/nanopc-t6-rk3588/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2023 Rockchip Electronics Co,. Ltd. +# + +obj-y += nanopc-t6-rk3588.o diff --git a/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c new file mode 100644 index 00000000000..99bbef964e0 --- /dev/null +++ b/board/friendlyelec/nanopc-t6-rk3588/nanopc-t6-rk3588.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 Rockchip Electronics Co,. Ltd. + */ + +#include <fdtdec.h> +#include <fdt_support.h> + +#ifdef CONFIG_OF_BOARD_SETUP +int nanopc_t6_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + unsigned int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return nanopc_t6_add_reserved_memory_fdt_nodes(blob); +} +#endif diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 31a23504175..b0a315ba953 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -346,7 +346,7 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) } } -unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) +unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) { if (!IS_SD(mmc)) { switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) { diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index b472ca5b94a..64b32ca96df 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * Copyright (C) 2017, Grinn - http://grinn-global.com/ */ diff --git a/board/htc/endeavoru/endeavoru.c b/board/htc/endeavoru/endeavoru.c index 1d92870f91a..e1a0b242e2c 100644 --- a/board/htc/endeavoru/endeavoru.c +++ b/board/htc/endeavoru/endeavoru.c @@ -9,14 +9,12 @@ #include <common.h> #include <dm.h> -#include <env.h> #include <fdt_support.h> #include <i2c.h> #include <log.h> #include <asm/arch/pinmux.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/gpio.h> -#include <asm/arch-tegra/fuse.h> #include <asm/gpio.h> #include <linux/delay.h> #include "pinmux-config-endeavoru.h" @@ -104,13 +102,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif - -void nvidia_board_late_init(void) -{ - char serialno_str[17]; - - /* Set chip id as serialno */ - sprintf(serialno_str, "%016llx", tegra_chip_uid()); - env_set("serial#", serialno_str); - env_set("platform", "Tegra 3 T30"); -} diff --git a/board/inteno/xg6846/Kconfig b/board/inteno/xg6846/Kconfig new file mode 100644 index 00000000000..4dd78b3b196 --- /dev/null +++ b/board/inteno/xg6846/Kconfig @@ -0,0 +1,12 @@ +if BOARD_INTENO_XG6846 + +config SYS_BOARD + default "xg6846" + +config SYS_VENDOR + default "inteno" + +config SYS_CONFIG_NAME + default "inteno_xg6846" + +endif diff --git a/board/inteno/xg6846/MAINTAINERS b/board/inteno/xg6846/MAINTAINERS new file mode 100644 index 00000000000..ca41730940f --- /dev/null +++ b/board/inteno/xg6846/MAINTAINERS @@ -0,0 +1,6 @@ +INTENO XG6846 BOARD +M: Linus Walleij <linusw@kernel.org> +S: Maintained +F: board/inteno/xg6846 +F: include/configs/inteno_xg6846.h +F: configs/inteno_xg6846_ram_defconfig diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index c6576aa6523..f7e9b74f578 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -125,7 +125,6 @@ config SYS_IVM_EEPROM_PAGE_LEN config PG_WCOM_UBOOT_UPDATE_SUPPORTED bool "Enable U-Boot Field Fail-Safe Update Functionality" select EVENT - default n help Indicates that field fail-safe u-boot update is supported. This functionality works only for designs that are booting @@ -133,7 +132,6 @@ config PG_WCOM_UBOOT_UPDATE_SUPPORTED config PG_WCOM_UBOOT_BOOTPACKAGE bool "U-Boot Is Part Of Factory Boot-Package Image" - default n help Indicates that u-boot will be a part of the factory programmed boot-package image. @@ -149,7 +147,6 @@ config PG_WCOM_UBOOT_UPDATE_TEXT_BASE config PG_WCOM_UBOOT_UPDATE bool "U-Boot Is Part Of Factory Boot-Package Image" - default n help Indicates that u-boot will be a part of the embedded software and programmed at field. diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c index 83492601310..43afe593c78 100644 --- a/board/lego/ev3/legoev3.c +++ b/board/lego/ev3/legoev3.c @@ -4,7 +4,7 @@ * * Based on da850evm.c * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * * Based on da830evm.c. Original Copyrights follow: * diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig index 20ea4f5f324..53d776019d6 100644 --- a/board/lg/x3-t30/Kconfig +++ b/board/lg/x3-t30/Kconfig @@ -11,14 +11,12 @@ config SYS_CONFIG_NAME config DEVICE_P880 bool "Enable support for LG Optimus 4X HD" - default n help LG Optimus 4X HD derives from x3 board but has slight differences. config DEVICE_P895 bool "Enable support for LG Optimus Vu" - default n help LG Optimus Vu derives from x3 board but has slight differences. diff --git a/board/lg/x3-t30/MAINTAINERS b/board/lg/x3-t30/MAINTAINERS index 0ad29563e92..13c8588d0b9 100644 --- a/board/lg/x3-t30/MAINTAINERS +++ b/board/lg/x3-t30/MAINTAINERS @@ -2,8 +2,6 @@ X3 BOARD M: Svyatoslav Ryhel <clamor95@gmail.com> S: Maintained F: board/lg/x3-t30/ -F: configs/p880.config -F: configs/p895.config F: configs/x3_t30_defconfig F: doc/board/lg/x3_t30.rst F: include/configs/x3-t30.h diff --git a/configs/p880.config b/board/lg/x3-t30/configs/p880.config index 1a47b5f7692..1a47b5f7692 100644 --- a/configs/p880.config +++ b/board/lg/x3-t30/configs/p880.config diff --git a/configs/p895.config b/board/lg/x3-t30/configs/p895.config index 019a5662d62..019a5662d62 100644 --- a/configs/p895.config +++ b/board/lg/x3-t30/configs/p895.config diff --git a/board/lg/x3-t30/x3-t30.c b/board/lg/x3-t30/x3-t30.c index 594563cf52d..a08e00dd87c 100644 --- a/board/lg/x3-t30/x3-t30.c +++ b/board/lg/x3-t30/x3-t30.c @@ -9,7 +9,6 @@ #include <common.h> #include <dm.h> -#include <env.h> #include <fdt_support.h> #include <i2c.h> #include <log.h> @@ -164,13 +163,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif - -void nvidia_board_late_init(void) -{ - char serialno_str[17]; - - /* Set chip id as serialno */ - sprintf(serialno_str, "%016llx", tegra_chip_uid()); - env_set("serial#", serialno_str); - env_set("platform", "Tegra 3 T30"); -} diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile index c07a98e9389..c7da6e3fe0d 100644 --- a/board/logicpd/am3517evm/Makefile +++ b/board/logicpd/am3517evm/Makefile @@ -4,6 +4,6 @@ # # Based on ti/evm/Makefile # -# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ obj-y := am3517evm.o diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index e787441c746..e69a73f2af6 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -7,7 +7,7 @@ * Based on ti/evm/evm.c * * Copyright (C) 2010 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index aec2b410c88..283b4535a6b 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -7,7 +7,7 @@ * Based on ti/evm/evm.h * * Copyright (C) 2010 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _AM3517EVM_H_ diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index e52e0a59abc..59e1a425646 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -16,7 +16,7 @@ #define DRAM_1GB_SIZE 0x40000000ULL #define DRAM_2GB_ECC_SIZE 0x70000000ULL #define DRAM_2GB_SIZE 0x80000000ULL -#define DRAM_4GB_ECC_SIZE 0xE00000000ULL +#define DRAM_4GB_ECC_SIZE 0xE0000000ULL #define DRAM_4GB_SIZE 0x100000000ULL DECLARE_GLOBAL_DATA_PTR; @@ -29,7 +29,6 @@ int board_init(void) int dram_init(void) { struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; - uint64_t delta = 0ULL; /* * get dram active size value from bootblock. @@ -38,18 +37,22 @@ int dram_init(void) */ gd->ram_size = readl(&gcr->scrpad_c); - debug("%s: scrpad_c: %llx ", __func__, gd->ram_size); - if (gd->ram_size == 0) { + if (gd->ram_size == 0) gd->ram_size = readl(&gcr->scrpad_b); - debug("%s: scrpad_b: %llx ", __func__, gd->ram_size); - } else { + else gd->ram_size *= 0x100000ULL; - } - gd->bd->bi_dram[0].start = 0; debug("ram_size: %llx ", gd->ram_size); + return 0; +} + +int dram_init_banksize(void) +{ + + gd->bd->bi_dram[0].start = 0; + switch (gd->ram_size) { case DRAM_512MB_ECC_SIZE: case DRAM_512MB_SIZE: @@ -62,32 +65,28 @@ int dram_init(void) gd->bd->bi_dram[1].size = 0; break; case DRAM_4GB_ECC_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_ECC_SIZE; + gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; - delta = DRAM_4GB_SIZE - DRAM_2GB_ECC_SIZE; + gd->bd->bi_dram[1].size = DRAM_2GB_SIZE - + (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE); + /* use bank0 only */ + gd->ram_size = DRAM_2GB_SIZE; break; case DRAM_4GB_SIZE: gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; - delta = DRAM_4GB_SIZE - DRAM_2GB_SIZE; + /* use bank0 only */ + gd->ram_size = DRAM_2GB_SIZE; break; default: gd->bd->bi_dram[0].size = DRAM_1GB_SIZE; gd->bd->bi_dram[1].start = 0; gd->bd->bi_dram[1].size = 0; + gd->ram_size = DRAM_1GB_SIZE; break; } - gd->ram_size -= delta; - return 0; } -int dram_init_banksize(void) -{ - dram_init(); - - return 0; -} diff --git a/board/phytec/phycore_am335x_r2/Makefile b/board/phytec/phycore_am335x_r2/Makefile index ff6f8b42216..16ac38fd8be 100644 --- a/board/phytec/phycore_am335x_r2/Makefile +++ b/board/phytec/phycore_am335x_r2/Makefile @@ -2,7 +2,7 @@ # # Makefile # -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ ifdef CONFIG_SPL_BUILD obj-y += mux.o diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index eb573d076dd..5700effbd3f 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -4,7 +4,7 @@ * * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH * Copyright (C) 2019 DENX Software Engineering GmbH diff --git a/board/pine64/quartzpro64-rk3588/Kconfig b/board/pine64/quartzpro64-rk3588/Kconfig new file mode 100644 index 00000000000..96aa7921d32 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QUARTZPRO64_RK3588 + +config SYS_BOARD + default "quartzpro64-rk3588" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "quartzpro64-rk3588" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/pine64/quartzpro64-rk3588/MAINTAINERS b/board/pine64/quartzpro64-rk3588/MAINTAINERS new file mode 100644 index 00000000000..a7e944b7478 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/MAINTAINERS @@ -0,0 +1,8 @@ +QUARTZPRO64-RK3588 +M: Tom Fitzhenry <tom@tom-fitzhenry.me.uk> +S: Maintained +F: board/pine64/quartzpro64-rk3588 +F: include/configs/quartzpro64-rk3588.h +F: configs/quartzpro64-rk3588_defconfig +F: arch/arm/dts/rk3588-quartzpro64.dts +F: arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi diff --git a/board/pine64/quartzpro64-rk3588/Makefile b/board/pine64/quartzpro64-rk3588/Makefile new file mode 100644 index 00000000000..47819d9be93 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += quartzpro64-rk3588.o diff --git a/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c new file mode 100644 index 00000000000..bda804a89e2 --- /dev/null +++ b/board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Google, Inc + */ + +#include <fdtdec.h> +#include <fdt_support.h> + +#ifdef CONFIG_OF_BOARD_SETUP +int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob) +{ + struct fdt_memory gap1 = { + .start = 0x3fc000000, + .end = 0x3fc4fffff, + }; + struct fdt_memory gap2 = { + .start = 0x3fff00000, + .end = 0x3ffffffff, + }; + unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP; + unsigned int ret; + + /* + * Inject the reserved-memory nodes into the DTS + */ + ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1, NULL, 0, + NULL, flags); + if (ret) + return ret; + + return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2, NULL, 0, + NULL, flags); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return quartzpro64_add_reserved_memory_fdt_nodes(blob); +} +#endif diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c index 755747e665c..73201a8c69e 100644 --- a/board/renesas/rzg2l/rzg2l.c +++ b/board/renesas/rzg2l/rzg2l.c @@ -4,7 +4,6 @@ * Copyright (C) 2023 Renesas Electronics Corporation */ -#include <common.h> #include <fdtdec.h> #include <linux/libfdt.h> diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 6b2c257a170..2bd44bc5872 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -6,3 +6,17 @@ F: include/configs/evb_rk3588.h F: configs/evb-rk3588_defconfig F: arch/arm/dts/rk3588-evb1-v10.dts F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi + +ORANGEPI-5-RK3588 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/orangepi-5-rk3588s_defconfig +F: arch/arm/dts/rk3588s-orangepi-5.dts +F: arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi + +ORANGEPI-5-PLUS-RK3588 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/orangepi-5-plus-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-plus.dts +F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 8fa9197a6df..d077751cbe1 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -6,7 +6,7 @@ * * Based on: * U-Boot file:/board/ti/am335x/board.c - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/siemens/draco/Makefile b/board/siemens/draco/Makefile index 3e3394a8656..e94456ab1c3 100644 --- a/board/siemens/draco/Makefile +++ b/board/siemens/draco/Makefile @@ -7,7 +7,7 @@ # # Based on: # u-boot:/board/ti/am335x/Makefile -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ ifdef CONFIG_SPL_BUILD obj-y := mux.o diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index 8874659013f..8b13d23aca7 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -9,7 +9,7 @@ * Board functions for TI AM335X based boards * u-boot:/board/ti/am335x/board.c * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h index 7c29a45c036..f027427d1fb 100644 --- a/board/siemens/draco/board.h +++ b/board/siemens/draco/board.h @@ -9,7 +9,7 @@ * TI AM335x boards information header * u-boot:/board/ti/am335x/board.h * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _BOARD_H_ diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c index 3f2d41befeb..2632f050336 100644 --- a/board/siemens/draco/mux.c +++ b/board/siemens/draco/mux.c @@ -7,7 +7,7 @@ * * Based on: * u-boot:/board/ti/am335x/mux.c - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index e35e55fb5de..0b0686e2628 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -155,19 +155,20 @@ static bool board_is_advanced(void) strstr((char *)info->name, "IOT2050-ADVANCED") != NULL; } -static bool board_is_sr1(void) +static bool board_is_pg1(void) { struct iot2050_info *info = IOT2050_INFO_DATA; return info->magic == IOT2050_INFO_MAGIC && - strstr((char *)info->name, "-PG2") == NULL; + (strcmp((char *)info->name, "IOT2050-BASIC") == 0 || + strcmp((char *)info->name, "IOT2050-ADVANCED") == 0); } static bool board_is_m2(void) { struct iot2050_info *info = IOT2050_INFO_DATA; - return !board_is_sr1() && info->magic == IOT2050_INFO_MAGIC && + return info->magic == IOT2050_INFO_MAGIC && strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0; } @@ -217,14 +218,14 @@ void set_board_info_env(void) } if (board_is_advanced()) { - if (board_is_sr1()) + if (board_is_pg1()) fdtfile = "ti/k3-am6548-iot2050-advanced.dtb"; else if(board_is_m2()) fdtfile = "ti/k3-am6548-iot2050-advanced-m2.dtb"; else fdtfile = "ti/k3-am6548-iot2050-advanced-pg2.dtb"; } else { - if (board_is_sr1()) + if (board_is_pg1()) fdtfile = "ti/k3-am6528-iot2050-basic.dtb"; else fdtfile = "ti/k3-am6528-iot2050-basic-pg2.dtb"; diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile index 3e3394a8656..e94456ab1c3 100644 --- a/board/siemens/pxm2/Makefile +++ b/board/siemens/pxm2/Makefile @@ -7,7 +7,7 @@ # # Based on: # u-boot:/board/ti/am335x/Makefile -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ ifdef CONFIG_SPL_BUILD obj-y := mux.o diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 47f19bcb8fd..40aee7c8b3e 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -9,7 +9,7 @@ * * Board functions for TI AM335X based boards * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/siemens/pxm2/board.h b/board/siemens/pxm2/board.h index af21fc47432..9067e4d5aa8 100644 --- a/board/siemens/pxm2/board.h +++ b/board/siemens/pxm2/board.h @@ -9,7 +9,7 @@ * TI AM335x boards information header * u-boot:/board/ti/am335x/board.h * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _BOARD_H_ diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c index 2f35bb4a730..d21ef47771d 100644 --- a/board/siemens/pxm2/mux.c +++ b/board/siemens/pxm2/mux.c @@ -8,7 +8,7 @@ * Based on: * u-boot:/board/ti/am335x/mux.c * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/siemens/pxm2/pmic.h b/board/siemens/pxm2/pmic.h index 37660460aa8..f4ce7f16b29 100644 --- a/board/siemens/pxm2/pmic.h +++ b/board/siemens/pxm2/pmic.h @@ -4,7 +4,7 @@ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. * * Based on: - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef PMIC_H #define PMIC_H diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile index 3e3394a8656..e94456ab1c3 100644 --- a/board/siemens/rut/Makefile +++ b/board/siemens/rut/Makefile @@ -7,7 +7,7 @@ # # Based on: # u-boot:/board/ti/am335x/Makefile -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ ifdef CONFIG_SPL_BUILD obj-y := mux.o diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index a8b196a65c9..bad0b71ce2d 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -7,7 +7,7 @@ * Based on: * u-boot:/board/ti/am335x/board.c * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h index af21fc47432..9067e4d5aa8 100644 --- a/board/siemens/rut/board.h +++ b/board/siemens/rut/board.h @@ -9,7 +9,7 @@ * TI AM335x boards information header * u-boot:/board/ti/am335x/board.h * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _BOARD_H_ diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c index d80120bbdd2..894a9bf1e3d 100644 --- a/board/siemens/rut/mux.c +++ b/board/siemens/rut/mux.c @@ -8,7 +8,7 @@ * Based on: * u-boot:/board/ti/am335x/mux.c * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c index c82fb5763ec..d25c24b08b3 100644 --- a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c +++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c @@ -9,7 +9,6 @@ * Timur Tabi (timur@freescale.com) */ -#include <common.h> #include <command.h> #include <env.h> #include <i2c.h> diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index 6675548c2bf..c8696270ba2 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -6,7 +6,6 @@ * Pragnesh Patel <pragnesh.patel@sifive.com> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <asm/sections.h> diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 9585944d80c..ac4415ff3bb 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -20,39 +20,18 @@ #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) struct efi_fw_image fw_images[] = { -#if CONFIG_IS_ENABLED(FWU_MULTI_BANK_UPDATE) { .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID, .fw_name = u"DEVELOPERBOX-FIP", .image_index = 1, }, -#else - { - .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID, - .fw_name = u"DEVELOPERBOX-UBOOT", - .image_index = 1, - }, - { - .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID, - .fw_name = u"DEVELOPERBOX-FIP", - .image_index = 2, - }, - { - .image_type_id = DEVELOPERBOX_OPTEE_IMAGE_GUID, - .fw_name = u"DEVELOPERBOX-OPTEE", - .image_index = 3, - }, -#endif }; struct efi_capsule_update_info update_info = { - .dfu_string = "mtd nor1=u-boot.bin raw 200000 100000;" - "fip.bin raw 180000 78000;" - "optee.bin raw 500000 100000", + .dfu_string = "mtd nor1=fip.bin raw 600000 400000", .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; - #endif /* EFI_HAVE_CAPSULE_SUPPORT */ static struct mm_region sc2a11_mem_map[] = { diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index ad5f71a2018..336f0cdfc90 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/arch/eeprom.h> +#include <asm/arch/gpio.h> #include <asm/arch/regs.h> #include <asm/arch/spl.h> #include <asm/io.h> @@ -172,10 +173,32 @@ void spl_perform_fixups(struct spl_image_info *spl_image) /* Update the memory size which read form eeprom or DT */ fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); } + +static void jh7110_jtag_init(void) +{ + /* nTRST: GPIO36 */ + SYS_IOMUX_DOEN(36, HIGH); + SYS_IOMUX_DIN(36, 4); + /* TDI: GPIO61 */ + SYS_IOMUX_DOEN(61, HIGH); + SYS_IOMUX_DIN(61, 19); + /* TMS: GPIO63 */ + SYS_IOMUX_DOEN(63, HIGH); + SYS_IOMUX_DIN(63, 20); + /* TCK: GPIO60 */ + SYS_IOMUX_DOEN(60, HIGH); + SYS_IOMUX_DIN(60, 29); + /* TDO: GPIO44 */ + SYS_IOMUX_DOEN(44, 8); + SYS_IOMUX_DOUT(44, 22); +} + int spl_board_init_f(void) { int ret; + jh7110_jtag_init(); + ret = spl_soc_init(); if (ret) { debug("JH7110 SPL init failed: %d\n", ret); diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c index 75e4d037623..95297a18357 100644 --- a/board/synopsys/axs10x/axs10x.c +++ b/board/synopsys/axs10x/axs10x.c @@ -3,7 +3,6 @@ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. */ -#include <common.h> #include <cpu_func.h> #include <dwmmc.h> #include <init.h> diff --git a/board/synopsys/emsdp/emsdp.c b/board/synopsys/emsdp/emsdp.c index a3cee23411d..adec7d32199 100644 --- a/board/synopsys/emsdp/emsdp.c +++ b/board/synopsys/emsdp/emsdp.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Synopsys, Inc. All rights reserved. */ -#include <common.h> #include <command.h> #include <cpu_func.h> #include <dwmmc.h> diff --git a/board/synopsys/hsdk/clk-lib.h b/board/synopsys/hsdk/clk-lib.h index 970bcd4a17e..e1140a10b23 100644 --- a/board/synopsys/hsdk/clk-lib.h +++ b/board/synopsys/hsdk/clk-lib.h @@ -7,7 +7,6 @@ #ifndef __BOARD_CLK_LIB_H #define __BOARD_CLK_LIB_H -#include <common.h> #include <linux/bitops.h> enum clk_ctl_ops { diff --git a/board/synopsys/hsdk/env-lib.c b/board/synopsys/hsdk/env-lib.c index d85e8167332..85a2249f17f 100644 --- a/board/synopsys/hsdk/env-lib.c +++ b/board/synopsys/hsdk/env-lib.c @@ -7,6 +7,8 @@ #include "env-lib.h" #include <env.h> #include <log.h> +#include <vsprintf.h> +#include <linux/errno.h> #include <linux/printk.h> #define MAX_CMD_LEN 25 diff --git a/board/synopsys/hsdk/env-lib.h b/board/synopsys/hsdk/env-lib.h index 48c17c4d4f6..cabca1d0f3d 100644 --- a/board/synopsys/hsdk/env-lib.h +++ b/board/synopsys/hsdk/env-lib.h @@ -7,7 +7,6 @@ #ifndef __BOARD_ENV_LIB_H #define __BOARD_ENV_LIB_H -#include <common.h> #include <config.h> #include <linux/kernel.h> diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index 6cbc89ae787..8eb10f2226f 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -4,7 +4,6 @@ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> */ -#include <common.h> #include <command.h> #include <config.h> #include <cpu_func.h> diff --git a/board/synopsys/iot_devkit/iot_devkit.c b/board/synopsys/iot_devkit/iot_devkit.c index 650958f94c2..dec49e3ce5d 100644 --- a/board/synopsys/iot_devkit/iot_devkit.c +++ b/board/synopsys/iot_devkit/iot_devkit.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Synopsys, Inc. All rights reserved. */ -#include <common.h> #include <cpu_func.h> #include <init.h> #include <malloc.h> diff --git a/board/synopsys/nsim/nsim.c b/board/synopsys/nsim/nsim.c index 00e5cc36414..5953b365fd2 100644 --- a/board/synopsys/nsim/nsim.c +++ b/board/synopsys/nsim/nsim.c @@ -3,7 +3,6 @@ * Copyright (C) 2020 Synopsys, Inc. All rights reserved. */ -#include <common.h> #include <init.h> #include <dm/device.h> #include <virtio_types.h> diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c index 839a692ce85..3f7d42f3eb8 100644 --- a/board/tcl/sl50/board.c +++ b/board/tcl/sl50/board.c @@ -4,7 +4,7 @@ * * Board functions for TCL SL50 board * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/tcl/sl50/board.h b/board/tcl/sl50/board.h index b8b9ed7e71c..e6246772a59 100644 --- a/board/tcl/sl50/board.h +++ b/board/tcl/sl50/board.h @@ -4,7 +4,7 @@ * * TCL SL50 boards information header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _BOARD_H_ diff --git a/board/tcl/sl50/mux.c b/board/tcl/sl50/mux.c index b0a1dad3aa7..ab9088145ab 100644 --- a/board/tcl/sl50/mux.c +++ b/board/tcl/sl50/mux.c @@ -2,7 +2,7 @@ /* * mux.c * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/theobroma-systems/ringneck_px30/ringneck-px30.c b/board/theobroma-systems/ringneck_px30/ringneck-px30.c index bb1bb4acf5c..537ce0d1d11 100644 --- a/board/theobroma-systems/ringneck_px30/ringneck-px30.c +++ b/board/theobroma-systems/ringneck_px30/ringneck-px30.c @@ -16,12 +16,14 @@ #include <usb.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/setup.h> #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/periph.h> #include <asm/arch-rockchip/misc.h> +#include <linux/delay.h> #include <power/regulator.h> #include <u-boot/sha256.h> @@ -169,3 +171,54 @@ int misc_init_r(void) return 0; } + +#define STM32_RST 100 /* GPIO3_A4 */ +#define STM32_BOOT 101 /* GPIO3_A5 */ + +void spl_board_init(void) +{ + /* + * Glitches on STM32_BOOT and STM32_RST lines during poweroff or power + * on may put the STM32 companion microcontroller into DFU mode, let's + * always reset it into normal mode instead. + * Toggling the STM32_RST line is safe to do with the ATtiny companion + * microcontroller variant because it will not trigger an MCU reset + * since only a UPDI reset command will. Since a UPDI reset is difficult + * to mistakenly trigger, glitches to the lines are theoretically also + * incapable of triggering an actual ATtiny reset. + */ + int ret; + + ret = gpio_request(STM32_RST, "STM32_RST"); + if (ret) { + debug("Failed to request STM32_RST\n"); + return; + } + + ret = gpio_request(STM32_BOOT, "STM32_BOOT"); + if (ret) { + debug("Failed to request STM32_BOOT\n"); + return; + } + + /* Rely on HW pull-down for inactive level */ + ret = gpio_direction_input(STM32_BOOT); + if (ret) { + debug("Failed to configure STM32_BOOT as input\n"); + return; + } + + ret = gpio_direction_output(STM32_RST, 0); + if (ret) { + debug("Failed to configure STM32_RST as output low\n"); + return; + } + + mdelay(1); + + ret = gpio_direction_output(STM32_RST, 1); + if (ret) { + debug("Failed to configure STM32_RST as output high\n"); + return; + } +} diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile index 3ccf66be5bb..2b1e21a1788 100644 --- a/board/ti/am335x/Makefile +++ b/board/ti/am335x/Makefile @@ -2,7 +2,7 @@ # # Makefile # -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index ecb9fa02de5..34f987c2b72 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -4,7 +4,7 @@ * * Board functions for TI AM335X based boards * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h index c2962111c1a..1284c160d81 100644 --- a/board/ti/am335x/board.h +++ b/board/ti/am335x/board.h @@ -4,7 +4,7 @@ * * TI AM335x boards information header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _BOARD_H_ diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 7d31adec142..0bad154f86e 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -1,7 +1,7 @@ /* * mux.c * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile index 8dc1d89e3ac..b618f632eff 100644 --- a/board/ti/am43xx/Makefile +++ b/board/ti/am43xx/Makefile @@ -2,7 +2,7 @@ # # Makefile # -# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 58bfe7cd455..ea0d0b92088 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -4,7 +4,7 @@ * * Board functions for TI AM43XX based boards * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h index 06b737445d4..37a169aaf75 100644 --- a/board/ti/am43xx/board.h +++ b/board/ti/am43xx/board.h @@ -5,7 +5,7 @@ * TI AM437x boards information header * Derived from AM335x board. * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _BOARD_H_ diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c index f59e93a0ebb..463f1cc7178 100644 --- a/board/ti/am43xx/mux.c +++ b/board/ti/am43xx/mux.c @@ -2,7 +2,7 @@ /* * mux.c * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 9ea507a8e96..b004a89bb32 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com * * Author: Felipe Balbi <balbi@ti.com> * diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index 54b7050a459..f2f428ef9b8 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com * * Author: Felipe Balbi <balbi@ti.com> * diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index 5fd19d652a6..78c7040c3da 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla <lokeshvutla@ti.com> choice diff --git a/board/ti/am65x/Makefile b/board/ti/am65x/Makefile index 94dddfcc4a5..079a86dae7f 100644 --- a/board/ti/am65x/Makefile +++ b/board/ti/am65x/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla <lokeshvutla@ti.com> # # SPDX-License-Identifier: GPL-2.0+ diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 8bb13ef5b2b..9de3ddaa280 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -2,7 +2,7 @@ /* * Board specific initialization for AM654 EVM * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> * */ diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 3172d87b465..26bf12e2e6d 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o obj-${CONFIG_CMD_EXTENSION} += cape_detect.o diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index ac39b25cd42..0ec6d1aaf4c 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -2,7 +2,7 @@ /* * Library to support early TI EVM EEPROM handling * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla * Steve Kipisz */ diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h index de7cb52dfcd..ca1aa80f2f0 100644 --- a/board/ti/common/board_detect.h +++ b/board/ti/common/board_detect.h @@ -2,7 +2,7 @@ /* * Library to support early TI EVM EEPROM handling * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com */ #ifndef __BOARD_DETECT_H diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index e6cb21f77bd..9505330ef30 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla <lokeshvutla@ti.com> choice diff --git a/board/ti/j721e/Makefile b/board/ti/j721e/Makefile index 97535f5d86d..6e910546756 100644 --- a/board/ti/j721e/Makefile +++ b/board/ti/j721e/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/ # Lokesh Vutla <lokeshvutla@ti.com> # # SPDX-License-Identifier: GPL-2.0+ diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index d4f7c1d9f93..c13c6b2533a 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -2,7 +2,7 @@ /* * Board specific initialization for J721E EVM * - * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> * */ diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 7795300abc8..01eb4965d92 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -2,7 +2,7 @@ /* * Board specific initialization for J721S2 EVM * - * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ * David Huang <d-huang@ti.com> * */ diff --git a/board/vscom/baltos/Makefile b/board/vscom/baltos/Makefile index 3ccf66be5bb..2b1e21a1788 100644 --- a/board/vscom/baltos/Makefile +++ b/board/vscom/baltos/Makefile @@ -2,7 +2,7 @@ # # Makefile # -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y := mux.o diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index 8f23cda8e4f..bc7dc5888f2 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -4,7 +4,7 @@ * * Board functions for TI AM335X based boards * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h index 630c9bba73b..db6e19123ae 100644 --- a/board/vscom/baltos/board.h +++ b/board/vscom/baltos/board.h @@ -4,7 +4,7 @@ * * TI AM335x boards information header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ */ #ifndef _BOARD_H_ diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c index e01899c83a9..7b99cf0e182 100644 --- a/board/vscom/baltos/mux.c +++ b/board/vscom/baltos/mux.c @@ -1,7 +1,7 @@ /* * mux.c * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index a427ac94a17..2b035d53589 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -10,7 +10,6 @@ * header files */ -#include <common.h> #include <config.h> #include <env.h> #include <init.h> diff --git a/boot/Kconfig b/boot/Kconfig index a01e6cb8aaf..fbc49c5bca4 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -685,6 +685,38 @@ config LEGACY_IMAGE_FORMAT loaded. If a board needs the legacy image format support in this case, enable it here. +config MEASURED_BOOT + bool "Measure boot images and configuration when booting without EFI" + depends on HASH && TPM_V2 + help + This option enables measurement of the boot process when booting + without UEFI . Measurement involves creating cryptographic hashes + of the binary images that are booting and storing them in the TPM. + In addition, a log of these hashes is stored in memory for the OS + to verify the booted images and configuration. Enable this if the + OS has configured some memory area for the event log and you intend + to use some attestation tools on your system. + +if MEASURED_BOOT + config MEASURE_DEVICETREE + bool "Measure the devicetree image" + default y if MEASURED_BOOT + help + On some platforms, the devicetree is not static as it may contain + random MAC addresses or other such data that changes each boot. + Therefore, it should not be measured into the TPM. In that case, + disable the measurement here. + + config MEASURE_IGNORE_LOG + bool "Ignore the existing event log" + default n + help + On platforms that use an event log memory region that persists + through system resets and are the first stage bootloader, then + this option should be enabled to ignore any existing data in the + event log memory region. +endif # MEASURED_BOOT + config SUPPORT_RAW_INITRD bool "Enable raw initrd images" help diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 44ae98a9269..4926a50da85 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -784,7 +784,7 @@ static int bootdev_hunt_drv(struct bootdev_hunter *info, uint seq, bool show) if (info->hunt) { ret = info->hunt(info, show); log_debug(" - hunt result %d\n", ret); - if (ret) + if (ret && ret != -ENOENT) return ret; } std->hunters_used |= BIT(seq); diff --git a/boot/bootflow.c b/boot/bootflow.c index be543c8588c..6922e7e0c4e 100644 --- a/boot/bootflow.c +++ b/boot/bootflow.c @@ -752,7 +752,7 @@ int cmdline_set_arg(char *buf, int maxlen, const char *cmdline, in_quote = false; continue; } - if (*p == '=') { + if (*p == '=' && !arg_end) { arg_end = p; val = p + 1; } else if (*p == '"') { @@ -788,7 +788,8 @@ int cmdline_set_arg(char *buf, int maxlen, const char *cmdline, } /* if this is the target arg, update it */ - if (!strncmp(from, set_arg, arg_end - from)) { + if (arg_end - from == set_arg_len && + !strncmp(from, set_arg, set_arg_len)) { if (!buf) { bool has_quote = val_end[-1] == '"'; diff --git a/boot/bootm.c b/boot/bootm.c index 8f96a80d425..cb61485c226 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -23,6 +23,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <linux/sizes.h> +#include <tpm-v2.h> #if defined(CONFIG_CMD_USB) #include <usb.h> #endif @@ -673,6 +674,75 @@ int bootm_process_cmdline_env(int flags) return 0; } +int bootm_measure(struct bootm_headers *images) +{ + int ret = 0; + + /* Skip measurement if EFI is going to do it */ + if (images->os.os == IH_OS_EFI && + IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL) && + IS_ENABLED(CONFIG_BOOTM_EFI)) + return ret; + + if (IS_ENABLED(CONFIG_MEASURED_BOOT)) { + struct tcg2_event_log elog; + struct udevice *dev; + void *initrd_buf; + void *image_buf; + const char *s; + u32 rd_len; + bool ign; + + elog.log_size = 0; + ign = IS_ENABLED(CONFIG_MEASURE_IGNORE_LOG); + ret = tcg2_measurement_init(&dev, &elog, ign); + if (ret) + return ret; + + image_buf = map_sysmem(images->os.image_start, + images->os.image_len); + ret = tcg2_measure_data(dev, &elog, 8, images->os.image_len, + image_buf, EV_COMPACT_HASH, + strlen("linux") + 1, (u8 *)"linux"); + if (ret) + goto unmap_image; + + rd_len = images->rd_end - images->rd_start; + initrd_buf = map_sysmem(images->rd_start, rd_len); + ret = tcg2_measure_data(dev, &elog, 9, rd_len, initrd_buf, + EV_COMPACT_HASH, strlen("initrd") + 1, + (u8 *)"initrd"); + if (ret) + goto unmap_initrd; + + if (IS_ENABLED(CONFIG_MEASURE_DEVICETREE)) { + ret = tcg2_measure_data(dev, &elog, 0, images->ft_len, + (u8 *)images->ft_addr, + EV_TABLE_OF_DEVICES, + strlen("dts") + 1, + (u8 *)"dts"); + if (ret) + goto unmap_initrd; + } + + s = env_get("bootargs"); + if (!s) + s = ""; + ret = tcg2_measure_data(dev, &elog, 1, strlen(s) + 1, (u8 *)s, + EV_PLATFORM_CONFIG_FLAGS, + strlen(s) + 1, (u8 *)s); + +unmap_initrd: + unmap_sysmem(initrd_buf); + +unmap_image: + unmap_sysmem(image_buf); + tcg2_measurement_term(dev, &elog, ret != 0); + } + + return ret; +} + /** * Execute selected states of the bootm command. * @@ -724,6 +794,10 @@ int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc, if (!ret && (states & BOOTM_STATE_FINDOTHER)) ret = bootm_find_other(cmdtp, flag, argc, argv); + if (IS_ENABLED(CONFIG_MEASURED_BOOT) && !ret && + (states & BOOTM_STATE_MEASURE)) + bootm_measure(images); + /* Load the OS */ if (!ret && (states & BOOTM_STATE_LOADOS)) { iflag = bootm_disable_interrupts(); diff --git a/boot/bootmeth_cros.c b/boot/bootmeth_cros.c index 20e0b1e89c3..cd72db8250c 100644 --- a/boot/bootmeth_cros.c +++ b/boot/bootmeth_cros.c @@ -406,7 +406,7 @@ static int cros_read_file(struct udevice *dev, struct bootflow *bflow, return -ENOSYS; } -#if CONFIG_IS_ENABLED(BOOSTD_FULL) +#if CONFIG_IS_ENABLED(BOOTSTD_FULL) static int cros_read_all(struct udevice *dev, struct bootflow *bflow) { int ret; @@ -419,7 +419,7 @@ static int cros_read_all(struct udevice *dev, struct bootflow *bflow) return 0; } -#endif /* BOOSTD_FULL */ +#endif /* BOOTSTD_FULL */ static int cros_boot(struct udevice *dev, struct bootflow *bflow) { @@ -458,9 +458,9 @@ static struct bootmeth_ops cros_bootmeth_ops = { .read_bootflow = cros_read_bootflow, .read_file = cros_read_file, .boot = cros_boot, -#if CONFIG_IS_ENABLED(BOOSTD_FULL) +#if CONFIG_IS_ENABLED(BOOTSTD_FULL) .read_all = cros_read_all, -#endif /* BOOSTD_FULL */ +#endif /* BOOTSTD_FULL */ }; static const struct udevice_id cros_bootmeth_ids[] = { diff --git a/boot/bootmeth_efi_mgr.c b/boot/bootmeth_efi_mgr.c index e9d973429f7..e6c42d41fb8 100644 --- a/boot/bootmeth_efi_mgr.c +++ b/boot/bootmeth_efi_mgr.c @@ -14,6 +14,8 @@ #include <bootmeth.h> #include <command.h> #include <dm.h> +#include <efi_loader.h> +#include <efi_variable.h> /** * struct efi_mgr_priv - private info for the efi-mgr driver @@ -46,13 +48,26 @@ static int efi_mgr_check(struct udevice *dev, struct bootflow_iter *iter) static int efi_mgr_read_bootflow(struct udevice *dev, struct bootflow *bflow) { struct efi_mgr_priv *priv = dev_get_priv(dev); + efi_status_t ret; + efi_uintn_t size; + u16 *bootorder; if (priv->fake_dev) { bflow->state = BOOTFLOWST_READY; return 0; } - /* To be implemented */ + ret = efi_init_obj_list(); + if (ret) + return log_msg_ret("init", ret); + + /* Enable this method if the "BootOrder" UEFI exists. */ + bootorder = efi_get_var(u"BootOrder", &efi_global_variable_guid, + &size); + if (bootorder) { + bflow->state = BOOTFLOWST_READY; + return 0; + } return -EINVAL; } diff --git a/boot/fdt_support.c b/boot/fdt_support.c index 5e49078f8c3..b15d07765fe 100644 --- a/boot/fdt_support.c +++ b/boot/fdt_support.c @@ -2095,7 +2095,7 @@ int fdt_overlay_apply_verbose(void *fdt, void *fdto) printf("failed on fdt_overlay_apply(): %s\n", fdt_strerror(err)); if (!has_symbols) { - printf("base fdt does did not have a /__symbols__ node\n"); + printf("base fdt does not have a /__symbols__ node\n"); printf("make sure you've compiled with -@\n"); } } diff --git a/cmd/Kconfig b/cmd/Kconfig index 5bc0a92d57a..df6d71c103f 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -246,7 +246,6 @@ config CMD_BOOTM_PRE_LOAD bool "enable pre-load on bootm" depends on CMD_BOOTM depends on IMAGE_PRE_LOAD - default n help Enable support of stage pre-load for the bootm command. This stage allow to check or modify the image provided @@ -1314,6 +1313,13 @@ config CMD_BKOPS_ENABLE on a eMMC device. The feature is optionally available on eMMC devices conforming to standard >= 4.41. +config CMD_MMC_REG + bool "Enable support for reading card registers in the mmc command" + depends on CMD_MMC + help + Enable the commands for reading card registers. This is useful + mostly for debugging or extracting details from the card. + config CMD_MMC_RPMB bool "Enable support for RPMB in the mmc command" depends on SUPPORT_EMMC_RPMB @@ -1568,6 +1574,14 @@ config CMD_USB_SDP Enables the command "sdp" which is used to have U-Boot emulating the Serial Download Protocol (SDP) via USB. +config CMD_RKMTD + bool "rkmtd" + select RKMTD + help + Enable the command "rkmtd" to create a virtual block device to transfer + Rockchip boot block data to and from NAND with block orientated tools + like "ums" and "rockusb". + config CMD_ROCKUSB bool "rockusb" depends on USB_FUNCTION_ROCKUSB @@ -1826,6 +1840,10 @@ config BOOTP_PXE_CLIENTARCH default 0x15 if ARM default 0x0 if X86 +config BOOTP_PXE_DHCP_OPTION + bool "Request & store 'pxe_configfile' from BOOTP/DHCP server" + depends on BOOTP_PXE + config BOOTP_VCI_STRING string depends on CMD_BOOTP @@ -2352,7 +2370,6 @@ config CMD_VIDCONSOLE config CMD_SELECT_FONT bool "select font size" depends on VIDEO - default n help Enabling this will provide 'font' command. Allows font selection at runtime. @@ -2872,7 +2889,6 @@ config CMD_UBIFS config MMC_SPEED_MODE_SET bool "set speed mode using mmc command" depends on CMD_MMC - default n help Enable setting speed mode using mmc rescan and mmc dev commands. The speed mode is provided as the last argument in these commands diff --git a/cmd/Makefile b/cmd/Makefile index 44db5f22861..9a6790cc170 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -151,6 +151,7 @@ obj-$(CONFIG_CMD_REISER) += reiser.o obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o obj-$(CONFIG_CMD_RNG) += rng.o obj-$(CONFIG_CMD_KASLRSEED) += kaslrseed.o +obj-$(CONFIG_CMD_RKMTD) += rkmtd.o obj-$(CONFIG_CMD_ROCKUSB) += rockusb.o obj-$(CONFIG_CMD_RTC) += rtc.o obj-$(CONFIG_SANDBOX) += host.o diff --git a/cmd/booti.c b/cmd/booti.c index 1d531bdd065..a6c7db272c5 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -127,6 +127,7 @@ int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH BOOTM_STATE_RAMDISK | #endif + BOOTM_STATE_MEASURE | BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO, &images, 1); diff --git a/cmd/bootm.c b/cmd/bootm.c index 3e504ccfe81..6ded091dd55 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -147,6 +147,8 @@ int do_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) BOOTM_STATE_OS_GO; if (IS_ENABLED(CONFIG_SYS_BOOT_RAMDISK_HIGH)) states |= BOOTM_STATE_RAMDISK; + if (IS_ENABLED(CONFIG_MEASURED_BOOT)) + states |= BOOTM_STATE_MEASURE; if (IS_ENABLED(CONFIG_PPC) || IS_ENABLED(CONFIG_MIPS)) states |= BOOTM_STATE_OS_CMDLINE; ret = do_bootm_states(cmdtp, flag, argc, argv, states, &images, 1); diff --git a/cmd/bootz.c b/cmd/bootz.c index 742889f21de..dd6fe4904b0 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -81,6 +81,7 @@ int do_bootz(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH BOOTM_STATE_RAMDISK | #endif + BOOTM_STATE_MEASURE | BOOTM_STATE_OS_PREP | BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO, &images, 1); diff --git a/cmd/cbfs.c b/cmd/cbfs.c index 8a61f2c26f9..3cfc9eb2727 100644 --- a/cmd/cbfs.c +++ b/cmd/cbfs.c @@ -118,7 +118,7 @@ static int do_cbfs_ls(struct cmd_tbl *cmdtp, int flag, int argc, case CBFS_TYPE_CBFSHEADER: type_name = "cbfs header"; break; - case CBFS_TYPE_STAGE: + case CBFS_TYPE_LEGACY_STAGE: type_name = "stage"; break; case CBFS_TYPE_PAYLOAD: diff --git a/cmd/mmc.c b/cmd/mmc.c index c6bd81cebbc..96befb27eec 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -1110,6 +1110,93 @@ static int do_mmc_boot_wp(struct cmd_tbl *cmdtp, int flag, return CMD_RET_SUCCESS; } +#if CONFIG_IS_ENABLED(CMD_MMC_REG) +static int do_mmc_reg(struct cmd_tbl *cmdtp, int flag, + int argc, char *const argv[]) +{ + ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); + struct mmc *mmc; + int i, ret; + u32 off; + + if (argc < 3 || argc > 5) + return CMD_RET_USAGE; + + mmc = find_mmc_device(curr_device); + if (!mmc) { + printf("no mmc device at slot %x\n", curr_device); + return CMD_RET_FAILURE; + } + + if (IS_SD(mmc)) { + printf("SD registers are not supported\n"); + return CMD_RET_FAILURE; + } + + off = simple_strtoul(argv[3], NULL, 10); + if (!strcmp(argv[2], "cid")) { + if (off > 3) + return CMD_RET_USAGE; + printf("CID[%i]: 0x%08x\n", off, mmc->cid[off]); + if (argv[4]) + env_set_hex(argv[4], mmc->cid[off]); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "csd")) { + if (off > 3) + return CMD_RET_USAGE; + printf("CSD[%i]: 0x%08x\n", off, mmc->csd[off]); + if (argv[4]) + env_set_hex(argv[4], mmc->csd[off]); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "dsr")) { + printf("DSR: 0x%08x\n", mmc->dsr); + if (argv[4]) + env_set_hex(argv[4], mmc->dsr); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "ocr")) { + printf("OCR: 0x%08x\n", mmc->ocr); + if (argv[4]) + env_set_hex(argv[4], mmc->ocr); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "rca")) { + printf("RCA: 0x%08x\n", mmc->rca); + if (argv[4]) + env_set_hex(argv[4], mmc->rca); + return CMD_RET_SUCCESS; + } + if (!strcmp(argv[2], "extcsd") && + mmc->version >= MMC_VERSION_4_41) { + ret = mmc_send_ext_csd(mmc, ext_csd); + if (ret) + return CMD_RET_FAILURE; + if (!strcmp(argv[3], "all")) { + /* Dump the entire register */ + printf("EXT_CSD:"); + for (i = 0; i < MMC_MAX_BLOCK_LEN; i++) { + if (!(i % 10)) + printf("\n%03i: ", i); + printf(" %02x", ext_csd[i]); + } + printf("\n"); + return CMD_RET_SUCCESS; + } + off = simple_strtoul(argv[3], NULL, 10); + if (off > 512) + return CMD_RET_USAGE; + printf("EXT_CSD[%i]: 0x%02x\n", off, ext_csd[off]); + if (argv[4]) + env_set_hex(argv[4], ext_csd[off]); + return CMD_RET_SUCCESS; + } + + return CMD_RET_FAILURE; +} +#endif + static struct cmd_tbl cmd_mmc[] = { U_BOOT_CMD_MKENT(info, 1, 0, do_mmcinfo, "", ""), U_BOOT_CMD_MKENT(read, 4, 1, do_mmc_read, "", ""), @@ -1142,6 +1229,9 @@ static struct cmd_tbl cmd_mmc[] = { U_BOOT_CMD_MKENT(bkops-enable, 2, 0, do_mmc_bkops_enable, "", ""), U_BOOT_CMD_MKENT(bkops, 4, 0, do_mmc_bkops, "", ""), #endif +#if CONFIG_IS_ENABLED(CMD_MMC_REG) + U_BOOT_CMD_MKENT(reg, 5, 0, do_mmc_reg, "", ""), +#endif }; static int do_mmcops(struct cmd_tbl *cmdtp, int flag, int argc, @@ -1230,6 +1320,12 @@ U_BOOT_CMD( "mmc bkops <dev> [auto|manual] [enable|disable]\n" " - configure background operations handshake on device\n" #endif +#if CONFIG_IS_ENABLED(CMD_MMC_REG) + "mmc reg read <reg> <offset> [env] - read card register <reg> offset <offset>\n" + " (optionally into [env] variable)\n" + " - reg: cid/csd/dsr/ocr/rca/extcsd\n" + " - offset: for cid/csd [0..3], for extcsd [0..511,all]\n" +#endif ); /* Old command kept for compatibility. Same as 'mmc info' */ diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index ca24a5c1c4b..744b1c20aa8 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -240,9 +240,16 @@ static int mmc_burn_image(size_t image_size) #endif /* SD reserves LBA-0 for MBR and boots from LBA-1, - * MMC/eMMC boots from LBA-0 + * MMC/eMMC boots from LBA-0 and LBA-4096 */ - start_lba = IS_SD(mmc) ? 1 : 0; + if (IS_SD(mmc)) + start_lba = 1; +#ifdef CONFIG_SUPPORT_EMMC_BOOT + else if (part) + start_lba = 0; +#endif + else + start_lba = 4096; #ifdef CONFIG_BLK blk_count = image_size / mmc->write_bl_len; if (image_size % mmc->write_bl_len) diff --git a/cmd/pstore.c b/cmd/pstore.c index cd6f6feb2fd..9795eea2dbc 100644 --- a/cmd/pstore.c +++ b/cmd/pstore.c @@ -486,6 +486,8 @@ void fdt_fixup_pstore(void *blob) { char node[32]; int nodeoffset; /* node offset from libfdt */ + u32 addr_cells_root; + u32 size_cells_root; u32 addr_cells; u32 size_cells; @@ -495,6 +497,8 @@ void fdt_fixup_pstore(void *blob) log_err("fdt_path_offset() returned %s\n", fdt_strerror(nodeoffset)); return; } + addr_cells_root = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#address-cells", 2); + size_cells_root = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#size-cells", 2); nodeoffset = fdt_find_or_add_subnode(blob, nodeoffset, "reserved-memory"); if (nodeoffset < 0) { @@ -503,8 +507,10 @@ void fdt_fixup_pstore(void *blob) return; } - addr_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#address-cells", 2); - size_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0, "#size-cells", 2); + addr_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0, + "#address-cells", addr_cells_root); + size_cells = fdt_getprop_u32_default_node(blob, nodeoffset, 0, + "#size-cells", size_cells_root); fdt_setprop_u32(blob, nodeoffset, "#address-cells", addr_cells); fdt_setprop_u32(blob, nodeoffset, "#size-cells", size_cells); diff --git a/cmd/pxe.c b/cmd/pxe.c index 704589702f2..21134eb7a30 100644 --- a/cmd/pxe.c +++ b/cmd/pxe.c @@ -141,6 +141,14 @@ int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep, bool use_ipv6) env_get("bootfile"), use_ipv6)) return -ENOMEM; + if (IS_ENABLED(CONFIG_BOOTP_PXE_DHCP_OPTION) && + pxelinux_configfile && !use_ipv6) { + if (pxe_dhcp_option_path(&ctx, pxefile_addr_r) > 0) + goto done; + + goto error_exit; + } + if (IS_ENABLED(CONFIG_DHCP6_PXE_DHCP_OPTION) && pxelinux_configfile && use_ipv6) { if (pxe_dhcp_option_path(&ctx, pxefile_addr_r) > 0) diff --git a/cmd/remoteproc.c b/cmd/remoteproc.c index ca3b436242a..ea8724a187d 100644 --- a/cmd/remoteproc.c +++ b/cmd/remoteproc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2015 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> #include <command.h> diff --git a/cmd/rkmtd.c b/cmd/rkmtd.c new file mode 100644 index 00000000000..5b80427cb94 --- /dev/null +++ b/cmd/rkmtd.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Driver interface derived from: + * /cmd/host.c + * Copyright (c) 2012, Google Inc. + * + * Copyright (C) 2023 Johan Jonker <jbx6244@gmail.com> + */ + +#include <common.h> +#include <blk.h> +#include <command.h> +#include <dm.h> +#include <rkmtd.h> +#include <stdio.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> + +static int do_rkmtd_bind(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + const char *label; + int ret; + + argc--; + argv++; + + if (argc < 1) + return CMD_RET_USAGE; + + if (argc > 1) + return CMD_RET_USAGE; + + label = argv[0]; + ret = rkmtd_create_attach_mtd(label, &dev); + if (ret) { + printf("Cannot create device / bind mtd\n"); + return CMD_RET_FAILURE; + } + + return 0; +} + +static struct udevice *parse_rkmtd_label(const char *label) +{ + struct udevice *dev; + + dev = rkmtd_find_by_label(label); + if (!dev) { + int devnum; + char *ep; + + devnum = hextoul(label, &ep); + if (*ep || + uclass_find_device_by_seq(UCLASS_RKMTD, devnum, &dev)) { + printf("No such device '%s'\n", label); + return NULL; + } + } + + return dev; +} + +static int do_rkmtd_unbind(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + const char *label; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + + label = argv[1]; + dev = parse_rkmtd_label(label); + if (!dev) + return CMD_RET_FAILURE; + + ret = rkmtd_detach(dev); + if (ret) { + printf("Cannot detach mtd\n"); + return CMD_RET_FAILURE; + } + + ret = device_unbind(dev); + if (ret) { + printf("Cannot unbind device '%s'\n", dev->name); + return CMD_RET_FAILURE; + } + + return 0; +} + +static void show_rkmtd_dev(struct udevice *dev) +{ + struct rkmtd_dev *plat = dev_get_plat(dev); + struct blk_desc *desc; + struct udevice *blk; + int ret; + + printf("%3d ", dev_seq(dev)); + + ret = blk_get_from_parent(dev, &blk); + if (ret) + return; + + desc = dev_get_uclass_plat(blk); + printf("%12lu %-15s\n", (unsigned long)desc->lba, plat->label); +} + +static int do_rkmtd_info(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + + if (argc < 1) + return CMD_RET_USAGE; + + dev = NULL; + if (argc >= 2) { + dev = parse_rkmtd_label(argv[1]); + if (!dev) + return CMD_RET_FAILURE; + } + + printf("%3s %12s %-15s\n", "dev", "blocks", "label"); + if (dev) { + show_rkmtd_dev(dev); + } else { + struct uclass *uc; + + uclass_id_foreach_dev(UCLASS_RKMTD, dev, uc) + show_rkmtd_dev(dev); + } + + return 0; +} + +static int do_rkmtd_dev(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + const char *label; + + if (argc < 1 || argc > 3) + return CMD_RET_USAGE; + + if (argc == 1) { + struct rkmtd_dev *plat; + + dev = rkmtd_get_cur_dev(); + if (!dev) { + printf("No current rkmtd device\n"); + return CMD_RET_FAILURE; + } + plat = dev_get_plat(dev); + printf("Current rkmtd device: %d: %s\n", dev_seq(dev), + plat->label); + return 0; + } + + label = argv[1]; + dev = parse_rkmtd_label(argv[1]); + if (!dev) + return CMD_RET_FAILURE; + + rkmtd_set_cur_dev(dev); + + return 0; +} + +static struct cmd_tbl cmd_rkmtd_sub[] = { + U_BOOT_CMD_MKENT(bind, 4, 0, do_rkmtd_bind, "", ""), + U_BOOT_CMD_MKENT(unbind, 4, 0, do_rkmtd_unbind, "", ""), + U_BOOT_CMD_MKENT(info, 3, 0, do_rkmtd_info, "", ""), + U_BOOT_CMD_MKENT(dev, 0, 1, do_rkmtd_dev, "", ""), +}; + +static int do_rkmtd(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct cmd_tbl *c; + + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_rkmtd_sub, ARRAY_SIZE(cmd_rkmtd_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + rkmtd, 8, 1, do_rkmtd, + "Rockchip MTD sub-system", + "bind <label> - bind RKMTD device\n" + "rkmtd unbind <label> - unbind RKMTD device\n" + "rkmtd info [<label>] - show all available RKMTD devices\n" + "rkmtd dev [<label>] - show or set current RKMTD device\n" +); @@ -604,7 +604,7 @@ static int do_spi_flash(struct cmd_tbl *cmdtp, int flag, int argc, ret = do_spi_flash_read_write(argc, argv); else if (strcmp(cmd, "erase") == 0) ret = do_spi_flash_erase(argc, argv); - else if (strcmp(cmd, "protect") == 0) + else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0) ret = do_spi_protect(argc, argv); else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test")) ret = do_spi_flash_test(argc, argv); @@ -629,8 +629,10 @@ U_BOOT_LONGHELP(sf, "sf update addr offset|partition len - erase and write `len' bytes from memory\n" " at `addr' to flash at `offset'\n" " or to start of mtd `partition'\n" +#ifdef CONFIG_SPI_FLASH_LOCK "sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n" " at address 'sector'" +#endif #ifdef CONFIG_CMD_SF_TEST "\nsf test offset len - run a very basic destructive test" #endif diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile index 87f85b2c232..5f9c64f598a 100644 --- a/cmd/ti/Makefile +++ b/cmd/ti/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ obj-$(CONFIG_CMD_DDR3) += ddr3.o obj-$(CONFIG_CMD_PD) += pd.o diff --git a/cmd/ufs.c b/cmd/ufs.c index 143e946370f..282b4146e92 100644 --- a/cmd/ufs.c +++ b/cmd/ufs.c @@ -2,7 +2,7 @@ /** * ufs.c - UFS specific U-Boot commands * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * */ #include <common.h> diff --git a/common/Kconfig b/common/Kconfig index 93c96f23b01..0f548195197 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -28,26 +28,26 @@ config CONSOLE_RECORD_OUT_SIZE depends on CONSOLE_RECORD default 0x400 if CONSOLE_RECORD help - Set the size of the console output buffer. When this fills up, no - more data will be recorded until some is removed. The buffer is - allocated immediately after the malloc() region is ready. + Set the size of the console recording output buffer. When this fills + up, no more data will be recorded until some is removed. The buffer + is allocated immediately after the malloc() region is ready. config CONSOLE_RECORD_OUT_SIZE_F hex "Output buffer size before relocation" depends on CONSOLE_RECORD default 0x400 if CONSOLE_RECORD help - Set the size of the console output buffer before relocation. When - this fills up, no more data will be recorded until some is removed. - The buffer is allocated immediately after the early malloc() region is - ready. + Set the size of the console recording output buffer before + relocation. When this fills up, no more data will be recorded until + some is removed. The buffer is allocated immediately after the early + malloc() region is ready. config CONSOLE_RECORD_IN_SIZE hex "Input buffer size" depends on CONSOLE_RECORD default 0x100 if CONSOLE_RECORD help - Set the size of the console input buffer. When this contains data, + Set the size of the console recording input buffer. When this contains data, tstc() and getc() will use this in preference to real device input. The buffer is allocated immediately after the malloc() region is ready. @@ -224,6 +224,16 @@ config CONSOLE_FLUSH_SUPPORT help This enables compilation of flush() function for console flush support. +config CONSOLE_FLUSH_ON_NEWLINE + bool "Flush console buffer on every newline character" + depends on DM_SERIAL + help + This makes the serial core code flush the console device + whenever a newline (\n) character has been emitted. This can + be especially useful when "printf debugging", as otherwise + lots of output could still be in the UART's FIFO by the time + one hits the code which causes the CPU to hang or reset. + config CONSOLE_MUX bool "Enable console multiplexing" default y if VIDEO || LCD diff --git a/common/cli_getch.c b/common/cli_getch.c index 61d4cb261b8..0ee79087774 100644 --- a/common/cli_getch.c +++ b/common/cli_getch.c @@ -46,6 +46,8 @@ static int cli_ch_esc(struct cli_ch_state *cch, int ichar, case 1: if (ichar == '[' || ichar == 'O') act = ESC_SAVE; + else + act = ESC_CONVERTED; break; case 2: switch (ichar) { diff --git a/common/spl/Makefile b/common/spl/Makefile index 4f8eb2ec0ca..4809f9c3ec1 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2012 -# Texas Instruments Incorporated - http://www.ti.com/ +# Texas Instruments Incorporated - https://www.ti.com/ # Aneesh V <aneesh@ti.com> # Based on common/Makefile. # diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 0b01368d9de..82689da1401 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -365,10 +365,22 @@ int __weak spl_mmc_boot_partition(const u32 boot_device) } #endif +unsigned long __weak arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect) +{ + return raw_sect; +} + +unsigned long __weak board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect) +{ + return arch_spl_mmc_get_uboot_raw_sector(mmc, raw_sect); +} + unsigned long __weak spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) { - return raw_sect; + return board_spl_mmc_get_uboot_raw_sector(mmc, raw_sect); } int default_spl_mmc_emmc_boot_partition(struct mmc *mmc) diff --git a/configs/ad401_defconfig b/configs/ad401_defconfig index b9aca3ab0db..b44b9c63e83 100644 --- a/configs/ad401_defconfig +++ b/configs/ad401_defconfig @@ -51,6 +51,7 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC_A1=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_GADGET=y diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 8c32b4b20dd..6cfb5a7d321 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -58,6 +58,7 @@ CONFIG_MMC_SDHCI_NPCM=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHY_BROADCOM=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/bananapi-cm4-cm4io_defconfig b/configs/bananapi-cm4-cm4io_defconfig index bb43cc41e5f..116147fc9af 100644 --- a/configs/bananapi-cm4-cm4io_defconfig +++ b/configs/bananapi-cm4-cm4io_defconfig @@ -17,12 +17,17 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -37,6 +42,7 @@ CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y CONFIG_BUTTON_ADC=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y diff --git a/configs/bananapi-m2-pro_defconfig b/configs/bananapi-m2-pro_defconfig index 4f8cec99565..2a3958b0fd0 100644 --- a/configs/bananapi-m2-pro_defconfig +++ b/configs/bananapi-m2-pro_defconfig @@ -16,12 +16,17 @@ CONFIG_IDENT_STRING="bpi-m2-pro" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -33,6 +38,7 @@ CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y diff --git a/configs/bananapi-m2s_defconfig b/configs/bananapi-m2s_defconfig index 3dd8ddcdca3..405ce3a93a9 100644 --- a/configs/bananapi-m2s_defconfig +++ b/configs/bananapi-m2s_defconfig @@ -18,12 +18,17 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -36,6 +41,7 @@ CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y diff --git a/configs/bananapi-m5_defconfig b/configs/bananapi-m5_defconfig index 696d2fcc5c1..6de5d5fe7bb 100644 --- a/configs/bananapi-m5_defconfig +++ b/configs/bananapi-m5_defconfig @@ -16,12 +16,17 @@ CONFIG_IDENT_STRING="bpi-m5" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -33,6 +38,7 @@ CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y diff --git a/configs/beelink-gsking-x_defconfig b/configs/beelink-gsking-x_defconfig index c0220973902..99e36e970a1 100644 --- a/configs/beelink-gsking-x_defconfig +++ b/configs/beelink-gsking-x_defconfig @@ -17,12 +17,17 @@ CONFIG_IDENT_STRING=" beelink" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -32,6 +37,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/beelink-gt1-ultimate_defconfig b/configs/beelink-gt1-ultimate_defconfig index c0d22c41472..1313dde92f5 100644 --- a/configs/beelink-gt1-ultimate_defconfig +++ b/configs/beelink-gt1-ultimate_defconfig @@ -16,6 +16,10 @@ CONFIG_IDENT_STRING=" beelink-gt1" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y @@ -23,6 +27,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -33,6 +38,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig index 42e1ba65602..5c21d8eeabe 100644 --- a/configs/beelink-gtking_defconfig +++ b/configs/beelink-gtking_defconfig @@ -17,12 +17,17 @@ CONFIG_IDENT_STRING=" beelink" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -32,6 +37,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig index a3713326c1c..37bb4cde792 100644 --- a/configs/beelink-gtkingpro_defconfig +++ b/configs/beelink-gtkingpro_defconfig @@ -17,12 +17,17 @@ CONFIG_IDENT_STRING=" beelink" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -32,6 +37,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index cb06db61fba..3c3f6d55d50 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -96,7 +96,6 @@ CONFIG_NETCONSOLE=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_OF_TRANSLATE is not set -# CONFIG_SPL_BLK is not set CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_MMC_OMAP_HS=y diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig index 074936d575a..3cd6aa09245 100644 --- a/configs/corstone1000_defconfig +++ b/configs/corstone1000_defconfig @@ -14,7 +14,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" -CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" +CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r $filesize; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" CONFIG_CONSOLE_RECORD=y CONFIG_LOGLEVEL=7 # CONFIG_DISPLAY_CPUINFO is not set @@ -55,6 +55,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_USB=y diff --git a/configs/eDPU_defconfig b/configs/eDPU_defconfig index f51df7861a2..aef75c7780a 100644 --- a/configs/eDPU_defconfig +++ b/configs/eDPU_defconfig @@ -20,6 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DEFAULT_ENV_IS_RW=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="eDPU>> " diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 02254ef7088..21c657a441c 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_TIME=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y -# CONFIG_SPL_BLK is not set CONFIG_CLK=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/grouper_common_defconfig b/configs/grouper_common_defconfig index 54256ca97b5..258d7b1139c 100644 --- a/configs/grouper_common_defconfig +++ b/configs/grouper_common_defconfig @@ -59,8 +59,6 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_GPIO_HOG=y CONFIG_SYS_I2C_TEGRA=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_GPIO=y CONFIG_BUTTON_KEYBOARD=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig index ed53c11ad03..0b3259866e7 100644 --- a/configs/imx28_xea_sb_defconfig +++ b/configs/imx28_xea_sb_defconfig @@ -68,7 +68,6 @@ CONFIG_HOSTNAME="xea" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_DEVRES=y -# CONFIG_SPL_BLK is not set CONFIG_MXS_GPIO=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_MXS=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 47e62bef378..9ced5ed0f65 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -81,6 +81,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y +CONFIG_ADC=y CONFIG_ADC_IMX93=y CONFIG_SPL_CLK_IMX93=y CONFIG_CLK_IMX93=y diff --git a/configs/inteno_xg6846_ram_defconfig b/configs/inteno_xg6846_ram_defconfig new file mode 100644 index 00000000000..00fe36da687 --- /dev/null +++ b/configs/inteno_xg6846_ram_defconfig @@ -0,0 +1,73 @@ +CONFIG_MIPS=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_TEXT_BASE=0x81c00000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="inteno,xg6846" +CONFIG_DM_RESET=y +CONFIG_IDENT_STRING="Inteno XG6846" +CONFIG_SYS_LOAD_ADDR=0x81000000 +CONFIG_ARCH_BMIPS=y +CONFIG_SOC_BMIPS_BCM6328=y +CONFIG_SYS_MIPS_TIMER_FREQ=160000000 +CONFIG_MIPS_CACHE_SETUP=y +CONFIG_MIPS_CACHE_DISABLE=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REMAKE_ELF=y +CONFIG_BOOTDELAY=1 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Boot XG6846 in %d seconds\n" +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="sf probe; sf read 0x81000000 0x40000 0x500000; bootm 0x81000000" +CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="XG6846 # " +CONFIG_SYS_MAXARGS=24 +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=541 +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +CONFIG_SYS_BOOTM_LEN=0x1000000 +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_SPI=y +# CONFIG_CMD_SLEEP is not set +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DMA=y +CONFIG_BCM6348_IUDMA=y +CONFIG_LED=y +CONFIG_LED_BCM6328=y +CONFIG_LED_BLINK=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_RESET_DELAY=20 +CONFIG_POWER_DOMAIN=y +CONFIG_BCM6328_POWER_DOMAIN=y +CONFIG_RESET_BCM6345=y +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_BCM63XX_HSSPI=y +CONFIG_LZMA=y diff --git a/configs/jethub_j100_defconfig b/configs/jethub_j100_defconfig index 549d5514f7a..1e6d5c713bd 100644 --- a/configs/jethub_j100_defconfig +++ b/configs/jethub_j100_defconfig @@ -18,6 +18,10 @@ CONFIG_IDENT_STRING=" jethubj100" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y @@ -26,6 +30,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_IMI is not set CONFIG_CMD_EEPROM=y CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_RANDOM_UUID=y CONFIG_CMD_I2C=y @@ -39,6 +44,7 @@ CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y CONFIG_MMC_MESON_GX=y diff --git a/configs/jethub_j80_defconfig b/configs/jethub_j80_defconfig index df9b8f3aedf..b370e5d1d4d 100644 --- a/configs/jethub_j80_defconfig +++ b/configs/jethub_j80_defconfig @@ -18,6 +18,10 @@ CONFIG_IDENT_STRING=" jethubj80" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set @@ -27,6 +31,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_IMI is not set CONFIG_CMD_EEPROM=y CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_RANDOM_UUID=y CONFIG_CMD_I2C=y @@ -40,6 +45,7 @@ CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y CONFIG_MMC_MESON_GX=y diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig index 38b9b2b71ce..28e90522451 100644 --- a/configs/khadas-vim2_defconfig +++ b/configs/khadas-vim2_defconfig @@ -16,6 +16,10 @@ CONFIG_IDENT_STRING=" khadas-vim2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set @@ -24,6 +28,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -36,6 +41,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index ccd6f6f8a07..b41c2660fff 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3" CONFIG_OF_LIBFDT_OVERLAY=y @@ -19,6 +20,10 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y @@ -45,7 +50,10 @@ CONFIG_CMD_AB_SELECT=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index 5c3d565971d..88197f5f5e9 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-khadas-vim3" CONFIG_OF_LIBFDT_OVERLAY=y @@ -19,6 +20,10 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y @@ -43,7 +48,10 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig index d611124325c..5df4b92143b 100644 --- a/configs/khadas-vim3_defconfig +++ b/configs/khadas-vim3_defconfig @@ -18,12 +18,17 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set @@ -41,6 +46,7 @@ CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y CONFIG_BUTTON_ADC=y +CONFIG_DFU_RAM=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y CONFIG_MMC_MESON_GX=y diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index 0d6de800138..3381d2e9270 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l" CONFIG_OF_LIBFDT_OVERLAY=y @@ -19,6 +20,10 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y @@ -45,7 +50,10 @@ CONFIG_CMD_AB_SELECT=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index 827752f2437..3fa587ef1db 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x0 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-khadas-vim3l" CONFIG_OF_LIBFDT_OVERLAY=y @@ -19,6 +20,10 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y @@ -43,7 +48,10 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig index f959d33689f..de8fdd83cce 100644 --- a/configs/khadas-vim3l_defconfig +++ b/configs/khadas-vim3l_defconfig @@ -18,12 +18,17 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set @@ -41,6 +46,7 @@ CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y CONFIG_BUTTON_ADC=y +CONFIG_DFU_RAM=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y CONFIG_MMC_MESON_GX=y diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig index 6a9e8516163..d27ab6f5907 100644 --- a/configs/khadas-vim_defconfig +++ b/configs/khadas-vim_defconfig @@ -16,6 +16,10 @@ CONFIG_IDENT_STRING=" khadas-vim" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set @@ -24,6 +28,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -34,6 +39,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_MESON_GXL=y CONFIG_DM_MDIO=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 1aab1575911..8d3f1a7b098 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -45,7 +45,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y -# CONFIG_SPL_BLK is not set CONFIG_CLK=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index 0fa7f3de79b..bc17b423a2d 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -19,6 +19,10 @@ CONFIG_IDENT_STRING=" libretech-ac" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -28,6 +32,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -41,6 +46,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig index dee03b3c5f2..baa9b1b3dbc 100644 --- a/configs/libretech-cc_defconfig +++ b/configs/libretech-cc_defconfig @@ -16,6 +16,10 @@ CONFIG_IDENT_STRING=" libretech-cc" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y @@ -23,6 +27,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -33,6 +38,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_MESON_GXL=y CONFIG_DM_MDIO=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index 628c6bab388..ba74b241ab9 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -18,6 +18,10 @@ CONFIG_IDENT_STRING=" libretech-cc-v2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -26,6 +30,7 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -37,6 +42,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig index 1c8787c8abf..cd138d696e7 100644 --- a/configs/libretech-s905d-pc_defconfig +++ b/configs/libretech-s905d-pc_defconfig @@ -19,6 +19,10 @@ CONFIG_IDENT_STRING=" libretech-s905d-pc" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -27,6 +31,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -39,6 +44,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig index 170492eb3f3..dabb4ca4ece 100644 --- a/configs/libretech-s912-pc_defconfig +++ b/configs/libretech-s912-pc_defconfig @@ -18,6 +18,10 @@ CONFIG_IDENT_STRING=" libretech-s912-pc" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set @@ -26,6 +30,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -38,6 +43,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig index fe57fd1892d..954870bff82 100644 --- a/configs/mt7620_rfb_defconfig +++ b/configs/mt7620_rfb_defconfig @@ -54,7 +54,6 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y # CONFIG_SIMPLE_BUS is not set # CONFIG_SPL_SIMPLE_BUS is not set -# CONFIG_SPL_BLK is not set CONFIG_GPIO_HOG=y # CONFIG_INPUT is not set CONFIG_MMC=y diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 829567014fd..e6fb80167a6 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -22,6 +22,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DEFAULT_ENV_IS_RW=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_MAXARGS=32 diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 6c68c239e25..8e79fc7ce93 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -24,6 +24,7 @@ CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DEFAULT_ENV_IS_RW=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig new file mode 100644 index 00000000000..070399ce2a8 --- /dev/null +++ b/configs/nanopc-t6-rk3588_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_NANOPCT6_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_ERRNO_STR=y diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig index ef101cf430d..41dbf7981f8 100644 --- a/configs/nanopi-k2_defconfig +++ b/configs/nanopi-k2_defconfig @@ -15,6 +15,10 @@ CONFIG_IDENT_STRING=" nanopi-k2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index ff4895622cb..038ef42e9d8 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -19,7 +19,8 @@ CONFIG_DEBUG_UART_CLOCK=166666667 CONFIG_IDENT_STRING="\nZyXEL NSA310S/320S 1/2-Bay Power Media Server" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 9481cbc42be..5f9f323e06e 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -15,6 +15,10 @@ CONFIG_IDENT_STRING=" odroid-c2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig index 315dc5cadb3..fe1f8612580 100644 --- a/configs/odroid-c4_defconfig +++ b/configs/odroid-c4_defconfig @@ -17,12 +17,17 @@ CONFIG_IDENT_STRING=" odroid-c4/hc4" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -34,6 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig index fb8ce5ccada..bc0bf9b8961 100644 --- a/configs/odroid-go-ultra_defconfig +++ b/configs/odroid-go-ultra_defconfig @@ -17,11 +17,16 @@ CONFIG_IDENT_STRING=" odroid-go-ultra" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -37,6 +42,7 @@ CONFIG_SARADC_MESON=y CONFIG_BUTTON=y CONFIG_BUTTON_ADC=y CONFIG_BUTTON_GPIO=y +CONFIG_DFU_RAM=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y CONFIG_MMC_MESON_GX=y diff --git a/configs/odroid-hc4_defconfig b/configs/odroid-hc4_defconfig index b2507150c7f..43168115889 100644 --- a/configs/odroid-hc4_defconfig +++ b/configs/odroid-hc4_defconfig @@ -19,12 +19,17 @@ CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -41,6 +46,7 @@ CONFIG_SARADC_MESON=y CONFIG_SATA=y CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig index e55de380a41..9694f04a66e 100644 --- a/configs/odroid-n2_defconfig +++ b/configs/odroid-n2_defconfig @@ -17,12 +17,17 @@ CONFIG_IDENT_STRING=" odroid-n2/n2-plus" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -34,6 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_MDIO=y diff --git a/configs/odroid-n2l_defconfig b/configs/odroid-n2l_defconfig index 983ac883ecc..673e0cffb24 100644 --- a/configs/odroid-n2l_defconfig +++ b/configs/odroid-n2l_defconfig @@ -17,12 +17,17 @@ CONFIG_IDENT_STRING=" odroid-n2l" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -34,6 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MESON_G12A_USB_PHY=y CONFIG_PINCTRL=y diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig new file mode 100644 index 00000000000..04736996217 --- /dev/null +++ b/configs/orangepi-5-plus-rk3588_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-orangepi-5-plus" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-plus.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig new file mode 100644 index 00000000000..feb45a53853 --- /dev/null +++ b/configs/orangepi-5-rk3588s_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-orangepi-5" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/p200_defconfig b/configs/p200_defconfig index 42e7eb855e5..cd579ef5f14 100644 --- a/configs/p200_defconfig +++ b/configs/p200_defconfig @@ -15,6 +15,10 @@ CONFIG_IDENT_STRING=" p200" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/p201_defconfig b/configs/p201_defconfig index 5c983751d05..b2f0a0ccdb4 100644 --- a/configs/p201_defconfig +++ b/configs/p201_defconfig @@ -16,6 +16,10 @@ CONFIG_IDENT_STRING=" p201" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/p212_defconfig b/configs/p212_defconfig index 2fcf3b30f4f..b90391d9b5f 100644 --- a/configs/p212_defconfig +++ b/configs/p212_defconfig @@ -16,6 +16,10 @@ CONFIG_IDENT_STRING=" p212" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index 2747c3c72d9..ff6411d8949 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -17,7 +17,8 @@ CONFIG_IDENT_STRING="\nPogoplug V4" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_PCI=y CONFIG_LTO=y -CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_BOOTDELAY=10 diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index fbe84d57029..de7267e228e 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -21,7 +21,6 @@ CONFIG_BOOTCOMMAND="test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $ # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y -CONFIG_SYS_PBSIZE=276 CONFIG_CMD_REGINFO=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 9ace68e73f1..cf74a48ea2c 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -12,8 +12,6 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 0c7389e2f91..aeef2f35b0e 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -13,8 +13,6 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index e63d6fd9346..db9c971c2f7 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -19,8 +19,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 9a8bbef192b..9fb40b22f9b 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -12,8 +12,6 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 1d0f021adeb..e3b123ca4d1 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -15,8 +15,6 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index b048bb8aed0..d6bf3130fe3 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -18,8 +18,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_SYS_MALLOC=y -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=276 CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index f02e9125a6d..2ff49fbd6ac 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -46,7 +46,6 @@ CONFIG_SPL_NET=y CONFIG_SPL_PCI=y CONFIG_SPL_PCH=y CONFIG_SPL_RTC=y -CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 4b2787d4aae..246ac6b6b8a 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -24,7 +24,6 @@ CONFIG_LOG=y CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_PCI_INIT_R=y -CONFIG_SYS_PBSIZE=532 CONFIG_CMD_CPU=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 5fdf496a459..c010c25a928 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -27,8 +27,6 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_PCI_INIT_R=y -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 1347b86f34b..9cc1f5f7c40 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -28,8 +28,6 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_PCI_INIT_R=y -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig new file mode 100644 index 00000000000..d6b35c72647 --- /dev/null +++ b/configs/quartzpro64-rk3588_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZPRO64_RK3588=y +CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig index a905100a794..2dfff6af3bd 100644 --- a/configs/radxa-e25-rk3568_defconfig +++ b/configs/radxa-e25-rk3568_defconfig @@ -54,7 +54,6 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y -CONFIG_AHCI_PCI=y CONFIG_DWC_AHCI=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/radxa-zero2_defconfig b/configs/radxa-zero2_defconfig index b1aa3c27f83..e9415762ff3 100644 --- a/configs/radxa-zero2_defconfig +++ b/configs/radxa-zero2_defconfig @@ -16,12 +16,17 @@ CONFIG_IDENT_STRING=" radxa-zero2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -32,6 +37,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/radxa-zero_defconfig b/configs/radxa-zero_defconfig index 23f30f6b113..103ff8a321d 100644 --- a/configs/radxa-zero_defconfig +++ b/configs/radxa-zero_defconfig @@ -16,12 +16,17 @@ CONFIG_IDENT_STRING=" radxa-zero" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -32,6 +37,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index b4666d0e90f..b314636b4d9 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x4000000 CONFIG_SPL_BSS_MAX_SIZE=0x4000 +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set @@ -53,6 +54,7 @@ CONFIG_SPL_ATF=y # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig index bccdb1e3ecd..a6471a51951 100644 --- a/configs/rock5a-rk3588s_defconfig +++ b/configs/rock5a-rk3588s_defconfig @@ -39,13 +39,16 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y @@ -61,12 +64,23 @@ CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PHY_REALTEK=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y -CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y CONFIG_ERRNO_STR=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 447913faccc..0595325e810 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_PCI=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y @@ -35,7 +36,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y @@ -63,6 +63,8 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y CONFIG_SPL_CLK=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y @@ -89,6 +91,8 @@ CONFIG_SPL_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y @@ -97,7 +101,6 @@ CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y -# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/s400_defconfig b/configs/s400_defconfig index 9a7d520f905..8e22c95f882 100644 --- a/configs/s400_defconfig +++ b/configs/s400_defconfig @@ -16,12 +16,17 @@ CONFIG_IDENT_STRING=" s400" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -31,6 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE_MESON8B=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 1a033b22018..6c488bac2b3 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -50,7 +50,6 @@ CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_LOADM=y -CONFIG_CMD_MBR=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_READ=y @@ -58,6 +57,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_TEMPERATURE=y CONFIG_CMD_USB=y +CONFIG_CMD_RKMTD=y CONFIG_CMD_WDT=y CONFIG_CMD_WRITE=y CONFIG_CMD_CAT=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 47417cb0391..bc5bcb2a623 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -14,6 +14,7 @@ CONFIG_FIT_RSASSA_PSS=y CONFIG_FIT_CIPHER=y CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_MEASURED_BOOT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y @@ -73,8 +74,6 @@ CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y CONFIG_CMD_LOADM=y CONFIG_CMD_LSBLK=y -CONFIG_CMD_MBR=y -CONFIG_CMD_MMC=y CONFIG_CMD_MUX=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y @@ -84,6 +83,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_TEMPERATURE=y CONFIG_CMD_USB=y +CONFIG_CMD_RKMTD=y CONFIG_CMD_WDT=y CONFIG_CMD_WRITE=y CONFIG_CMD_AXI=y @@ -241,6 +241,7 @@ CONFIG_PINCTRL_SANDBOX=y CONFIG_PINCTRL_SINGLE=y CONFIG_POWER_DOMAIN=y CONFIG_SANDBOX_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y CONFIG_DM_PMIC_PFUZE100=y @@ -337,7 +338,6 @@ CONFIG_CMD_DHRYSTONE=y CONFIG_ECDSA=y CONFIG_ECDSA_VERIFY=y CONFIG_TPM=y -CONFIG_SHA384=y CONFIG_ERRNO_STR=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 29ae4532c50..0b637727d9f 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -43,14 +43,14 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_MBR=y -CONFIG_CMD_MMC=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y +CONFIG_CMD_READ=y CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_TEMPERATURE=y CONFIG_CMD_USB=y +CONFIG_CMD_WRITE=y CONFIG_BOOTP_DNS2=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TFTPSRV=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index db05e630832..cd412ee2693 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -80,7 +80,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_MBR=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 56072b15ad2..eeccee62b8c 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -66,7 +66,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_MBR=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index 5bd0281796d..293e294d57a 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -74,7 +74,6 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y -CONFIG_CMD_MBR=y CONFIG_CMD_OSD=y CONFIG_CMD_PCI=y CONFIG_CMD_REMOTEPROC=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index 63e4ebe649a..c4a49fbd6f0 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -21,6 +21,10 @@ CONFIG_IDENT_STRING=" sei510" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run load_logo" @@ -34,6 +38,7 @@ CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set CONFIG_CMD_BCB=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y # CONFIG_CMD_LOADS is not set @@ -49,6 +54,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x6000000 CONFIG_FASTBOOT_FLASH=y diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index ff7bcb330e6..ae254c62f2a 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -21,6 +21,10 @@ CONFIG_IDENT_STRING=" sei610" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run load_logo" @@ -34,6 +38,7 @@ CONFIG_CMD_ADTIMG=y CONFIG_CMD_ABOOTIMG=y # CONFIG_CMD_IMI is not set CONFIG_CMD_BCB=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y # CONFIG_CMD_LOADS is not set @@ -49,6 +54,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x6000000 CONFIG_FASTBOOT_FLASH=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 157391a71c0..b8052f1deea 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -73,7 +73,6 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y -# CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_BOOTCOUNT=y CONFIG_DM_BOOTCOUNT_RTC=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index b21754feafc..b15e7d24db1 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -120,6 +120,8 @@ CONFIG_SPL_PINCTRL_STARFIVE=y CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y CONFIG_PINCTRL_STARFIVE=y # CONFIG_RAM_SIFIVE is not set +CONFIG_DM_RNG=y +CONFIG_RNG_JH7110=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_TIMER_EARLY=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index b6cd0a47fa7..1d241529be7 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -25,6 +25,8 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=1441792 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000 @@ -76,7 +78,10 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_WGET=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -101,6 +106,8 @@ CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index d1acf9c657e..6e0c4a8cf9f 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -23,6 +23,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_ARMV7_VIRT is not set CONFIG_SYS_LOAD_ADDR=0xc2000000 +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=1441792 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000 @@ -74,7 +76,10 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_TFTPPUT=y CONFIG_SYS_DISABLE_AUTOLOAD=y +CONFIG_CMD_WGET=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -99,6 +104,8 @@ CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="192.168.1.1" +CONFIG_PROT_TCP_SACK=y +CONFIG_IPV6=y CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig index 8e03a606589..092c0aa2b01 100644 --- a/configs/transformer_t30_defconfig +++ b/configs/transformer_t30_defconfig @@ -20,7 +20,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_KEYED_CTRLC=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="setenv gpio_button 150; if run check_button; then poweroff; fi; setenv gpio_button 131; if run check_button; then bootmenu; fi; run bootcmd_mmc1; run bootcmd_mmc0; poweroff;" +CONFIG_BOOTCOMMAND="setenv skip_boot 0; setenv gpio_button 150; if run check_button; then poweroff; fi; setenv gpio_button 131; if run check_button; then bootmenu; fi; if test ${skip_boot} -eq 1; then; else run bootcmd_usb0; run bootcmd_mmc1; run bootcmd_mmc0; poweroff; fi" CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x8000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index e0ca6337bd6..c9815b612f0 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -52,9 +52,10 @@ CONFIG_CMD_HASH=y CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y +CONFIG_OF_LIST="armada-3720-turris-mox armada-3720-ripe-atlas" CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NETCONSOLE=y diff --git a/configs/u200_defconfig b/configs/u200_defconfig index a841a663633..21c90e7678e 100644 --- a/configs/u200_defconfig +++ b/configs/u200_defconfig @@ -16,12 +16,17 @@ CONFIG_IDENT_STRING=" u200" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -31,6 +36,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_DM_MDIO=y CONFIG_DM_MDIO_MUX=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 988f9ed0d84..6c48b33dca1 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -20,6 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DEFAULT_ENV_IS_RW=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="uDPU>> " diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index bb20a2227f6..eec1d964b91 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -79,6 +79,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_READ=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -108,6 +109,12 @@ CONFIG_BOOTCOUNT_ENV=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y CONFIG_FSL_CAAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y @@ -138,6 +145,7 @@ CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y @@ -160,14 +168,20 @@ CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_EHCI_HCD=y -CONFIG_MXC_USB_OTG_HACTIVE=y +# CONFIG_USB_EHCI_MX7 is not set CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_IMX_WATCHDOG=y CONFIG_HEXDUMP=y diff --git a/configs/videostrong-kii-pro_defconfig b/configs/videostrong-kii-pro_defconfig index 4a2ff343850..3eda8f14a21 100644 --- a/configs/videostrong-kii-pro_defconfig +++ b/configs/videostrong-kii-pro_defconfig @@ -14,6 +14,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" kii-pro" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig index 324062e4fa8..9bf3de9e7aa 100644 --- a/configs/wetek-core2_defconfig +++ b/configs/wetek-core2_defconfig @@ -16,6 +16,10 @@ CONFIG_IDENT_STRING=" wetek-core2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y @@ -23,6 +27,7 @@ CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set CONFIG_CMD_ADC=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y @@ -33,6 +38,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SARADC_MESON=y +CONFIG_DFU_RAM=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/wetek-hub_defconfig b/configs/wetek-hub_defconfig index 4091a19713a..fd92b041e73 100644 --- a/configs/wetek-hub_defconfig +++ b/configs/wetek-hub_defconfig @@ -14,6 +14,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" wetek-hub" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/wetek-play2_defconfig b/configs/wetek-play2_defconfig index 3ef43909007..b887419a6ba 100644 --- a/configs/wetek-play2_defconfig +++ b/configs/wetek-play2_defconfig @@ -14,6 +14,10 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_IDENT_STRING=" wetek-play2" CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_MISC_INIT_R=y diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig index 389ca50703e..539ce2d3c08 100644 --- a/configs/xilinx_versal_mini_ospi_defconfig +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_PROMPT="Versal> " CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +# CONFIG_SPI_FLASH_LOCK is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig index 5724aa3040f..336aa8548e9 100644 --- a/configs/xilinx_versal_mini_qspi_defconfig +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -61,6 +61,7 @@ CONFIG_SYS_PROMPT="Versal> " # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_LOCK is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y diff --git a/configs/xilinx_versal_net_mini_ospi_defconfig b/configs/xilinx_versal_net_mini_ospi_defconfig index 0656b23ae17..db3e7c80b2e 100644 --- a/configs/xilinx_versal_net_mini_ospi_defconfig +++ b/configs/xilinx_versal_net_mini_ospi_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_PROMPT="Versal NET> " CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SOFT_RESET=y CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +# CONFIG_SPI_FLASH_LOCK is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/xilinx_versal_net_mini_qspi_defconfig b/configs/xilinx_versal_net_mini_qspi_defconfig index c0e9ba9f76f..37b3e769836 100644 --- a/configs/xilinx_versal_net_mini_qspi_defconfig +++ b/configs/xilinx_versal_net_mini_qspi_defconfig @@ -60,6 +60,7 @@ CONFIG_SYS_PROMPT="Versal NET> " # CONFIG_MMC is not set CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_LOCK is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index ccc9431ca83..0553ac6b17c 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -85,6 +85,7 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 CONFIG_MTD=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index b588887fa3b..6a2c03ccdd0 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -6,6 +6,7 @@ CONFIG_ARCH_VERSAL=y CONFIG_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x100000 CONFIG_NR_DRAM_BANKS=36 +CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 817fb4142d1..c3ee9beaef2 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -126,6 +126,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index a1adfb9e5d1..4a74ca76a28 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -77,6 +77,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y # CONFIG_DM_MAILBOX is not set # CONFIG_MMC is not set # CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_LOCK is not set # CONFIG_SPI_FLASH_UNLOCK_ALL is not set CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y diff --git a/disk/part.c b/disk/part.c index 85244b09f35..36b88205eca 100644 --- a/disk/part.c +++ b/disk/part.c @@ -197,6 +197,7 @@ void dev_print(struct blk_desc *desc) case UCLASS_PVBLOCK: case UCLASS_HOST: case UCLASS_BLKMAP: + case UCLASS_RKMTD: printf ("Vendor: %s Rev: %s Prod: %s\n", desc->vendor, desc->revision, @@ -330,6 +331,9 @@ static void print_part_header(const char *type, struct blk_desc *desc) case UCLASS_PVBLOCK: puts("PV BLOCK"); break; + case UCLASS_RKMTD: + puts("RKMTD"); + break; case UCLASS_VIRTIO: puts("VirtIO"); break; diff --git a/disk/part_dos.c b/disk/part_dos.c index 33374384373..567ead7511d 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -466,7 +466,7 @@ int layout_mbr_partitions(struct disk_partition *p, int count, ext = &p[i]; } - if (count < 4) + if (count <= 4) return 0; if (!ext) { diff --git a/doc/README.davinci b/doc/README.davinci index f368f99a41e..ea81279a0f3 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -70,7 +70,7 @@ http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development- 2) TI OMAP-L138 LCDK http://focus.ti.com/docs/prod/folders/print/omap-l138.html -http://www.ti.com/tool/TMDXLCDK138 +https://www.ti.com/tool/TMDXLCDK138 Davinci special defines ======================= diff --git a/doc/README.omap3 b/doc/README.omap3 index 3a1ac8101d6..d1e6be94a11 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -163,8 +163,8 @@ Links [1] OMAP3: -http://www.ti.com/omap3 (high volume) and -http://www.ti.com/omap35x (broad market) +https://www.ti.com/omap3 (high volume) and +https://www.ti.com/omap35x (broad market) [2] OMAP3530 BeagleBoard: diff --git a/doc/README.serial_dt_baud b/doc/README.serial_dt_baud new file mode 100644 index 00000000000..f8768d0e1bc --- /dev/null +++ b/doc/README.serial_dt_baud @@ -0,0 +1,41 @@ +Fetch serial baudrate from DT +----------------------------- + +To support fetching of baudrate from DT, the following is done:- + +The baudrate configured in Kconfig symbol CONFIG_BAUDRATE is taken by default by serial. +If change of baudrate is required then the Kconfig symbol CONFIG_BAUDRATE needs to +changed and U-Boot recompilation is required or the U-Boot environment needs to be updated. + +To avoid this, add support to fetch the baudrate directly from the device tree file and +update the environment. + +The default environment stores the default baudrate value. When default baudrate and dtb +baudrate are not same glitches are seen on the serial. +So, the environment also needs to be updated with the dtb baudrate to avoid the glitches on +the serial which is enabled by OF_SERIAL_BAUD. + +The Kconfig SPL_ENV_SUPPORT needs to be enabled to allow patching in SPL. + +The Kconfig DEFAULT_ENV_IS_RW which is enabled by OF_SERIAL_BAUD with making the environment +writable. + +The ofnode_read_baud() function parses and fetches the baudrate value from the DT. This value +is validated and updated to baudrate during serial init. Padding is added at the end of the +default environment and the dt baudrate is updated with the latest value. + +Example:- + +The serial port options are of the form "bbbbpnf", where "bbbb" is the baud rate, "p" is parity ("n", "o", or "e"), +"n" is number of bits, and "f" is flow control ("r" for RTS or omit it). Default is "115200n8". + +chosen { + bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/ram0 rw init_fatal_sh=1"; + stdout-path = "serial0:115200n8"; + }; + +From the chosen node, stdout-path property is obtained as string. + + stdout-path = "serial0:115200n8"; + +The string is parsed to get the baudrate 115200. This string is converted to integer and updated to the environment. diff --git a/doc/api/index.rst b/doc/api/index.rst index 2f0218c47a3..51b2013af36 100644 --- a/doc/api/index.rst +++ b/doc/api/index.rst @@ -12,6 +12,7 @@ U-Boot API documentation efi event getopt + interrupt linker_lists lmb logging diff --git a/doc/api/interrupt.rst b/doc/api/interrupt.rst new file mode 100644 index 00000000000..5721231d919 --- /dev/null +++ b/doc/api/interrupt.rst @@ -0,0 +1,6 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Interrupt API +============= + +.. kernel-doc:: include/interrupt.h diff --git a/doc/board/rockchip/index.rst b/doc/board/rockchip/index.rst index 0c377e9bbba..9a87a035e95 100644 --- a/doc/board/rockchip/index.rst +++ b/doc/board/rockchip/index.rst @@ -8,3 +8,4 @@ Rockchip :maxdepth: 2 rockchip + rkmtd diff --git a/doc/board/rockchip/rkmtd.rst b/doc/board/rockchip/rkmtd.rst new file mode 100644 index 00000000000..1481380ba6c --- /dev/null +++ b/doc/board/rockchip/rkmtd.rst @@ -0,0 +1,105 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2023 Johan Jonker <jbx6244@gmail.com> + +RKMTD +===== + +Info +---- + +The command rkmtd creates a virtual block device to transfer +Rockchip boot block data to and from NAND with block orientated +tools like "ums" and "rockusb". + +It uses the Rockchip MTD driver to scan for boot blocks and copies +data from the first block in a GPT formatted virtual disk. +Data must be written in U-boot "idbloader.img" format and start at +partition "loader1" offset 64. The data header is parsed +for length and offset. When the last sector is received +it erases up to 5 erase blocks on NAND and writes boot blocks +in a pattern depending on the NAND ID. Data is then verified. +When a block turns out bad the block header is discarded. + +Limitations +----------- + +- Support with CONFIG_ROCKCHIP_NAND MTD driver only. +- Support for Rockchip boot block header type 1 only. +- Pattern for listed NAND IDs only. (Logic still not disclosed by Rockchip) +- The MTD framework driver data and NAND ID must be extracted at a lower level. + +Available rkmtd commands +------------------------ + +.. code-block:: bash + + rkmtd bind <label> - bind RKMTD device + rkmtd unbind <label> - unbind RKMTD device + rkmtd info [<label>] - show all available RKMTD devices + rkmtd dev [<label>] - show or set current RKMTD device + +U-boot settings +--------------- + +Config to enable Rockchip MTD support: + +.. code-block:: bash + + CONFIG_MTD=y + CONFIG_MTD_RAW_NAND=y + CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT=y + CONFIG_SYS_NAND_USE_FLASH_BBT=y + CONFIG_ROCKCHIP_NAND=y + +Option to keep existing NAND data unchanged: + +.. code-block:: bash + + CONFIG_ROCKCHIP_NAND_SKIP_BBTSCAN=y + +Commands to enable: + +.. code-block:: bash + + CONFIG_CMD_USB=y + CONFIG_CMD_RKMTD=y + CONFIG_CMD_ROCKUSB=y + CONFIG_CMD_USB_MASS_STORAGE=y + +Linux Host (PC) tool commands combinations that work +---------------------------------------------------- + +.. table:: + :widths: 20 44 + + ==================== ============================================ + U-boot Linux + ==================== ============================================ + rkmtd bind 0 + rockusb 0 rkmtd 0 + upgrade_tool pl + + upgrade_tool rl 64 512 idbloader_backup.img + + upgrade_tool wl 64 idbloader.img + + upgrade_tool rd + + rkdeveloptool ppt + + rkdeveloptool rl 64 512 idbloader_backup.img + + rkdeveloptool wlx loader1 idbloader.img + + rkdeveloptool wl 64 idbloader.img + + rkdeveloptool rd + + rkflashtool r 64 512 > idbloader_backup.img + + rkflashtool w 64 512 < idbloader.img + ums 0 rkmtd 0 + dd if=/dev/sda1 of=idbloader_backup.img + + dd if=idbloader.img of=/dev/sda1 + ==================== ============================================ diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 8262fc0d32c..18d0b6f0891 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -115,8 +115,12 @@ List of mainline supported Rockchip boards: - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) + - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588) + - Pine64 QuartzPro64 (quartzpro64-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) + - Xunlong Orange Pi 5 (orangepi-5-rk3588s) + - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) * rv1108 - Rockchip Evb-rv1108 (evb-rv1108) diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst index aa7080e26cd..46712c379b6 100644 --- a/doc/board/socionext/developerbox.rst +++ b/doc/board/socionext/developerbox.rst @@ -42,9 +42,10 @@ Compile from source You can build U-Boot without any additinal source code.:: cd u-boot + git checkout v2023.07 export ARCH=arm64 export CROSS_COMPILE=aarch64-linux-gnu- - make SynQuacer_defconfig + make synquacer_developerbox_defconfig make -j `noproc` Then, expand the binary to 1MB for preparing flash.:: @@ -211,8 +212,8 @@ can be installed via NOR flash writer. Once the flasher tool is running we are ready to flash the images.:: Write the FIP image to the Bank-0 & 1 at 6MB and 10MB offset.:: - flash rawwrite 600000 180000 - flash rawwrite a00000 180000 + flash rawwrite 600000 400000 + flash rawwrite a00000 400000 >> Send SPI_NOR_NEWFIP.fd via XMODEM (Control-A S in minicom) << flash rawwrite 500000 1000 diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst index 2ba651eb6df..4627da3bc07 100644 --- a/doc/board/ti/am335x_evm.rst +++ b/doc/board/ti/am335x_evm.rst @@ -59,7 +59,7 @@ from Texas Instruments. The tools used to generate boot images for secure devices are part of a secure development package (SECDEV) that can be downloaded from: - http://www.ti.com/mysecuresoftware (login required) + https://www.ti.com/mysecuresoftware (login required) The secure development package is access controlled due to NDA and export control restrictions. Access must be requested and granted by TI before the diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst index 7cebb1ca62d..bf9e4c46a41 100644 --- a/doc/board/ti/am65x_evm.rst +++ b/doc/board/ti/am65x_evm.rst @@ -22,7 +22,7 @@ cores, voltage domains and peripherals: 3. MAIN domain: * Quad core 64-bit ARM Cortex-A53 -More info can be found in TRM: http://www.ti.com/lit/pdf/spruid7 +More info can be found in TRM: https://www.ti.com/lit/pdf/spruid7 Platform information: diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index cadaac01781..cbb7da657ac 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -27,7 +27,7 @@ specific processing cores and peripherals: * 2 x C66x Digital signal processor sub system * C71x Digital signal processor sub-system with MMA. -More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1 +More info can be found in TRM: https://www.ti.com/lit/pdf/spruil1 Platform information: diff --git a/doc/board/ti/ks2_evm.rst b/doc/board/ti/ks2_evm.rst index 0a789037a6a..5e3ecad6b2e 100644 --- a/doc/board/ti/ks2_evm.rst +++ b/doc/board/ti/ks2_evm.rst @@ -17,17 +17,17 @@ Documentation for this board can be found at: The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K. More details on these SoCs are available at company websites: -K2K: http://www.ti.com/product/tci6638k2k -K2H: http://www.ti.com/product/tci6638k2h +K2K: https://www.ti.com/product/tci6638k2k +K2H: https://www.ti.com/product/tci6638k2h The K2E SoC details are available at - http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + https://www.ti.com/lit/ds/symlink/66ak2e05.pdf The K2L SoC details are available at - http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf + https://www.ti.com/lit/ds/symlink/tci6630k2l.pdf The K2G SoC details are available at - http://www.ti.com/lit/ds/symlink/66ak2g02.pdf + https://www.ti.com/lit/ds/symlink/66ak2g02.pdf Board Configuration ------------------- diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst index a0650a51db4..23501dea376 100644 --- a/doc/build/gcc.rst +++ b/doc/build/gcc.rst @@ -60,8 +60,14 @@ For building U-Boot on Alpine Linux at least the following packages are needed: .. code-block:: bash - apk add alpine-sdk bc bison dtc flex linux-headers ncurses-dev \ - openssl-dev perl python3 py3-setuptools python3-dev sdl2-dev + apk add alpine-sdk bc bison dtc flex gnutls-dev linux-headers ncurses-dev \ + openssl-dev py3-elftools py3-setuptools python3-dev swig util-linux-dev + +Depending on the build target further packages may be needed: + +* sandbox with lcd: sdl2-dev +* riscv64 S-mode targests: opensbi +* some arm64 targets: arm-trusted-firmware Prerequisites ------------- diff --git a/doc/develop/driver-model/debugging.rst b/doc/develop/driver-model/debugging.rst index bbb2794340f..e13abddae66 100644 --- a/doc/develop/driver-model/debugging.rst +++ b/doc/develop/driver-model/debugging.rst @@ -49,7 +49,7 @@ to see errors. Common ones are: of_to_plat() method in the driver. If there is no error, you should check if the device is actually bound. Call -dm_dump_all() just before you locate the device to make sure it exists. +dm_dump_tree() just before you locate the device to make sure it exists. If it does not exist, check your device tree compatible strings match up with what the driver expects (in the struct udevice_id array). diff --git a/doc/develop/driver-model/remoteproc-framework.rst b/doc/develop/driver-model/remoteproc-framework.rst index 566495a21c4..03a0bd0f4b4 100644 --- a/doc/develop/driver-model/remoteproc-framework.rst +++ b/doc/develop/driver-model/remoteproc-framework.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: GPL-2.0+ .. (C) Copyright 2015 -.. Texas Instruments Incorporated - http://www.ti.com/ +.. Texas Instruments Incorporated - https://www.ti.com/ Remote Processor Framework ========================== diff --git a/doc/develop/driver-model/soc-framework.rst b/doc/develop/driver-model/soc-framework.rst index 2609fda6442..357e7fc8c90 100644 --- a/doc/develop/driver-model/soc-framework.rst +++ b/doc/develop/driver-model/soc-framework.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: GPL-2.0+ .. (C) Copyright 2020 -.. Texas Instruments Incorporated - http://www.ti.com/ +.. Texas Instruments Incorporated - https://www.ti.com/ SOC ID Framework ================ diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 72343386b50..0e753453b69 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -50,8 +50,7 @@ Current Status * U-Boot v2023.10 was released on Mon 02 October 2023. -* The Merge Window for the next release (v2024.01) is **open** until the -rc1 - release on Mon 23 October 2023. +* The Merge Window for the next release (v2024.01) is **closed**. * The next branch is now **closed**. @@ -63,11 +62,11 @@ Future Releases .. The following commented out dates are for when release candidates are planned to be tagged. -.. For the next scheduled release, release candidates were made on:: +For the next scheduled release, release candidates were made on:: -.. * U-Boot v2024.01-rc1 was released on Mon 23 October 2023. +* U-Boot v2024.01-rc1 was released on Mon 23 October 2023. -.. * U-Boot v2024.01-rc2 was released on Mon 06 November 2023. +* U-Boot v2024.01-rc2 was released on Mon 06 November 2023. .. * U-Boot v2024.01-rc3 was released on Mon 20 November 2023. diff --git a/doc/device-tree-bindings/clock/ti,cdce9xx.txt b/doc/device-tree-bindings/clock/ti,cdce9xx.txt index 0d01f2d5cc3..62701d2145d 100644 --- a/doc/device-tree-bindings/clock/ti,cdce9xx.txt +++ b/doc/device-tree-bindings/clock/ti,cdce9xx.txt @@ -4,10 +4,10 @@ Reference This binding uses the common clock binding[1]. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] http://www.ti.com/product/cdce913 -[3] http://www.ti.com/product/cdce925 -[4] http://www.ti.com/product/cdce937 -[5] http://www.ti.com/product/cdce949 +[2] https://www.ti.com/product/cdce913 +[3] https://www.ti.com/product/cdce925 +[4] https://www.ti.com/product/cdce937 +[5] https://www.ti.com/product/cdce949 The driver provides clock sources for each output Y1 through Y5. diff --git a/doc/device-tree-bindings/pmic/max77663.txt b/doc/device-tree-bindings/pmic/max77663.txt new file mode 100644 index 00000000000..ddb7d3eb143 --- /dev/null +++ b/doc/device-tree-bindings/pmic/max77663.txt @@ -0,0 +1,84 @@ +MAXIM, MAX77663 PMIC + +This device uses two drivers: +- drivers/power/pmic/max77663.c (for parent device) +- drivers/power/regulator/max77663_regulator.c (for child regulators) + +This chapter describes the binding info for the PMIC driver and regulators. + +Required properties for PMIC: +- compatible: "maxim,max77663" +- reg: usually 0x1c or 0x3c + +With those two properties, the pmic device can be used for read/write only. +To bind each regulator, the optional regulators subnode should exists. + +Optional subnode: +- name: regulators (subnode list of each device's regulator) + +Regulators subnode contains set on supported regulators. + +Required properties: +- regulator-name: used for regulator uclass platform data '.name', + +List of supported regulator nodes names for max77663: +- sd0, sd1, sd2, sd3, ldo0, ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8 + +Optional: +- regulator-min-microvolt: minimum allowed Voltage to set +- regulator-max-microvolt: minimum allowed Voltage to set +- regulator-always-on: regulator should be never disabled +- regulator-boot-on: regulator should be enabled by the bootloader + +Linux driver binding for this driver is compatible. + +Example: + +max77663@1c { + compatible = "maxim,max77663"; + reg = <0x1c>; + + regulators { + sd0 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + ... + + ldo0 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ... + + ldo2 { + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "vdd_sdmmc3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + ... + + ldo8 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; +}; diff --git a/doc/device-tree-bindings/pmic/tps65911.txt b/doc/device-tree-bindings/pmic/tps65911.txt new file mode 100644 index 00000000000..29270efbfe0 --- /dev/null +++ b/doc/device-tree-bindings/pmic/tps65911.txt @@ -0,0 +1,78 @@ +Texas Instruments, TPS65911 PMIC + +This device uses two drivers: +- drivers/power/pmic/tps65910.c (for parent device) +- drivers/power/regulator/tps65911_regulator.c (for child regulators) + +This chapter describes the binding info for the PMIC driver and regulators. + +Required properties for PMIC: +- compatible: "ti,tps65911" +- reg: 0x2d + +With those two properties, the pmic device can be used for read/write only. +To bind each regulator, the optional regulators subnode should exists. + +Optional subnode: +- name: regulators (subnode list of each device's regulator) + +Regulators subnode contains set on supported regulators. + +Required properties: +- regulator-name: used for regulator uclass platform data '.name', + +List of supported regulator nodes names for tps65911: +- vdd1, vdd2, vddctrl, vddio +- ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8 + +vddio in datasheet is referred as vio, but for reduction of code and +unification of smps regulators it is named vddio. + +Optional: +- regulator-min-microvolt: minimum allowed Voltage to set +- regulator-max-microvolt: minimum allowed Voltage to set +- regulator-always-on: regulator should be never disabled +- regulator-boot-on: regulator should be enabled by the bootloader + +Example: + +tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + regulators { + vdd1 { + regulator-name = "vdd_1v2_backlight"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ... + + vddio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ... + + ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + }; +}; diff --git a/doc/device-tree-bindings/pmic/tps80031.txt b/doc/device-tree-bindings/pmic/tps80031.txt new file mode 100644 index 00000000000..577e6de1c1f --- /dev/null +++ b/doc/device-tree-bindings/pmic/tps80031.txt @@ -0,0 +1,76 @@ +Texas Instruments, TPS80031/TPS80032 PMIC + +This device uses two drivers: +- drivers/power/pmic/tps80031.c (for parent device) +- drivers/power/regulator/tps80031_regulator.c (for child regulators) + +This chapter describes the binding info for the PMIC driver and regulators. + +Required properties for PMIC: +- compatible: "ti,tps80031" or "ti,tps80032" +- reg: 0x48 + +With those two properties, the pmic device can be used for read/write only. +To bind each regulator, the optional regulators subnode should exists. + +Optional subnode: +- name: regulators (subnode list of each device's regulator) + +Regulators subnode contains set on supported regulators. + +Required properties: +- regulator-name: used for regulator uclass platform data '.name', + +List of supported regulator nodes names for tps80031/tps80032: +- smps1, smps2, smps3, smps4, smps5 +- ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldoln, ldousb + +SMPS5 in Linux 3.1.10 is referred as vio, but datasheet clearly names it SMPS5. + +Optional: +- regulator-min-microvolt: minimum allowed Voltage to set +- regulator-max-microvolt: minimum allowed Voltage to set +- regulator-always-on: regulator should be never disabled +- regulator-boot-on: regulator should be enabled by the bootloader + +Example: + +tps80032@48 { + compatible = "ti,tps80032"; + reg = <0x48>; + + regulators { + smps1 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + ... + + smps5 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + ... + + ldousb { + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; +}; diff --git a/doc/device-tree-bindings/video/tilcdc/tilcdc.txt b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt index 7bf1bb44481..7600801055d 100644 --- a/doc/device-tree-bindings/video/tilcdc/tilcdc.txt +++ b/doc/device-tree-bindings/video/tilcdc/tilcdc.txt @@ -46,7 +46,7 @@ Optional nodes: crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is for Blue[3-7]. For more details see section 3.1.1 in AM335x Silicon Errata: - http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360 + https://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360 Example: diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index 6d45a3fefff..39ececb96c2 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -23,4 +23,4 @@ sphinxcontrib-htmlhelp==2.0.0 sphinxcontrib-jsmath==1.0.1 sphinxcontrib-qthelp==1.0.3 sphinxcontrib-serializinghtml==1.1.5 -urllib3==2.0.6 +urllib3==2.0.7 diff --git a/doc/usage/cmd/gpt.rst b/doc/usage/cmd/gpt.rst index f6115ecb0ee..cbbe44ab58d 100644 --- a/doc/usage/cmd/gpt.rst +++ b/doc/usage/cmd/gpt.rst @@ -156,6 +156,7 @@ read', 'gpt swap' and 'gpt rename', you must specify CONFIG_CMD_GPT_RENAME=y. Examples ~~~~~~~~ + Create 6 partitions on a disk:: => setenv gpt_parts 'uuid_disk=bec9fc2a-86c1-483d-8a0e-0109732277d7; @@ -192,10 +193,9 @@ Get the information about the partition named 'rootfs':: Get the list of partition names on the disk:: => gpt enumerate - => echo gpt_partition_list + => echo ${gpt_partition_list} boot rootfs system-data [ext] user modules ramdisk - Get the GUID for a disk:: => gpt guid mmc 0 @@ -209,6 +209,7 @@ Set the bootable flag for the 'boot' partition and clear it for all others:: => gpt set-bootable mmc 0 boot Swap the order of the 'boot' and 'rootfs' partition table entries:: + => gpt setenv mmc 0 rootfs => echo ${gpt_partition_entry} 2 diff --git a/doc/usage/cmd/mmc.rst b/doc/usage/cmd/mmc.rst index 71a0303109c..c0924ba5769 100644 --- a/doc/usage/cmd/mmc.rst +++ b/doc/usage/cmd/mmc.rst @@ -21,6 +21,7 @@ Synopsis mmc bootpart-resize <dev> <dev part size MB> <RPMB part size MB> mmc partconf <dev> [[varname] | [<boot_ack> <boot_partition> <partition_access>]] mmc rst-function <dev> <value> + mmc reg read <reg> <offset> [env] Description ----------- @@ -183,6 +184,31 @@ The 'mmc rst-function' command changes the RST_n_FUNCTION field. 0x3 Reserved +The 'mmc reg read <reg> <offset> [env]' reads eMMC card register and +either print it to standard output, or store the value in environment +variable. + +<reg> with +optional offset <offset> into the register array, and print it to +standard output or store it into environment variable [env]. + + reg + cid + The Device IDentification (CID) register. Uses offset. + csd + The Device-Specific Data (CSD) register. Uses offset. + dsr + The driver stage register (DSR). + ocr + The operation conditions register (OCR). + rca + The relative Device address (RCA) register. + extcsd + The Extended CSD register. Uses offset. + offset + For 'cid'/'csd' 128 bit registers '[0..3]' in 32-bit increments. For 'extcsd' 512 bit register '[0..512,all]' in 8-bit increments, or 'all' to read the entire register. + env + Optional environment variable into which 32-bit value read from register should be stored. Examples -------- diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst index 68cacbbef66..8845a71df36 100644 --- a/doc/usage/dfu.rst +++ b/doc/usage/dfu.rst @@ -121,6 +121,11 @@ mmc with + offset + is the offset in the device (hexadecimal without "0x") + size + is the size of the access area (hexadecimal without "0x") + or 0 which means whole device partid being the GPT or DOS partition index, num diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 98b4719c408..d8e23fcacff 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -14,6 +14,7 @@ Use U-Boot partitions cmdline semihosting + measured_boot Shell commands -------------- @@ -37,8 +38,8 @@ Shell commands cmd/bootm cmd/bootmenu cmd/bootmeth - cmd/button cmd/bootz + cmd/button cmd/cat cmd/cbsysinfo cmd/cedit @@ -56,8 +57,8 @@ Shell commands cmd/env cmd/event cmd/exception - cmd/extension cmd/exit + cmd/extension cmd/false cmd/fatinfo cmd/fatload @@ -93,15 +94,15 @@ Shell commands cmd/rng cmd/saves cmd/sbi - cmd/sf cmd/scp03 cmd/seama cmd/setexpr + cmd/sf cmd/size cmd/sleep + cmd/sm cmd/sound cmd/source - cmd/sm cmd/temperature cmd/tftpput cmd/trace diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst new file mode 100644 index 00000000000..0aad5908590 --- /dev/null +++ b/doc/usage/measured_boot.rst @@ -0,0 +1,31 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Measured Boot +===================== + +U-Boot can perform a measured boot, the process of hashing various components +of the boot process, extending the results in the TPM and logging the +component's measurement in memory for the operating system to consume. + +By default, U-Boot will measure the operating system (linux) image, the +initrd image, and the "bootargs" environment variable. By enabling +CONFIG_MEASURE_DEVICETREE, U-Boot will also measure the devicetree image. + +The operating system typically would verify that the hashes found in the +TPM PCRs match the contents of the event log. This can further be checked +against the hash results of previous boots. + +Requirements +--------------------- + +* A hardware TPM 2.0 supported by the U-Boot drivers +* CONFIG_TPM=y +* CONFIG_MEASURED_BOOT=y +* Device-tree configuration of the TPM device to specify the memory area + for event logging. The TPM device node must either contain a phandle to + a reserved memory region or "linux,sml-base" and "linux,sml-size" + indicating the address and size of the memory region. An example can be + found in arch/sandbox/dts/test.dts +* The operating system must also be configured to use the memory regions + specified in the U-Boot device-tree in order to make use of the event + log. diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index 4336732dee5..a01d73846b7 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -66,6 +66,7 @@ config STM32_ADC config ADC_IMX93 bool "Enable NXP IMX93 ADC driver" + depends on ADC help This enables basic driver for NXP IMX93 ADC. It provides: diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c index dcb5fcf476b..64fc078bada 100644 --- a/drivers/ata/sata.c +++ b/drivers/ata/sata.c @@ -65,7 +65,7 @@ int sata_rescan(bool verbose) ret = uclass_find_first_device(UCLASS_AHCI, &dev); if (ret || !dev) { printf("Cannot find SATA device (err=%d)\n", ret); - return -ENOSYS; + return -ENOENT; } ret = device_remove(dev, DM_REMOVE_NORMAL); diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 1abea3f10db..048a6caef00 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -262,3 +262,10 @@ config SYS_64BIT_LBA help Make the block subsystem use 64bit sector addresses, rather than the default of 32bit. + +config RKMTD + bool "Rockchip rkmtd virtual block device" + help + Enable "rkmtd" class and driver to create a virtual block device + to transfer Rockchip boot block data to and from NAND with block + orientate tools like "ums" and "rockusb". diff --git a/drivers/block/Makefile b/drivers/block/Makefile index a161d145fd3..fdcba5c8318 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -11,6 +11,7 @@ endif ifndef CONFIG_SPL_BUILD obj-$(CONFIG_IDE) += ide.o +obj-$(CONFIG_RKMTD) += rkmtd.o endif obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o @@ -19,3 +20,4 @@ obj-$(CONFIG_BLKMAP) += blkmap.o obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o obj-$(CONFIG_EFI_MEDIA_BLK) += efi_blk.o + diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index f126547cc7e..77066da352a 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -36,6 +36,7 @@ static struct { { UCLASS_VIRTIO, "virtio" }, { UCLASS_PVBLOCK, "pvblock" }, { UCLASS_BLKMAP, "blkmap" }, + { UCLASS_RKMTD, "rkmtd" }, }; static enum uclass_id uclass_name_to_iftype(const char *uclass_idname) @@ -440,7 +441,7 @@ long blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *buf) start, blkcnt, desc->blksz, buf)) return blkcnt; - if (IS_ENABLED(CONFIG_BOUNCE_BUFFER)) { + if (IS_ENABLED(CONFIG_BOUNCE_BUFFER) && desc->bb) { struct blk_bounce_buffer bbstate = { .dev = dev }; int ret; @@ -477,7 +478,7 @@ long blk_write(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, blkcache_invalidate(desc->uclass_id, desc->devnum); - if (IS_ENABLED(CONFIG_BOUNCE_BUFFER)) { + if (IS_ENABLED(CONFIG_BOUNCE_BUFFER) && desc->bb) { struct blk_bounce_buffer bbstate = { .dev = dev }; int ret; diff --git a/drivers/block/rkmtd.c b/drivers/block/rkmtd.c new file mode 100644 index 00000000000..c55f052e51b --- /dev/null +++ b/drivers/block/rkmtd.c @@ -0,0 +1,1152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Some functions are derived from: + * https://github.com/rockchip-linux/u-boot/blob/next-dev/drivers/rknand/rk_ftl_arm_v7.S + * Copyright (c) 2016-2018, Fuzhou Rockchip Electronics Co., Ltd + * + * Driver interface derived from: + * /drivers/block/host_dev.c + * /drivers/block/host-uclass.c + * Copyright 2022 Google LLC + * Written by Simon Glass <sjg@chromium.org> + * + * Copyright (C) 2023 Johan Jonker <jbx6244@gmail.com> + */ + +#include <blk.h> +#include <dm.h> +#include <nand.h> +#include <part.h> +#include <rkmtd.h> +#include <stddef.h> +#include <stdio.h> +#include <stdlib.h> +#include <dm/device-internal.h> +#include <dm/devres.h> +#include <dm/lists.h> +#include <dm/root.h> +#include <dm/uclass-internal.h> +#include <linux/mtd/mtd.h> +#if !IS_ENABLED(CONFIG_SANDBOX) +#include <linux/mtd/rawnand.h> +#endif +#include <u-boot/crc.h> + +struct nand_para_info nand_para_tbl[] = { + {6, {0x2c, 0x64, 0x44, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x44, 0x44, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 1064, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x68, 0x04, 0x4a, 0xa9, 0x00}, 4, 1, 8, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x88, 0x04, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xa8, 0x05, 0xcb, 0xa9, 0x00}, 4, 2, 16, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x68, 0x04, 0x46, 0x89, 0x00}, 4, 1, 8, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x48, 0x04, 0x4a, 0xa5, 0x00}, 4, 1, 8, 256, 2, 2, 1024, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x84, 0x64, 0x3c, 0xa5, 0x00}, 4, 1, 32, 512, 2, 2, 1024, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x64, 0x54, 0xa9, 0x00}, 4, 1, 32, 512, 2, 2, 1024, 0x01df, 4, 18, 60, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xd7, 0x94, 0x3e, 0x84, 0x00}, 4, 1, 8, 128, 2, 2, 4096, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x48, 0x04, 0x46, 0x85, 0x00}, 4, 1, 8, 256, 2, 2, 1024, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x88, 0x05, 0xc6, 0x89, 0x00}, 4, 2, 8, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x88, 0x24, 0x4b, 0xa9, 0x00}, 4, 1, 16, 256, 2, 2, 2048, 0x011f, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x68, 0x00, 0x27, 0xa9, 0x00}, 4, 1, 16, 128, 1, 2, 2048, 0x011f, 0, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x64, 0x64, 0x56, 0xa5, 0x00}, 4, 1, 24, 512, 2, 2, 700, 0x01df, 4, 18, 60, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0x84, 0xc5, 0x4b, 0xa9, 0x00}, 4, 2, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xd5, 0xd1, 0xa6, 0x68, 0x00}, 4, 2, 8, 64, 1, 2, 2048, 0x0117, 0, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xdc, 0x90, 0xa6, 0x54, 0x00}, 4, 1, 8, 64, 1, 2, 1024, 0x0117, 0, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x64, 0x64, 0x54, 0xa4, 0x00}, 4, 1, 32, 512, 2, 1, 1024, 0x01df, 4, 18, 60, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x44, 0x32, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x64, 0x44, 0x32, 0xa5, 0x00}, 4, 1, 32, 512, 2, 1, 1048, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x64, 0x64, 0x3c, 0xa5, 0x00}, 4, 1, 32, 512, 2, 1, 1044, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x44, 0x32, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 4, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x44, 0x34, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 4, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0xc4, 0x34, 0xaa, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x44, 0x34, 0xa4, 0x00}, 4, 1, 32, 512, 2, 1, 2184, 0x05c7, 5, 19, 60, 32, 1, 0, 1, 0, 1, {0, 0, 0, 0, 0}}, + {5, {0x2c, 0x84, 0x64, 0x3c, 0xa9, 0x00}, 4, 1, 32, 512, 2, 2, 1024, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x2c, 0xa4, 0x64, 0x32, 0xaa, 0x04}, 4, 1, 32, 1024, 2, 1, 2192, 0x05c7, 10, 19, 60, 32, 1, 0, 4, 0, 1, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x94, 0xd2, 0x04, 0x43}, 2, 1, 16, 256, 2, 2, 2048, 0x01d9, 1, 1, 24, 32, 4, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3}, 2, 1, 16, 256, 2, 2, 1024, 0x01d9, 1, 2, 40, 32, 4, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd7, 0x94, 0x91, 0x60, 0x44}, 2, 1, 16, 256, 2, 2, 1046, 0x01d9, 1, 3, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4}, 2, 1, 16, 256, 2, 2, 2090, 0x01d9, 1, 4, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x94, 0xeb, 0x74, 0x44}, 2, 1, 32, 256, 2, 2, 1066, 0x01d9, 1, 7, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd5, 0x94, 0xda, 0x74, 0xc4}, 2, 1, 16, 256, 2, 2, 530, 0x01d9, 1, 3, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd7, 0x94, 0x9a, 0x74, 0x42}, 2, 1, 16, 256, 2, 2, 1024, 0x0119, 1, 0, 24, 32, 4, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a}, 2, 1, 32, 256, 2, 2, 1060, 0x01d9, 2, 5, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd7, 0x14, 0x9e, 0x34, 0x4a}, 2, 1, 16, 256, 2, 2, 1056, 0x01d9, 2, 5, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x94, 0xa7, 0x42, 0x48}, 2, 1, 32, 256, 2, 2, 1060, 0x01d9, 2, 5, 40, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xde, 0x14, 0xab, 0x42, 0x4a}, 2, 1, 32, 256, 2, 2, 1056, 0x01d9, 2, 6, 40, 32, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0x3a, 0x14, 0xab, 0x42, 0x4a}, 2, 1, 32, 256, 2, 2, 2092, 0x01d9, 2, 5, 40, 32, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0xd5, 0x94, 0x9a, 0x74, 0x42}, 2, 1, 16, 256, 2, 1, 1024, 0x0111, 1, 0, 24, 32, 4, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xad, 0x3a, 0x14, 0x03, 0x08, 0x50}, 2, 1, 32, 388, 2, 2, 1362, 0x01d9, 9, 8, 40, 32, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x64, 0x44, 0x4b, 0xa9, 0x00}, 7, 1, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x88, 0x24, 0x4b, 0xa9, 0x84}, 7, 1, 16, 256, 2, 2, 2048, 0x01df, 3, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x88, 0x24, 0x4b, 0xa9, 0x00}, 7, 1, 16, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x68, 0x24, 0x4a, 0xa9, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x68, 0x04, 0x4a, 0xa9, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0xd7, 0x94, 0x3e, 0x84, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x68, 0x04, 0x46, 0xa9, 0x00}, 7, 1, 8, 256, 2, 2, 2048, 0x0117, 1, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x89, 0x64, 0x64, 0x3c, 0xa1, 0x00}, 7, 1, 32, 512, 2, 1, 1024, 0x01c7, 4, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {5, {0x89, 0x84, 0x64, 0x3c, 0xa5, 0x00}, 7, 1, 32, 512, 2, 2, 1024, 0x01c7, 4, 17, 40, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x89, 0x88, 0x24, 0x3b, 0xa9, 0x00}, 7, 1, 16, 192, 2, 2, 2048, 0x0117, 12, 0, 24, 32, 1, 0, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x84, 0x93, 0x72, 0x57}, 1, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x84, 0x93, 0x72, 0x57}, 1, 1, 32, 256, 2, 1, 2092, 0x05c1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0x3a, 0x85, 0x93, 0x76, 0x57}, 1, 2, 32, 256, 2, 1, 2092, 0x05e1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd5, 0x84, 0x32, 0x72, 0x56}, 1, 1, 16, 128, 2, 1, 2056, 0x05c1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56}, 1, 1, 16, 128, 2, 2, 2058, 0x05d1, 2, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x82, 0x76, 0x56}, 1, 1, 16, 256, 2, 2, 2062, 0x05d1, 1, 33, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0x50}, 1, 1, 32, 256, 2, 2, 1066, 0x05d9, 2, 34, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0x3a, 0x95, 0x93, 0x7a, 0x50}, 1, 2, 32, 256, 2, 2, 1066, 0x05d9, 2, 34, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x94, 0x32, 0x76, 0x55}, 1, 1, 16, 128, 2, 2, 2050, 0x0191, 2, 0, 24, 32, 1, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0x57}, 1, 1, 32, 256, 2, 2, 1058, 0x05d9, 2, 33, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x84, 0x93, 0x72, 0x50}, 1, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 34, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0x51}, 1, 1, 32, 256, 2, 2, 1074, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0x3a, 0x94, 0x93, 0x76, 0x51}, 1, 1, 32, 256, 2, 2, 2106, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xd7, 0x84, 0x93, 0x72, 0x51}, 1, 1, 32, 256, 2, 1, 1056, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x98, 0xde, 0x94, 0x93, 0x76, 0xd1}, 1, 1, 32, 256, 2, 2, 1074, 0x05d9, 2, 35, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0x57}, 8, 1, 32, 256, 2, 2, 1058, 0x05d9, 2, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xd7, 0x84, 0x93, 0x72, 0x57}, 8, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 66, 40, 32, 2, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0xa4, 0x82, 0x76, 0x56}, 8, 1, 16, 256, 2, 2, 2082, 0x01d9, 1, 65, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0x50}, 8, 1, 32, 256, 2, 2, 1066, 0x05d9, 2, 67, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xd7, 0x84, 0x93, 0x72, 0x50}, 8, 1, 32, 256, 2, 1, 1060, 0x05c1, 2, 67, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0xa4, 0x82, 0x76, 0xd7}, 8, 1, 16, 256, 2, 2, 2090, 0x04d9, 1, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x84, 0x93, 0x72, 0x57}, 8, 1, 32, 256, 2, 1, 2092, 0x05c1, 2, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0x3a, 0x94, 0x93, 0x76, 0x51}, 8, 1, 32, 256, 2, 2, 2106, 0x01d9, 2, 68, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0x51}, 8, 1, 32, 256, 2, 2, 1074, 0x01d9, 2, 68, 40, 32, 3, 1, 4, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0x3a, 0xa4, 0x93, 0x7a, 0x50}, 8, 1, 32, 256, 2, 2, 2138, 0x05d9, 2, 0, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x82, 0x76, 0x56}, 8, 1, 16, 256, 2, 2, 2062, 0x01d9, 1, 0, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0x45, 0xde, 0x94, 0x93, 0x76, 0xd7}, 8, 1, 32, 256, 2, 2, 1058, 0x05d9, 2, 66, 40, 32, 3, 1, 1, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xd7, 0x94, 0x7e, 0x64, 0x44}, 0, 1, 16, 128, 2, 2, 2048, 0x01d9, 2, 49, 60, 36, 3, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xde, 0xd5, 0x7e, 0x68, 0x44}, 0, 2, 16, 128, 2, 2, 2048, 0x01f9, 2, 49, 60, 36, 3, 0, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xd7, 0x94, 0x7a, 0x54, 0x43}, 0, 1, 16, 128, 2, 2, 2076, 0x0199, 2, 0, 40, 36, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xde, 0xd5, 0x7a, 0x58, 0x43}, 0, 2, 16, 128, 2, 2, 2076, 0x01b9, 2, 0, 40, 36, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xd5, 0x94, 0x76, 0x54, 0x43}, 0, 1, 16, 128, 2, 2, 1038, 0x0119, 2, 0, 24, 36, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xd7, 0x14, 0x76, 0x54, 0xc2}, 0, 1, 16, 128, 2, 2, 2076, 0x0491, 2, 0, 24, 40, 3, 1, 3, 0, 0, {0, 0, 0, 0, 0}}, + {6, {0xec, 0xde, 0x94, 0xc3, 0xa4, 0xca}, 0, 1, 32, 792, 2, 1, 688, 0x04c1, 11, 50, 40, 32, 3, 1, 1, 0, 1, {0, 0, 0, 0, 0}}, +}; + +#if !IS_ENABLED(CONFIG_SANDBOX) +static int rkmtd_write_oob(struct rkmtd_dev *plat, ulong off, u_char *datbuf, u_char *oobbuf) +{ + struct mtd_info *mtd = plat->mtd; + struct mtd_oob_ops ops; + loff_t addr; + int ret; + + off &= ~(mtd->writesize - 1); + addr = (loff_t)off; + + memset(&ops, 0, sizeof(ops)); + ops.datbuf = datbuf; + ops.oobbuf = oobbuf; + ops.len = mtd->writesize; + ops.ooblen = mtd->oobsize; + ops.mode = MTD_OPS_PLACE_OOB; + ret = mtd_write_oob(mtd, addr, &ops); + if (ret < 0) { + debug("Error (%d) writing page %08lx\n", ret, off); + return 1; + } + + return 0; +} + +static int rkmtd_read_oob(struct rkmtd_dev *plat, ulong off, u_char *datbuf, u_char *oobbuf) +{ + struct mtd_info *mtd = plat->mtd; + struct mtd_oob_ops ops; + loff_t addr; + int ret; + + off &= ~(mtd->writesize - 1); + addr = (loff_t)off; + + memset(&ops, 0, sizeof(ops)); + ops.datbuf = datbuf; + ops.oobbuf = oobbuf; + ops.len = mtd->writesize; + ops.ooblen = mtd->oobsize; + ops.mode = MTD_OPS_PLACE_OOB; + ret = mtd_read_oob(mtd, addr, &ops); + if (ret < 0) { + debug("Error (%d) reading page %08lx\n", ret, off); + return 1; + } + + return 0; +} + +static int rkmtd_erase(struct rkmtd_dev *plat, ulong off) +{ + struct mtd_info *mtd = plat->mtd; + struct erase_info info; + loff_t addr; + int ret; + + off &= ~(mtd->writesize - 1); + addr = (loff_t)off; + + memset(&info, 0, sizeof(info)); + info.mtd = mtd; + info.addr = addr; + info.len = mtd->erasesize; + info.scrub = 1; + ret = mtd_erase(mtd, &info); + if (ret) { + debug("Error (%d) erasing page %08lx\n", ret, off); + return 1; + } + + return 0; +} +#endif +void rkmtd_scan_block(struct rkmtd_dev *plat) +{ + plat->blk_counter = 0; + +#if !IS_ENABLED(CONFIG_SANDBOX) + u32 blk; + + for (blk = 0; blk < plat->boot_blks; blk++) { + rkmtd_read_oob(plat, blk * plat->mtd->erasesize, plat->datbuf, plat->oobbuf); + if (*(u32 *)plat->datbuf == RK_TAG) { + struct sector0 *sec0 = (struct sector0 *)plat->datbuf; + + rkmtd_rc4(plat->datbuf, 512); + + plat->idblock[plat->blk_counter].blk = blk; + plat->idblock[plat->blk_counter].offset = sec0->boot_code1_offset; + plat->idblock[plat->blk_counter].boot_size = sec0->flash_boot_size; + + debug("\nblk : %d\n", plat->idblock[plat->blk_counter].blk); + debug("offset : %d\n", plat->idblock[plat->blk_counter].offset); + debug("boot_size : %d\n", plat->idblock[plat->blk_counter].boot_size); + + plat->blk_counter += 1; + + if (plat->blk_counter >= ARRAY_SIZE(plat->idblock)) + return; + } + } +#endif +} + +void rkmtd_read_block(struct rkmtd_dev *plat, u32 idx, u8 *buf) +{ +#if !IS_ENABLED(CONFIG_SANDBOX) + ulong off = plat->idblock[idx].blk * plat->mtd->erasesize; + struct nand_chip *chip = mtd_to_nand(plat->mtd); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int counter = 0; + u32 spare0 = 0; + u32 *p_spare; + int sector; + int page; + + rkmtd_read_oob(plat, off, + plat->datbuf, plat->oobbuf); + + memcpy(buf, plat->datbuf, BLK_SIZE); + + while (counter < plat->idblock[idx].boot_size) { + if (spare0) + page = (plat->idblock[idx].offset + spare0) / 4; + else + page = (plat->idblock[idx].offset + counter) / 4; + + rkmtd_read_oob(plat, + off + page * plat->mtd->writesize, + plat->datbuf, plat->oobbuf); + + sector = plat->idblock[idx].offset + counter; + + memcpy(&buf[(sector / 4) * BLK_SIZE], plat->datbuf, BLK_SIZE); + + p_spare = (u32 *)&plat->oobbuf[(ecc->steps - 1) * NFC_SYS_DATA_SIZE]; + + spare0 = *p_spare; + if (spare0 == -1) + break; + + counter += 4; + } +#endif +} + +void rkmtd_write_block(struct rkmtd_dev *plat, u32 idx, u8 *buf) +{ +#if !IS_ENABLED(CONFIG_SANDBOX) + ulong off = plat->idblock[idx].blk * plat->mtd->erasesize; + struct nand_chip *chip = mtd_to_nand(plat->mtd); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int counter = 0; + u32 *p_spare; + int sector; + int page; + int j, w, r; + + rkmtd_erase(plat, off); + + memset(plat->datbuf, 0xff, plat->mtd->writesize); + memcpy(plat->datbuf, buf, BLK_SIZE); + memset(plat->oobbuf, 0xff, plat->mtd->oobsize); + + rkmtd_write_oob(plat, off, + plat->datbuf, plat->oobbuf); + + while (counter < plat->idblock[idx].boot_size) { + sector = plat->idblock[idx].offset + counter; + + memset(plat->datbuf, 0xff, plat->mtd->writesize); + memcpy(plat->datbuf, &buf[(sector / 4) * BLK_SIZE], BLK_SIZE); + memset(plat->oobbuf, 0xff, plat->mtd->oobsize); + + p_spare = (u32 *)&plat->oobbuf[(ecc->steps - 1) * NFC_SYS_DATA_SIZE]; + + *p_spare = (plat->page_table[sector / 4 + 1] - 1) * 4; + + page = plat->page_table[sector / 4]; + + rkmtd_write_oob(plat, + off + page * plat->mtd->writesize, + plat->datbuf, plat->oobbuf); + + counter += 4; + } + + memset(plat->check, 0, BUF_SIZE); + rkmtd_read_block(plat, idx, plat->check); + + for (j = 0; j < BLK_SIZE; j++) { + w = *(buf + j); + r = *(plat->check + j); + + if (r != w) + goto dumpblock; + } + + for (j = 0; j < (plat->idblock[idx].boot_size * 512); j++) { + w = *(buf + plat->idblock[idx].offset * 512 + j); + r = *(plat->check + plat->idblock[idx].offset * 512 + j); + + if (r != w) + goto dumpblock; + } + + debug("write OK\n"); + return; + +dumpblock: + debug("write and check error:%x r=%x w=%x\n", j, r, w); + + plat->idblock[idx].offset = 0; + plat->idblock[idx].boot_size = 0; + + memset(plat->datbuf, 0xff, plat->mtd->writesize); + memset(plat->datbuf, 0, BLK_SIZE); + memset(plat->oobbuf, 0xff, plat->mtd->oobsize); + + rkmtd_write_oob(plat, off, plat->datbuf, plat->oobbuf); +#endif +} + +ulong rkmtd_bread(struct udevice *udev, lbaint_t start, + lbaint_t blkcnt, void *dst) +{ + struct blk_desc *block_dev = dev_get_uclass_plat(udev); + struct udevice *parent_dev = dev_get_parent(udev); + struct rkmtd_dev *plat = dev_get_plat(parent_dev); + char *buf = dst; + int i; + + if (blkcnt == 0) + return 0; + + if (start > (block_dev->lba - 1) || + (start + blkcnt) > block_dev->lba) + return 0; + + memset(dst, 0, blkcnt * block_dev->blksz); + + for (i = start; i < (start + blkcnt); i++) { + if (i == 0) { + debug("mbr : %d\n", i); + + memcpy(&buf[(i - start) * block_dev->blksz], + plat->mbr, sizeof(legacy_mbr)); + } else if (i == 1) { + debug("gpt_h : %d\n", i); + + memcpy(&buf[(i - start) * block_dev->blksz], + plat->gpt_h, sizeof(gpt_header)); + } else if (i == (block_dev->lba - 1)) { + debug("gpt_h2 : %d\n", i); + + memcpy(&buf[(i - start) * block_dev->blksz], + plat->gpt_h2, sizeof(gpt_header)); + } else if (i == 2 || i == (block_dev->lba - 33)) { + debug("gpt_e : %d\n", i); + + memcpy(&buf[(i - start) * block_dev->blksz], + plat->gpt_e, sizeof(gpt_entry)); + } else if (i >= 64 && i < (block_dev->lba - 33)) { + debug("rd : %d\n", i); + + memcpy(&buf[(i - start) * block_dev->blksz], + &plat->idb[(i - 64) * block_dev->blksz], block_dev->blksz); + } + } + + return blkcnt; +} + +ulong rkmtd_bwrite(struct udevice *udev, lbaint_t start, + lbaint_t blkcnt, const void *src) +{ + struct blk_desc *block_dev = dev_get_uclass_plat(udev); + struct udevice *parent_dev = dev_get_parent(udev); + struct rkmtd_dev *plat = dev_get_plat(parent_dev); + struct sector0 *sec0; + int i, j; + + if (blkcnt == 0) + return 0; + + if (start > (block_dev->lba - 1) || + (start + blkcnt) > block_dev->lba) + return 0; + + for (i = start; i < (start + blkcnt); i++) { + debug("wr : %d\n", i); + + if (i >= 64 && i < (block_dev->lba - 33)) { + if (i == 64) { + debug("first block\n"); + + plat->idb_need_write_back = 1; + memset(plat->idb, 0, BUF_SIZE); + } + + if (plat->idb_need_write_back) { + char *buf = (char *)src; + + memcpy(&plat->idb[(i - 64) * block_dev->blksz], + &buf[(i - start) * block_dev->blksz], + block_dev->blksz); + + if (i == 64) { + memcpy(plat->check, plat->idb, 512); + + if (*(u32 *)plat->check == RK_TAG) { + rkmtd_rc4(plat->check, 512); + + sec0 = (struct sector0 *)plat->check; + plat->offset = sec0->boot_code1_offset; + plat->boot_size = sec0->flash_boot_size; + + if (plat->offset + plat->boot_size > 512) { + debug("max size limit\n"); + plat->idb_need_write_back = 0; + } + } else { + debug("no IDB block found\n"); + plat->idb_need_write_back = 0; + } + } + + if (i == (64 + plat->offset + plat->boot_size - 1)) { + debug("last block\n"); + + plat->idb_need_write_back = 0; + + if (!plat->blk_counter) { + plat->idblock[0].blk = 2; + plat->idblock[1].blk = 3; + plat->idblock[2].blk = 4; + plat->idblock[3].blk = 5; + plat->idblock[4].blk = 6; + plat->blk_counter = 5; + } + + for (j = 0; j < plat->blk_counter; j++) { + if (plat->idblock[j].blk < plat->boot_blks) { + plat->idblock[j].offset = plat->offset; + plat->idblock[j].boot_size = plat->boot_size; + rkmtd_write_block(plat, j, plat->idb); + } + } + + rkmtd_scan_block(plat); + + if (!IS_ENABLED(CONFIG_SANDBOX)) + memset(plat->idb, 0, BUF_SIZE); + + if (plat->blk_counter) + rkmtd_read_block(plat, 0, plat->idb); + } + } + } else if (plat->idb_need_write_back) { + plat->idb_need_write_back = 0; + + memset(plat->idb, 0, BUF_SIZE); + + if (plat->blk_counter) + rkmtd_read_block(plat, 0, plat->idb); + } + } + + return blkcnt; +} + +static const struct blk_ops rkmtd_blk_ops = { + .read = rkmtd_bread, + .write = rkmtd_bwrite, +}; + +U_BOOT_DRIVER(rkmtd_blk) = { + .name = "rkmtd_blk", + .id = UCLASS_BLK, + .ops = &rkmtd_blk_ops, +}; + +void rkmtd_build_page_table(struct rkmtd_dev *plat) +{ + u32 counter; + u32 counter2; + + switch (plat->lsb_mode) { + case 0: + counter = 0; + do { + u16 val = counter; + + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 1: + counter = 0; + do { + u16 val = counter; + + if (counter > 3) { + u16 offset; + + if (counter & 1) + offset = 3; + else + offset = 2; + val = 2 * counter - offset; + } + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 2: + counter = 0; + do { + u16 val = counter; + + if (counter > 1) + val = 2 * counter - 1; + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 3: + counter = 0; + do { + u16 val = counter; + + if (counter > 5) { + u16 offset; + + if (counter & 1) + offset = 5; + else + offset = 4; + val = 2 * counter - offset; + } + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 4: + counter = 8; + plat->page_table[0] = 0; + plat->page_table[1] = 1; + plat->page_table[2] = 2; + plat->page_table[3] = 3; + plat->page_table[4] = 4; + plat->page_table[5] = 5; + plat->page_table[6] = 7; + plat->page_table[7] = 8; + do { + u32 offset; + u32 val; + + if (counter & 1) + offset = 7; + else + offset = 6; + val = 2 * counter - offset; + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 5: + counter = 0; + counter2 = 16; + do { + u16 val = counter; + + plat->page_table[counter++] = val; + } while (counter != 16); + do { + plat->page_table[counter++] = counter2; + counter2 = counter2 + 2; + } while (counter != 512); + break; + case 6: + counter = 0; + counter2 = 0; + do { + u16 val = counter; + + if (counter > 5) { + u16 offset; + + if (counter & 1) + offset = 12; + else + offset = 10; + val = counter2 - offset; + } + plat->page_table[counter++] = val; + counter2 = counter2 + 3; + } while (counter != 512); + break; + case 9: + counter = 3; + counter2 = 3; + plat->page_table[0] = 0; + plat->page_table[1] = 1; + plat->page_table[2] = 2; + do { + plat->page_table[counter++] = counter2; + counter2 = counter2 + 2; + } while (counter != 512); + break; + case 10: + counter = 0; + counter2 = 63; + do { + u16 val = counter; + + plat->page_table[counter++] = val; + } while (counter != 63); + do { + plat->page_table[counter++] = counter2; + counter2 = counter2 + 2; + } while (counter != 512); + break; + case 11: + counter = 0; + do { + u16 val = counter; + + plat->page_table[counter++] = val; + } while (counter != 8); + do { + u32 offset; + u32 val; + + if (counter & 1) + offset = 7; + else + offset = 6; + val = 2 * counter - offset; + plat->page_table[counter++] = val; + } while (counter != 512); + break; + case 12: + counter = 4; + plat->page_table[0] = 0; + plat->page_table[1] = 1; + plat->page_table[2] = 2; + plat->page_table[3] = 3; + do { + u32 val = counter - 1 + (counter >> 1); + + plat->page_table[counter++] = val; + } while (counter != 512); + break; + } +} + +static inline u32 efi_crc32(const void *buf, u32 len) +{ + return crc32(0, buf, len); +} + +int rkmtd_init_plat(struct udevice *dev) +{ + static const efi_guid_t partition_basic_data_guid = PARTITION_BASIC_DATA_GUID; + struct rkmtd_dev *plat = dev_get_plat(dev); + size_t efiname_len, dosname_len; + uchar name[] = "loader1"; + u32 calc_crc32; + int k; + + gen_rand_uuid_str(plat->uuid_disk_str, UUID_STR_FORMAT_GUID); + gen_rand_uuid_str(plat->uuid_part_str, UUID_STR_FORMAT_GUID); + + debug("uuid_part_str : %s\n", plat->uuid_part_str); + debug("uuid_disk_str : %s\n", plat->uuid_disk_str); + + plat->idb = devm_kzalloc(plat->dev, BUF_SIZE, GFP_KERNEL); + if (!plat->idb) + return -ENOMEM; + + plat->check = devm_kzalloc(plat->dev, BUF_SIZE, GFP_KERNEL); + if (!plat->check) + return -ENOMEM; + + plat->mbr = devm_kzalloc(plat->dev, sizeof(legacy_mbr), GFP_KERNEL); + if (!plat->mbr) + return -ENOMEM; + + plat->gpt_e = devm_kzalloc(plat->dev, sizeof(gpt_entry), GFP_KERNEL); + if (!plat->gpt_e) + return -ENOMEM; + + plat->gpt_h = devm_kzalloc(plat->dev, sizeof(gpt_header), GFP_KERNEL); + if (!plat->gpt_h) + return -ENOMEM; + + plat->gpt_h2 = devm_kzalloc(plat->dev, sizeof(gpt_header), GFP_KERNEL); + if (!plat->gpt_h2) + return -ENOMEM; + + /* Init mbr */ + plat->mbr->signature = MSDOS_MBR_SIGNATURE; + plat->mbr->partition_record[0].sys_ind = EFI_PMBR_OSTYPE_EFI_GPT; + plat->mbr->partition_record[0].start_sect = 1; + plat->mbr->partition_record[0].nr_sects = LBA - 1; + + /* Init gpt_e */ + plat->gpt_e->starting_lba = cpu_to_le64(64); + plat->gpt_e->ending_lba = cpu_to_le64(LBA - 34); + + debug("starting_lba : %llu\n", le64_to_cpu(plat->gpt_e->starting_lba)); + debug("ending_lba : %llu\n", le64_to_cpu(plat->gpt_e->ending_lba)); + + memcpy(plat->gpt_e->partition_type_guid.b, &partition_basic_data_guid, 16); + + uuid_str_to_bin(plat->uuid_part_str, plat->gpt_e->unique_partition_guid.b, + UUID_STR_FORMAT_GUID); + + efiname_len = sizeof(plat->gpt_e->partition_name) / sizeof(efi_char16_t); + dosname_len = sizeof(name); + + for (k = 0; k < min(dosname_len, efiname_len); k++) + plat->gpt_e->partition_name[k] = (efi_char16_t)(name[k]); + + /* Init gpt_h */ + plat->gpt_h->signature = cpu_to_le64(GPT_HEADER_SIGNATURE_UBOOT); + plat->gpt_h->revision = cpu_to_le32(GPT_HEADER_REVISION_V1); + plat->gpt_h->header_size = cpu_to_le32(sizeof(gpt_header)); + plat->gpt_h->first_usable_lba = cpu_to_le64(64); + plat->gpt_h->last_usable_lba = cpu_to_le64(LBA - 34); + plat->gpt_h->num_partition_entries = cpu_to_le32(1); + plat->gpt_h->sizeof_partition_entry = cpu_to_le32(sizeof(gpt_entry)); + + uuid_str_to_bin(plat->uuid_disk_str, plat->gpt_h->disk_guid.b, + UUID_STR_FORMAT_GUID); + + plat->gpt_h->partition_entry_array_crc32 = 0; + calc_crc32 = efi_crc32((const unsigned char *)plat->gpt_e, + le32_to_cpu(plat->gpt_h->num_partition_entries) * + le32_to_cpu(plat->gpt_h->sizeof_partition_entry)); + plat->gpt_h->partition_entry_array_crc32 = cpu_to_le32(calc_crc32); + + debug("partition crc32 : 0x%08x\n", calc_crc32); + + plat->gpt_h->my_lba = cpu_to_le64(1); + plat->gpt_h->partition_entry_lba = cpu_to_le64(2); + plat->gpt_h->alternate_lba = cpu_to_le64(LBA - 1); + + plat->gpt_h->header_crc32 = 0; + calc_crc32 = efi_crc32((const unsigned char *)plat->gpt_h, + le32_to_cpu(plat->gpt_h->header_size)); + plat->gpt_h->header_crc32 = cpu_to_le32(calc_crc32); + + debug("header h1 crc32 : 0x%08x\n", calc_crc32); + + /* Init gpt_h2 */ + memcpy(plat->gpt_h2, plat->gpt_h, sizeof(gpt_header)); + + plat->gpt_h2->my_lba = cpu_to_le64(LBA - 1); + plat->gpt_h2->partition_entry_lba = + cpu_to_le64(le64_to_cpu(plat->gpt_h2->last_usable_lba) + 1); + plat->gpt_h2->alternate_lba = cpu_to_le64(1); + + plat->gpt_h2->header_crc32 = 0; + calc_crc32 = efi_crc32((const unsigned char *)plat->gpt_h2, + le32_to_cpu(plat->gpt_h2->header_size)); + plat->gpt_h2->header_crc32 = cpu_to_le32(calc_crc32); + + debug("header h2 crc32 : 0x%08x\n", calc_crc32); + + part_init(plat->desc); + + return 0; +} + +static void rkmtd_blk_kmalloc_release(struct udevice *dev, void *res) +{ + /* noop */ +} + +static int rkmtd_bind(struct udevice *dev) +{ + struct rkmtd_dev *plat = dev_get_plat(dev); + char dev_name[30], *str; + struct blk_desc *desc; + struct udevice *bdev; + int ret; + + snprintf(dev_name, sizeof(dev_name), "%s.%s", dev->name, "blk"); + + str = devres_alloc(rkmtd_blk_kmalloc_release, strlen(dev_name) + 1, GFP_KERNEL); + if (unlikely(!str)) + return -ENOMEM; + + strcpy(str, dev_name); + + ret = blk_create_device(dev, "rkmtd_blk", str, UCLASS_RKMTD, + -1, 512, LBA, &bdev); + if (ret) { + free(str); + return log_msg_ret("blk", ret); + } + + devres_add(dev, str); + + desc = dev_get_uclass_plat(bdev); + sprintf(desc->vendor, "0x%.4x", 0x2207); + memcpy(desc->product, "RKMTD", sizeof("RKMTD")); + memcpy(desc->revision, "V1.00", sizeof("V1.00")); + plat->desc = desc; + + return 0; +} + +static int rkmtd_attach_mtd(struct udevice *dev) +{ + struct rkmtd_dev *plat = dev_get_plat(dev); + struct mtd_info *mtd; + struct udevice *blk; + int ret; + + plat->dev = dev; + + /* Sanity check that rkmtd_bind() has been used */ + ret = blk_find_from_parent(dev, &blk); + if (ret) + return ret; + +#if IS_ENABLED(CONFIG_SANDBOX) + plat->mtd = devm_kzalloc(dev, sizeof(struct mtd_info), GFP_KERNEL); + if (!plat->mtd) + return -ENOMEM; + + mtd = plat->mtd; + mtd->erasesize = 2 ^ 3 * BLK_SIZE; + mtd->writesize = BLK_SIZE; + mtd->oobsize = BLK_SIZE / STEP_SIZE * NFC_SYS_DATA_SIZE; + plat->boot_blks = 0; + plat->lsb_mode = 0; +#else + struct nand_chip *chip; + u8 id[6]; + int i, j; + u32 tmp; + + mtd = get_nand_dev_by_index(0); + if (!mtd) + return -ENOSYS; + + chip = mtd_to_nand(mtd); + + ret = ofnode_read_u32(chip->flash_node, "rockchip,boot-blks", &tmp); + plat->boot_blks = ret ? 0 : tmp; + plat->mtd = mtd; + + if (chip->select_chip) + chip->select_chip(mtd, 0); + + nand_readid_op(chip, 0, id, 6); + + if (chip->select_chip) + chip->select_chip(mtd, -1); + + for (i = 0; i < ARRAY_SIZE(nand_para_tbl); i++) { + plat->info = (struct nand_para_info *)&nand_para_tbl[i]; + for (j = 0; j < plat->info->id_bytes; j++) { + if (plat->info->nand_id[j] != id[j]) + break; + if (j == plat->info->id_bytes - 1) + goto valid; + } + } + + debug("no nand_para_info found\n"); + return -ENODEV; +valid: + plat->lsb_mode = plat->info->lsb_mode; + + debug("FLASH ID :"); + + for (j = 0; j < plat->info->id_bytes; j++) + debug(" %x", id[j]); + + debug("\n"); +#endif + + rkmtd_build_page_table(plat); + + plat->datbuf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL); + if (!plat->datbuf) + return -ENOMEM; + + plat->oobbuf = devm_kzalloc(dev, mtd->oobsize, GFP_KERNEL); + if (!plat->oobbuf) + return -ENOMEM; + + debug("erasesize %8d\n", mtd->erasesize); + debug("writesize %8d\n", mtd->writesize); + debug("oobsize %8d\n", mtd->oobsize); + debug("boot_blks %8d\n", plat->boot_blks); + debug("lsb_mode %8d\n", plat->lsb_mode); + + ret = rkmtd_init_plat(dev); + if (ret) { + debug("rkmtd_init_plat failed\n"); + return -ENOENT; + } + + rkmtd_scan_block(plat); + + memset(plat->idb, 0, BUF_SIZE); + + if (plat->blk_counter) + rkmtd_read_block(plat, 0, plat->idb); + + return 0; +} + +int rkmtd_detach_mtd(struct udevice *dev) +{ + int ret; + + ret = device_remove(dev, DM_REMOVE_NORMAL); + if (ret) + return log_msg_ret("rem", ret); + + ret = device_chld_unbind(dev, NULL); + if (ret) + return log_msg_ret("unb", ret); + + return 0; +} + +struct rkmtd_ops rkmtd_ops = { + .attach_mtd = rkmtd_attach_mtd, + .detach_mtd = rkmtd_detach_mtd, +}; + +U_BOOT_DRIVER(rkmtd_drv) = { + .name = "rkmtd_drv", + .id = UCLASS_RKMTD, + .ops = &rkmtd_ops, + .bind = rkmtd_bind, + .plat_auto = sizeof(struct rkmtd_dev), +}; + +struct rkmtd_priv { + struct udevice *cur_dev; +}; + +void rkmtd_rc4(u8 *buf, u32 len) +{ + u8 S[256], K[256], temp; + u32 i, j, t, x; + u8 key[16] = { 124, 78, 3, 4, 85, 5, 9, 7, 45, 44, 123, 56, 23, 13, 23, 17}; + + j = 0; + for (i = 0; i < 256; i++) { + S[i] = (u8)i; + j &= 0x0f; + K[i] = key[j]; + j++; + } + + j = 0; + for (i = 0; i < 256; i++) { + j = (j + S[i] + K[i]) % 256; + temp = S[i]; + S[i] = S[j]; + S[j] = temp; + } + + i = 0; + j = 0; + for (x = 0; x < len; x++) { + i = (i + 1) % 256; + j = (j + S[i]) % 256; + temp = S[i]; + S[i] = S[j]; + S[j] = temp; + t = (S[i] + (S[j] % 256)) % 256; + buf[x] = buf[x] ^ S[t]; + } +} + +struct udevice *rkmtd_get_cur_dev(void) +{ + struct uclass *uc = uclass_find(UCLASS_RKMTD); + + if (uc) { + struct rkmtd_priv *priv = uclass_get_priv(uc); + + return priv->cur_dev; + } + + return NULL; +} + +void rkmtd_set_cur_dev(struct udevice *dev) +{ + struct uclass *uc = uclass_find(UCLASS_RKMTD); + + if (uc) { + struct rkmtd_priv *priv = uclass_get_priv(uc); + + priv->cur_dev = dev; + } +} + +struct udevice *rkmtd_find_by_label(const char *label) +{ + struct udevice *dev; + struct uclass *uc; + + uclass_id_foreach_dev(UCLASS_RKMTD, dev, uc) { + struct rkmtd_dev *plat = dev_get_plat(dev); + + if (plat->label && !strcmp(label, plat->label)) + return dev; + } + + return NULL; +} + +int rkmtd_attach(struct udevice *dev) +{ + struct rkmtd_ops *ops = rkmtd_get_ops(dev); + + if (!ops->attach_mtd) + return -ENOSYS; + + return ops->attach_mtd(dev); +} + +int rkmtd_detach(struct udevice *dev) +{ + struct rkmtd_ops *ops = rkmtd_get_ops(dev); + + if (!ops->detach_mtd) + return -ENOSYS; + + if (dev == rkmtd_get_cur_dev()) + rkmtd_set_cur_dev(NULL); + + return ops->detach_mtd(dev); +} + +static void rkmtd_drv_kmalloc_release(struct udevice *dev, void *res) +{ + /* noop */ +} + +int rkmtd_create_device(const char *label, struct udevice **devp) +{ + char dev_name[30], *str, *label_new; + struct udevice *dev, *blk; + struct rkmtd_dev *plat; + int ret; + + /* unbind any existing device with this label */ + dev = rkmtd_find_by_label(label); + if (dev) { + ret = rkmtd_detach(dev); + if (ret) + return log_msg_ret("det", ret); + + ret = device_unbind(dev); + if (ret) + return log_msg_ret("unb", ret); + } + + snprintf(dev_name, sizeof(dev_name), "rkmtd-%s", label); + + str = devres_alloc(rkmtd_drv_kmalloc_release, strlen(dev_name) + 1, GFP_KERNEL); + if (unlikely(!str)) + return -ENOMEM; + + strcpy(str, dev_name); + + ret = device_bind_driver(dm_root(), "rkmtd_drv", str, &dev); + if (ret) { + free(str); + return log_msg_ret("drv", ret); + } + + devres_add(dev, str); + + if (!blk_find_from_parent(dev, &blk)) { + struct blk_desc *desc = dev_get_uclass_plat(blk); + + desc->removable = true; + } + + label_new = devm_kzalloc(dev, strlen(label) + 1, GFP_KERNEL); + if (!label_new) + return -ENOMEM; + + strcpy(label_new, label); + + plat = dev_get_plat(dev); + plat->label = label_new; + *devp = dev; + + return 0; +} + +int rkmtd_create_attach_mtd(const char *label, struct udevice **devp) +{ + struct udevice *dev; + int ret; + + ret = rkmtd_create_device(label, &dev); + if (ret) + return log_msg_ret("cre", ret); + + ret = rkmtd_attach(dev); + if (ret) { + device_unbind(dev); + return log_msg_ret("att", ret); + } + *devp = dev; + + return 0; +} + +UCLASS_DRIVER(rkmtd) = { + .name = "rkmtd", + .id = UCLASS_RKMTD, + .post_bind = dm_scan_fdt_dev, + .priv_auto = sizeof(struct rkmtd_priv), +}; diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 570252d186a..3c56253b1ea 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -79,14 +79,6 @@ config BOOTCOUNT_RAM Store the bootcount in DRAM protected against bit errors due to short power loss or holding a system in RESET. -config BOOTCOUNT_I2C - bool "Boot counter on I2C device" - help - Enable support for the bootcounter on an i2c (like RTC) device. - CFG_SYS_I2C_RTC_ADDR = i2c chip address - CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for - the bootcounter. - config BOOTCOUNT_AT91 bool "Boot counter for Atmel AT91SAM9XE" depends on AT91SAM9XE @@ -117,6 +109,16 @@ config DM_BOOTCOUNT_RTC Accesses to the backing store are performed using the write16 and read16 ops of DM RTC devices. +config DM_BOOTCOUNT_I2C + bool "Driver Model boot counter on I2C device" + depends on DM_I2C + help + Enable support for the bootcounter on a generic i2c device, like a RTC + or PMIC. The bootcounter is configured in the device tree using the + "u-boot,bootcount-i2c" compatible string. It requires a phandle + 'i2cbcdev' for the i2c device and an 'offset' property used within the + device. + config DM_BOOTCOUNT_I2C_EEPROM bool "Support i2c eeprom devices as a backing store for bootcount" depends on I2C_EEPROM @@ -175,14 +177,6 @@ config BOOTCOUNT_BOOTLIMIT counter being cleared. If set to 0, do not set a boot limit in the environment. -config BOOTCOUNT_ALEN - int "I2C address length" - default 1 - depends on BOOTCOUNT_I2C - help - Length of the the I2C address at SYS_BOOTCOUNT_ADDR for storing - the boot counter. - config SYS_BOOTCOUNT_SINGLEWORD bool "Use single word to pack boot count and magic value" depends on BOOTCOUNT_GENERIC @@ -218,7 +212,7 @@ config SYS_BOOTCOUNT_ADDR default 0x44E3E000 if BOOTCOUNT_AM33XX || BOOTCOUNT_AM33XX_NVMEM default 0xE0115FF8 if ARCH_LS1043A || ARCH_LS1021A depends on BOOTCOUNT_AM33XX || BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \ - BOOTCOUNT_I2C || BOOTCOUNT_AM33XX_NVMEM + BOOTCOUNT_AM33XX_NVMEM help Set the address used for reading and writing the boot counter. @@ -226,13 +220,11 @@ config SYS_BOOTCOUNT_MAGIC hex "Magic value for the boot counter" default 0xB001C041 if BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \ BOOTCOUNT_AM33XX || BOOTCOUNT_ENV || \ - BOOTCOUNT_RAM || BOOTCOUNT_I2C || \ - BOOTCOUNT_AT91 || DM_BOOTCOUNT + BOOTCOUNT_RAM || BOOTCOUNT_AT91 || DM_BOOTCOUNT default 0xB0 if BOOTCOUNT_AM33XX_NVMEM depends on BOOTCOUNT_GENERIC || BOOTCOUNT_EXT || \ BOOTCOUNT_AM33XX || BOOTCOUNT_ENV || \ - BOOTCOUNT_RAM || BOOTCOUNT_I2C || \ - BOOTCOUNT_AT91 || DM_BOOTCOUNT || \ + BOOTCOUNT_RAM || BOOTCOUNT_AT91 || DM_BOOTCOUNT || \ BOOTCOUNT_AM33XX_NVMEM help Set the magic value used for the boot counter. diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index b65959a384b..e7771f5b36d 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -6,7 +6,6 @@ obj-$(CONFIG_BOOTCOUNT_AT91) += bootcount_at91.o obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o -obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o obj-$(CONFIG_BOOTCOUNT_EXT) += bootcount_ext.o obj-$(CONFIG_BOOTCOUNT_AM33XX_NVMEM) += bootcount_nvmem.o @@ -14,5 +13,6 @@ obj-$(CONFIG_DM_BOOTCOUNT) += bootcount-uclass.o obj-$(CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_DM_BOOTCOUNT_RTC) += rtc.o obj-$(CONFIG_DM_BOOTCOUNT_I2C_EEPROM) += i2c-eeprom.o +obj-$(CONFIG_DM_BOOTCOUNT_I2C) += bootcount_dm_i2c.o obj-$(CONFIG_DM_BOOTCOUNT_SPI_FLASH) += spi-flash.o obj-$(CONFIG_DM_BOOTCOUNT_SYSCON) += bootcount_syscon.o diff --git a/drivers/bootcount/bootcount_dm_i2c.c b/drivers/bootcount/bootcount_dm_i2c.c new file mode 100644 index 00000000000..e27034cbeb0 --- /dev/null +++ b/drivers/bootcount/bootcount_dm_i2c.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 + * Philip Richard Oberfichtner <pro@denx.de> + * + * Based on previous work from Heiko Schocher (legacy bootcount_i2c.c driver) + */ + +#include <bootcount.h> +#include <dm.h> +#include <i2c.h> + +#define BC_MAGIC 0x55 + +struct bootcount_i2c_priv { + struct udevice *bcdev; + unsigned int offset; +}; + +static int bootcount_i2c_set(struct udevice *dev, const u32 val) +{ + int ret; + struct bootcount_i2c_priv *priv = dev_get_priv(dev); + + ret = dm_i2c_reg_write(priv->bcdev, priv->offset, BC_MAGIC); + if (ret < 0) + goto err_exit; + + ret = dm_i2c_reg_write(priv->bcdev, priv->offset + 1, val & 0xff); + if (ret < 0) + goto err_exit; + + return 0; + +err_exit: + log_debug("%s: Error writing to I2C device (%d)\n", __func__, ret); + return ret; +} + +static int bootcount_i2c_get(struct udevice *dev, u32 *val) +{ + int ret; + struct bootcount_i2c_priv *priv = dev_get_priv(dev); + + ret = dm_i2c_reg_read(priv->bcdev, priv->offset); + if (ret < 0) + goto err_exit; + + if ((ret & 0xff) != BC_MAGIC) { + log_debug("%s: Invalid Magic, reset bootcounter.\n", __func__); + *val = 0; + return bootcount_i2c_set(dev, 0); + } + + ret = dm_i2c_reg_read(priv->bcdev, priv->offset + 1); + if (ret < 0) + goto err_exit; + + *val = ret; + return 0; + +err_exit: + log_debug("%s: Error reading from I2C device (%d)\n", __func__, ret); + return ret; +} + +static int bootcount_i2c_probe(struct udevice *dev) +{ + struct bootcount_i2c_priv *priv = dev_get_priv(dev); + int ret; + + ret = dev_read_u32(dev, "offset", &priv->offset); + if (ret) + goto exit; + + ret = i2c_get_chip_by_phandle(dev, "i2cbcdev", &priv->bcdev); + +exit: + if (ret) + log_debug("%s failed, ret = %d\n", __func__, ret); + + return ret; +} + +static const struct bootcount_ops bootcount_i2c_ops = { + .get = bootcount_i2c_get, + .set = bootcount_i2c_set, +}; + +static const struct udevice_id bootcount_i2c_ids[] = { + { .compatible = "u-boot,bootcount-i2c" }, + { } +}; + +U_BOOT_DRIVER(bootcount_i2c) = { + .name = "bootcount-i2c", + .id = UCLASS_BOOTCOUNT, + .priv_auto = sizeof(struct bootcount_i2c_priv), + .probe = bootcount_i2c_probe, + .of_match = bootcount_i2c_ids, + .ops = &bootcount_i2c_ops, +}; diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c deleted file mode 100644 index b3ac67ea35d..00000000000 --- a/drivers/bootcount/bootcount_i2c.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#include <bootcount.h> -#include <linux/compiler.h> -#include <i2c.h> - -#define BC_MAGIC 0xbc - -void bootcount_store(ulong a) -{ - unsigned char buf[3]; - int ret; - - buf[0] = BC_MAGIC; - buf[1] = (a & 0xff); - ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, - CONFIG_BOOTCOUNT_ALEN, buf, 2); - if (ret != 0) - puts("Error writing bootcount\n"); -} - -ulong bootcount_load(void) -{ - unsigned char buf[3]; - int ret; - - ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, - CONFIG_BOOTCOUNT_ALEN, buf, 2); - if (ret != 0) { - puts("Error loading bootcount\n"); - return 0; - } - if (buf[0] == BC_MAGIC) - return buf[1]; - - bootcount_store(0); - - return 0; -} diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c index f23465d7e1f..b8700f517fc 100644 --- a/drivers/clk/clk-cdce9xx.c +++ b/drivers/clk/clk-cdce9xx.c @@ -2,7 +2,7 @@ /* * Texas Instruments CDCE913/925/937/949 clock synthesizer driver * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Tero Kristo <t-kristo@ti.com> * * Based on Linux kernel clk-cdce925.c. diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index f186fcbcdb8..3b5e3f9c86b 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -422,12 +422,13 @@ int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) return clk_get_by_index_nodev(node, index, clk); } -int clk_release_all(struct clk *clk, int count) +int clk_release_all(struct clk *clk, unsigned int count) { - int i, ret; + unsigned int i; + int ret; for (i = 0; i < count; i++) { - debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]); + debug("%s(clk[%u]=%p)\n", __func__, i, &clk[i]); /* check if clock has been previously requested */ if (!clk[i].dev) @@ -477,7 +478,7 @@ void clk_free(struct clk *clk) ulong clk_get_rate(struct clk *clk) { const struct clk_ops *ops; - int ret; + ulong ret; debug("%s(clk=%p)\n", __func__, clk); if (!clk_valid(clk)) @@ -655,7 +656,7 @@ int clk_enable(struct clk *clk) } if (ops->enable) { - ret = ops->enable(clk); + ret = ops->enable(clkp ? clkp : clk); if (ret) { printf("Enable %s failed\n", clk->dev->name); return ret; @@ -712,7 +713,7 @@ int clk_disable(struct clk *clk) } if (ops->disable) { - ret = ops->disable(clk); + ret = ops->disable(clkp ? clkp : clk); if (ret) return ret; } diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c index 1075ba73339..d0f5bb37530 100644 --- a/drivers/clk/meson/a1.c +++ b/drivers/clk/meson/a1.c @@ -241,6 +241,12 @@ static const struct meson_clk_info *meson_clocks[] = { [CLKID_USB_PHY_IN] = CLK_GATE("usb_phy_in", A1_SYS_OSCIN_CTRL, 2, EXTERNAL_XTAL ), + [CLKID_USB_CTRL_IN] = CLK_GATE("usb_ctrl_in", A1_SYS_OSCIN_CTRL, 3, + EXTERNAL_XTAL + ), + [CLKID_USB_CTRL] = CLK_GATE("usb_ctrl", A1_SYS_CLK_EN0, 28, + CLKID_SYS + ), [CLKID_USB_PHY] = CLK_GATE("usb_phy", A1_SYS_CLK_EN0, 27, CLKID_SYS ), diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 2336028a736..c8baad1a6c8 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -5,7 +5,6 @@ * Copyright (C) 2021-2023 Renesas Electronics Corp. */ -#include <common.h> #include <dm/device.h> #include <dt-bindings/clock/r9a07g044-cpg.h> #include <linux/clk-provider.h> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3295ebb90ba..e54508c35ce 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -11,7 +11,6 @@ * Copyright (C) 2015 Renesas Electronics Corp. */ -#include <common.h> #include <asm/io.h> #include <clk-uclass.h> #include <dm.h> diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index d657ef38f3c..1bb31b3313b 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -168,13 +168,71 @@ rockchip_pll_clk_set_by_auto(ulong fin_hz, return rate_table; } +static u32 +rockchip_rk3588_pll_k_get(u32 m, u32 p, u32 s, u64 fin_hz, u64 fvco) +{ + u64 fref, fout, ffrac; + u32 k = 0; + + fref = fin_hz / p; + ffrac = fvco - (m * fref); + fout = ffrac * 65536; + k = fout / fref; + if (k > 32767) { + fref = fin_hz / p; + ffrac = ((m + 1) * fref) - fvco; + fout = ffrac * 65536; + k = ((fout * 10 / fref) + 7) / 10; + if (k > 32767) + k = 0; + else + k = ~k + 1; + } + return k; +} + +static struct rockchip_pll_rate_table * +rockchip_rk3588_pll_frac_by_auto(unsigned long fin_hz, unsigned long fout_hz) +{ + struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; + u32 p, m, s, k; + u64 fvco; + + for (s = 0; s <= 6; s++) { + fvco = (u64)fout_hz << s; + if (fvco < RK3588_VCO_MIN_HZ || fvco > RK3588_VCO_MAX_HZ) + continue; + for (p = 1; p <= 4; p++) { + for (m = 64; m <= 1023; m++) { + if ((fvco >= m * fin_hz / p) && + (fvco < (m + 1) * fin_hz / p)) { + k = rockchip_rk3588_pll_k_get(m, p, s, + fin_hz, + fvco); + if (!k) + continue; + rate_table->p = p; + rate_table->s = s; + rate_table->k = k; + if (k > 32767) + rate_table->m = m + 1; + else + rate_table->m = m; + return rate_table; + } + } + } + } + return NULL; +} + static struct rockchip_pll_rate_table * rk3588_pll_clk_set_by_auto(unsigned long fin_hz, unsigned long fout_hz) { struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table; u32 p, m, s; - ulong fvco, fref, fout, ffrac; + ulong fvco; if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) return NULL; @@ -202,27 +260,12 @@ rk3588_pll_clk_set_by_auto(unsigned long fin_hz, } pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); } else { - for (s = 0; s <= 6; s++) { - fvco = fout_hz << s; - if (fvco < RK3588_VCO_MIN_HZ || - fvco > RK3588_VCO_MAX_HZ) - continue; - for (p = 1; p <= 4; p++) { - for (m = 64; m <= 1023; m++) { - if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) { - rate_table->p = p; - rate_table->m = m; - rate_table->s = s; - fref = fin_hz / p; - ffrac = fvco - (m * fref); - fout = ffrac * 65536; - rate_table->k = fout / fref; - return rate_table; - } - } - } - } - pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz); + rate_table = rockchip_rk3588_pll_frac_by_auto(fin_hz, fout_hz); + if (!rate_table) + pr_err("CANNOT FIND Fout by auto,fout = %lu\n", + fout_hz); + else + return rate_table; } return NULL; } @@ -533,11 +576,22 @@ static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, rate = OSC_HZ / p; rate *= m; - if (k) { + if (k & BIT(15)) { + /* fractional mode */ + u64 frac_rate64; + + k = (~(k - 1)) & RK3588_PLLCON2_K_MASK; + frac_rate64 = OSC_HZ * k; + postdiv = p; + postdiv *= 65536; + do_div(frac_rate64, postdiv); + rate -= frac_rate64; + } else { /* fractional mode */ u64 frac_rate64 = OSC_HZ * k; - postdiv = p * 65536; + postdiv = p; + postdiv *= 65536; do_div(frac_rate64, postdiv); rate += frac_rate64; } diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 599b7b130eb..68f5bbbb9e5 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1838,7 +1838,7 @@ static ulong rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv, rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru, VPLL, div * rate); } else { - for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) { + for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) { switch (i) { case DCLK_VOP_SEL_GPLL: pll_rate = priv->gpll_hz; @@ -2785,9 +2785,15 @@ static int rk3568_dclk_vop_set_parent(struct clk *clk, struct clk *parent) if (parent->id == PLL_VPLL) { rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT); - } else { + } else if (parent->id == PLL_HPLL) { rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT); + } else if (parent->id == PLL_CPLL) { + rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, + DCLK_VOP_SEL_CPLL << DCLK0_VOP_SEL_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, + DCLK_VOP_SEL_GPLL << DCLK0_VOP_SEL_SHIFT); } return 0; diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 119b1337bdf..a995dd5591d 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -36,6 +36,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { RK3588_PLL_RATE(816000000, 2, 272, 2, 0), RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(742500000, 4, 495, 2, 0), RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), RK3588_PLL_RATE(600000000, 2, 200, 2, 0), RK3588_PLL_RATE(594000000, 2, 198, 2, 0), @@ -305,12 +306,18 @@ static ulong rk3588_top_set_clk(struct rk3588_clk_priv *priv, switch (clk_id) { case ACLK_TOP_ROOT: - src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + if (!(priv->cpll_hz % rate)) { + src_clk = ACLK_TOP_ROOT_SRC_SEL_CPLL; + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + } else { + src_clk = ACLK_TOP_ROOT_SRC_SEL_GPLL; + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + } assert(src_clk_div - 1 <= 31); rk_clrsetreg(&cru->clksel_con[8], ACLK_TOP_ROOT_DIV_MASK | ACLK_TOP_ROOT_SRC_SEL_MASK, - (ACLK_TOP_ROOT_SRC_SEL_GPLL << + (src_clk << ACLK_TOP_ROOT_SRC_SEL_SHIFT) | (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT); break; @@ -1123,13 +1130,23 @@ static ulong rk3588_dclk_vop_set_clk(struct rk3588_clk_priv *priv, } if (sel == DCLK_VOP_SRC_SEL_V0PLL) { - div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate); - rk_clrsetreg(&cru->clksel_con[conid], - mask, - DCLK_VOP_SRC_SEL_V0PLL << sel_shift | - ((div - 1) << div_shift)); - rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], - priv->cru, V0PLL, div * rate); + pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], + priv->cru, V0PLL); + if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) { + div = DIV_ROUND_UP(pll_rate, rate); + rk_clrsetreg(&cru->clksel_con[conid], + mask, + DCLK_VOP_SRC_SEL_V0PLL << sel_shift | + ((div - 1) << div_shift)); + } else { + div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate); + rk_clrsetreg(&cru->clksel_con[conid], + mask, + DCLK_VOP_SRC_SEL_V0PLL << sel_shift | + ((div - 1) << div_shift)); + rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], + priv->cru, V0PLL, div * rate); + } } else { for (i = 0; i <= DCLK_VOP_SRC_SEL_AUPLL; i++) { switch (i) { diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 31aaf3340f9..a835541e48e 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -539,6 +539,16 @@ static int jh7110_stgcrg_init(struct udevice *dev) "pcie1_tl", "stg_axiahb", OFFSET(JH7110_STGCLK_PCIE1_TL))); + /* Security clocks */ + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK), + starfive_clk_gate(priv->reg, + "sec_ahb", "stg_axiahb", + OFFSET(JH7110_STGCLK_SEC_HCLK))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB), + starfive_clk_gate(priv->reg, + "sec_misc_ahb", "stg_axiahb", + OFFSET(JH7110_STGCLK_SEC_MISCAHB))); + return 0; } diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c index bf762c558ef..8323e6e6919 100644 --- a/drivers/clk/ti/clk-k3-pll.c +++ b/drivers/clk/ti/clk-k3-pll.c @@ -2,7 +2,7 @@ /* * Texas Instruments K3 SoC PLL clock driver * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ * Tero Kristo <t-kristo@ti.com> */ @@ -25,6 +25,23 @@ #define PLL_16FFT_FREQ_CTRL0 0x30 #define PLL_16FFT_FREQ_CTRL1 0x34 #define PLL_16FFT_DIV_CTRL 0x38 +#define PLL_16FFT_CAL_CTRL 0x60 +#define PLL_16FFT_CAL_STAT 0x64 + +/* CAL STAT register bits */ +#define PLL_16FFT_CAL_STAT_CAL_LOCK BIT(31) + +/* CFG register bits */ +#define PLL_16FFT_CFG_PLL_TYPE_SHIFT (0) +#define PLL_16FFT_CFG_PLL_TYPE_MASK (0x3 << 0) +#define PLL_16FFT_CFG_PLL_TYPE_FRACF 1 + +/* CAL CTRL register bits */ +#define PLL_16FFT_CAL_CTRL_CAL_EN BIT(31) +#define PLL_16FFT_CAL_CTRL_FAST_CAL BIT(20) +#define PLL_16FFT_CAL_CTRL_CAL_BYP BIT(15) +#define PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT 16 +#define PLL_16FFT_CAL_CTRL_CAL_CNT_MASK (0x7 << 16) /* CTRL register bits */ #define PLL_16FFT_CTRL_BYPASS_EN BIT(31) @@ -40,9 +57,14 @@ /* DIV CTRL register bits */ #define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f -#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24 +/* HSDIV register bits*/ #define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15) +/* FREQ_CTRL1 bits */ +#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24 +#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK 0xffffff +#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT 0 + /* KICK register magic values */ #define PLL_KICK0_VALUE 0x68ef3490 #define PLL_KICK1_VALUE 0xd172bc5a @@ -63,18 +85,65 @@ static int ti_pll_wait_for_lock(struct clk *clk) { struct ti_pll_clk *pll = to_clk_pll(clk); u32 stat; + u32 cfg; + u32 cal; + u32 freq_ctrl1; int i; + u32 pllfm; + u32 pll_type; + int success; for (i = 0; i < 100000; i++) { stat = readl(pll->reg + PLL_16FFT_STAT); - if (stat & PLL_16FFT_STAT_LOCK) - return 0; + if (stat & PLL_16FFT_STAT_LOCK) { + success = 1; + break; + } } - printf("%s: pll (%s) failed to lock\n", __func__, - clk->dev->name); + /* Enable calibration if not in fractional mode of the FRACF PLL */ + freq_ctrl1 = readl(pll->reg + PLL_16FFT_FREQ_CTRL1); + pllfm = freq_ctrl1 & PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_MASK; + pllfm >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_SHIFT; + cfg = readl(pll->reg + PLL_16FFT_CFG); + pll_type = (cfg & PLL_16FFT_CFG_PLL_TYPE_MASK) >> PLL_16FFT_CFG_PLL_TYPE_SHIFT; + + if (success && pll_type == PLL_16FFT_CFG_PLL_TYPE_FRACF && pllfm == 0) { + cal = readl(pll->reg + PLL_16FFT_CAL_CTRL); - return -EBUSY; + /* Enable calibration for FRACF */ + cal |= PLL_16FFT_CAL_CTRL_CAL_EN; + + /* Enable fast cal mode */ + cal |= PLL_16FFT_CAL_CTRL_FAST_CAL; + + /* Disable calibration bypass */ + cal &= ~PLL_16FFT_CAL_CTRL_CAL_BYP; + + /* Set CALCNT to 2 */ + cal &= ~PLL_16FFT_CAL_CTRL_CAL_CNT_MASK; + cal |= 2 << PLL_16FFT_CAL_CTRL_CAL_CNT_SHIFT; + + /* Note this register does not readback the written value. */ + writel(cal, pll->reg + PLL_16FFT_CAL_CTRL); + + success = 0; + for (i = 0; i < 100000; i++) { + stat = readl(pll->reg + PLL_16FFT_CAL_STAT); + if (stat & PLL_16FFT_CAL_STAT_CAL_LOCK) { + success = 1; + break; + } + } + } + + if (success == 0) { + printf("%s: pll (%s) failed to lock\n", __func__, + clk->dev->name); + return -EBUSY; + } else { + return 0; + } } static ulong ti_pll_clk_get_rate(struct clk *clk) diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 10f7240f77a..eb76195bd75 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -2,7 +2,7 @@ /* * Texas Instruments K3 clock driver * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ * Tero Kristo <t-kristo@ti.com> */ diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c index 8fc3254c996..9e5760d3354 100644 --- a/drivers/clk/ti/clk-sci.c +++ b/drivers/clk/ti/clk-sci.c @@ -2,7 +2,7 @@ /* * Texas Instruments System Control Interface (TI SCI) clock driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Andreas Dannenberg <dannenberg@ti.com> * * Loosely based on Linux kernel sci-clk.c... diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 29a42945102..f72ea416cf1 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -991,6 +991,24 @@ ofnode ofnode_get_chosen_node(const char *name) return ofnode_path(prop); } +int ofnode_read_baud(void) +{ + const char *str, *p; + u32 baud; + + str = ofnode_read_chosen_string("stdout-path"); + if (!str) + return -EINVAL; + + /* Parse string serial0:115200n8 */ + p = strchr(str, ':'); + if (!p) + return -EINVAL; + + baud = dectoul(p + 1, NULL); + return baud; +} + const void *ofnode_read_aliases_prop(const char *propname, int *sizep) { ofnode node; diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 91a51cc5fe7..eaad19633f1 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -77,7 +77,6 @@ endif config FSL_DCP_RNG bool "Enable Random Number Generator support" depends on DM_RNG - default n help Enable support for the hardware based random number generator module of the DCP. It uses the True Random Number Generator (TRNG) diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index cdb3c18b01d..12c54e90ef7 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -387,6 +387,16 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char **argv, int a dfu->data.mmc.lba_blk_size = mmc->read_bl_len; /* + * In case the size is zero (i.e. mmc raw 0x10 0), + * assume the user intends to use whole device. + */ + if (third_arg == 0) { + struct blk_desc *blk_dev = mmc_get_blk_desc(mmc); + + dfu->data.mmc.lba_size = blk_dev->lba; + } + + /* * Check for an extra entry at dfu_alt_info env variable * specifying the mmc HW defined partition number */ diff --git a/drivers/dma/ti/k3-psil-am64.c b/drivers/dma/ti/k3-psil-am64.c index 15742c3723d..6180e2a1996 100644 --- a/drivers/dma/ti/k3-psil-am64.c +++ b/drivers/dma/ti/k3-psil-am64.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> */ diff --git a/drivers/dma/ti/k3-psil-am654.c b/drivers/dma/ti/k3-psil-am654.c index d16c07566b5..ce86600e556 100644 --- a/drivers/dma/ti/k3-psil-am654.c +++ b/drivers/dma/ti/k3-psil-am654.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> */ diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index 28078c6bd8d..563bc57e206 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com */ #ifndef K3_PSIL_PRIV_H_ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index f23c8ca2b74..963321aa1e3 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> */ diff --git a/drivers/dma/ti/k3-psil.h b/drivers/dma/ti/k3-psil.h index 1e0fe06c0a4..af60a9924e2 100644 --- a/drivers/dma/ti/k3-psil.h +++ b/drivers/dma/ti/k3-psil.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com */ #ifndef K3_PSIL_H_ diff --git a/drivers/dma/ti/k3-udma-hwdef.h b/drivers/dma/ti/k3-udma-hwdef.h index 5d50bbcb031..3d6b4d10fff 100644 --- a/drivers/dma/ti/k3-udma-hwdef.h +++ b/drivers/dma/ti/k3-udma-hwdef.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com * * * This program is free software; you can redistribute it and/or modify diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 9273c70e9d9..8a62d63dfef 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> */ #define pr_fmt(fmt) "udma: " fmt diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c index 8c17b19eaf5..f1e91d151ea 100644 --- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c +++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c @@ -144,8 +144,6 @@ static int ffa_print_error_log(u32 ffa_id, int ffa_errno) return -EINVAL; abi_idx = FFA_ID_TO_ERRMAP_ID(ffa_id); - if (abi_idx < 0 || abi_idx >= FFA_ERRMAP_COUNT) - return -EINVAL; if (!err_msg_map[abi_idx].err_str[err_idx]) return -EINVAL; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 43fb7fa7787..8ea15c7ed33 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -203,6 +203,8 @@ int zynqmp_pm_feature(const u32 api_id) /* Check feature check API version */ ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0, ret_payload); + if (ret) + return ret; /* Return feature check version */ return ret_payload[1] & FIRMWARE_VERSION_MASK; diff --git a/drivers/firmware/scmi/Makefile b/drivers/firmware/scmi/Makefile index 1a23d498170..dae42863589 100644 --- a/drivers/firmware/scmi/Makefile +++ b/drivers/firmware/scmi/Makefile @@ -4,4 +4,5 @@ obj-y += smt.o obj-$(CONFIG_SCMI_AGENT_SMCCC) += smccc_agent.o obj-$(CONFIG_SCMI_AGENT_MAILBOX) += mailbox_agent.o obj-$(CONFIG_SCMI_AGENT_OPTEE) += optee_agent.o +obj-$(CONFIG_SCMI_POWER_DOMAIN) += pwdom.o obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o diff --git a/drivers/firmware/scmi/pwdom.c b/drivers/firmware/scmi/pwdom.c new file mode 100644 index 00000000000..de2ba4755ac --- /dev/null +++ b/drivers/firmware/scmi/pwdom.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SCMI Power domain management protocol + * + * Copyright (C) 2023 Linaro Limited + * author: AKASHI Takahiro <takahiro.akashi@linaro.org> + */ + +#include <dm.h> +#include <malloc.h> +#include <scmi_agent.h> +#include <scmi_protocols.h> +#include <string.h> +#include <asm/types.h> + +int scmi_pwd_protocol_attrs(struct udevice *dev, int *num_pwdoms, + u64 *stats_addr, size_t *stats_len) +{ + struct scmi_pwd_protocol_attrs_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN, + .message_id = SCMI_PROTOCOL_ATTRIBUTES, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + if (!dev || !num_pwdoms || !stats_addr || !stats_len) + return -EINVAL; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + *num_pwdoms = SCMI_PWD_PROTO_ATTRS_NUM_PWD(out.attributes); + *stats_addr = ((u64)out.stats_addr_high << 32) + out.stats_addr_low; + *stats_len = out.stats_len; + + return 0; +} + +int scmi_pwd_protocol_message_attrs(struct udevice *dev, s32 message_id, + u32 *attributes) +{ + struct scmi_pwd_protocol_msg_attrs_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN, + .message_id = SCMI_PROTOCOL_MESSAGE_ATTRIBUTES, + .in_msg = (u8 *)&message_id, + .in_msg_sz = sizeof(message_id), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + if (!dev || !attributes) + return -EINVAL; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + *attributes = out.attributes; + + return 0; +} + +int scmi_pwd_attrs(struct udevice *dev, u32 domain_id, u32 *attributes, + u8 **name) +{ + struct scmi_pwd_attrs_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN, + .message_id = SCMI_PWD_ATTRIBUTES, + .in_msg = (u8 *)&domain_id, + .in_msg_sz = sizeof(domain_id), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + if (!dev || !attributes || !name) + return -EINVAL; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + *name = strdup(out.name); + if (!*name) + return -ENOMEM; + + *attributes = out.attributes; + + return 0; +} + +int scmi_pwd_state_set(struct udevice *dev, u32 flags, u32 domain_id, + u32 pstate) +{ + struct scmi_pwd_state_set_in in; + s32 status; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN, + .message_id = SCMI_PWD_STATE_SET, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&status, + .out_msg_sz = sizeof(status), + }; + int ret; + + if (!dev) + return -EINVAL; + + in.flags = flags; + in.domain_id = domain_id; + in.pstate = pstate; + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (status) + return scmi_to_linux_errno(status); + + return 0; +} + +int scmi_pwd_state_get(struct udevice *dev, u32 domain_id, u32 *pstate) +{ + struct scmi_pwd_state_get_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN, + .message_id = SCMI_PWD_STATE_GET, + .in_msg = (u8 *)&domain_id, + .in_msg_sz = sizeof(domain_id), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + if (!dev || !pstate) + return -EINVAL; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + *pstate = out.pstate; + + return 0; +} + +int scmi_pwd_name_get(struct udevice *dev, u32 domain_id, u8 **name) +{ + struct scmi_pwd_name_get_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_POWER_DOMAIN, + .message_id = SCMI_PWD_NAME_GET, + .in_msg = (u8 *)&domain_id, + .in_msg_sz = sizeof(domain_id), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + if (!dev || !name) + return -EINVAL; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + *name = strdup(out.extended_name); + if (!*name) + return -ENOMEM; + + return 0; +} diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c index eb567dd900d..d1318096266 100644 --- a/drivers/firmware/scmi/sandbox-scmi_agent.c +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -43,6 +43,8 @@ #define SANDBOX_SCMI_AGENT_NAME "OSPM" #define SANDBOX_SCMI_PLATFORM_NAME "platform" +#define SANDBOX_SCMI_PWD_PROTOCOL_VERSION SCMI_PWD_PROTOCOL_VERSION + /** * struct sandbox_channel - Description of sandbox transport * @channel_id: Channel identifier @@ -64,6 +66,7 @@ struct scmi_channel { }; static u8 protocols[] = { + SCMI_PROTOCOL_ID_POWER_DOMAIN, SCMI_PROTOCOL_ID_CLOCK, SCMI_PROTOCOL_ID_RESET_DOMAIN, SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN, @@ -71,6 +74,12 @@ static u8 protocols[] = { #define NUM_PROTOCOLS ARRAY_SIZE(protocols) +static struct sandbox_scmi_pwd scmi_pwdom[] = { + { .id = 0 }, + { .id = 1 }, + { .id = 2 }, +}; + static struct sandbox_scmi_clk scmi_clk[] = { { .rate = 333 }, { .rate = 200 }, @@ -458,6 +467,238 @@ static int sandbox_scmi_base_reset_agent_configuration(struct udevice *dev, return 0; } +/* Power Domain Management Protocol */ + +/** + * sandbox_scmi_pwd_protocol_version - implement SCMI_PROTOCOL_VERSION + * @dev: SCMI device + * @msg: SCMI message + * + * Implement SCMI_PROTOCOL_VERSION command. + * + * Return: 0 on success, error code on failure + */ +static int sandbox_scmi_pwd_protocol_version(struct udevice *dev, + struct scmi_msg *msg) +{ + struct scmi_protocol_version_out *out = NULL; + + if (!msg->out_msg || msg->out_msg_sz < sizeof(*out)) + return -EINVAL; + + out = (struct scmi_protocol_version_out *)msg->out_msg; + out->version = SANDBOX_SCMI_PWD_PROTOCOL_VERSION; + out->status = SCMI_SUCCESS; + + return 0; +} + +/** + * sandbox_scmi_pwd_protocol_attribs - implement SCMI_PWD_PROTOCOL_ATTRS + * @dev: SCMI device + * @msg: SCMI message + * + * Implement SCMI_PWD_PROTOCOL_ATTRS command. + * + * Return: 0 on success, error code on failure + */ +static int sandbox_scmi_pwd_protocol_attribs(struct udevice *dev, + struct scmi_msg *msg) +{ + struct scmi_pwd_protocol_attrs_out *out; + + if (!msg->out_msg || msg->out_msg_sz < sizeof(*out)) + return -EINVAL; + + out = (struct scmi_pwd_protocol_attrs_out *)msg->out_msg; + + out->attributes = ARRAY_SIZE(scmi_pwdom); + out->stats_addr_low = 0; + out->stats_addr_high = 0; + out->stats_len = 0; + out->status = SCMI_SUCCESS; + + return 0; +} + +/** + * sandbox_scmi_pwd_protocol_msg_attribs - implement + SCMI_PWD_PROTOCOL_MESSAGE_ATTRS + * @dev: SCMI device + * @msg: SCMI message + * + * Implement SCMI_PWD_PROTOCOL_MESSAGE_ATTRS command. + * + * Return: 0 on success, error code on failure + */ +static int sandbox_scmi_pwd_protocol_msg_attribs(struct udevice *dev, + struct scmi_msg *msg) +{ + u32 message_id; + struct scmi_pwd_protocol_msg_attrs_out *out; + + if (!msg->in_msg || msg->in_msg_sz < sizeof(message_id) || + !msg->out_msg || msg->out_msg_sz < sizeof(*out)) + return -EINVAL; + + message_id = *(u32 *)msg->in_msg; + + out = (struct scmi_pwd_protocol_msg_attrs_out *)msg->out_msg; + if (message_id <= SCMI_PWD_STATE_GET || + message_id == SCMI_PWD_NAME_GET) { + out->attributes = 0; + out->status = SCMI_SUCCESS; + } else { + out->status = SCMI_NOT_FOUND; + } + + return 0; +} + +/** + * sandbox_scmi_pwd_attribs - implement SCMI_PWD_ATTRS + * @dev: SCMI device + * @msg: SCMI message + * + * Implement SCMI_PWD_ATTRS command. + * + * Return: 0 on success, error code on failure + */ +static int sandbox_scmi_pwd_attribs(struct udevice *dev, struct scmi_msg *msg) +{ + u32 domain_id; + struct scmi_pwd_attrs_out *out; + + if (!msg->in_msg || msg->in_msg_sz < sizeof(domain_id) || + !msg->out_msg || msg->out_msg_sz < sizeof(*out)) + return -EINVAL; + + domain_id = *(u32 *)msg->in_msg; + out = (struct scmi_pwd_attrs_out *)msg->out_msg; + + if (domain_id >= ARRAY_SIZE(scmi_pwdom)) { + out->status = SCMI_NOT_FOUND; + + return 0; + } + + out->attributes = + SCMI_PWD_ATTR_PSTATE_SYNC | SCMI_PWD_ATTR_EXTENDED_NAME; + /* just 15-char + NULL */ + snprintf(out->name, SCMI_PWD_NAME_LENGTH_MAX, "power-domain--%d", + domain_id); + out->status = SCMI_SUCCESS; + + return 0; +} + +/** + * sandbox_scmi_pwd_state_set - implement SCMI_PWD_STATE_SET + * @dev: SCMI device + * @msg: SCMI message + * + * Implement SCMI_PWD_STATE_SET command. + * + * Return: 0 on success, error code on failure + */ +static int sandbox_scmi_pwd_state_set(struct udevice *dev, struct scmi_msg *msg) +{ + struct scmi_pwd_state_set_in *in; + s32 *status; + + if (!msg->in_msg || msg->in_msg_sz < sizeof(in) || + !msg->out_msg || msg->out_msg_sz < sizeof(*status)) + return -EINVAL; + + in = (struct scmi_pwd_state_set_in *)msg->in_msg; + status = (s32 *)msg->out_msg; + + if (in->domain_id >= ARRAY_SIZE(scmi_pwdom)) { + *status = SCMI_NOT_FOUND; + + return 0; + } + + if ((in->flags & SCMI_PWD_SET_FLAGS_ASYNC) || + (in->pstate != SCMI_PWD_PSTATE_TYPE_LOST && in->pstate)) { + *status = SCMI_INVALID_PARAMETERS; + + return 0; + } + + scmi_pwdom[in->domain_id].pstate = in->pstate; + *status = SCMI_SUCCESS; + + return 0; +} + +/** + * sandbox_scmi_pwd_state_get - implement SCMI_PWD_STATE_GET + * @dev: SCMI device + * @msg: SCMI message + * + * Implement SCMI_PWD_STATE_GET command. + * + * Return: 0 on success, error code on failure + */ +static int sandbox_scmi_pwd_state_get(struct udevice *dev, struct scmi_msg *msg) +{ + u32 domain_id; + struct scmi_pwd_state_get_out *out; + + if (!msg->in_msg || msg->in_msg_sz < sizeof(domain_id) || + !msg->out_msg || msg->out_msg_sz < sizeof(*out)) + return -EINVAL; + + domain_id = *(u32 *)msg->in_msg; + out = (struct scmi_pwd_state_get_out *)msg->out_msg; + + if (domain_id >= ARRAY_SIZE(scmi_pwdom)) { + out->status = SCMI_NOT_FOUND; + + return 0; + } + + out->pstate = scmi_pwdom[domain_id].pstate; + out->status = SCMI_SUCCESS; + + return 0; +} + +/** + * sandbox_scmi_pwd_name_get - implement SCMI_PWD_NAME_GET + * @dev: SCMI device + * @msg: SCMI message + * + * Implement SCMI_PWD_NAME_GET command. + * + * Return: 0 on success, error code on failure + */ +static int sandbox_scmi_pwd_name_get(struct udevice *dev, struct scmi_msg *msg) +{ + u32 domain_id; + struct scmi_pwd_name_get_out *out; + + if (!msg->in_msg || msg->in_msg_sz < sizeof(domain_id) || + !msg->out_msg || msg->out_msg_sz < sizeof(*out)) + return -EINVAL; + + domain_id = *(u32 *)msg->in_msg; + out = (struct scmi_pwd_name_get_out *)msg->out_msg; + + if (domain_id >= ARRAY_SIZE(scmi_pwdom)) { + out->status = SCMI_NOT_FOUND; + + return 0; + } + + snprintf(out->extended_name, SCMI_PWD_EXTENDED_NAME_MAX, + "power-domain--%d-extended", domain_id); + out->status = SCMI_SUCCESS; + + return 0; +} + /* Clock Protocol */ static int sandbox_scmi_clock_protocol_attribs(struct udevice *dev, @@ -918,6 +1159,26 @@ static int sandbox_scmi_test_process_msg(struct udevice *dev, break; } break; + case SCMI_PROTOCOL_ID_POWER_DOMAIN: + switch (msg->message_id) { + case SCMI_PROTOCOL_VERSION: + return sandbox_scmi_pwd_protocol_version(dev, msg); + case SCMI_PROTOCOL_ATTRIBUTES: + return sandbox_scmi_pwd_protocol_attribs(dev, msg); + case SCMI_PROTOCOL_MESSAGE_ATTRIBUTES: + return sandbox_scmi_pwd_protocol_msg_attribs(dev, msg); + case SCMI_PWD_ATTRIBUTES: + return sandbox_scmi_pwd_attribs(dev, msg); + case SCMI_PWD_STATE_SET: + return sandbox_scmi_pwd_state_set(dev, msg); + case SCMI_PWD_STATE_GET: + return sandbox_scmi_pwd_state_get(dev, msg); + case SCMI_PWD_NAME_GET: + return sandbox_scmi_pwd_name_get(dev, msg); + default: + break; + } + break; case SCMI_PROTOCOL_ID_CLOCK: switch (msg->message_id) { case SCMI_PROTOCOL_ATTRIBUTES: @@ -960,7 +1221,6 @@ static int sandbox_scmi_test_process_msg(struct udevice *dev, break; } break; - case SCMI_PROTOCOL_ID_POWER_DOMAIN: case SCMI_PROTOCOL_ID_SYSTEM: case SCMI_PROTOCOL_ID_PERF: case SCMI_PROTOCOL_ID_SENSOR: @@ -993,6 +1253,9 @@ static int sandbox_scmi_test_probe(struct udevice *dev) struct sandbox_scmi_agent *agent = dev_get_priv(dev); *agent = (struct sandbox_scmi_agent){ + .pwdom_version = SANDBOX_SCMI_PWD_PROTOCOL_VERSION, + .pwdom = scmi_pwdom, + .pwdom_count = ARRAY_SIZE(scmi_pwdom), .clk = scmi_clk, .clk_count = ARRAY_SIZE(scmi_clk), .reset = scmi_reset, diff --git a/drivers/firmware/scmi/sandbox-scmi_devices.c b/drivers/firmware/scmi/sandbox-scmi_devices.c index 9baeb469ec0..facb5b06ffb 100644 --- a/drivers/firmware/scmi/sandbox-scmi_devices.c +++ b/drivers/firmware/scmi/sandbox-scmi_devices.c @@ -29,12 +29,14 @@ /* * struct sandbox_scmi_device_priv - Storage for device handles used by test + * @pwdom: Power domain device * @clk: Array of clock instances used by tests * @reset_clt: Array of the reset controller instances used by tests * @regulators: Array of regulator device references used by the tests * @devices: Resources exposed by sandbox_scmi_devices_ctx() */ struct sandbox_scmi_device_priv { + struct power_domain pwdom; struct clk clk[SCMI_TEST_DEVICES_CLK_COUNT]; struct reset_ctl reset_ctl[SCMI_TEST_DEVICES_RD_COUNT]; struct udevice *regulators[SCMI_TEST_DEVICES_VOLTD_COUNT]; @@ -77,6 +79,8 @@ static int sandbox_scmi_devices_probe(struct udevice *dev) size_t n; priv->devices = (struct sandbox_scmi_devices){ + .pwdom = &priv->pwdom, + .pwdom_count = 1, .clk = priv->clk, .clk_count = SCMI_TEST_DEVICES_CLK_COUNT, .reset = priv->reset_ctl, @@ -85,6 +89,12 @@ static int sandbox_scmi_devices_probe(struct udevice *dev) .regul_count = SCMI_TEST_DEVICES_VOLTD_COUNT, }; + ret = power_domain_get_by_index(dev, priv->devices.pwdom, 0); + if (ret) { + dev_err(dev, "%s: Failed on power domain\n", __func__); + return ret; + } + for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) { ret = clk_get_by_index(dev, n, priv->devices.clk + n); if (ret) { diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 6f585b96f74..0f1003e167e 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -86,6 +86,9 @@ struct udevice *scmi_get_protocol(struct udevice *dev, case SCMI_PROTOCOL_ID_BASE: proto = priv->base_dev; break; + case SCMI_PROTOCOL_ID_POWER_DOMAIN: + proto = priv->pwdom_dev; + break; case SCMI_PROTOCOL_ID_CLOCK: proto = priv->clock_dev; break; @@ -133,6 +136,9 @@ static int scmi_add_protocol(struct udevice *dev, case SCMI_PROTOCOL_ID_BASE: priv->base_dev = proto; break; + case SCMI_PROTOCOL_ID_POWER_DOMAIN: + priv->pwdom_dev = proto; + break; case SCMI_PROTOCOL_ID_CLOCK: priv->clock_dev = proto; break; @@ -405,6 +411,11 @@ static int scmi_bind_protocols(struct udevice *dev) drv = NULL; name = ofnode_get_name(node); switch (protocol_id) { + case SCMI_PROTOCOL_ID_POWER_DOMAIN: + if (CONFIG_IS_ENABLED(SCMI_POWER_DOMAIN) && + scmi_protocol_is_supported(dev, protocol_id)) + drv = DM_DRIVER_GET(scmi_power_domain); + break; case SCMI_PROTOCOL_ID_CLOCK: if (CONFIG_IS_ENABLED(CLK_SCMI) && scmi_protocol_is_supported(dev, protocol_id)) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 166bd78ca50..6e9f93e9a30 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -3,7 +3,7 @@ * Texas Instruments System Control Interface Protocol Driver * Based on drivers/firmware/ti_sci.c from Linux. * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index 101210eb215..bb8bc7beead 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -6,7 +6,7 @@ * The system works in a message response protocol * See: http://processors.wiki.ti.com/index.php/TISCI for details * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Based on drivers/firmware/ti_sci.h from Linux. * */ diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index 1a461fab619..567ce8911a7 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause */ /* - * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ * */ diff --git a/drivers/gpio/pcf8575_gpio.c b/drivers/gpio/pcf8575_gpio.c index d5930d941fc..f38e215c4d6 100644 --- a/drivers/gpio/pcf8575_gpio.c +++ b/drivers/gpio/pcf8575_gpio.c @@ -2,7 +2,7 @@ /* * PCF8575 I2C GPIO EXPANDER DRIVER * - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ * * Vignesh R <vigneshr@ti.com> * diff --git a/drivers/gpio/rzg2l-gpio.c b/drivers/gpio/rzg2l-gpio.c index 7c908d05475..2477af7874b 100644 --- a/drivers/gpio/rzg2l-gpio.c +++ b/drivers/gpio/rzg2l-gpio.c @@ -5,7 +5,6 @@ * Copyright (C) 2021-2023 Renesas Electronics Corp. */ -#include <common.h> #include <asm-generic/gpio.h> #include <asm/io.h> #include <dm/device.h> diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index e54de42abc3..215ce010cb7 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -24,6 +24,17 @@ */ #define DW_I2C_COMP_TYPE 0x44570140 +/* + * This constant is used to calculate when during the clock high phase the data + * bit shall be read. The value was copied from the Linux v6.5 function + * i2c_dw_scl_hcnt() which provides the following explanation: + * + * "This is just an experimental rule: the tHD;STA period turned out to be + * proportinal to (_HCNT + 3). With this setting, we could meet both tHIGH and + * tHD;STA timing specs." + */ +#define T_HD_STA_OFFSET 3 + static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) { u32 ena = enable ? IC_ENABLE_0B : 0; @@ -155,10 +166,10 @@ static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode, /* * Back-solve for hcnt and lcnt according to the following equations: - * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time + * SCL_High_time = [(HCNT + IC_*_SPKLEN + T_HD_STA_OFFSET) * ic_clk] + SCL_Fall_time * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time */ - hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt; + hcnt = min_thigh_cnt - fall_cnt - T_HD_STA_OFFSET - spk_cnt; lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1; if (hcnt < 0 || lcnt < 0) { @@ -170,13 +181,13 @@ static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode, * Now add things back up to ensure the period is hit. If it is off, * split the difference and bias to lcnt for remainder */ - tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1; + tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1; if (tot < period_cnt) { diff = (period_cnt - tot) / 2; hcnt += diff; lcnt += diff; - tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1; + tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1; lcnt += period_cnt - tot; } diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index 8867a560bd8..5405067861e 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -388,6 +388,81 @@ int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, return 0; } +/* Find and probe I2C bus based on a chip attached to it */ +static int i2c_get_parent_bus(ofnode chip, struct udevice **devp) +{ + ofnode node; + struct udevice *dev; + int ret; + + node = ofnode_get_parent(chip); + if (!ofnode_valid(node)) + return -ENODEV; + + ret = uclass_get_device_by_ofnode(UCLASS_I2C, node, &dev); + if (ret) { + *devp = NULL; + return ret; + } + + *devp = dev; + return 0; +} + +int i2c_get_chip_by_phandle(const struct udevice *parent, const char *prop_name, + struct udevice **devp) +{ + ofnode node; + uint phandle; + struct udevice *bus, *chip; + char *dev_name; + int ret; + + debug("%s: Searching I2C chip for phandle \"%s\"\n", + __func__, prop_name); + + dev_name = strdup(prop_name); + if (!dev_name) { + ret = -ENOMEM; + goto err_exit; + } + + ret = dev_read_u32(parent, "i2cbcdev", &phandle); + if (ret) + goto err_exit; + + node = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(node)) { + ret = -ENODEV; + goto err_exit; + } + + ret = i2c_get_parent_bus(node, &bus); + if (ret) + goto err_exit; + + ret = device_bind_driver_to_node(bus, "i2c_generic_chip_drv", + dev_name, node, &chip); + if (ret) + goto err_exit; + + ret = device_probe(chip); + if (ret) { + device_unbind(chip); + goto err_exit; + } + + debug("%s succeeded\n", __func__); + *devp = chip; + return 0; + +err_exit: + free(dev_name); + debug("%s failed, ret = %d\n", __func__, ret); + *devp = NULL; + return ret; +} + int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, struct udevice **devp) { diff --git a/drivers/i2c/npcm_i2c.c b/drivers/i2c/npcm_i2c.c index ea4ef532565..b867b6c8e91 100644 --- a/drivers/i2c/npcm_i2c.c +++ b/drivers/i2c/npcm_i2c.c @@ -517,11 +517,6 @@ static int npcm_i2c_init_clk(struct npcm_i2c_bus *bus, u32 bus_freq) u32 sclfrq; u8 hldt, val; - if (bus_freq > I2C_FREQ_100K) { - printf("Support standard mode only\n"); - return -EINVAL; - } - /* SCLFRQ = T(SCL)/4/T(CLK) = FREQ(CLK)/4/FREQ(SCL) */ sclfrq = freq / (bus_freq * 4); if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX) diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index e0a18d8a97d..05f6b1795d6 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -2,7 +2,7 @@ /* * Texas Instruments' K3 Secure proxy Driver * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 22cb9d637c5..d10edd27746 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -61,7 +61,6 @@ config TI_GPMC if TI_GPMC config TI_GPMC_DEBUG bool "Debug Texas Instruments GPMC timings" - default n help Enable this to print GPMC timings before and after the GPMC registers are programmed. This should not be left enabled on production systems. diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index f511a529b1e..775e78c9a5b 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -2,7 +2,7 @@ /* * Texas Instruments GPMC Driver * - * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include <asm/io.h> diff --git a/drivers/memory/ti-gpmc.h b/drivers/memory/ti-gpmc.h index 90f8e656c8f..6fe098af0ec 100644 --- a/drivers/memory/ti-gpmc.h +++ b/drivers/memory/ti-gpmc.h @@ -2,7 +2,7 @@ /* * Texas Instruments GPMC Driver * - * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ /* GPMC register offsets */ diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index fccd9b89b81..97057de8bf9 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -375,7 +375,6 @@ config SPL_MXC_OCOTP config NPCM_OTP bool "Nnvoton NPCM BMC On-Chip OTP Memory Support" depends on (ARM && ARCH_NPCM) - default n help Support NPCM BMC OTP memory (fuse). To compile this driver as a module, choose M here: the module diff --git a/drivers/misc/cros_ec_spi.c b/drivers/misc/cros_ec_spi.c index 001f0a85ca9..591ff30df89 100644 --- a/drivers/misc/cros_ec_spi.c +++ b/drivers/misc/cros_ec_spi.c @@ -151,7 +151,7 @@ int cros_ec_spi_command(struct udevice *udev, uint8_t cmd, int cmd_version, /* Response code is first byte of message */ if (p[0] != EC_RES_SUCCESS) { - printf("%s: Returned status %d\n", __func__, p[0]); + log_debug("Returned status %d\n", p[0]); return -(int)(p[0]); } diff --git a/drivers/misc/esm_pmic.c b/drivers/misc/esm_pmic.c index b971f32f6a1..a518f750611 100644 --- a/drivers/misc/esm_pmic.c +++ b/drivers/misc/esm_pmic.c @@ -2,7 +2,7 @@ /* * PMIC Error Signal Monitor driver * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Tero Kristo <t-kristo@ti.com> * */ diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index bdd7e018cc6..9111bd724cb 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -60,6 +60,17 @@ static int i2c_eeprom_std_read(struct udevice *dev, int offset, uint8_t *buf, return dm_i2c_read(dev, offset, buf, size); } +static int i2c_eeprom_len(int offset, int len, int pagesize) +{ + int page_offset = offset & (pagesize - 1); + int maxlen = pagesize - page_offset; + + if (len > maxlen) + len = maxlen; + + return len; +} + static int i2c_eeprom_std_write(struct udevice *dev, int offset, const uint8_t *buf, int size) { @@ -67,7 +78,7 @@ static int i2c_eeprom_std_write(struct udevice *dev, int offset, int ret; while (size > 0) { - int write_size = min_t(int, size, priv->pagesize); + int write_size = i2c_eeprom_len(offset, size, priv->pagesize); ret = dm_i2c_write(dev, offset, buf, write_size); if (ret) @@ -227,6 +238,13 @@ static const struct i2c_eeprom_drv_data atmel24c32_data = { .offset_len = 2, }; +static const struct i2c_eeprom_drv_data atmel24c32d_wlp_data = { + .size = 32, + .pagesize = 32, + .addr_offset_mask = 0, + .offset_len = 2, +}; + static const struct i2c_eeprom_drv_data atmel24c64_data = { .size = 8192, .pagesize = 32, @@ -266,6 +284,7 @@ static const struct udevice_id i2c_eeprom_std_ids[] = { { .compatible = "atmel,24c16a", (ulong)&atmel24c16a_data }, { .compatible = "atmel,24mac402", (ulong)&atmel24mac402_data }, { .compatible = "atmel,24c32", (ulong)&atmel24c32_data }, + { .compatible = "atmel,24c32d-wl", (ulong)&atmel24c32d_wlp_data }, { .compatible = "atmel,24c64", (ulong)&atmel24c64_data }, { .compatible = "atmel,24c128", (ulong)&atmel24c128_data }, { .compatible = "atmel,24c256", (ulong)&atmel24c256_data }, diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index acfc7318452..0d29eff1ac0 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -2,7 +2,7 @@ /* * Texas Instruments' K3 Clas 0 Adaptive Voltage Scaling driver * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Tero Kristo <t-kristo@ti.com> * */ @@ -15,6 +15,7 @@ #include <k3-avs.h> #include <dm/device_compat.h> #include <linux/bitops.h> +#include <linux/delay.h> #include <power/regulator.h> #define AM6_VTM_DEVINFO(i) (priv->base + 0x100 + 0x20 * (i)) @@ -25,11 +26,28 @@ #define AM6_VTM_OPP_SHIFT(opp) (8 * (opp)) #define AM6_VTM_OPP_MASK 0xff +#define K3_VTM_DEVINFO_PWR0_OFFSET 0x4 +#define K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK 0xf0 +#define K3_VTM_TMPSENS0_CTRL_OFFSET 0x300 +#define K3_VTM_TMPSENS_STAT_OFFSET 0x8 +#define K3_VTM_ANYMAXT_OUTRG_ALERT_EN 0x1 +#define K3_VTM_LOW_TEMP_OFFSET 0x10 +#define K3_VTM_MISC_CTRL2_OFFSET 0x10 +#define K3_VTM_MISC_CTRL1_OFFSET 0xc +#define K3_VTM_TMPSENS_CTRL1_SOC BIT(5) +#define K3_VTM_TMPSENS_CTRL_CLRZ BIT(6) +#define K3_VTM_TMPSENS_CTRL_MAXT_OUTRG_EN BIT(11) +#define K3_VTM_ADC_COUNT_FOR_123C 0x2f8 +#define K3_VTM_ADC_COUNT_FOR_105C 0x288 +#define K3_VTM_ADC_WA_VALUE 0x2c +#define K3_VTM_FUSE_MASK 0xc0000000 + #define VD_FLAG_INIT_DONE BIT(0) struct k3_avs_privdata { void *base; struct vd_config *vd_config; + struct udevice *dev; }; struct opp { @@ -237,6 +255,88 @@ static int k3_avs_configure(struct udevice *dev, struct k3_avs_privdata *priv) return 0; } +/* k3_avs_program_tshut : Program thermal shutdown value for SOC + * set the values corresponding to thresholds to ~123C and 105C + * This is optional feature, Few times OS driver takes care of + * tshut programing. + */ + +static void k3_avs_program_tshut(struct k3_avs_privdata *priv) +{ + int cnt, id, val; + int workaround_needed = 0; + u32 ctrl_offset; + void __iomem *cfg2_base; + void __iomem *fuse_base; + + cfg2_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 1); + if (IS_ERR(cfg2_base)) { + dev_err(priv->dev, "cfg base is not defined\n"); + return; + } + + /* + * Some of TI's J721E SoCs require a software trimming procedure + * for the temperature monitors to function properly. To determine + * if this particular SoC is NOT affected, both bits in the + * WKUP_SPARE_FUSE0[31:30] will be set (0xC0000000) indicating + * when software trimming should NOT be applied. + * + * https://www.ti.com/lit/er/sprz455c/sprz455c.pdf + * This routine checks if workaround_needed to be applied or not + * based upon workaround_needed, adjust fixed value of tshut high and low + */ + + if (device_is_compatible(priv->dev, "ti,j721e-vtm")) { + fuse_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 2); + if (IS_ERR(fuse_base)) { + dev_err(priv->dev, "fuse-base is not defined for J721E Soc\n"); + return; + } + + if (!((readl(fuse_base) & K3_VTM_FUSE_MASK) == K3_VTM_FUSE_MASK)) + workaround_needed = 1; + } + + dev_dbg(priv->dev, "Work around %sneeded\n", workaround_needed ? "" : "not "); + + /* Get the sensor count in the VTM */ + val = readl(priv->base + K3_VTM_DEVINFO_PWR0_OFFSET); + cnt = val & K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK; + cnt >>= __ffs(K3_VTM_DEVINFO_PWR0_TEMPSENS_CT_MASK); + + /* Program the thermal sensors */ + for (id = 0; id < cnt; id++) { + ctrl_offset = K3_VTM_TMPSENS0_CTRL_OFFSET + id * 0x20; + + val = readl(cfg2_base + ctrl_offset); + val |= (K3_VTM_TMPSENS_CTRL_MAXT_OUTRG_EN | + K3_VTM_TMPSENS_CTRL1_SOC | + K3_VTM_TMPSENS_CTRL_CLRZ | BIT(4)); + writel(val, cfg2_base + ctrl_offset); + } + + /* + * Program TSHUT thresholds + * Step 1: set the thresholds to ~123C and 105C WKUP_VTM_MISC_CTRL2 + * Step 2: WKUP_VTM_TMPSENS_CTRL_j set the MAXT_OUTRG_EN bit + * This is already taken care as per of init + * Step 3: WKUP_VTM_MISC_CTRL set the ANYMAXT_OUTRG_ALERT_EN bit + */ + + /* Low thresholds for tshut*/ + val = (K3_VTM_ADC_COUNT_FOR_105C - workaround_needed * K3_VTM_ADC_WA_VALUE) + << K3_VTM_LOW_TEMP_OFFSET; + /* high thresholds */ + val |= K3_VTM_ADC_COUNT_FOR_123C - workaround_needed * K3_VTM_ADC_WA_VALUE; + + writel(val, cfg2_base + K3_VTM_MISC_CTRL2_OFFSET); + /* ramp-up delay from Linux code */ + mdelay(100); + val = readl(cfg2_base + K3_VTM_MISC_CTRL1_OFFSET) | K3_VTM_ANYMAXT_OUTRG_ALERT_EN; + writel(val, cfg2_base + K3_VTM_MISC_CTRL1_OFFSET); +} + /** * k3_avs_probe: parses VD info from VTM, and re-configures the OPP data * @@ -255,6 +355,7 @@ static int k3_avs_probe(struct udevice *dev) int ret; priv = dev_get_priv(dev); + priv->dev = dev; k3_avs_priv = priv; @@ -294,6 +395,9 @@ static int k3_avs_probe(struct udevice *dev) k3_avs_program_voltage(priv, vd, vd->opp); } + if (!device_is_compatible(priv->dev, "ti,am654-avs")) + k3_avs_program_tshut(priv); + return 0; } diff --git a/drivers/misc/k3_esm.c b/drivers/misc/k3_esm.c index 41faeb3d858..f6ac18bdc75 100644 --- a/drivers/misc/k3_esm.c +++ b/drivers/misc/k3_esm.c @@ -2,7 +2,7 @@ /* * Texas Instruments' K3 Error Signalling Module driver * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Tero Kristo <t-kristo@ti.com> * */ diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c index 4814e0e501c..4f757083a1b 100644 --- a/drivers/misc/rockchip-otp.c +++ b/drivers/misc/rockchip-otp.c @@ -61,11 +61,20 @@ #define RK3588_OTPC_INT_ST 0x0084 #define RK3588_RD_DONE BIT(1) +#define RV1126_OTP_NVM_CEB 0x00 +#define RV1126_OTP_NVM_RSTB 0x04 +#define RV1126_OTP_NVM_ST 0x18 +#define RV1126_OTP_NVM_RADDR 0x1C +#define RV1126_OTP_NVM_RSTART 0x20 +#define RV1126_OTP_NVM_RDATA 0x24 +#define RV1126_OTP_READ_ST 0x30 + struct rockchip_otp_plat { void __iomem *base; }; struct rockchip_otp_data { + int (*init)(struct udevice *dev); int (*read)(struct udevice *dev, int offset, void *buf, int size); int offset; int size; @@ -232,6 +241,48 @@ static int rockchip_rk3588_otp_read(struct udevice *dev, int offset, return 0; } +static int rockchip_rv1126_otp_init(struct udevice *dev) +{ + struct rockchip_otp_plat *otp = dev_get_plat(dev); + int ret; + + writel(0x0, otp->base + RV1126_OTP_NVM_CEB); + ret = rockchip_otp_poll_timeout(otp, 0x1, RV1126_OTP_NVM_ST); + + if (ret) + return ret; + + writel(0x1, otp->base + RV1126_OTP_NVM_RSTB); + ret = rockchip_otp_poll_timeout(otp, 0x4, RV1126_OTP_NVM_ST); + + if (ret) + return ret; + + return 0; +} + +static int rockchip_rv1126_otp_read(struct udevice *dev, int offset, void *buf, + int size) +{ + struct rockchip_otp_plat *otp = dev_get_plat(dev); + u32 status = 0; + u8 *buffer = buf; + int ret = 0; + + while (size--) { + writel(offset++, otp->base + RV1126_OTP_NVM_RADDR); + writel(0x1, otp->base + RV1126_OTP_NVM_RSTART); + ret = readl_poll_timeout(otp->base + RV1126_OTP_READ_ST, + status, !status, OTPC_TIMEOUT); + if (ret) + return ret; + + *buffer++ = (u8)(readl(otp->base + RV1126_OTP_NVM_RDATA) & 0xFF); + } + + return 0; +} + static int rockchip_otp_read(struct udevice *dev, int offset, void *buf, int size) { @@ -286,6 +337,20 @@ static int rockchip_otp_of_to_plat(struct udevice *dev) return 0; } +static int rockchip_otp_probe(struct udevice *dev) +{ + struct rockchip_otp_data *data; + + data = (struct rockchip_otp_data *)dev_get_driver_data(dev); + if (!data) + return -EINVAL; + + if (data->init) + return data->init(dev); + + return 0; +} + static const struct rockchip_otp_data px30_data = { .read = rockchip_px30_otp_read, .size = 0x40, @@ -304,6 +369,12 @@ static const struct rockchip_otp_data rk3588_data = { .block_size = 4, }; +static const struct rockchip_otp_data rv1126_data = { + .init = rockchip_rv1126_otp_init, + .read = rockchip_rv1126_otp_read, + .size = 0x40, +}; + static const struct udevice_id rockchip_otp_ids[] = { { .compatible = "rockchip,px30-otp", @@ -321,6 +392,10 @@ static const struct udevice_id rockchip_otp_ids[] = { .compatible = "rockchip,rk3588-otp", .data = (ulong)&rk3588_data, }, + { + .compatible = "rockchip,rv1126-otp", + .data = (ulong)&rv1126_data, + }, {} }; @@ -331,4 +406,5 @@ U_BOOT_DRIVER(rockchip_otp) = { .of_to_plat = rockchip_otp_of_to_plat, .plat_auto = sizeof(struct rockchip_otp_plat), .ops = &rockchip_otp_ops, + .probe = rockchip_otp_probe, }; diff --git a/drivers/misc/vexpress_config.c b/drivers/misc/vexpress_config.c index 2baca48109f..99aad1412ae 100644 --- a/drivers/misc/vexpress_config.c +++ b/drivers/misc/vexpress_config.c @@ -92,7 +92,7 @@ static struct misc_ops vexpress_config_ops = { static int vexpress_config_probe(struct udevice *dev) { struct ofnode_phandle_args args; - struct vexpress_config_sysreg *priv; + struct vexpress_config_sysreg *priv = dev_get_priv(dev); const char *prop; int err, prop_size; @@ -105,11 +105,9 @@ static int vexpress_config_probe(struct udevice *dev) if (!prop || (strncmp(prop, "arm,vexpress-sysreg", 19) != 0)) return -ENOENT; - priv = calloc(1, sizeof(*priv)); if (!priv) return -ENOMEM; - dev_get_uclass_priv(dev) = priv; priv->addr = ofnode_get_addr(args.node); return dev_read_u32(dev, "arm,vexpress,site", &priv->site); @@ -127,4 +125,5 @@ U_BOOT_DRIVER(vexpress_config_drv) = { .bind = dm_scan_fdt_dev, .probe = vexpress_config_probe, .ops = &vexpress_config_ops, + .priv_auto = sizeof(struct vexpress_config_sysreg), }; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index de01b9687ba..17618c3bdcc 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -46,6 +46,7 @@ config SPL_DM_MMC depends on SPL_DM && DM_MMC default n if ARCH_MVEBU && !MVEBU_SPL_BOOT_DEVICE_MMC default y + select SPL_BLK help This enables the MultiMediaCard (MMC) uclass which supports MMC and Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.) @@ -390,12 +391,6 @@ config HSMMC2_8BIT depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \ AM43XX || ARCH_KEYSTONE) -config SH_SDHI - bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" - depends on ARCH_RMOBILE - help - Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform - config SH_MMCIF bool "SuperH/Renesas ARM SoCs on-chip MMCIF host controller support" depends on ARCH_RMOBILE || SH diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 2c65c4765ab..e9cf1fcc640 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -49,7 +49,6 @@ obj-$(CONFIG_MMC_PCI) += pci_mmc.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o -obj-$(CONFIG_SH_SDHI) += sh_sdhi.o obj-$(CONFIG_STM32_SDMMC2) += stm32_sdmmc2.o obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o obj-$(CONFIG_NEXELL_DWMMC) += nexell_dw_mmc.o diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index fd667aeafda..05595bdac39 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * * Texas Instruments' K3 SD Host Controller Interface */ diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 9fb70440293..4d163ccba04 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -50,8 +50,8 @@ static int pci_mmc_probe(struct udevice *dev) desc = mmc_get_blk_desc(&plat->mmc); desc->removable = !(plat->cfg.host_caps & MMC_CAP_NONREMOVABLE); - host->ioaddr = (void *)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, - PCI_REGION_MEM); + host->ioaddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, + PCI_REGION_TYPE, PCI_REGION_MEM); host->name = dev->name; host->cd_gpio = priv->cd_gpio; host->mmc = &plat->mmc; diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 1ea6e1066f2..8cd501c5f7c 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> */ -#include <common.h> #include <bouncebuf.h> #include <clk.h> #include <fdtdec.h> @@ -998,7 +997,7 @@ static int rzg2l_sdhi_setup(struct udevice *dev) ret = reset_get_by_index(dev, 0, &rst); if (ret < 0) { dev_err(dev, "failed to get reset line\n"); - goto err_reset; + goto err_get_reset; } ret = reset_deassert(&rst); @@ -1016,6 +1015,8 @@ static int rzg2l_sdhi_setup(struct udevice *dev) err_tmio_probe: reset_assert(&rst); err_reset: + reset_free(&rst); +err_get_reset: clk_disable(&aclk); err_aclk: clk_disable(&imclk2); diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index fc9c6c37996..0178ed8a11e 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -306,14 +306,19 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (stat & SDHCI_INT_ERROR) break; - if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { - if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { + if (host->quirks & SDHCI_QUIRK_BROKEN_R1B && + cmd->resp_type & MMC_RSP_BUSY && !data) { + unsigned int state = + sdhci_readl(host, SDHCI_PRESENT_STATE); + + if (!(state & SDHCI_DAT_ACTIVE)) return 0; - } else { - printf("%s: Timeout for status update!\n", - __func__); - return -ETIMEDOUT; - } + } + + if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { + printf("%s: Timeout for status update: %08x %08x\n", + __func__, stat, mask); + return -ETIMEDOUT; } } while ((stat & mask) != mask); diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c deleted file mode 100644 index 3ce7cbf71f8..00000000000 --- a/drivers/mmc/sh_sdhi.c +++ /dev/null @@ -1,910 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * drivers/mmc/sh_sdhi.c - * - * SD/MMC driver for Renesas rmobile ARM SoCs. - * - * Copyright (C) 2011,2013-2017 Renesas Electronics Corporation - * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * Copyright (C) 2008-2009 Renesas Solutions Corp. - */ - -#include <common.h> -#include <log.h> -#include <malloc.h> -#include <mmc.h> -#include <dm.h> -#include <part.h> -#include <dm/device_compat.h> -#include <linux/bitops.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/compat.h> -#include <linux/io.h> -#include <linux/sizes.h> -#include <asm/arch/rmobile.h> -#include <asm/arch/sh_sdhi.h> -#include <asm/global_data.h> -#include <clk.h> - -#define DRIVER_NAME "sh-sdhi" - -struct sh_sdhi_host { - void __iomem *addr; - int ch; - int bus_shift; - unsigned long quirks; - unsigned char wait_int; - unsigned char sd_error; - unsigned char detect_waiting; - unsigned char app_cmd; -}; - -static inline void sh_sdhi_writeq(struct sh_sdhi_host *host, int reg, u64 val) -{ - writeq(val, host->addr + (reg << host->bus_shift)); -} - -static inline u64 sh_sdhi_readq(struct sh_sdhi_host *host, int reg) -{ - return readq(host->addr + (reg << host->bus_shift)); -} - -static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val) -{ - writew(val, host->addr + (reg << host->bus_shift)); -} - -static inline u16 sh_sdhi_readw(struct sh_sdhi_host *host, int reg) -{ - return readw(host->addr + (reg << host->bus_shift)); -} - -static void sh_sdhi_detect(struct sh_sdhi_host *host) -{ - sh_sdhi_writew(host, SDHI_OPTION, - OPT_BUS_WIDTH_1 | sh_sdhi_readw(host, SDHI_OPTION)); - - host->detect_waiting = 0; -} - -static int sh_sdhi_intr(void *dev_id) -{ - struct sh_sdhi_host *host = dev_id; - int state1 = 0, state2 = 0; - - state1 = sh_sdhi_readw(host, SDHI_INFO1); - state2 = sh_sdhi_readw(host, SDHI_INFO2); - - debug("%s: state1 = %x, state2 = %x\n", __func__, state1, state2); - - /* CARD Insert */ - if (state1 & INFO1_CARD_IN) { - sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_IN); - if (!host->detect_waiting) { - host->detect_waiting = 1; - sh_sdhi_detect(host); - } - sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END | - INFO1M_ACCESS_END | INFO1M_CARD_IN | - INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); - return -EAGAIN; - } - /* CARD Removal */ - if (state1 & INFO1_CARD_RE) { - sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_CARD_RE); - if (!host->detect_waiting) { - host->detect_waiting = 1; - sh_sdhi_detect(host); - } - sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END | - INFO1M_ACCESS_END | INFO1M_CARD_RE | - INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); - sh_sdhi_writew(host, SDHI_SDIO_INFO1_MASK, SDIO_INFO1M_ON); - sh_sdhi_writew(host, SDHI_SDIO_MODE, SDIO_MODE_OFF); - return -EAGAIN; - } - - if (state2 & INFO2_ALL_ERR) { - sh_sdhi_writew(host, SDHI_INFO2, - (unsigned short)~(INFO2_ALL_ERR)); - sh_sdhi_writew(host, SDHI_INFO2_MASK, - INFO2M_ALL_ERR | - sh_sdhi_readw(host, SDHI_INFO2_MASK)); - host->sd_error = 1; - host->wait_int = 1; - return 0; - } - /* Respons End */ - if (state1 & INFO1_RESP_END) { - sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END); - sh_sdhi_writew(host, SDHI_INFO1_MASK, - INFO1M_RESP_END | - sh_sdhi_readw(host, SDHI_INFO1_MASK)); - host->wait_int = 1; - return 0; - } - /* SD_BUF Read Enable */ - if (state2 & INFO2_BRE_ENABLE) { - sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BRE_ENABLE); - sh_sdhi_writew(host, SDHI_INFO2_MASK, - INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ | - sh_sdhi_readw(host, SDHI_INFO2_MASK)); - host->wait_int = 1; - return 0; - } - /* SD_BUF Write Enable */ - if (state2 & INFO2_BWE_ENABLE) { - sh_sdhi_writew(host, SDHI_INFO2, ~INFO2_BWE_ENABLE); - sh_sdhi_writew(host, SDHI_INFO2_MASK, - INFO2_BWE_ENABLE | INFO2M_BUF_ILL_WRITE | - sh_sdhi_readw(host, SDHI_INFO2_MASK)); - host->wait_int = 1; - return 0; - } - /* Access End */ - if (state1 & INFO1_ACCESS_END) { - sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_ACCESS_END); - sh_sdhi_writew(host, SDHI_INFO1_MASK, - INFO1_ACCESS_END | - sh_sdhi_readw(host, SDHI_INFO1_MASK)); - host->wait_int = 1; - return 0; - } - return -EAGAIN; -} - -static int sh_sdhi_wait_interrupt_flag(struct sh_sdhi_host *host) -{ - int timeout = 10000000; - - while (1) { - timeout--; - if (timeout < 0) { - debug(DRIVER_NAME": %s timeout\n", __func__); - return 0; - } - - if (!sh_sdhi_intr(host)) - break; - - udelay(1); /* 1 usec */ - } - - return 1; /* Return value: NOT 0 = complete waiting */ -} - -static int sh_sdhi_clock_control(struct sh_sdhi_host *host, unsigned long clk) -{ - u32 clkdiv, i, timeout; - - if (sh_sdhi_readw(host, SDHI_INFO2) & (1 << 14)) { - printf(DRIVER_NAME": Busy state ! Cannot change the clock\n"); - return -EBUSY; - } - - sh_sdhi_writew(host, SDHI_CLK_CTRL, - ~CLK_ENABLE & sh_sdhi_readw(host, SDHI_CLK_CTRL)); - - if (clk == 0) - return -EIO; - - clkdiv = 0x80; - i = CONFIG_SH_SDHI_FREQ >> (0x8 + 1); - for (; clkdiv && clk >= (i << 1); (clkdiv >>= 1)) - i <<= 1; - - sh_sdhi_writew(host, SDHI_CLK_CTRL, clkdiv); - - timeout = 100000; - /* Waiting for SD Bus busy to be cleared */ - while (timeout--) { - if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000)) - break; - } - - if (timeout) - sh_sdhi_writew(host, SDHI_CLK_CTRL, - CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL)); - else - return -EBUSY; - - return 0; -} - -static int sh_sdhi_sync_reset(struct sh_sdhi_host *host) -{ - u32 timeout; - sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_ON); - sh_sdhi_writew(host, SDHI_SOFT_RST, SOFT_RST_OFF); - sh_sdhi_writew(host, SDHI_CLK_CTRL, - CLK_ENABLE | sh_sdhi_readw(host, SDHI_CLK_CTRL)); - - timeout = 100000; - while (timeout--) { - if (!(sh_sdhi_readw(host, SDHI_INFO2) & INFO2_CBUSY)) - break; - udelay(100); - } - - if (!timeout) - return -EBUSY; - - if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF) - sh_sdhi_writew(host, SDHI_HOST_MODE, 1); - - return 0; -} - -static int sh_sdhi_error_manage(struct sh_sdhi_host *host) -{ - unsigned short e_state1, e_state2; - int ret; - - host->sd_error = 0; - host->wait_int = 0; - - e_state1 = sh_sdhi_readw(host, SDHI_ERR_STS1); - e_state2 = sh_sdhi_readw(host, SDHI_ERR_STS2); - if (e_state2 & ERR_STS2_SYS_ERROR) { - if (e_state2 & ERR_STS2_RES_STOP_TIMEOUT) - ret = -ETIMEDOUT; - else - ret = -EILSEQ; - debug("%s: ERR_STS2 = %04x\n", - DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS2)); - sh_sdhi_sync_reset(host); - - sh_sdhi_writew(host, SDHI_INFO1_MASK, - INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); - return ret; - } - if (e_state1 & ERR_STS1_CRC_ERROR || e_state1 & ERR_STS1_CMD_ERROR) - ret = -EILSEQ; - else - ret = -ETIMEDOUT; - - debug("%s: ERR_STS1 = %04x\n", - DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS1)); - sh_sdhi_sync_reset(host); - sh_sdhi_writew(host, SDHI_INFO1_MASK, - INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); - return ret; -} - -static int sh_sdhi_single_read(struct sh_sdhi_host *host, struct mmc_data *data) -{ - long time; - unsigned short blocksize, i; - unsigned short *p = (unsigned short *)data->dest; - u64 *q = (u64 *)data->dest; - - if ((unsigned long)p & 0x00000001) { - debug(DRIVER_NAME": %s: The data pointer is unaligned.", - __func__); - return -EIO; - } - - host->wait_int = 0; - sh_sdhi_writew(host, SDHI_INFO2_MASK, - ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) & - sh_sdhi_readw(host, SDHI_INFO2_MASK)); - sh_sdhi_writew(host, SDHI_INFO1_MASK, - ~INFO1M_ACCESS_END & - sh_sdhi_readw(host, SDHI_INFO1_MASK)); - time = sh_sdhi_wait_interrupt_flag(host); - if (time == 0 || host->sd_error != 0) - return sh_sdhi_error_manage(host); - - host->wait_int = 0; - blocksize = sh_sdhi_readw(host, SDHI_SIZE); - if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) - for (i = 0; i < blocksize / 8; i++) - *q++ = sh_sdhi_readq(host, SDHI_BUF0); - else - for (i = 0; i < blocksize / 2; i++) - *p++ = sh_sdhi_readw(host, SDHI_BUF0); - - time = sh_sdhi_wait_interrupt_flag(host); - if (time == 0 || host->sd_error != 0) - return sh_sdhi_error_manage(host); - - host->wait_int = 0; - return 0; -} - -static int sh_sdhi_multi_read(struct sh_sdhi_host *host, struct mmc_data *data) -{ - long time; - unsigned short blocksize, i, sec; - unsigned short *p = (unsigned short *)data->dest; - u64 *q = (u64 *)data->dest; - - if ((unsigned long)p & 0x00000001) { - debug(DRIVER_NAME": %s: The data pointer is unaligned.", - __func__); - return -EIO; - } - - debug("%s: blocks = %d, blocksize = %d\n", - __func__, data->blocks, data->blocksize); - - host->wait_int = 0; - for (sec = 0; sec < data->blocks; sec++) { - sh_sdhi_writew(host, SDHI_INFO2_MASK, - ~(INFO2M_BRE_ENABLE | INFO2M_BUF_ILL_READ) & - sh_sdhi_readw(host, SDHI_INFO2_MASK)); - - time = sh_sdhi_wait_interrupt_flag(host); - if (time == 0 || host->sd_error != 0) - return sh_sdhi_error_manage(host); - - host->wait_int = 0; - blocksize = sh_sdhi_readw(host, SDHI_SIZE); - if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) - for (i = 0; i < blocksize / 8; i++) - *q++ = sh_sdhi_readq(host, SDHI_BUF0); - else - for (i = 0; i < blocksize / 2; i++) - *p++ = sh_sdhi_readw(host, SDHI_BUF0); - } - - return 0; -} - -static int sh_sdhi_single_write(struct sh_sdhi_host *host, - struct mmc_data *data) -{ - long time; - unsigned short blocksize, i; - const unsigned short *p = (const unsigned short *)data->src; - const u64 *q = (const u64 *)data->src; - - if ((unsigned long)p & 0x00000001) { - debug(DRIVER_NAME": %s: The data pointer is unaligned.", - __func__); - return -EIO; - } - - debug("%s: blocks = %d, blocksize = %d\n", - __func__, data->blocks, data->blocksize); - - host->wait_int = 0; - sh_sdhi_writew(host, SDHI_INFO2_MASK, - ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) & - sh_sdhi_readw(host, SDHI_INFO2_MASK)); - sh_sdhi_writew(host, SDHI_INFO1_MASK, - ~INFO1M_ACCESS_END & - sh_sdhi_readw(host, SDHI_INFO1_MASK)); - - time = sh_sdhi_wait_interrupt_flag(host); - if (time == 0 || host->sd_error != 0) - return sh_sdhi_error_manage(host); - - host->wait_int = 0; - blocksize = sh_sdhi_readw(host, SDHI_SIZE); - if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) - for (i = 0; i < blocksize / 8; i++) - sh_sdhi_writeq(host, SDHI_BUF0, *q++); - else - for (i = 0; i < blocksize / 2; i++) - sh_sdhi_writew(host, SDHI_BUF0, *p++); - - time = sh_sdhi_wait_interrupt_flag(host); - if (time == 0 || host->sd_error != 0) - return sh_sdhi_error_manage(host); - - host->wait_int = 0; - return 0; -} - -static int sh_sdhi_multi_write(struct sh_sdhi_host *host, struct mmc_data *data) -{ - long time; - unsigned short i, sec, blocksize; - const unsigned short *p = (const unsigned short *)data->src; - const u64 *q = (const u64 *)data->src; - - debug("%s: blocks = %d, blocksize = %d\n", - __func__, data->blocks, data->blocksize); - - host->wait_int = 0; - for (sec = 0; sec < data->blocks; sec++) { - sh_sdhi_writew(host, SDHI_INFO2_MASK, - ~(INFO2M_BWE_ENABLE | INFO2M_BUF_ILL_WRITE) & - sh_sdhi_readw(host, SDHI_INFO2_MASK)); - - time = sh_sdhi_wait_interrupt_flag(host); - if (time == 0 || host->sd_error != 0) - return sh_sdhi_error_manage(host); - - host->wait_int = 0; - blocksize = sh_sdhi_readw(host, SDHI_SIZE); - if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) - for (i = 0; i < blocksize / 8; i++) - sh_sdhi_writeq(host, SDHI_BUF0, *q++); - else - for (i = 0; i < blocksize / 2; i++) - sh_sdhi_writew(host, SDHI_BUF0, *p++); - } - - return 0; -} - -static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd) -{ - unsigned short i, j, cnt = 1; - unsigned short resp[8]; - - if (cmd->resp_type & MMC_RSP_136) { - cnt = 4; - resp[0] = sh_sdhi_readw(host, SDHI_RSP00); - resp[1] = sh_sdhi_readw(host, SDHI_RSP01); - resp[2] = sh_sdhi_readw(host, SDHI_RSP02); - resp[3] = sh_sdhi_readw(host, SDHI_RSP03); - resp[4] = sh_sdhi_readw(host, SDHI_RSP04); - resp[5] = sh_sdhi_readw(host, SDHI_RSP05); - resp[6] = sh_sdhi_readw(host, SDHI_RSP06); - resp[7] = sh_sdhi_readw(host, SDHI_RSP07); - - /* SDHI REGISTER SPECIFICATION */ - for (i = 7, j = 6; i > 0; i--) { - resp[i] = (resp[i] << 8) & 0xff00; - resp[i] |= (resp[j--] >> 8) & 0x00ff; - } - resp[0] = (resp[0] << 8) & 0xff00; - } else { - resp[0] = sh_sdhi_readw(host, SDHI_RSP00); - resp[1] = sh_sdhi_readw(host, SDHI_RSP01); - } - -#if defined(__BIG_ENDIAN_BITFIELD) - if (cnt == 4) { - cmd->response[0] = (resp[6] << 16) | resp[7]; - cmd->response[1] = (resp[4] << 16) | resp[5]; - cmd->response[2] = (resp[2] << 16) | resp[3]; - cmd->response[3] = (resp[0] << 16) | resp[1]; - } else { - cmd->response[0] = (resp[0] << 16) | resp[1]; - } -#else - if (cnt == 4) { - cmd->response[0] = (resp[7] << 16) | resp[6]; - cmd->response[1] = (resp[5] << 16) | resp[4]; - cmd->response[2] = (resp[3] << 16) | resp[2]; - cmd->response[3] = (resp[1] << 16) | resp[0]; - } else { - cmd->response[0] = (resp[1] << 16) | resp[0]; - } -#endif /* __BIG_ENDIAN_BITFIELD */ -} - -static unsigned short sh_sdhi_set_cmd(struct sh_sdhi_host *host, - struct mmc_data *data, unsigned short opc) -{ - if (host->app_cmd) { - if (!data) - host->app_cmd = 0; - return opc | BIT(6); - } - - switch (opc) { - case MMC_CMD_SWITCH: - return opc | (data ? 0x1c00 : 0x40); - case MMC_CMD_SEND_EXT_CSD: - return opc | (data ? 0x1c00 : 0); - case MMC_CMD_SEND_OP_COND: - return opc | 0x0700; - case MMC_CMD_APP_CMD: - host->app_cmd = 1; - default: - return opc; - } -} - -static unsigned short sh_sdhi_data_trans(struct sh_sdhi_host *host, - struct mmc_data *data, unsigned short opc) -{ - if (host->app_cmd) { - host->app_cmd = 0; - switch (opc) { - case SD_CMD_APP_SEND_SCR: - case SD_CMD_APP_SD_STATUS: - return sh_sdhi_single_read(host, data); - default: - printf(DRIVER_NAME": SD: NOT SUPPORT APP CMD = d'%04d\n", - opc); - return -EINVAL; - } - } else { - switch (opc) { - case MMC_CMD_WRITE_MULTIPLE_BLOCK: - return sh_sdhi_multi_write(host, data); - case MMC_CMD_READ_MULTIPLE_BLOCK: - return sh_sdhi_multi_read(host, data); - case MMC_CMD_WRITE_SINGLE_BLOCK: - return sh_sdhi_single_write(host, data); - case MMC_CMD_READ_SINGLE_BLOCK: - case MMC_CMD_SWITCH: - case MMC_CMD_SEND_EXT_CSD:; - return sh_sdhi_single_read(host, data); - default: - printf(DRIVER_NAME": SD: NOT SUPPORT CMD = d'%04d\n", opc); - return -EINVAL; - } - } -} - -static int sh_sdhi_start_cmd(struct sh_sdhi_host *host, - struct mmc_data *data, struct mmc_cmd *cmd) -{ - long time; - unsigned short shcmd, opc = cmd->cmdidx; - int ret = 0; - unsigned long timeout; - - debug("opc = %d, arg = %x, resp_type = %x\n", - opc, cmd->cmdarg, cmd->resp_type); - - if (opc == MMC_CMD_STOP_TRANSMISSION) { - /* SDHI sends the STOP command automatically by STOP reg */ - sh_sdhi_writew(host, SDHI_INFO1_MASK, ~INFO1M_ACCESS_END & - sh_sdhi_readw(host, SDHI_INFO1_MASK)); - - time = sh_sdhi_wait_interrupt_flag(host); - if (time == 0 || host->sd_error != 0) - return sh_sdhi_error_manage(host); - - sh_sdhi_get_response(host, cmd); - return 0; - } - - if (data) { - if ((opc == MMC_CMD_READ_MULTIPLE_BLOCK) || - opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) { - sh_sdhi_writew(host, SDHI_STOP, STOP_SEC_ENABLE); - sh_sdhi_writew(host, SDHI_SECCNT, data->blocks); - } - sh_sdhi_writew(host, SDHI_SIZE, data->blocksize); - } - - shcmd = sh_sdhi_set_cmd(host, data, opc); - - /* - * U-Boot cannot use interrupt. - * So this flag may not be clear by timing - */ - sh_sdhi_writew(host, SDHI_INFO1, ~INFO1_RESP_END); - - sh_sdhi_writew(host, SDHI_INFO1_MASK, - INFO1M_RESP_END | sh_sdhi_readw(host, SDHI_INFO1_MASK)); - sh_sdhi_writew(host, SDHI_ARG0, - (unsigned short)(cmd->cmdarg & ARG0_MASK)); - sh_sdhi_writew(host, SDHI_ARG1, - (unsigned short)((cmd->cmdarg >> 16) & ARG1_MASK)); - - timeout = 100000; - /* Waiting for SD Bus busy to be cleared */ - while (timeout--) { - if ((sh_sdhi_readw(host, SDHI_INFO2) & 0x2000)) - break; - } - - host->wait_int = 0; - sh_sdhi_writew(host, SDHI_INFO1_MASK, - ~INFO1M_RESP_END & sh_sdhi_readw(host, SDHI_INFO1_MASK)); - sh_sdhi_writew(host, SDHI_INFO2_MASK, - ~(INFO2M_CMD_ERROR | INFO2M_CRC_ERROR | - INFO2M_END_ERROR | INFO2M_TIMEOUT | - INFO2M_RESP_TIMEOUT | INFO2M_ILA) & - sh_sdhi_readw(host, SDHI_INFO2_MASK)); - - sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(shcmd & CMD_MASK)); - time = sh_sdhi_wait_interrupt_flag(host); - if (!time) { - host->app_cmd = 0; - return sh_sdhi_error_manage(host); - } - - if (host->sd_error) { - switch (cmd->cmdidx) { - case MMC_CMD_ALL_SEND_CID: - case MMC_CMD_SELECT_CARD: - case SD_CMD_SEND_IF_COND: - case MMC_CMD_APP_CMD: - ret = -ETIMEDOUT; - break; - default: - debug(DRIVER_NAME": Cmd(d'%d) err\n", opc); - debug(DRIVER_NAME": cmdidx = %d\n", cmd->cmdidx); - ret = sh_sdhi_error_manage(host); - break; - } - host->sd_error = 0; - host->wait_int = 0; - host->app_cmd = 0; - return ret; - } - - if (sh_sdhi_readw(host, SDHI_INFO1) & INFO1_RESP_END) { - host->app_cmd = 0; - return -EINVAL; - } - - if (host->wait_int) { - sh_sdhi_get_response(host, cmd); - host->wait_int = 0; - } - - if (data) - ret = sh_sdhi_data_trans(host, data, opc); - - debug("ret = %d, resp = %08x, %08x, %08x, %08x\n", - ret, cmd->response[0], cmd->response[1], - cmd->response[2], cmd->response[3]); - return ret; -} - -static int sh_sdhi_send_cmd_common(struct sh_sdhi_host *host, - struct mmc_cmd *cmd, struct mmc_data *data) -{ - host->sd_error = 0; - - return sh_sdhi_start_cmd(host, data, cmd); -} - -static int sh_sdhi_set_ios_common(struct sh_sdhi_host *host, struct mmc *mmc) -{ - int ret; - - ret = sh_sdhi_clock_control(host, mmc->clock); - if (ret) - return -EINVAL; - - if (mmc->bus_width == 8) - sh_sdhi_writew(host, SDHI_OPTION, - OPT_BUS_WIDTH_8 | (~OPT_BUS_WIDTH_M & - sh_sdhi_readw(host, SDHI_OPTION))); - else if (mmc->bus_width == 4) - sh_sdhi_writew(host, SDHI_OPTION, - OPT_BUS_WIDTH_4 | (~OPT_BUS_WIDTH_M & - sh_sdhi_readw(host, SDHI_OPTION))); - else - sh_sdhi_writew(host, SDHI_OPTION, - OPT_BUS_WIDTH_1 | (~OPT_BUS_WIDTH_M & - sh_sdhi_readw(host, SDHI_OPTION))); - - debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); - - return 0; -} - -static int sh_sdhi_initialize_common(struct sh_sdhi_host *host) -{ - int ret = sh_sdhi_sync_reset(host); - - sh_sdhi_writew(host, SDHI_PORTSEL, USE_1PORT); - -#if defined(__BIG_ENDIAN_BITFIELD) - sh_sdhi_writew(host, SDHI_EXT_SWAP, SET_SWAP); -#endif - - sh_sdhi_writew(host, SDHI_INFO1_MASK, INFO1M_RESP_END | - INFO1M_ACCESS_END | INFO1M_CARD_RE | - INFO1M_DATA3_CARD_RE | INFO1M_DATA3_CARD_IN); - - return ret; -} - -#ifndef CONFIG_DM_MMC -static void *mmc_priv(struct mmc *mmc) -{ - return (void *)mmc->priv; -} - -static int sh_sdhi_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct sh_sdhi_host *host = mmc_priv(mmc); - - return sh_sdhi_send_cmd_common(host, cmd, data); -} - -static int sh_sdhi_set_ios(struct mmc *mmc) -{ - struct sh_sdhi_host *host = mmc_priv(mmc); - - return sh_sdhi_set_ios_common(host, mmc); -} - -static int sh_sdhi_initialize(struct mmc *mmc) -{ - struct sh_sdhi_host *host = mmc_priv(mmc); - - return sh_sdhi_initialize_common(host); -} - -static const struct mmc_ops sh_sdhi_ops = { - .send_cmd = sh_sdhi_send_cmd, - .set_ios = sh_sdhi_set_ios, - .init = sh_sdhi_initialize, -}; - -#ifdef CONFIG_RCAR_GEN3 -static struct mmc_config sh_sdhi_cfg = { - .name = DRIVER_NAME, - .ops = &sh_sdhi_ops, - .f_min = CLKDEV_INIT, - .f_max = CLKDEV_HS_DATA, - .voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, - .host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS | - MMC_MODE_HS_52MHz, - .part_type = PART_TYPE_DOS, - .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, -}; -#else -static struct mmc_config sh_sdhi_cfg = { - .name = DRIVER_NAME, - .ops = &sh_sdhi_ops, - .f_min = CLKDEV_INIT, - .f_max = CLKDEV_HS_DATA, - .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, - .host_caps = MMC_MODE_4BIT | MMC_MODE_HS, - .part_type = PART_TYPE_DOS, - .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, -}; -#endif - -int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks) -{ - int ret = 0; - struct mmc *mmc; - struct sh_sdhi_host *host = NULL; - - if (ch >= CFG_SYS_SH_SDHI_NR_CHANNEL) - return -ENODEV; - - host = malloc(sizeof(struct sh_sdhi_host)); - if (!host) - return -ENOMEM; - - mmc = mmc_create(&sh_sdhi_cfg, host); - if (!mmc) { - ret = -1; - goto error; - } - - host->ch = ch; - host->addr = (void __iomem *)addr; - host->quirks = quirks; - - if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) - host->bus_shift = 2; - else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF) - host->bus_shift = 1; - - return ret; -error: - free(host); - return ret; -} - -#else - -struct sh_sdhi_plat { - struct mmc_config cfg; - struct mmc mmc; -}; - -int sh_sdhi_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, - struct mmc_data *data) -{ - struct sh_sdhi_host *host = dev_get_priv(dev); - - return sh_sdhi_send_cmd_common(host, cmd, data); -} - -int sh_sdhi_dm_set_ios(struct udevice *dev) -{ - struct sh_sdhi_host *host = dev_get_priv(dev); - struct mmc *mmc = mmc_get_mmc_dev(dev); - - return sh_sdhi_set_ios_common(host, mmc); -} - -static const struct dm_mmc_ops sh_sdhi_dm_ops = { - .send_cmd = sh_sdhi_dm_send_cmd, - .set_ios = sh_sdhi_dm_set_ios, -}; - -static int sh_sdhi_dm_bind(struct udevice *dev) -{ - struct sh_sdhi_plat *plat = dev_get_plat(dev); - - return mmc_bind(dev, &plat->mmc, &plat->cfg); -} - -static int sh_sdhi_dm_probe(struct udevice *dev) -{ - struct sh_sdhi_plat *plat = dev_get_plat(dev); - struct sh_sdhi_host *host = dev_get_priv(dev); - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct clk sh_sdhi_clk; - const u32 quirks = dev_get_driver_data(dev); - fdt_addr_t base; - int ret; - - base = dev_read_addr(dev); - if (base == FDT_ADDR_T_NONE) - return -EINVAL; - - host->addr = devm_ioremap(dev, base, SZ_2K); - if (!host->addr) - return -ENOMEM; - - ret = clk_get_by_index(dev, 0, &sh_sdhi_clk); - if (ret) { - debug("failed to get clock, ret=%d\n", ret); - return ret; - } - - ret = clk_enable(&sh_sdhi_clk); - if (ret) { - debug("failed to enable clock, ret=%d\n", ret); - return ret; - } - - host->quirks = quirks; - - if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) - host->bus_shift = 2; - else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF) - host->bus_shift = 1; - - plat->cfg.name = dev->name; - plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; - - switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", - 1)) { - case 8: - plat->cfg.host_caps |= MMC_MODE_8BIT; - break; - case 4: - plat->cfg.host_caps |= MMC_MODE_4BIT; - break; - case 1: - break; - default: - dev_err(dev, "Invalid \"bus-width\" value\n"); - return -EINVAL; - } - - sh_sdhi_initialize_common(host); - - plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; - plat->cfg.f_min = CLKDEV_INIT; - plat->cfg.f_max = CLKDEV_HS_DATA; - plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - - upriv->mmc = &plat->mmc; - - return 0; -} - -static const struct udevice_id sh_sdhi_sd_match[] = { - { .compatible = "renesas,sdhi-r8a7795", .data = SH_SDHI_QUIRK_64BIT_BUF }, - { .compatible = "renesas,sdhi-r8a7796", .data = SH_SDHI_QUIRK_64BIT_BUF }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(sh_sdhi_mmc) = { - .name = "sh-sdhi-mmc", - .id = UCLASS_MMC, - .of_match = sh_sdhi_sd_match, - .bind = sh_sdhi_dm_bind, - .probe = sh_sdhi_dm_probe, - .priv_auto = sizeof(struct sh_sdhi_host), - .plat_auto = sizeof(struct sh_sdhi_plat), - .ops = &sh_sdhi_dm_ops, -}; -#endif diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index f76fee3ea0f..d507adbb363 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -37,6 +37,9 @@ struct tegra_mmc_priv { unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ int mmc_id; /* peripheral id */ + + int tap_value; + int trim_value; }; static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, @@ -526,31 +529,6 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) printf("%s: Warning: Autocal timed out!\n", __func__); /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */ } - -#if defined(CONFIG_TEGRA210) - u32 tap_value, trim_value; - - /* Set tap/trim values for SDMMC1/3 @ <48MHz here */ - val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */ - val &= IO_TRIM_BYPASS_MASK; - if (id == PERIPH_ID_SDMMC1) { - tap_value = 4; /* default */ - if (val) - tap_value = 3; - trim_value = 2; - } else { /* SDMMC3 */ - tap_value = 3; - trim_value = 3; - } - - val = readl(&priv->reg->venclkctl); - val &= ~TRIM_VAL_MASK; - val |= (trim_value << TRIM_VAL_SHIFT); - val &= ~TAP_VAL_MASK; - val |= (tap_value << TAP_VAL_SHIFT); - writel(val, &priv->reg->venclkctl); - debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val); -#endif /* T210 */ #endif /* T30/T210 */ } @@ -588,6 +566,22 @@ static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) /* Make sure SDIO pads are set up */ tegra_mmc_pad_init(priv); + + if (!IS_ERR_VALUE(priv->tap_value) || + !IS_ERR_VALUE(priv->trim_value)) { + u32 val; + + val = readl(&priv->reg->venclkctl); + + val &= ~TRIM_VAL_MASK; + val |= (priv->trim_value << TRIM_VAL_SHIFT); + + val &= ~TAP_VAL_MASK; + val |= (priv->tap_value << TAP_VAL_SHIFT); + + writel(val, &priv->reg->venclkctl); + debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val); + } } static int tegra_mmc_init(struct udevice *dev) @@ -742,6 +736,14 @@ static int tegra_mmc_probe(struct udevice *dev) if (dm_gpio_is_valid(&priv->pwr_gpio)) dm_gpio_set_value(&priv->pwr_gpio, 1); + ret = dev_read_u32(dev, "nvidia,default-tap", &priv->tap_value); + if (ret) + priv->tap_value = ret; + + ret = dev_read_u32(dev, "nvidia,default-trim", &priv->trim_value); + if (ret) + priv->trim_value = ret; + upriv->mmc = &plat->mmc; return tegra_mmc_init(dev); diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c index d1e26815996..890c496b535 100644 --- a/drivers/mmc/tmio-common.c +++ b/drivers/mmc/tmio-common.c @@ -122,7 +122,10 @@ static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd, long wait = 1000000; int ret; - while (!(tmio_sd_readl(priv, reg) & flag)) { + while (true) { + if (tmio_sd_readl(priv, reg) & flag) + return tmio_sd_check_error(dev, cmd); + if (wait-- < 0) { dev_err(dev, "timeout\n"); return -ETIMEDOUT; @@ -756,7 +759,8 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks) dev_dbg(dev, "version %x\n", priv->version); if (priv->version >= 0x10) { priv->caps |= TMIO_SD_CAP_DMA_INTERNAL; - priv->caps |= TMIO_SD_CAP_DIV1024; + if (!(priv->caps & TMIO_SD_CAP_RCAR)) + priv->caps |= TMIO_SD_CAP_DIV1024; } if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", diff --git a/drivers/mtd/hbmc-am654.c b/drivers/mtd/hbmc-am654.c index c86e504da30..8161087b50c 100644 --- a/drivers/mtd/hbmc-am654.c +++ b/drivers/mtd/hbmc-am654.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 // -// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ +// Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ // Author: Vignesh Raghavendra <vigneshr@ti.com> #include <common.h> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d624589a892..a13e6f59cbd 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -611,6 +611,14 @@ config ROCKCHIP_NAND NFC v800: RK3308, RV1108 NFC v900: PX30, RK3326 +config ROCKCHIP_NAND_SKIP_BBTSCAN + bool "Skip the automatic BBT scan with Rockchip NAND controllers" + depends on ROCKCHIP_NAND + help + Skip the automatic BBT scan with the NAND_SKIP_BBTSCAN + option when data content is not in MTD format or + must remain unchanged. + config TEGRA_NAND bool "Support for NAND controller on Tegra SoCs" depends on ARCH_TEGRA diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index 274489ecbc6..088cc7fead2 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -955,6 +955,9 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum) chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER; + if (IS_ENABLED(CONFIG_ROCKCHIP_NAND_SKIP_BBTSCAN)) + chip->options |= NAND_SKIP_BBTSCAN; + rk_nfc_hw_init(nfc); ret = nand_scan_ident(mtd, nsels, NULL); if (ret) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index a9617c6c58c..732b0760452 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -82,6 +82,7 @@ if SPI_FLASH config BOOTDEV_SPI_FLASH bool "SPI Flash bootdev support" + depends on BOOTSTD help Enable a boot device for SPI flash. This allows reading a script from SPI flash so that it can be used to boot an Operating System. @@ -107,7 +108,6 @@ config SPI_FLASH_SMART_HWCAPS config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT bool "Command extension type is INVERT for Software Reset on boot" - default n help Because of SFDP information can not be get before boot. So define command extension type is INVERT when Software Reset on boot only. @@ -134,6 +134,13 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_LOCK + bool "Enable the Locking feature" + default y + help + Enable the SPI flash lock support. By default this is set to y. + If you intend not to use the lock support you should say n here. + config SPI_FLASH_UNLOCK_ALL bool "Unlock the entire SPI flash on u-boot startup" default y diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index db20feb4dae..9a1801ba93d 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1100,6 +1100,7 @@ static int spansion_erase_non_uniform(struct spi_nor *nor, u32 addr, } #endif +#if defined(CONFIG_SPI_FLASH_LOCK) #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) /* Write status register and ensure bits in mask match written values */ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) @@ -1387,6 +1388,7 @@ static int stm_is_unlocked(struct spi_nor *nor, loff_t ofs, uint64_t len) return stm_is_unlocked_sr(nor, ofs, len, status); } #endif /* CONFIG_SPI_FLASH_STMICRO */ +#endif static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) { @@ -1462,6 +1464,7 @@ read_err: return ret; } +#if defined(CONFIG_SPI_FLASH_LOCK) #ifdef CONFIG_SPI_FLASH_SST /* * sst26 flash series has its own block protection implementation: @@ -1730,6 +1733,8 @@ sst_write_err: return ret; } #endif +#endif + /* * Write an address range to the nor chip. Data must be written in * FLASH_PAGESIZE chunks. The address range may be any size provided @@ -4104,6 +4109,7 @@ int spi_nor_scan(struct spi_nor *nor) mtd->_read = spi_nor_read; mtd->_write = spi_nor_write; +#if defined(CONFIG_SPI_FLASH_LOCK) #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) /* NOR protection support for STmicro/Micron chips and similar */ if (JEDEC_MFR(info) == SNOR_MFR_ST || @@ -4127,7 +4133,7 @@ int spi_nor_scan(struct spi_nor *nor) nor->flash_is_unlocked = sst26_is_unlocked; } #endif - +#endif if (info->flags & USE_FSR) nor->flags |= SNOR_F_USE_FSR; if (info->flags & SPI_NOR_HAS_TB) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index b03dd1cd08e..3cb132dcffc 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -3,7 +3,7 @@ * * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. * Copyright (C) 2016 Jagan Teki <jagan@openedev.com> - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> @@ -532,6 +532,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XTX /* XTX Technology Limited */ diff --git a/drivers/mux/mux-uclass.c b/drivers/mux/mux-uclass.c index 8870305313a..c98576ceb81 100644 --- a/drivers/mux/mux-uclass.c +++ b/drivers/mux/mux-uclass.c @@ -7,7 +7,7 @@ * Copyright (C) 2017 Axentia Technologies AB * Author: Peter Rosin <peda@axentia.se> * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 29304fd7775..ebab4d9f2e5 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -903,6 +903,23 @@ config MEDIATEK_ETH This Driver support MediaTek Ethernet GMAC Say Y to enable support for the MediaTek Ethernet GMAC. +config HIFEMAC_ETH + bool "HiSilicon Fast Ethernet Controller" + select DM_CLK + select DM_RESET + select PHYLIB + help + This driver supports HIFEMAC Ethernet controller found on + HiSilicon SoCs. + +config HIFEMAC_MDIO + bool "HiSilicon Fast Ethernet Controller MDIO interface" + depends on DM_MDIO + select DM_CLK + help + This driver supports the internal MDIO interface of HIFEMAC + Ethernet controller. + config HIGMACV300_ETH bool "HiSilicon Gigabit Ethernet Controller" select DM_RESET diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1d444f5b4a6..1ce6fea323c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,8 @@ obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o +obj-$(CONFIG_HIFEMAC_ETH) += hifemac.o +obj-$(CONFIG_HIFEMAC_MDIO) += hifemac_mdio.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 20b86e74cec..a174344b3ef 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -19,6 +19,7 @@ #include <net.h> #include <pci.h> #include <reset.h> +#include <phys2bus.h> #include <asm/cache.h> #include <dm/device_compat.h> #include <dm/device-internal.h> @@ -232,8 +233,10 @@ static void tx_descs_init(struct dw_eth_dev *priv) for (idx = 0; idx < CFG_TX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; - desc_p->dmamac_addr = (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]; - desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; + desc_p->dmamac_addr = dev_phys_to_bus(priv->dev, + (ulong)&txbuffs[idx * CFG_ETH_BUFSIZE]); + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, + (ulong)&desc_table_p[idx + 1]); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | @@ -251,14 +254,15 @@ static void tx_descs_init(struct dw_eth_dev *priv) } /* Correcting the last pointer of the chain */ - desc_p->dmamac_next = (ulong)&desc_table_p[0]; + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]); /* Flush all Tx buffer descriptors at once */ flush_dcache_range((ulong)priv->tx_mac_descrtable, (ulong)priv->tx_mac_descrtable + sizeof(priv->tx_mac_descrtable)); - writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); + writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]), + &dma_p->txdesclistaddr); priv->tx_currdescnum = 0; } @@ -280,8 +284,10 @@ static void rx_descs_init(struct dw_eth_dev *priv) for (idx = 0; idx < CFG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; - desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]; - desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; + desc_p->dmamac_addr = dev_phys_to_bus(priv->dev, + (ulong)&rxbuffs[idx * CFG_ETH_BUFSIZE]); + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, + (ulong)&desc_table_p[idx + 1]); desc_p->dmamac_cntl = (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | @@ -291,14 +297,15 @@ static void rx_descs_init(struct dw_eth_dev *priv) } /* Correcting the last pointer of the chain */ - desc_p->dmamac_next = (ulong)&desc_table_p[0]; + desc_p->dmamac_next = dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]); /* Flush all Rx buffer descriptors at once */ flush_dcache_range((ulong)priv->rx_mac_descrtable, (ulong)priv->rx_mac_descrtable + sizeof(priv->rx_mac_descrtable)); - writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); + writel(dev_phys_to_bus(priv->dev, (ulong)&desc_table_p[0]), + &dma_p->rxdesclistaddr); priv->rx_currdescnum = 0; } @@ -448,7 +455,7 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) ulong desc_start = (ulong)desc_p; ulong desc_end = desc_start + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); - ulong data_start = desc_p->dmamac_addr; + ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr); ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); /* * Strictly we only need to invalidate the "txrx_status" field @@ -515,7 +522,7 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) ulong desc_start = (ulong)desc_p; ulong desc_end = desc_start + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); - ulong data_start = desc_p->dmamac_addr; + ulong data_start = dev_bus_to_phys(priv->dev, desc_p->dmamac_addr); ulong data_end; /* Invalidate entire buffer descriptor */ @@ -532,7 +539,8 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) /* Invalidate received data */ data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); invalidate_dcache_range(data_start, data_end); - *packetp = (uchar *)(ulong)desc_p->dmamac_addr; + *packetp = (uchar *)(ulong)dev_bus_to_phys(priv->dev, + desc_p->dmamac_addr); } return length; @@ -757,6 +765,7 @@ int designware_eth_probe(struct udevice *dev) goto mdio_err; } priv->bus = miiphy_get_dev_by_name(dev->name); + priv->dev = dev; ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 9da4e902cb0..918a38615ad 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -241,6 +241,7 @@ struct dw_eth_dev { int clock_count; /* number of clock in clock list */ #endif + struct udevice *dev; struct phy_device *phydev; struct mii_dev *bus; }; diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 18466cfe257..a4e3698c600 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -746,6 +746,7 @@ static int eqos_start(struct udevice *dev) u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; ulong last_rx_desc; ulong desc_pad; + ulong addr64; debug("%s(dev=%p):\n", __func__, dev); @@ -1039,25 +1040,25 @@ static int eqos_start(struct udevice *dev) for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) { struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true); - rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + - (i * EQOS_MAX_PACKET_SIZE)); + + addr64 = (ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE)); + rx_desc->des0 = lower_32_bits(addr64); + rx_desc->des1 = upper_32_bits(addr64); rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; mb(); eqos->config->ops->eqos_flush_desc(rx_desc); - eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf + - (i * EQOS_MAX_PACKET_SIZE), - EQOS_MAX_PACKET_SIZE); + eqos->config->ops->eqos_inval_buffer((void *)addr64, EQOS_MAX_PACKET_SIZE); } - writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); - writel((ulong)eqos_get_desc(eqos, 0, false), - &eqos->dma_regs->ch0_txdesc_list_address); + addr64 = (ulong)eqos_get_desc(eqos, 0, false); + writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_haddress); + writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_address); writel(EQOS_DESCRIPTORS_TX - 1, &eqos->dma_regs->ch0_txdesc_ring_length); - writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress); - writel((ulong)eqos_get_desc(eqos, 0, true), - &eqos->dma_regs->ch0_rxdesc_list_address); + addr64 = (ulong)eqos_get_desc(eqos, 0, true); + writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_haddress); + writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_address); writel(EQOS_DESCRIPTORS_RX - 1, &eqos->dma_regs->ch0_rxdesc_ring_length); @@ -1162,8 +1163,8 @@ static int eqos_send(struct udevice *dev, void *packet, int length) eqos->tx_desc_idx++; eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX; - tx_desc->des0 = (ulong)eqos->tx_dma_buf; - tx_desc->des1 = 0; + tx_desc->des0 = lower_32_bits((ulong)eqos->tx_dma_buf); + tx_desc->des1 = upper_32_bits((ulong)eqos->tx_dma_buf); tx_desc->des2 = length; /* * Make sure that if HW sees the _OWN write below, it will see all the @@ -1234,14 +1235,17 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) for (idx = eqos->rx_desc_idx - idx_mask; idx <= eqos->rx_desc_idx; idx++) { + ulong addr64; + rx_desc = eqos_get_desc(eqos, idx, true); rx_desc->des0 = 0; + rx_desc->des1 = 0; mb(); eqos->config->ops->eqos_flush_desc(rx_desc); eqos->config->ops->eqos_inval_buffer(packet, length); - rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + - (idx * EQOS_MAX_PACKET_SIZE)); - rx_desc->des1 = 0; + addr64 = (ulong)(eqos->rx_dma_buf + (idx * EQOS_MAX_PACKET_SIZE)); + rx_desc->des0 = lower_32_bits(addr64); + rx_desc->des1 = upper_32_bits(addr64); rx_desc->des2 = 0; /* * Make sure that if HW sees the _OWN write below, diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 41e6ba760e2..84a2a7cf904 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5718,15 +5718,9 @@ static const struct eth_ops e1000_eth_ops = { .write_hwaddr = e1000_write_hwaddr, }; -static const struct udevice_id e1000_eth_ids[] = { - { .compatible = "intel,e1000" }, - { } -}; - U_BOOT_DRIVER(eth_e1000) = { .name = "eth_e1000", .id = UCLASS_ETH, - .of_match = e1000_eth_ids, .bind = e1000_eth_bind, .probe = e1000_eth_probe, .ops = &e1000_eth_ops, diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 587d3658fa9..9b536fd5ab8 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -13,6 +13,7 @@ #include <common.h> #include <clk.h> +#include <reset.h> #include <cpu_func.h> #include <dm.h> #include <log.h> @@ -91,6 +92,7 @@ struct ftgmac100_data { u32 max_speed; struct clk_bulk clks; + struct reset_ctl *reset_ctl; /* End of RX/TX ring buffer bits. Depend on model */ u32 rxdes0_edorr_mask; @@ -569,6 +571,8 @@ static int ftgmac100_of_to_plat(struct udevice *dev) priv->txdes0_edotr_mask = BIT(15); } + priv->reset_ctl = devm_reset_control_get_optional(dev, NULL); + return clk_get_bulk(dev, &priv->clks); } @@ -594,6 +598,12 @@ static int ftgmac100_probe(struct udevice *dev) if (ret) goto out; + if (priv->reset_ctl) { + ret = reset_deassert(priv->reset_ctl); + if (ret) + goto out; + } + /* * If DM MDIO is enabled, the MDIO bus will be initialized later in * dm_eth_phy_connect @@ -629,6 +639,8 @@ static int ftgmac100_remove(struct udevice *dev) free(priv->phydev); mdio_unregister(priv->bus); mdio_free(priv->bus); + if (priv->reset_ctl) + reset_assert(priv->reset_ctl); clk_release_bulk(&priv->clks); return 0; diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c new file mode 100644 index 00000000000..b61a29e6360 --- /dev/null +++ b/drivers/net/hifemac.c @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Hisilicon Fast Ethernet MAC Driver + * Adapted from linux + * + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + * Copyright (c) 2023 Yang Xiwen <forbidden405@outlook.com> + */ + +#include <dm.h> +#include <clk.h> +#include <miiphy.h> +#include <net.h> +#include <reset.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <linux/delay.h> +#include <linux/kernel.h> + +/* MAC control register list */ +#define MAC_PORTSEL 0x0200 +#define MAC_PORTSEL_STAT_CPU BIT(0) +#define MAC_PORTSEL_RMII BIT(1) +#define MAC_PORTSET 0x0208 +#define MAC_PORTSET_DUPLEX_FULL BIT(0) +#define MAC_PORTSET_LINKED BIT(1) +#define MAC_PORTSET_SPEED_100M BIT(2) +#define MAC_SET 0x0210 +#define MAX_FRAME_SIZE 1600 +#define MAX_FRAME_SIZE_MASK GENMASK(10, 0) +#define BIT_PAUSE_EN BIT(18) +#define RX_COALESCE_SET 0x0340 +#define RX_COALESCED_FRAME_OFFSET 24 +#define RX_COALESCED_FRAMES 8 +#define RX_COALESCED_TIMER 0x74 +#define QLEN_SET 0x0344 +#define RX_DEPTH_OFFSET 8 +#define MAX_HW_FIFO_DEPTH 64 +#define HW_TX_FIFO_DEPTH 1 +#define MAX_HW_RX_FIFO_DEPTH (MAX_HW_FIFO_DEPTH - HW_TX_FIFO_DEPTH) +#define HW_RX_FIFO_DEPTH min(PKTBUFSRX, MAX_HW_RX_FIFO_DEPTH) +#define IQFRM_DES 0x0354 +#define RX_FRAME_LEN_MASK GENMASK(11, 0) +#define RX_FRAME_IN_INDEX_MASK GENMASK(17, 12) +#define IQ_ADDR 0x0358 +#define EQ_ADDR 0x0360 +#define EQFRM_LEN 0x0364 +#define ADDRQ_STAT 0x036C +#define TX_CNT_INUSE_MASK GENMASK(5, 0) +#define BIT_TX_READY BIT(24) +#define BIT_RX_READY BIT(25) +/* global control register list */ +#define GLB_HOSTMAC_L32 0x0000 +#define GLB_HOSTMAC_H16 0x0004 +#define GLB_SOFT_RESET 0x0008 +#define SOFT_RESET_ALL BIT(0) +#define GLB_FWCTRL 0x0010 +#define FWCTRL_VLAN_ENABLE BIT(0) +#define FWCTRL_FW2CPU_ENA BIT(5) +#define FWCTRL_FWALL2CPU BIT(7) +#define GLB_MACTCTRL 0x0014 +#define MACTCTRL_UNI2CPU BIT(1) +#define MACTCTRL_MULTI2CPU BIT(3) +#define MACTCTRL_BROAD2CPU BIT(5) +#define MACTCTRL_MACT_ENA BIT(7) +#define GLB_IRQ_STAT 0x0030 +#define GLB_IRQ_ENA 0x0034 +#define IRQ_ENA_PORT0_MASK GENMASK(7, 0) +#define IRQ_ENA_PORT0 BIT(18) +#define IRQ_ENA_ALL BIT(19) +#define GLB_IRQ_RAW 0x0038 +#define IRQ_INT_RX_RDY BIT(0) +#define IRQ_INT_TX_PER_PACKET BIT(1) +#define IRQ_INT_TX_FIFO_EMPTY BIT(6) +#define IRQ_INT_MULTI_RXRDY BIT(7) +#define DEF_INT_MASK (IRQ_INT_MULTI_RXRDY | \ + IRQ_INT_TX_PER_PACKET | \ + IRQ_INT_TX_FIFO_EMPTY) +#define GLB_MAC_L32_BASE 0x0100 +#define GLB_MAC_H16_BASE 0x0104 +#define MACFLT_HI16_MASK GENMASK(15, 0) +#define BIT_MACFLT_ENA BIT(17) +#define BIT_MACFLT_FW2CPU BIT(21) +#define GLB_MAC_H16(reg) (GLB_MAC_H16_BASE + ((reg) * 0x8)) +#define GLB_MAC_L32(reg) (GLB_MAC_L32_BASE + ((reg) * 0x8)) +#define MAX_MAC_FILTER_NUM 8 +#define MAX_UNICAST_ADDRESSES 2 +#define MAX_MULTICAST_ADDRESSES (MAX_MAC_FILTER_NUM - \ + MAX_UNICAST_ADDRESSES) +/* software tx and rx queue number, should be power of 2 */ +#define TXQ_NUM 64 +#define RXQ_NUM 128 + +#define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us" +#define MAC_RESET_DELAY_PROPERTY "hisilicon,mac-reset-delay-us" +#define MAC_RESET_ASSERT_PERIOD 200000 + +enum phy_reset_delays { + PRE_DELAY, + PULSE, + POST_DELAY, + DELAYS_NUM, +}; + +enum clk_type { + CLK_MAC, + CLK_BUS, + CLK_PHY, + CLK_NUM, +}; + +struct hisi_femac_priv { + void __iomem *port_base; + void __iomem *glb_base; + struct clk *clks[CLK_NUM]; + struct reset_ctl *mac_rst; + struct reset_ctl *phy_rst; + u32 phy_reset_delays[DELAYS_NUM]; + u32 mac_reset_delay; + + struct phy_device *phy; + + u32 link_status; +}; + +static void hisi_femac_irq_enable(struct hisi_femac_priv *priv, int irqs) +{ + u32 val; + + val = readl(priv->glb_base + GLB_IRQ_ENA); + writel(val | irqs, priv->glb_base + GLB_IRQ_ENA); +} + +static void hisi_femac_irq_disable(struct hisi_femac_priv *priv, int irqs) +{ + u32 val; + + val = readl(priv->glb_base + GLB_IRQ_ENA); + writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA); +} + +static void hisi_femac_port_init(struct hisi_femac_priv *priv) +{ + u32 val; + + /* MAC gets link status info and phy mode by software config */ + val = MAC_PORTSEL_STAT_CPU; + if (priv->phy->interface == PHY_INTERFACE_MODE_RMII) + val |= MAC_PORTSEL_RMII; + writel(val, priv->port_base + MAC_PORTSEL); + + /*clear all interrupt status */ + writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW); + hisi_femac_irq_disable(priv, IRQ_ENA_PORT0_MASK | IRQ_ENA_PORT0); + + val = readl(priv->glb_base + GLB_FWCTRL); + val &= ~(FWCTRL_VLAN_ENABLE | FWCTRL_FWALL2CPU); + val |= FWCTRL_FW2CPU_ENA; + writel(val, priv->glb_base + GLB_FWCTRL); + + val = readl(priv->glb_base + GLB_MACTCTRL); + val |= (MACTCTRL_BROAD2CPU | MACTCTRL_MACT_ENA); + writel(val, priv->glb_base + GLB_MACTCTRL); + + val = readl(priv->port_base + MAC_SET); + val &= ~MAX_FRAME_SIZE_MASK; + val |= MAX_FRAME_SIZE; + writel(val, priv->port_base + MAC_SET); + + val = RX_COALESCED_TIMER | + (RX_COALESCED_FRAMES << RX_COALESCED_FRAME_OFFSET); + writel(val, priv->port_base + RX_COALESCE_SET); + + val = (HW_RX_FIFO_DEPTH << RX_DEPTH_OFFSET) | HW_TX_FIFO_DEPTH; + writel(val, priv->port_base + QLEN_SET); +} + +static void hisi_femac_rx_refill(struct hisi_femac_priv *priv) +{ + int i; + ulong addr; + + for (i = 0; i < HW_RX_FIFO_DEPTH; i++) { + addr = (ulong)net_rx_packets[i]; + writel(addr, priv->port_base + IQ_ADDR); + } +} + +static void hisi_femac_adjust_link(struct udevice *dev) +{ + struct hisi_femac_priv *priv = dev_get_priv(dev); + struct phy_device *phy = priv->phy; + u32 status = 0; + + if (phy->link) + status |= MAC_PORTSET_LINKED; + if (phy->duplex == DUPLEX_FULL) + status |= MAC_PORTSET_DUPLEX_FULL; + if (phy->speed == SPEED_100) + status |= MAC_PORTSET_SPEED_100M; + + writel(status, priv->port_base + MAC_PORTSET); +} + +static int hisi_femac_port_reset(struct hisi_femac_priv *priv) +{ + u32 val; + + val = readl(priv->glb_base + GLB_SOFT_RESET); + val |= SOFT_RESET_ALL; + writel(val, priv->glb_base + GLB_SOFT_RESET); + + udelay(800); + + val &= ~SOFT_RESET_ALL; + writel(val, priv->glb_base + GLB_SOFT_RESET); + + return 0; +} + +static int hisi_femac_set_hw_mac_addr(struct udevice *dev) +{ + struct hisi_femac_priv *priv = dev_get_priv(dev); + struct eth_pdata *plat = dev_get_plat(dev); + unsigned char *mac = plat->enetaddr; + u32 reg; + + reg = mac[1] | (mac[0] << 8); + writel(reg, priv->glb_base + GLB_HOSTMAC_H16); + + reg = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24); + writel(reg, priv->glb_base + GLB_HOSTMAC_L32); + + return 0; +} + +static int hisi_femac_start(struct udevice *dev) +{ + int ret; + struct hisi_femac_priv *priv = dev_get_priv(dev); + + hisi_femac_port_reset(priv); + hisi_femac_set_hw_mac_addr(dev); + hisi_femac_rx_refill(priv); + + ret = phy_startup(priv->phy); + if (ret) + return log_msg_ret("Failed to startup phy", ret); + + if (!priv->phy->link) { + debug("%s: link down\n", __func__); + return -ENODEV; + } + + hisi_femac_adjust_link(dev); + + writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW); + hisi_femac_irq_enable(priv, IRQ_ENA_ALL | IRQ_ENA_PORT0 | DEF_INT_MASK); + + return 0; +} + +static int hisi_femac_send(struct udevice *dev, void *packet, int length) +{ + struct hisi_femac_priv *priv = dev_get_priv(dev); + ulong addr = (ulong)packet; + int ret; + + // clear previous irq + writel(IRQ_INT_TX_PER_PACKET, priv->glb_base + GLB_IRQ_RAW); + + // flush cache + flush_cache(addr, length + ETH_FCS_LEN); + + // write packet address + writel(addr, priv->port_base + EQ_ADDR); + + // write packet length (and send it) + writel(length + ETH_FCS_LEN, priv->port_base + EQFRM_LEN); + + // wait until FIFO is empty + ret = wait_for_bit_le32(priv->glb_base + GLB_IRQ_RAW, IRQ_INT_TX_PER_PACKET, true, 50, false); + if (ret == -ETIMEDOUT) + return log_msg_ret("FIFO timeout", ret); + + return 0; +} + +static int hisi_femac_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct hisi_femac_priv *priv = dev_get_priv(dev); + int val, index, length; + + val = readl(priv->glb_base + GLB_IRQ_RAW); + if (!(val & IRQ_INT_RX_RDY)) + return -EAGAIN; + + val = readl(priv->port_base + IQFRM_DES); + index = (val & RX_FRAME_IN_INDEX_MASK) >> 12; + length = val & RX_FRAME_LEN_MASK; + + // invalidate cache + invalidate_dcache_range((ulong)net_rx_packets[index], (ulong)net_rx_packets[index] + length); + *packetp = net_rx_packets[index]; + + // Tell hardware we will process the packet + writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW); + + return length; +} + +static int hisi_femac_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct hisi_femac_priv *priv = dev_get_priv(dev); + ulong addr = (ulong)packet; + + // Tell hardware the packet can be reused + writel(addr, priv->port_base + IQ_ADDR); + + return 0; +} + +static void hisi_femac_stop(struct udevice *dev) +{ + struct hisi_femac_priv *priv = dev_get_priv(dev); + + // assert internal reset + writel(SOFT_RESET_ALL, priv->glb_base + GLB_SOFT_RESET); +} + +int hisi_femac_of_to_plat(struct udevice *dev) +{ + int ret, i; + struct hisi_femac_priv *priv = dev_get_priv(dev); + static const char * const clk_strs[] = { + [CLK_MAC] = "mac", + [CLK_BUS] = "bus", + [CLK_PHY] = "phy", + }; + + priv->port_base = dev_remap_addr_name(dev, "port"); + if (IS_ERR(priv->port_base)) + return log_msg_ret("Failed to remap port address space", PTR_ERR(priv->port_base)); + + priv->glb_base = dev_remap_addr_name(dev, "glb"); + if (IS_ERR(priv->glb_base)) + return log_msg_ret("Failed to remap global address space", PTR_ERR(priv->glb_base)); + + for (i = 0; i < ARRAY_SIZE(clk_strs); i++) { + priv->clks[i] = devm_clk_get(dev, clk_strs[i]); + if (IS_ERR(priv->clks[i])) { + dev_err(dev, "Error getting clock %s\n", clk_strs[i]); + return log_msg_ret("Failed to get clocks", PTR_ERR(priv->clks[i])); + } + } + + priv->mac_rst = devm_reset_control_get(dev, "mac"); + if (IS_ERR(priv->mac_rst)) + return log_msg_ret("Failed to get MAC reset", PTR_ERR(priv->mac_rst)); + + priv->phy_rst = devm_reset_control_get(dev, "phy"); + if (IS_ERR(priv->phy_rst)) + return log_msg_ret("Failed to get PHY reset", PTR_ERR(priv->phy_rst)); + + ret = dev_read_u32_array(dev, + PHY_RESET_DELAYS_PROPERTY, + priv->phy_reset_delays, + DELAYS_NUM); + if (ret < 0) + return log_msg_ret("Failed to get PHY reset delays", ret); + + priv->mac_reset_delay = dev_read_u32_default(dev, + MAC_RESET_DELAY_PROPERTY, + MAC_RESET_ASSERT_PERIOD); + + return 0; +} + +static int hisi_femac_phy_reset(struct hisi_femac_priv *priv) +{ + struct reset_ctl *rst = priv->phy_rst; + u32 *delays = priv->phy_reset_delays; + int ret; + + // Disable MAC clk before phy reset + ret = clk_disable(priv->clks[CLK_MAC]); + if (ret < 0) + return log_msg_ret("Failed to disable MAC clock", ret); + ret = clk_disable(priv->clks[CLK_BUS]); + if (ret < 0) + return log_msg_ret("Failed to disable bus clock", ret); + + udelay(delays[PRE_DELAY]); + + ret = reset_assert(rst); + if (ret < 0) + return log_msg_ret("Failed to assert reset", ret); + + udelay(delays[PULSE]); + + ret = reset_deassert(rst); + if (ret < 0) + return log_msg_ret("Failed to deassert reset", ret); + + udelay(delays[POST_DELAY]); + + ret = clk_enable(priv->clks[CLK_MAC]); + if (ret < 0) + return log_msg_ret("Failed to enable MAC clock", ret); + ret = clk_enable(priv->clks[CLK_BUS]); + if (ret < 0) + return log_msg_ret("Failed to enable MAC bus clock", ret); + + return 0; +} + +int hisi_femac_probe(struct udevice *dev) +{ + struct hisi_femac_priv *priv = dev_get_priv(dev); + int ret, i; + + // Enable clocks + for (i = 0; i < CLK_NUM; i++) { + ret = clk_prepare_enable(priv->clks[i]); + if (ret < 0) + return log_msg_ret("Failed to enable clks", ret); + } + + // Reset MAC + ret = reset_assert(priv->mac_rst); + if (ret < 0) + return log_msg_ret("Failed to assert MAC reset", ret); + + udelay(priv->mac_reset_delay); + + ret = reset_deassert(priv->mac_rst); + if (ret < 0) + return log_msg_ret("Failed to deassert MAC reset", ret); + + // Reset PHY + ret = hisi_femac_phy_reset(priv); + if (ret < 0) + return log_msg_ret("Failed to reset phy", ret); + + // Connect to PHY + priv->phy = dm_eth_phy_connect(dev); + if (!priv->phy) + return log_msg_ret("Failed to connect to phy", -EINVAL); + + hisi_femac_port_init(priv); + return 0; +} + +static const struct eth_ops hisi_femac_ops = { + .start = hisi_femac_start, + .send = hisi_femac_send, + .recv = hisi_femac_recv, + .free_pkt = hisi_femac_free_pkt, + .stop = hisi_femac_stop, + .write_hwaddr = hisi_femac_set_hw_mac_addr, +}; + +static const struct udevice_id hisi_femac_ids[] = { + {.compatible = "hisilicon,hisi-femac-v1",}, + {.compatible = "hisilicon,hisi-femac-v2",}, + {.compatible = "hisilicon,hi3516cv300-femac",}, + {.compatible = "hisilicon,hi3798mv200-femac",}, + {}, +}; + +U_BOOT_DRIVER(hisi_femac_driver) = { + .name = "eth_hisi_femac", + .id = UCLASS_ETH, + .of_match = of_match_ptr(hisi_femac_ids), + .of_to_plat = hisi_femac_of_to_plat, + .ops = &hisi_femac_ops, + .probe = hisi_femac_probe, + .plat_auto = sizeof(struct eth_pdata), + .priv_auto = sizeof(struct hisi_femac_priv), +}; diff --git a/drivers/net/hifemac_mdio.c b/drivers/net/hifemac_mdio.c new file mode 100644 index 00000000000..343c5f3a38a --- /dev/null +++ b/drivers/net/hifemac_mdio.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Hisilicon Fast Ethernet MDIO Bus Driver + * + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + */ + +#include <dm.h> +#include <clk.h> +#include <miiphy.h> +#include <linux/io.h> +#include <linux/iopoll.h> + +#define MDIO_RWCTRL 0x00 +#define MDIO_RO_DATA 0x04 +#define MDIO_WRITE BIT(13) +#define MDIO_RW_FINISH BIT(15) +#define BIT_PHY_ADDR_OFFSET 8 +#define BIT_WR_DATA_OFFSET 16 + +struct hisi_femac_mdio_data { + struct clk *clk; + void __iomem *membase; +}; + +static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data) +{ + u32 val; + + return readl_poll_timeout(data->membase + MDIO_RWCTRL, + val, val & MDIO_RW_FINISH, 10000); +} + +static int hisi_femac_mdio_read(struct udevice *dev, int addr, int devad, int reg) +{ + struct hisi_femac_mdio_data *data = dev_get_priv(dev); + int ret; + + ret = hisi_femac_mdio_wait_ready(data); + if (ret) + return ret; + + writel((addr << BIT_PHY_ADDR_OFFSET) | reg, + data->membase + MDIO_RWCTRL); + + ret = hisi_femac_mdio_wait_ready(data); + if (ret) + return ret; + + return readl(data->membase + MDIO_RO_DATA) & 0xFFFF; +} + +static int hisi_femac_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val) +{ + struct hisi_femac_mdio_data *data = dev_get_priv(dev); + int ret; + + ret = hisi_femac_mdio_wait_ready(data); + if (ret) + return ret; + + writel(MDIO_WRITE | (val << BIT_WR_DATA_OFFSET) | + (addr << BIT_PHY_ADDR_OFFSET) | reg, + data->membase + MDIO_RWCTRL); + + return hisi_femac_mdio_wait_ready(data); +} + +static int hisi_femac_mdio_of_to_plat(struct udevice *dev) +{ + struct hisi_femac_mdio_data *data = dev_get_priv(dev); + int ret; + + data->membase = dev_remap_addr(dev); + if (IS_ERR(data->membase)) { + ret = PTR_ERR(data->membase); + return log_msg_ret("Failed to remap base addr", ret); + } + + // clk is optional + data->clk = devm_clk_get_optional(dev, NULL); + + return 0; +} + +static int hisi_femac_mdio_probe(struct udevice *dev) +{ + struct hisi_femac_mdio_data *data = dev_get_priv(dev); + int ret; + + ret = clk_prepare_enable(data->clk); + if (ret) + return log_msg_ret("Failed to enable clk", ret); + + return 0; +} + +static const struct mdio_ops hisi_femac_mdio_ops = { + .read = hisi_femac_mdio_read, + .write = hisi_femac_mdio_write, +}; + +static const struct udevice_id hisi_femac_mdio_dt_ids[] = { + { .compatible = "hisilicon,hisi-femac-mdio" }, + { } +}; + +U_BOOT_DRIVER(hisi_femac_mdio_driver) = { + .name = "hisi-femac-mdio", + .id = UCLASS_MDIO, + .of_match = hisi_femac_mdio_dt_ids, + .of_to_plat = hisi_femac_mdio_of_to_plat, + .probe = hisi_femac_mdio_probe, + .ops = &hisi_femac_mdio_ops, + .priv_auto = sizeof(struct hisi_femac_mdio_data), +}; diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c index 64e860e324d..c073f81e72d 100644 --- a/drivers/net/mv88e6xxx.c +++ b/drivers/net/mv88e6xxx.c @@ -29,6 +29,7 @@ #include <dm/device-internal.h> #include <dm/lists.h> #include <dm/of_extra.h> +#include <linux/bitfield.h> #include <linux/delay.h> #include <miiphy.h> #include <net/dsa.h> @@ -110,20 +111,35 @@ */ #define SMI_BUSY BIT(15) #define SMI_CMD_CLAUSE_22 BIT(12) -#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10) -#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10) -#define SMI_CMD_ADDR_SHIFT 5 -#define SMI_CMD_ADDR_MASK 0x1f -#define SMI_CMD_REG_SHIFT 0 -#define SMI_CMD_REG_MASK 0x1f +#define SMI_CMD_OP_MASK GENMASK(11, 10) +#define SMI_CMD_CLAUSE_22_OP_WRITE 0x1 +#define SMI_CMD_CLAUSE_22_OP_READ 0x2 +#define SMI_CMD_CLAUSE_45_OP_WRITE_ADDR 0x0 +#define SMI_CMD_CLAUSE_45_OP_WRITE 0x1 +#define SMI_CMD_CLAUSE_45_OP_READ 0x3 + +#define SMI_CMD_ADDR_MASK GENMASK(9, 5) +#define SMI_CMD_REG_MASK GENMASK(4, 0) #define SMI_CMD_READ(addr, reg) \ - (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_READ) | \ - (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \ - (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT) + (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_READ)) | \ + (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \ + (FIELD_PREP(SMI_CMD_REG_MASK, reg)) #define SMI_CMD_WRITE(addr, reg) \ - (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_WRITE) | \ - (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \ - (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT) + (SMI_BUSY | SMI_CMD_CLAUSE_22 | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_22_OP_WRITE)) | \ + (FIELD_PREP(SMI_CMD_ADDR_MASK, addr)) | \ + (FIELD_PREP(SMI_CMD_REG_MASK, reg)) +#define SMI_CMD_SET_C45_ADDR(phyad, devad) \ + (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_WRITE_ADDR)) | \ + (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \ + (FIELD_PREP(SMI_CMD_REG_MASK, devad)) +#define SMI_CMD_READ_C45(phyad, devad) \ + (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_READ)) | \ + (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \ + (FIELD_PREP(SMI_CMD_REG_MASK, devad)) +#define SMI_CMD_WRITE_C45(phyad, devad) \ + (SMI_BUSY | FIELD_PREP(SMI_CMD_OP_MASK, SMI_CMD_CLAUSE_45_OP_WRITE)) | \ + (FIELD_PREP(SMI_CMD_ADDR_MASK, phyad)) | \ + (FIELD_PREP(SMI_CMD_REG_MASK, devad)) /* ID register values for different switch models */ #define PORT_SWITCH_ID_6020 0x0200 @@ -272,12 +288,37 @@ static int mv88e6xxx_phy_wait(struct udevice *dev) static int mv88e6xxx_phy_read_indirect(struct udevice *dev, int phyad, int devad, int reg) { struct mv88e6xxx_priv *priv = dev_get_priv(dev); + u16 smi_cmd; int res; + if (devad >= 0) { + /* + * For C45 we need to write the register address into the + * PHY Data register first and then call the Write Address + * Register OP in the PHY command register. + */ + res = mv88e6xxx_reg_write(dev, priv->global2, + GLOBAL2_REG_PHY_DATA, + reg); + + res = mv88e6xxx_reg_write(dev, priv->global2, + GLOBAL2_REG_PHY_CMD, + SMI_CMD_SET_C45_ADDR(phyad, devad)); + + /* Wait for busy bit to clear */ + res = mv88e6xxx_phy_wait(dev); + if (res < 0) + return res; + + /* Set the actual C45 or C22 OP-s */ + smi_cmd = SMI_CMD_READ_C45(phyad, devad); + } else + smi_cmd = SMI_CMD_READ(phyad, reg); + /* Issue command to read */ res = mv88e6xxx_reg_write(dev, priv->global2, GLOBAL2_REG_PHY_CMD, - SMI_CMD_READ(phyad, reg)); + smi_cmd); /* Wait for data to be read */ res = mv88e6xxx_phy_wait(dev); @@ -293,8 +334,33 @@ static int mv88e6xxx_phy_write_indirect(struct udevice *dev, int phyad, int devad, int reg, u16 data) { struct mv88e6xxx_priv *priv = dev_get_priv(dev); + u16 smi_cmd; int res; + if (devad >= 0) { + /* + * For C45 we need to write the register address into the + * PHY Data register first and then call the Write Address + * Register OP in the PHY command register. + */ + res = mv88e6xxx_reg_write(dev, priv->global2, + GLOBAL2_REG_PHY_DATA, + reg); + + res = mv88e6xxx_reg_write(dev, priv->global2, + GLOBAL2_REG_PHY_CMD, + SMI_CMD_SET_C45_ADDR(phyad, devad)); + + /* Wait for busy bit to clear */ + res = mv88e6xxx_phy_wait(dev); + if (res < 0) + return res; + + /* Set the actual C45 or C22 OP-s */ + smi_cmd = SMI_CMD_WRITE_C45(phyad, devad); + } else + smi_cmd = SMI_CMD_WRITE(phyad, reg); + /* Set the data to write */ res = mv88e6xxx_reg_write(dev, priv->global2, GLOBAL2_REG_PHY_DATA, data); @@ -303,7 +369,7 @@ static int mv88e6xxx_phy_write_indirect(struct udevice *dev, int phyad, /* Issue the write command */ res = mv88e6xxx_reg_write(dev, priv->global2, GLOBAL2_REG_PHY_CMD, - SMI_CMD_WRITE(phyad, reg)); + smi_cmd); if (res < 0) return res; diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index 8d32d73b07f..f9d4782580e 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -81,7 +81,10 @@ /* RGMIIDCTL bits */ #define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 -#define DP83869_CLK_DELAY_DEF 7 +#define DP83869_CLK_DELAY_STEP 250 +#define DP83869_CLK_DELAY_MIN 250 +#define DP83869_CLK_DELAY_MAX 4000 +#define DP83869_CLK_DELAY_DEFAULT 2000 /* CFG2 bits */ #define MII_DP83869_CFG2_SPEEDOPT_10EN 0x0040 @@ -157,10 +160,6 @@ static int dp83869_config_port_mirroring(struct phy_device *phydev) return 0; } -static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, - 1750, 2000, 2250, 2500, 2750, 3000, - 3250, 3500, 3750, 4000}; - static int dp83869_set_strapped_mode(struct phy_device *phydev) { struct dp83869_private *dp83869 = phydev->priv; @@ -183,7 +182,6 @@ static int dp83869_set_strapped_mode(struct phy_device *phydev) static int dp83869_of_init(struct phy_device *phydev) { struct dp83869_private * const dp83869 = phydev->priv; - const int delay_entries = ARRAY_SIZE(dp83869_internal_delay); int ret; ofnode node; @@ -238,32 +236,45 @@ static int dp83869_of_init(struct phy_device *phydev) dp83869->tx_fifo_depth = ofnode_read_s32_default(node, "tx-fifo-depth", DP83869_PHYCR_FIFO_DEPTH_4_B_NIB); + /* Internal clock delay values can be configured in steps of + * 250ps (0.25ns). The register field for clock delay is 4-bits wide, + * the values range from 0b0000 for 0.25ns to 0b1111 for 4ns. + */ + /* RX delay *must* be specified if internal delay of RX is used. */ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { - dp83869->rx_int_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", - DP83869_CLK_DELAY_DEF); - if (dp83869->rx_int_delay > delay_entries) { - dp83869->rx_int_delay = DP83869_CLK_DELAY_DEF; - pr_debug("rx-internal-delay-ps not set/invalid, default to %ups\n", - dp83869_internal_delay[dp83869->rx_int_delay]); + dp83869->rx_int_delay = ofnode_read_u32_default(node, + "rx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT); + if (dp83869->rx_int_delay > DP83869_CLK_DELAY_MAX || + dp83869->rx_int_delay < DP83869_CLK_DELAY_MIN || + dp83869->rx_int_delay % DP83869_CLK_DELAY_STEP) { + dp83869->rx_int_delay = DP83869_CLK_DELAY_DEFAULT; + pr_warn("rx-internal-delay-ps not set/invalid, default" + " to %ups\n", DP83869_CLK_DELAY_DEFAULT); } - dp83869->rx_int_delay = dp83869_internal_delay[dp83869->rx_int_delay]; + dp83869->rx_int_delay = + (dp83869->rx_int_delay - DP83869_CLK_DELAY_STEP) + / DP83869_CLK_DELAY_STEP; } - /* TX delay *must* be specified if internal delay of RX is used. */ + /* TX delay *must* be specified if internal delay of TX is used. */ if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { - dp83869->tx_int_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", - DP83869_CLK_DELAY_DEF); - if (dp83869->tx_int_delay > delay_entries) { - dp83869->tx_int_delay = DP83869_CLK_DELAY_DEF; - pr_debug("tx-internal-delay-ps not set/invalid, default to %ups\n", - dp83869_internal_delay[dp83869->tx_int_delay]); + dp83869->tx_int_delay = ofnode_read_u32_default(node, + "tx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT); + if (dp83869->tx_int_delay > DP83869_CLK_DELAY_MAX || + dp83869->tx_int_delay < DP83869_CLK_DELAY_MIN || + dp83869->tx_int_delay % DP83869_CLK_DELAY_STEP) { + dp83869->tx_int_delay = DP83869_CLK_DELAY_DEFAULT; + pr_warn("tx-internal-delay-ps not set/invalid, default" + " to %ups\n", DP83869_CLK_DELAY_DEFAULT); } - dp83869->tx_int_delay = dp83869_internal_delay[dp83869->tx_int_delay]; + dp83869->tx_int_delay = + (dp83869->tx_int_delay - DP83869_CLK_DELAY_STEP) + / DP83869_CLK_DELAY_STEP; } return 0; diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c index fa4831427d5..db879bc73f2 100644 --- a/drivers/net/phy/et1011c.c +++ b/drivers/net/phy/et1011c.c @@ -3,7 +3,7 @@ * ET1011C PHY driver * * Derived from Linux kernel driver by Chaithrika U S - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ */ #include <config.h> #include <phy.h> diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 02660e4fbb4..c75f4186285 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ config DRIVER_TI_CPSW bool "TI Common Platform Ethernet Switch" diff --git a/drivers/net/ti/Makefile b/drivers/net/ti/Makefile index 8d3808bb4b6..0ce0cf2828a 100644 --- a/drivers/net/ti/Makefile +++ b/drivers/net/ti/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index 877be7fca52..9a5e9642df1 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -2,7 +2,7 @@ /* * CPSW Ethernet Switch Driver * - * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010-2018 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/drivers/net/ti/cpsw_mdio.c b/drivers/net/ti/cpsw_mdio.c index ac791faa813..74cc956785f 100644 --- a/drivers/net/ti/cpsw_mdio.c +++ b/drivers/net/ti/cpsw_mdio.c @@ -2,7 +2,7 @@ /* * CPSW MDIO generic driver for TI AMxx/K2x/EMAC devices. * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/drivers/net/ti/cpsw_mdio.h b/drivers/net/ti/cpsw_mdio.h index 9b98763656f..ddf65a4686d 100644 --- a/drivers/net/ti/cpsw_mdio.h +++ b/drivers/net/ti/cpsw_mdio.h @@ -2,7 +2,7 @@ /* * CPSW MDIO generic driver API for TI AMxx/K2x/EMAC devices. * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef CPSW_MDIO_H_ diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 5d4de86e71a..2e8723186c0 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ # Written by Jean-Jacques Hiblot <jjhiblot@ti.com> obj-y += allwinner/ diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index fc5044fd5d3..4bb8a0ca7f3 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -7,7 +7,7 @@ * Copyright (c) 2018 Cadence Design Systems * Author: Alan Douglas <adouglas@cadence.com> * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Jean-Jacques Hiblot <jjhiblot@ti.com> * */ diff --git a/drivers/phy/keystone-usb-phy.c b/drivers/phy/keystone-usb-phy.c index 6799e232370..3bb9c0814c1 100644 --- a/drivers/phy/keystone-usb-phy.c +++ b/drivers/phy/keystone-usb-phy.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/drivers/phy/nop-phy.c b/drivers/phy/nop-phy.c index d0904f4f075..c53e3216d0f 100644 --- a/drivers/phy/nop-phy.c +++ b/drivers/phy/nop-phy.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c index 2a9604cdcc4..d3d38062ecf 100644 --- a/drivers/phy/omap-usb2-phy.c +++ b/drivers/phy/omap-usb2-phy.c @@ -2,7 +2,7 @@ /* * OMAP USB2 PHY LAYER * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com * Written by Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index 22f2fe91487..0dcfe258bc4 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/drivers/phy/sandbox-phy.c b/drivers/phy/sandbox-phy.c index 7b3d988613b..7e123da25fb 100644 --- a/drivers/phy/sandbox-phy.c +++ b/drivers/phy/sandbox-phy.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c index 313735844ab..29a35ae5ffb 100644 --- a/drivers/phy/ti-pipe3-phy.c +++ b/drivers/phy/ti-pipe3-phy.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 72613399073..daf62f5deda 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 7976e3b3ed5..ff49819b58d 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -329,6 +329,7 @@ struct group_info { static const struct group_info npcm8xx_groups[] = { FUNC_LIST + {FN_gpio, "GPIO", NULL, 0, 0, 0} }; /* Pin flags */ diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c index 7b045f75d3f..e88ec1c1837 100644 --- a/drivers/pinctrl/renesas/rzg2l-pfc.c +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -5,7 +5,6 @@ * Copyright (C) 2021-2023 Renesas Electronics Corp. */ -#include <common.h> #include <asm/io.h> #include <clk.h> #include <dm.h> diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 411c210756a..bd82d2f7044 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -83,6 +83,13 @@ config SANDBOX_POWER_DOMAIN simply accepts requests to power on/off various HW modules without actually doing anything beyond a little error checking. +config SCMI_POWER_DOMAIN + bool "Enable SCMI power domain driver" + depends on POWER_DOMAIN && SCMI_FIRMWARE + help + Enable power domain implementation based on SCMI power domain + management protocol. + config TEGRA186_POWER_DOMAIN bool "Enable Tegra186 BPMP-based power domain driver" depends on TEGRA186_BPMP diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index aa5a4ba57cd..2daab73eb75 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o +obj-$(CONFIG_SCMI_POWER_DOMAIN) += scmi-power-domain.o obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o diff --git a/drivers/power/domain/scmi-power-domain.c b/drivers/power/domain/scmi-power-domain.c new file mode 100644 index 00000000000..3cd0f075d95 --- /dev/null +++ b/drivers/power/domain/scmi-power-domain.c @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SCMI Power domain driver + * + * Copyright (C) 2023 Linaro Limited + * author: AKASHI Takahiro <takahiro.akashi@linaro.org> + */ + +#include <dm.h> +#include <malloc.h> +#include <power-domain.h> +#include <power-domain-uclass.h> +#include <scmi_agent.h> +#include <scmi_protocols.h> +#include <dm/device_compat.h> + +/** + * struct scmi_pwd_properties + * @attributes: Power domain attributes + * @name: Name of the domain + */ +struct scmi_pwd_properties { + u32 attributes; + u8 *name; /* not used now */ +}; + +/** + * struct scmi_power_domain_priv + * @num_pwdoms: Number of power domains + * @prop: Pointer to domain's properties + * @stats_addr: Address of statistics memory region + * @stats_len: Length of statistics memory region + */ +struct scmi_power_domain_priv { + int num_pwdoms; + struct scmi_pwd_properties *prop; + u64 stats_addr; + size_t stats_len; +}; + +/** + * async_is_supported - check asynchronous transition + * @attributes: Power domain attributes + * + * Determine if the power transition can be done asynchronously. + * + * Return: true if supported, false if not + */ +static bool async_is_supported(u32 attributes) +{ + if (attributes & SCMI_PWD_ATTR_PSTATE_ASYNC) + return true; + + /* TODO: check attributes && SCMI_PWD_ATTR_PSTATE_SYNC */ + return false; +} + +/** + * scmi_power_domain_on - Enable the power domain + * @power_domain: Power domain + * + * Turn on the power domain. + * + * Return: 0 on success, error code on failure + */ +static int scmi_power_domain_on(struct power_domain *power_domain) +{ + struct scmi_power_domain_priv *priv = dev_get_priv(power_domain->dev); + u32 flags, pstate; + int ret; + + if (power_domain->id > priv->num_pwdoms) + return -EINVAL; + + if (async_is_supported(priv->prop[power_domain->id].attributes)) + flags = SCMI_PWD_SET_FLAGS_ASYNC; + else + flags = 0; + + /* ON */ + pstate = 0; + + ret = scmi_pwd_state_set(power_domain->dev, flags, power_domain->id, + pstate); + if (ret) { + dev_err(power_domain->dev, "failed to set the state on (%d)\n", + ret); + return ret; + } + + return 0; +} + +/** + * scmi_power_domain_off - Disable the power domain + * @power_domain: Power domain + * + * Turn off the power domain. + * + * Return: 0 on success, error code on failure + */ +static int scmi_power_domain_off(struct power_domain *power_domain) +{ + struct scmi_power_domain_priv *priv = dev_get_priv(power_domain->dev); + u32 flags, pstate; + int ret; + + if (power_domain->id > priv->num_pwdoms) + return -EINVAL; + + if (async_is_supported(priv->prop[power_domain->id].attributes)) + flags = SCMI_PWD_SET_FLAGS_ASYNC; + else + flags = 0; + + /* OFF */ + pstate = SCMI_PWD_PSTATE_TYPE_LOST; + + ret = scmi_pwd_state_set(power_domain->dev, flags, power_domain->id, + pstate); + if (ret) { + dev_err(power_domain->dev, "failed to set the state off (%d)\n", + ret); + return ret; + } + + return 0; +} + +/** + * scmi_power_domain_probe - Probe the power domain + * @dev: Power domain device + * + * Probe the power domain and initialize the properties. + * + * Return: 0 on success, error code on failure + */ +static int scmi_power_domain_probe(struct udevice *dev) +{ + struct scmi_power_domain_priv *priv = dev_get_priv(dev); + u32 version; + int i, ret; + + ret = devm_scmi_of_get_channel(dev); + if (ret) { + dev_err(dev, "failed to get channel (%d)\n", ret); + return ret; + } + + ret = scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_POWER_DOMAIN, + &version); + + ret = scmi_pwd_protocol_attrs(dev, &priv->num_pwdoms, &priv->stats_addr, + &priv->stats_len); + if (ret) { + dev_err(dev, "failed to get protocol attributes (%d)\n", ret); + return ret; + } + + priv->prop = calloc(sizeof(*priv->prop), priv->num_pwdoms); + if (!priv->prop) + return -ENOMEM; + + for (i = 0; i < priv->num_pwdoms; i++) { + ret = scmi_pwd_attrs(dev, i, &priv->prop[i].attributes, + &priv->prop[i].name); + if (ret) { + dev_err(dev, "failed to get attributes pwd:%d (%d)\n", + i, ret); + for (i--; i >= 0; i--) + free(priv->prop[i].name); + free(priv->prop); + + return ret; + } + } + + return 0; +} + +struct power_domain_ops scmi_power_domain_ops = { + .on = scmi_power_domain_on, + .off = scmi_power_domain_off, +}; + +U_BOOT_DRIVER(scmi_power_domain) = { + .name = "scmi_power_domain", + .id = UCLASS_POWER_DOMAIN, + .ops = &scmi_power_domain_ops, + .probe = scmi_power_domain_probe, + .priv_auto = sizeof(struct scmi_power_domain_priv), +}; diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index 9e7151307c8..b34c982f4f5 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -2,7 +2,7 @@ /* * Texas Instruments power domain driver * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ * Tero Kristo <t-kristo@ti.com> */ diff --git a/drivers/power/domain/ti-sci-power-domain.c b/drivers/power/domain/ti-sci-power-domain.c index 0140e5e5217..8d6abe13dbc 100644 --- a/drivers/power/domain/ti-sci-power-domain.c +++ b/drivers/power/domain/ti-sci-power-domain.c @@ -2,7 +2,7 @@ /* * Texas Instruments System Control Interface (TI SCI) power domain driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Andreas Dannenberg <dannenberg@ti.com> * * Loosely based on Linux kernel ti_sci_pm_domains.c... diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 4a6f0ce093a..454a6e0cf87 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -184,6 +184,15 @@ config SPL_DM_PMIC_PFUZE100 This config enables implementation of driver-model pmic uclass features for PMIC PFUZE100 in SPL. The driver implements read/write operations. +config DM_PMIC_MAX77663 + bool "Enable Driver Model for PMIC MAX77663" + ---help--- + This config enables implementation of driver-model pmic uclass features + for PMIC MAX77663. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 4 DC-to-DC Step-Down (SD) Regulators, 9 Low-Dropout Linear (LDO) Regulators, + 8 GPIOs, Real-Time Clock (RTC) and more with I2C Compatible Interface. + config DM_PMIC_MAX77686 bool "Enable Driver Model for PMIC MAX77686" ---help--- @@ -342,6 +351,17 @@ config DM_PMIC_TPS65910 DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO pmic children. +config DM_PMIC_TPS80031 + bool "Enable driver for Texas Instruments TPS80031/TPS80032 PMIC" + ---help--- + This config enables implementation of driver-model pmic uclass features + for TPS80031/TPS80032 PMICs. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 5 Buck Converters refered as Switched-mode power supply (SMPS), 11 General- + Purpose Low-Dropout Voltage Regulators (LDO), USB OTG Module, Real-Time + Clock (RTC) with Timer and Alarm Wake-Up, Two Digital PWM Outputs and more + with I2C Compatible Interface. PMIC occupies 4 I2C addresses. + config PMIC_STPMIC1 bool "Enable support for STMicroelectronics STPMIC1 PMIC" depends on DM_I2C diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 0b3b3d62d0e..55ee614364b 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o obj-$(CONFIG_$(SPL_)DM_PMIC_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o +obj-$(CONFIG_$(SPL_)DM_PMIC_MAX77663) += max77663.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o @@ -26,6 +27,7 @@ obj-$(CONFIG_$(SPL_)PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o +obj-$(CONFIG_$(SPL_)DM_PMIC_TPS80031) += tps80031.o obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c new file mode 100644 index 00000000000..68c3cbbc646 --- /dev/null +++ b/drivers/power/pmic/max77663.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <dm/lists.h> +#include <power/pmic.h> +#include <power/max77663.h> + +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "ldo", .driver = MAX77663_LDO_DRIVER }, + { .prefix = "sd", .driver = MAX77663_SD_DRIVER }, + { }, +}; + +static int max77663_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) { + log_debug("write error to device: %p register: %#x!\n", dev, reg); + return ret; + } + + return 0; +} + +static int max77663_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) { + log_debug("read error from device: %p register: %#x!\n", dev, reg); + return ret; + } + + return 0; +} + +static int max77663_bind(struct udevice *dev) +{ + ofnode regulators_node; + int children, ret; + + if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) { + ret = device_bind_driver(dev, MAX77663_RST_DRIVER, + "sysreset", NULL); + if (ret) { + log_err("cannot bind SYSRESET (ret = %d)\n", ret); + return ret; + } + } + + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + log_err("%s regulators subnode not found!\n", dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + log_err("%s - no child found\n", dev->name); + + /* Always return success for this device */ + return 0; +} + +static struct dm_pmic_ops max77663_ops = { + .read = max77663_read, + .write = max77663_write, +}; + +static const struct udevice_id max77663_ids[] = { + { .compatible = "maxim,max77663" }, + { } +}; + +U_BOOT_DRIVER(pmic_max77663) = { + .name = "max77663_pmic", + .id = UCLASS_PMIC, + .of_match = max77663_ids, + .bind = max77663_bind, + .ops = &max77663_ops, +}; diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index eb83c88d564..32f2a938b28 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -8,13 +8,13 @@ #include <fdtdec.h> #include <errno.h> #include <dm.h> +#include <dm/lists.h> #include <i2c.h> #include <log.h> #include <linux/printk.h> #include <power/pmic.h> #include <power/regulator.h> #include <power/palmas.h> -#include <dm/device.h> static const struct pmic_child_info pmic_children_info[] = { { .prefix = "ldo", .driver = PALMAS_LDO_DRIVER }, @@ -47,7 +47,16 @@ static int palmas_bind(struct udevice *dev) { ofnode pmic_node = ofnode_null(), regulators_node; ofnode subnode; - int children; + int children, ret; + + if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) { + ret = device_bind_driver(dev, PALMAS_RST_DRIVER, + "sysreset", NULL); + if (ret) { + log_err("cannot bind SYSRESET (ret = %d)\n", ret); + return ret; + } + } dev_for_each_subnode(subnode, dev) { const char *name; @@ -81,6 +90,24 @@ static int palmas_bind(struct udevice *dev) return 0; } +static int palmas_probe(struct udevice *dev) +{ + struct dm_i2c_chip *chip = dev_get_parent_plat(dev); + struct palmas_priv *priv = dev_get_priv(dev); + struct udevice *bus = dev_get_parent(dev); + u32 chip2_addr = chip->chip_addr + 1; + int ret; + + /* Palmas PMIC is multi chip and chips are located in a row */ + ret = i2c_get_chip(bus, chip2_addr, 1, &priv->chip2); + if (ret) { + log_err("cannot get second PMIC I2C chip (err %d)\n", ret); + return ret; + } + + return 0; +} + static struct dm_pmic_ops palmas_ops = { .read = palmas_read, .write = palmas_write, @@ -88,6 +115,7 @@ static struct dm_pmic_ops palmas_ops = { static const struct udevice_id palmas_ids[] = { { .compatible = "ti,tps659038", .data = TPS659038 }, + { .compatible = "ti,tps65913" , .data = TPS659038 }, { .compatible = "ti,tps65917" , .data = TPS65917 }, { } }; @@ -97,5 +125,7 @@ U_BOOT_DRIVER(pmic_palmas) = { .id = UCLASS_PMIC, .of_match = palmas_ids, .bind = palmas_bind, + .probe = palmas_probe, .ops = &palmas_ops, + .priv_auto = sizeof(struct palmas_priv), }; diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c index 59190d6f672..6426d1488a5 100644 --- a/drivers/power/pmic/pmic_tps62362.c +++ b/drivers/power/pmic/pmic_tps62362.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com + * (C) Copyright 2014 Texas Instruments Incorporated - https://www.ti.com * Author: Felipe Balbi <balbi@ti.com> */ diff --git a/drivers/power/pmic/pmic_tps65910_dm.c b/drivers/power/pmic/pmic_tps65910_dm.c index 8ead1db802a..ecf836eb0e6 100644 --- a/drivers/power/pmic/pmic_tps65910_dm.c +++ b/drivers/power/pmic/pmic_tps65910_dm.c @@ -5,6 +5,7 @@ #include <common.h> #include <dm.h> +#include <dm/lists.h> #include <i2c.h> #include <log.h> #include <linux/printk.h> @@ -12,13 +13,19 @@ #include <power/regulator.h> #include <power/tps65910_pmic.h> -static const struct pmic_child_info pmic_children_info[] = { +static const struct pmic_child_info tps65910_children_info[] = { { .prefix = "ldo_", .driver = TPS65910_LDO_DRIVER }, { .prefix = "buck_", .driver = TPS65910_BUCK_DRIVER }, { .prefix = "boost_", .driver = TPS65910_BOOST_DRIVER }, { }, }; +static const struct pmic_child_info tps65911_children_info[] = { + { .prefix = "ldo", .driver = TPS65911_LDO_DRIVER }, + { .prefix = "vdd", .driver = TPS65911_VDD_DRIVER }, + { }, +}; + static int pmic_tps65910_reg_count(struct udevice *dev) { return TPS65910_NUM_REGS; @@ -50,8 +57,19 @@ static int pmic_tps65910_read(struct udevice *dev, uint reg, u8 *buffer, static int pmic_tps65910_bind(struct udevice *dev) { + const struct pmic_child_info *tps6591x_children_info = + (struct pmic_child_info *)dev_get_driver_data(dev); ofnode regulators_node; - int children; + int children, ret; + + if (IS_ENABLED(CONFIG_SYSRESET_TPS65910)) { + ret = device_bind_driver(dev, TPS65910_RST_DRIVER, + "sysreset", NULL); + if (ret) { + log_err("cannot bind SYSRESET (ret = %d)\n", ret); + return ret; + } + } regulators_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regulators_node)) { @@ -59,7 +77,7 @@ static int pmic_tps65910_bind(struct udevice *dev) return -EINVAL; } - children = pmic_bind_children(dev, regulators_node, pmic_children_info); + children = pmic_bind_children(dev, regulators_node, tps6591x_children_info); if (!children) debug("%s has no children (regulators)\n", dev->name); @@ -83,7 +101,8 @@ static struct dm_pmic_ops pmic_tps65910_ops = { }; static const struct udevice_id pmic_tps65910_match[] = { - { .compatible = "ti,tps65910" }, + { .compatible = "ti,tps65910", .data = (ulong)&tps65910_children_info }, + { .compatible = "ti,tps65911", .data = (ulong)&tps65911_children_info }, { /* sentinel */ } }; diff --git a/drivers/power/pmic/tps80031.c b/drivers/power/pmic/tps80031.c new file mode 100644 index 00000000000..a2f935b0c6d --- /dev/null +++ b/drivers/power/pmic/tps80031.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <dm/lists.h> +#include <power/pmic.h> +#include <power/tps80031.h> + +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "ldo", .driver = TPS80031_LDO_DRIVER }, + { .prefix = "smps", .driver = TPS80031_SMPS_DRIVER }, + { }, +}; + +static int tps80031_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) { + log_debug("write error to device: %p register: %#x!\n", dev, reg); + return ret; + } + + return 0; +} + +static int tps80031_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) { + log_debug("read error from device: %p register: %#x!\n", dev, reg); + return ret; + } + + return 0; +} + +static int tps80031_bind(struct udevice *dev) +{ + ofnode regulators_node; + int children, ret; + + if (IS_ENABLED(CONFIG_SYSRESET_TPS80031)) { + ret = device_bind_driver(dev, TPS80031_RST_DRIVER, + "sysreset", NULL); + if (ret) { + log_err("cannot bind SYSRESET (ret = %d)\n", ret); + return ret; + } + } + + regulators_node = dev_read_subnode(dev, "regulators"); + if (!ofnode_valid(regulators_node)) { + log_err("%s regulators subnode not found!\n", dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + log_err("%s - no child found\n", dev->name); + + /* Always return success for this device */ + return 0; +} + +static struct dm_pmic_ops tps80031_ops = { + .read = tps80031_read, + .write = tps80031_write, +}; + +static const struct udevice_id tps80031_ids[] = { + { .compatible = "ti,tps80031" }, + { .compatible = "ti,tps80032" }, + { } +}; + +U_BOOT_DRIVER(pmic_tps80031) = { + .name = "tps80031_pmic", + .id = UCLASS_PMIC, + .of_match = tps80031_ids, + .bind = tps80031_bind, + .ops = &tps80031_ops, +}; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index eb5aa38c1cc..102ec7bc5f8 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -141,6 +141,15 @@ config SPL_REGULATOR_PWM This config enables implementation of driver-model regulator uclass features for PWM regulators in SPL. +config DM_REGULATOR_MAX77663 + bool "Enable Driver Model for REGULATOR MAX77663" + depends on DM_REGULATOR && DM_PMIC_MAX77663 + ---help--- + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX77663. The driver supports both DC-to-DC + Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators + found in MAX77663 PMIC and implements get/set api for value and enable. + config DM_REGULATOR_MAX77686 bool "Enable Driver Model for REGULATOR MAX77686" depends on DM_REGULATOR && DM_PMIC_MAX77686 @@ -337,6 +346,17 @@ config DM_REGULATOR_TPS65910 regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements the get/set api for value and enable. +config DM_REGULATOR_TPS65911 + bool "Enable driver for TPS65911 PMIC regulators" + depends on DM_PMIC_TPS65910 + ---help--- + This config enables implementation of driver-model regulator + uclass features for the TPS65911 PMIC. The driver supports Step-Down + DC-DC Converters for Processor Cores (VDD1 and VDD2), Step-Down DC-DC + Converter for I/O Power (VIO), Controller for External FETs (VDDCtrl) + and LDO Voltage Regulators found in TPS65911 PMIC and implements + get/set api for value and enable. + config DM_REGULATOR_TPS62360 bool "Enable driver for TPS6236x Power Regulator" depends on DM_REGULATOR @@ -347,6 +367,14 @@ config DM_REGULATOR_TPS62360 implements the get/set api for value only, as the power line is always on. +config DM_REGULATOR_TPS80031 + bool "Enable driver for TPS80031/TPS80032 PMIC regulators" + depends on DM_PMIC_TPS80031 + ---help--- + This enables implementation of driver-model regulator uclass + features for TPS80031/TPS80032 PMICs. The driver implements + get/set api for: value and enable. + config DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators" depends on DM_REGULATOR && PMIC_STPMIC1 diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index d9e0cd5949c..f79932d8330 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_MAX77663) += max77663_regulator.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o @@ -31,7 +32,9 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o obj-$(CONFIG_DM_REGULATOR_TPS65910) += tps65910_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS65911) += tps65911_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_TPS80031) += tps80031_regulator.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o diff --git a/drivers/power/regulator/max77663_regulator.c b/drivers/power/regulator/max77663_regulator.c new file mode 100644 index 00000000000..ea4b7c63e5a --- /dev/null +++ b/drivers/power/regulator/max77663_regulator.c @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/max77663.h> + +/* fist row is control registers, second is voltage registers */ +static const char max77663_sd_reg[][MAX77663_SD_NUM] = { + { 0x1d, 0x1e, 0x1f, 0x20, 0x21 }, + { 0x16, 0x17, 0x18, 0x19, 0x2a }, +}; + +static const char max77663_ldo_reg[MAX77663_LDO_NUM] = { + 0x23, 0x25, 0x27, 0x29, 0x2b, 0x2d, 0x2f, 0x31, 0x33 +}; + +static int max77663_sd_enable(struct udevice *dev, int op, bool *enable) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->ctrl_reg; + int val, ret; + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + if (val & SD_STATUS_MASK) + *enable = true; + else + *enable = false; + + return 0; + } else if (op == PMIC_OP_SET) { + val &= ~SD_STATUS_MASK; + + if (*enable) + val |= SD_STATUS_MASK; + + ret = pmic_reg_write(dev->parent, adr, val); + if (ret) + return ret; + } + + return 0; +} + +/** + * max77663_*_volt2hex() - convert voltage in uV into + * applicable to register hex value + * + * @idx: regulator index + * @uV: voltage in uV + * + * Return: voltage in hex on success, -ve on failure + */ +static int max77663_sd_volt2hex(int idx, int uV) +{ + switch (idx) { + case 0: + /* SD0 has max voltage 1.4V */ + if (uV > SD0_VOLT_MAX) + return -EINVAL; + break; + case 1: + /* SD1 has max voltage 1.55V */ + if (uV > SD1_VOLT_MAX) + return -EINVAL; + break; + default: + /* SD2 and SD3 have max voltage 3.79V */ + if (uV > SD_VOLT_MAX) + return -EINVAL; + break; + }; + + if (uV < SD_VOLT_MIN) + uV = SD_VOLT_MIN; + + return (uV - SD_VOLT_BASE) / 12500; +} + +/** + * max77663_*_hex2volt() - convert register hex value into + * actual voltage in uV + * + * @idx: regulator index + * @hex: hex value of register + * + * Return: voltage in uV on success, -ve on failure + */ +static int max77663_sd_hex2volt(int idx, int hex) +{ + switch (idx) { + case 0: + /* SD0 has max voltage 1.4V */ + if (hex > SD0_VOLT_MAX_HEX) + return -EINVAL; + break; + case 1: + /* SD1 has max voltage 1.55V */ + if (hex > SD1_VOLT_MAX_HEX) + return -EINVAL; + break; + default: + /* SD2 and SD3 have max voltage 3.79V */ + if (hex > SD_VOLT_MAX_HEX) + return -EINVAL; + break; + }; + + if (hex < SD_VOLT_MIN_HEX) + hex = SD_VOLT_MIN_HEX; + + return SD_VOLT_BASE + hex * 12500; +} + +static int max77663_sd_val(struct udevice *dev, int op, int *uV) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->volt_reg; + int idx = dev->driver_data; + int hex, ret; + + if (op == PMIC_OP_GET) { + hex = pmic_reg_read(dev->parent, adr); + if (hex < 0) + return hex; + + *uV = 0; + + ret = max77663_sd_hex2volt(idx, hex); + if (ret < 0) + return ret; + *uV = ret; + + return 0; + } + + /* SD regulators use entire register for voltage */ + hex = max77663_sd_volt2hex(idx, *uV); + if (hex < 0) + return hex; + + return pmic_reg_write(dev->parent, adr, hex); +} + +static int max77663_sd_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + int idx = dev->driver_data; + + uc_pdata->type = REGULATOR_TYPE_BUCK; + uc_pdata->ctrl_reg = max77663_sd_reg[0][idx]; + uc_pdata->volt_reg = max77663_sd_reg[1][idx]; + + return 0; +} + +static int sd_get_value(struct udevice *dev) +{ + int uV; + int ret; + + ret = max77663_sd_val(dev, PMIC_OP_GET, &uV); + if (ret) + return ret; + + return uV; +} + +static int sd_set_value(struct udevice *dev, int uV) +{ + return max77663_sd_val(dev, PMIC_OP_SET, &uV); +} + +static int sd_get_enable(struct udevice *dev) +{ + bool enable = false; + int ret; + + ret = max77663_sd_enable(dev, PMIC_OP_GET, &enable); + if (ret) + return ret; + + return enable; +} + +static int sd_set_enable(struct udevice *dev, bool enable) +{ + return max77663_sd_enable(dev, PMIC_OP_SET, &enable); +} + +static const struct dm_regulator_ops max77663_sd_ops = { + .get_value = sd_get_value, + .set_value = sd_set_value, + .get_enable = sd_get_enable, + .set_enable = sd_set_enable, +}; + +U_BOOT_DRIVER(max77663_sd) = { + .name = MAX77663_SD_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &max77663_sd_ops, + .probe = max77663_sd_probe, +}; + +static int max77663_ldo_enable(struct udevice *dev, int op, bool *enable) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->ctrl_reg; + int val, ret; + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + if (val & LDO_STATUS_MASK) + *enable = true; + else + *enable = false; + + return 0; + } else if (op == PMIC_OP_SET) { + val &= ~LDO_STATUS_MASK; + + if (*enable) + val |= LDO_STATUS_MASK; + + ret = pmic_reg_write(dev->parent, adr, val); + if (ret) + return ret; + } + + return 0; +} + +static int max77663_ldo_volt2hex(int idx, int uV) +{ + switch (idx) { + case 0: + case 1: + if (uV > LDO01_VOLT_MAX) + return -EINVAL; + + return (uV - LDO_VOLT_BASE) / 25000; + case 4: + if (uV > LDO4_VOLT_MAX) + return -EINVAL; + + return (uV - LDO_VOLT_BASE) / 12500; + default: + if (uV > LDO_VOLT_MAX) + return -EINVAL; + + return (uV - LDO_VOLT_BASE) / 50000; + }; +} + +static int max77663_ldo_hex2volt(int idx, int hex) +{ + if (hex > LDO_VOLT_MAX_HEX) + return -EINVAL; + + switch (idx) { + case 0: + case 1: + return (hex * 25000) + LDO_VOLT_BASE; + case 4: + return (hex * 12500) + LDO_VOLT_BASE; + default: + return (hex * 50000) + LDO_VOLT_BASE; + }; +} + +static int max77663_ldo_val(struct udevice *dev, int op, int *uV) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->ctrl_reg; + int idx = dev->driver_data; + int hex, val, ret; + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + *uV = 0; + + ret = max77663_ldo_hex2volt(idx, val & LDO_VOLT_MASK); + if (ret < 0) + return ret; + + *uV = ret; + return 0; + } + + hex = max77663_ldo_volt2hex(idx, *uV); + if (hex < 0) + return hex; + + val &= ~LDO_VOLT_MASK; + + return pmic_reg_write(dev->parent, adr, val | hex); +} + +static int max77663_ldo_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + int idx = dev->driver_data; + + uc_pdata->type = REGULATOR_TYPE_LDO; + uc_pdata->ctrl_reg = max77663_ldo_reg[idx]; + + return 0; +} + +static int ldo_get_value(struct udevice *dev) +{ + int uV; + int ret; + + ret = max77663_ldo_val(dev, PMIC_OP_GET, &uV); + if (ret) + return ret; + + return uV; +} + +static int ldo_set_value(struct udevice *dev, int uV) +{ + return max77663_ldo_val(dev, PMIC_OP_SET, &uV); +} + +static int ldo_get_enable(struct udevice *dev) +{ + bool enable = false; + int ret; + + ret = max77663_ldo_enable(dev, PMIC_OP_GET, &enable); + if (ret) + return ret; + + return enable; +} + +static int ldo_set_enable(struct udevice *dev, bool enable) +{ + return max77663_ldo_enable(dev, PMIC_OP_SET, &enable); +} + +static const struct dm_regulator_ops max77663_ldo_ops = { + .get_value = ldo_get_value, + .set_value = ldo_set_value, + .get_enable = ldo_get_enable, + .set_enable = ldo_set_enable, +}; + +U_BOOT_DRIVER(max77663_ldo) = { + .name = MAX77663_LDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &max77663_ldo_ops, + .probe = max77663_ldo_probe, +}; diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c index 3c4eb83be77..d615e947340 100644 --- a/drivers/power/regulator/palmas_regulator.c +++ b/drivers/power/regulator/palmas_regulator.c @@ -301,19 +301,23 @@ static int palmas_ldo_probe(struct udevice *dev) uc_pdata->type = REGULATOR_TYPE_LDO; - if (dev->driver_data) { + /* check for ldoln and ldousb cases */ + if (!strcmp("ldoln", dev->name)) { + uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9]; + uc_pdata->volt_reg = palmas_ldo_volt[type][9]; + return 0; + } + + if (!strcmp("ldousb", dev->name)) { + uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10]; + uc_pdata->volt_reg = palmas_ldo_volt[type][10]; + return 0; + } + + if (dev->driver_data > 0) { u8 idx = dev->driver_data - 1; uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][idx]; uc_pdata->volt_reg = palmas_ldo_volt[type][idx]; - } else { - /* check for ldoln and ldousb cases */ - if (!strcmp("ldoln", dev->name)) { - uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9]; - uc_pdata->volt_reg = palmas_ldo_volt[type][9]; - } else if (!strcmp("ldousb", dev->name)) { - uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10]; - uc_pdata->volt_reg = palmas_ldo_volt[type][10]; - } } return 0; diff --git a/drivers/power/regulator/tps62360_regulator.c b/drivers/power/regulator/tps62360_regulator.c index b9f4504539e..7014b1982d0 100644 --- a/drivers/power/regulator/tps62360_regulator.c +++ b/drivers/power/regulator/tps62360_regulator.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Tero Kristo <t-kristo@ti.com> */ diff --git a/drivers/power/regulator/tps65911_regulator.c b/drivers/power/regulator/tps65911_regulator.c new file mode 100644 index 00000000000..2b5acdfcbb0 --- /dev/null +++ b/drivers/power/regulator/tps65911_regulator.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/tps65910_pmic.h> + +/* fist row is control registers, second is voltage registers */ +static const char tps65911_vdd_reg[][TPS65911_VDD_NUM] = { + { TPS65911_REG_VDD1, TPS65911_REG_VDD2, + TPS65911_REG_VDDCTRL, TPS65911_REG_VIO }, + { TPS65911_REG_VDD1_OP, TPS65911_REG_VDD2_OP, + TPS65911_REG_VDDCTRL_OP, 0x00 }, +}; + +static const char tps65911_ldo_reg[TPS65911_LDO_NUM] = { + TPS65911_REG_LDO1, TPS65911_REG_LDO2, TPS65911_REG_LDO3, + TPS65911_REG_LDO4, TPS65911_REG_LDO5, TPS65911_REG_LDO6, + TPS65911_REG_LDO7, TPS65911_REG_LDO8 +}; + +static int tps65911_regulator_enable(struct udevice *dev, int op, bool *enable) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->ctrl_reg; + int val, ret; + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + if (val & TPS65910_SUPPLY_STATE_ON) + *enable = true; + else + *enable = false; + + return 0; + } else if (op == PMIC_OP_SET) { + val &= ~TPS65910_SUPPLY_STATE_MASK; + + if (*enable) + val |= TPS65910_SUPPLY_STATE_ON; + + ret = pmic_reg_write(dev->parent, adr, val); + if (ret) + return ret; + } + + return 0; +} + +static int tps65911_get_enable(struct udevice *dev) +{ + bool enable = false; + int ret; + + ret = tps65911_regulator_enable(dev, PMIC_OP_GET, &enable); + if (ret) + return ret; + + return enable; +} + +static int tps65911_set_enable(struct udevice *dev, bool enable) +{ + return tps65911_regulator_enable(dev, PMIC_OP_SET, &enable); +} + +/** + * tps65911_vdd_volt2hex() - convert voltage in uV into + * applicable to register hex value + * + * @uV: voltage in uV + * + * Return: voltage in hex on success, -ve on failure + */ +static int tps65911_vdd_volt2hex(int uV) +{ + if (uV > TPS65911_VDD_VOLT_MAX) + return -EINVAL; + + if (uV < TPS65911_VDD_VOLT_MIN) + uV = TPS65911_VDD_VOLT_MIN; + + return (uV - TPS65911_VDD_VOLT_BASE) / 12500; +} + +/** + * tps65911_vdd_hex2volt() - convert register hex value into + * actual voltage in uV + * + * @hex: hex value of register + * + * Return: voltage in uV on success, -ve on failure + */ +static int tps65911_vdd_hex2volt(int hex) +{ + if (hex > TPS65910_VDD_SEL_MAX) + return -EINVAL; + + if (hex < TPS65910_VDD_SEL_MIN) + hex = TPS65910_VDD_SEL_MIN; + + return TPS65911_VDD_VOLT_BASE + hex * 12500; +} + +static int tps65911_vio_range[4] = { + 1500000, 1800000, 2500000, 3300000 +}; + +static int tps65911_vio_val(struct udevice *dev, int op, int *uV) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->volt_reg; + int i, val; + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + *uV = 0; + + val &= TPS65910_SEL_MASK; + + *uV = tps65911_vio_range[val >> 2]; + + return 0; + } + + val &= ~TPS65910_SEL_MASK; + + for (i = 0; i < ARRAY_SIZE(tps65911_vio_range); i++) + if (*uV <= tps65911_vio_range[i]) + break; + + return pmic_reg_write(dev->parent, adr, val | i << 2); +} + +static int tps65911_vdd_val(struct udevice *dev, int op, int *uV) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->volt_reg; + int val, ret; + + /* in case vdd is vio */ + if (!adr) + return tps65911_vio_val(dev, op, uV); + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + *uV = 0; + + ret = tps65911_vdd_hex2volt(val); + if (ret < 0) + return ret; + + *uV = ret; + return 0; + } + + val = tps65911_vdd_volt2hex(*uV); + if (val < 0) + return val; + + return pmic_reg_write(dev->parent, adr, val); +} + +static int tps65911_vdd_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + + uc_pdata->type = REGULATOR_TYPE_BUCK; + + /* check for vddctrl and vddio cases */ + if (!strcmp("vddctrl", dev->name)) { + uc_pdata->ctrl_reg = tps65911_vdd_reg[0][2]; + uc_pdata->volt_reg = tps65911_vdd_reg[1][2]; + return 0; + } + + if (!strcmp("vddio", dev->name)) { + uc_pdata->ctrl_reg = tps65911_vdd_reg[0][3]; + uc_pdata->volt_reg = tps65911_vdd_reg[1][3]; + return 0; + } + + if (dev->driver_data > 0) { + u8 idx = dev->driver_data - 1; + + uc_pdata->ctrl_reg = tps65911_vdd_reg[0][idx]; + uc_pdata->volt_reg = tps65911_vdd_reg[1][idx]; + } + + return 0; +} + +static int vdd_get_value(struct udevice *dev) +{ + int uV; + int ret; + + ret = tps65911_vdd_val(dev, PMIC_OP_GET, &uV); + if (ret) + return ret; + + return uV; +} + +static int vdd_set_value(struct udevice *dev, int uV) +{ + return tps65911_vdd_val(dev, PMIC_OP_SET, &uV); +} + +static const struct dm_regulator_ops tps65911_vdd_ops = { + .get_value = vdd_get_value, + .set_value = vdd_set_value, + .get_enable = tps65911_get_enable, + .set_enable = tps65911_set_enable, +}; + +U_BOOT_DRIVER(tps65911_vdd) = { + .name = TPS65911_VDD_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &tps65911_vdd_ops, + .probe = tps65911_vdd_probe, +}; + +/** + * tps65911_ldo_volt2hex() - convert voltage in uV into + * applicable to register hex value + * + * @idx: regulator index + * @uV: voltage in uV + * + * Return: voltage in hex on success, -ve on failure + */ +static int tps65911_ldo_volt2hex(int idx, int uV) +{ + int step; + + if (uV > TPS65911_LDO_VOLT_MAX) + return -EINVAL; + + if (uV < TPS65911_LDO_VOLT_BASE) + uV = TPS65911_LDO_VOLT_BASE; + + switch (idx) { + case 1: + case 2: + case 4: + step = TPS65911_LDO124_VOLT_STEP; + break; + case 3: + case 5: + case 6: + case 7: + case 8: + step = TPS65911_LDO358_VOLT_STEP; + break; + default: + return -EINVAL; + }; + + return ((uV - TPS65911_LDO_VOLT_BASE) / step) << 2; +} + +/** + * tps65911_ldo_hex2volt() - convert register hex value into + * actual voltage in uV + * + * @idx: regulator index + * @hex: hex value of register + * + * Return: voltage in uV on success, -ve on failure + */ +static int tps65911_ldo_hex2volt(int idx, int hex) +{ + int step; + + switch (idx) { + case 1: + case 2: + case 4: + if (hex > TPS65911_LDO124_VOLT_MAX_HEX) + return -EINVAL; + + step = TPS65911_LDO124_VOLT_STEP; + break; + case 3: + case 5: + case 6: + case 7: + case 8: + if (hex > TPS65911_LDO358_VOLT_MAX_HEX) + return -EINVAL; + + if (hex < TPS65911_LDO358_VOLT_MIN_HEX) + hex = TPS65911_LDO358_VOLT_MIN_HEX; + + step = TPS65911_LDO358_VOLT_STEP; + break; + default: + return -EINVAL; + }; + + return TPS65911_LDO_VOLT_BASE + hex * step; +} + +static int tps65911_ldo_val(struct udevice *dev, int op, int *uV) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->ctrl_reg; + int idx = dev->driver_data; + int val, hex, ret; + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + *uV = 0; + val &= TPS65911_LDO_SEL_MASK; + + ret = tps65911_ldo_hex2volt(idx, val >> 2); + if (ret < 0) + return ret; + + *uV = ret; + return 0; + } + + hex = tps65911_ldo_volt2hex(idx, *uV); + if (hex < 0) + return hex; + + val &= ~TPS65911_LDO_SEL_MASK; + + return pmic_reg_write(dev->parent, adr, val | hex); +} + +static int tps65911_ldo_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u8 idx = dev->driver_data - 1; + + uc_pdata->type = REGULATOR_TYPE_LDO; + uc_pdata->ctrl_reg = tps65911_ldo_reg[idx]; + + return 0; +} + +static int ldo_get_value(struct udevice *dev) +{ + int uV; + int ret; + + ret = tps65911_ldo_val(dev, PMIC_OP_GET, &uV); + if (ret) + return ret; + + return uV; +} + +static int ldo_set_value(struct udevice *dev, int uV) +{ + return tps65911_ldo_val(dev, PMIC_OP_SET, &uV); +} + +static const struct dm_regulator_ops tps65911_ldo_ops = { + .get_value = ldo_get_value, + .set_value = ldo_set_value, + .get_enable = tps65911_get_enable, + .set_enable = tps65911_set_enable, +}; + +U_BOOT_DRIVER(tps65911_ldo) = { + .name = TPS65911_LDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &tps65911_ldo_ops, + .probe = tps65911_ldo_probe, +}; diff --git a/drivers/power/regulator/tps80031_regulator.c b/drivers/power/regulator/tps80031_regulator.c new file mode 100644 index 00000000000..87696662e11 --- /dev/null +++ b/drivers/power/regulator/tps80031_regulator.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <power/pmic.h> +#include <power/regulator.h> +#include <power/tps80031.h> + +static const char tps80031_smps_reg[][TPS80031_SMPS_NUM] = { + { 0x54, 0x5a, 0x66, 0x42, 0x48 }, + { 0x56, 0x5c, 0x68, 0x44, 0x4a }, + { BIT(3), BIT(4), BIT(6), BIT(0), BIT(1) }, +}; + +static const char tps80031_ldo_reg[][TPS80031_LDO_NUM] = { + { 0x9e, 0x86, 0x8e, 0x8a, 0x9a, 0x92, 0xa6, 0x96, 0xa2 }, + { 0x9f, 0x87, 0x8f, 0x8b, 0x9b, 0x93, 0xa7, 0x97, 0xa3 }, +}; + +static int tps80031_regulator_enable(struct udevice *dev, int op, bool *enable) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->ctrl_reg; + int val, ret; + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + if (val & REGULATOR_MODE_ON) + *enable = true; + else + *enable = false; + + return 0; + } else if (op == PMIC_OP_SET) { + val &= ~REGULATOR_STATUS_MASK; + + if (*enable) + val |= REGULATOR_MODE_ON; + + ret = pmic_reg_write(dev->parent, adr, val); + if (ret) + return ret; + } + + return 0; +} + +static int tps80031_get_enable(struct udevice *dev) +{ + bool enable = false; + int ret; + + ret = tps80031_regulator_enable(dev, PMIC_OP_GET, &enable); + if (ret) + return ret; + + return enable; +} + +static int tps80031_set_enable(struct udevice *dev, bool enable) +{ + return tps80031_regulator_enable(dev, PMIC_OP_SET, &enable); +} + +/** + * tps80031_ldo_volt2hex() - convert voltage in uV into + * applicable to register hex value + * + * @uV: voltage in uV + * + * Return: voltage in hex on success, -ve on failure + */ +static int tps80031_ldo_volt2hex(int uV) +{ + if (uV > LDO_VOLT_MAX) + return -EINVAL; + + if (uV < LDO_VOLT_MIN) + uV = LDO_VOLT_MIN; + + return DIV_ROUND_UP(uV - LDO_VOLT_BASE, 102000); +} + +/** + * tps80031_ldo_hex2volt() - convert register hex value into + * actual voltage in uV + * + * @hex: hex value of register + * + * Return: voltage in uV on success, -ve on failure + */ +static int tps80031_ldo_hex2volt(int hex) +{ + if (hex > LDO_VOLT_MAX_HEX) + return -EINVAL; + + if (hex < LDO_VOLT_MIN_HEX) + hex = LDO_VOLT_MIN_HEX; + + return LDO_VOLT_BASE + hex * 102000; +} + +static int tps80031_ldo_val(struct udevice *dev, int op, int *uV) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + u32 adr = uc_pdata->volt_reg; + int val, hex, ret; + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + *uV = 0; + + ret = tps80031_ldo_hex2volt(val & LDO_VOLT_MASK); + if (ret < 0) + return ret; + + *uV = ret; + return 0; + } + + hex = tps80031_ldo_volt2hex(*uV); + if (hex < 0) + return hex; + + val &= ~LDO_VOLT_MASK; + + return pmic_reg_write(dev->parent, adr, val | hex); +} + +static int tps80031_ldo_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + + uc_pdata->type = REGULATOR_TYPE_LDO; + + /* check for ldoln and ldousb cases */ + if (!strcmp("ldoln", dev->name)) { + uc_pdata->ctrl_reg = tps80031_ldo_reg[CTRL][7]; + uc_pdata->volt_reg = tps80031_ldo_reg[VOLT][7]; + return 0; + } + + if (!strcmp("ldousb", dev->name)) { + uc_pdata->ctrl_reg = tps80031_ldo_reg[CTRL][8]; + uc_pdata->volt_reg = tps80031_ldo_reg[VOLT][8]; + return 0; + } + + if (dev->driver_data > 0) { + u8 idx = dev->driver_data - 1; + + uc_pdata->ctrl_reg = tps80031_ldo_reg[CTRL][idx]; + uc_pdata->volt_reg = tps80031_ldo_reg[VOLT][idx]; + } + + return 0; +} + +static int ldo_get_value(struct udevice *dev) +{ + int uV; + int ret; + + ret = tps80031_ldo_val(dev, PMIC_OP_GET, &uV); + if (ret) + return ret; + + return uV; +} + +static int ldo_set_value(struct udevice *dev, int uV) +{ + return tps80031_ldo_val(dev, PMIC_OP_SET, &uV); +} + +static const struct dm_regulator_ops tps80031_ldo_ops = { + .get_value = ldo_get_value, + .set_value = ldo_set_value, + .get_enable = tps80031_get_enable, + .set_enable = tps80031_set_enable, +}; + +U_BOOT_DRIVER(tps80031_ldo) = { + .name = TPS80031_LDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &tps80031_ldo_ops, + .probe = tps80031_ldo_probe, +}; + +struct tps80031_smps_priv { + int flags; +}; + +/* DCDC voltages for the selector of 0x39 to 0x3F */ +static int tps80031_dcdc_voltages[5] = { + 1350000, 1500000, 1800000, 1900000, 2100000 +}; + +/** + * tps80031_smps_volt2hex() - convert voltage in uV into + * applicable to register hex value + * + * @base: base voltage in uV + * @uV: voltage in uV + * + * Return: voltage in hex on success, -ve on failure + */ +static int tps80031_smps_volt2hex(u32 base, int uV) +{ + int i; + + if (uV < base) + return 1; + + if (uV > SMPS_VOLT_LINEAR) { + for (i = 0; i < ARRAY_SIZE(tps80031_dcdc_voltages); i++) + if (uV <= tps80031_dcdc_voltages[i]) + break; + + return SMPS_VOLT_NLINEAR_HEX + i; + } + + return DIV_ROUND_UP(uV - base, 12500); +} + +/** + * tps80031_smps_hex2volt() - convert register hex value into + * actual voltage in uV + * + * @base: base voltage in uV + * @hex: hex value of register + * + * Return: voltage in uV on success, -ve on failure + */ +static int tps80031_smps_hex2volt(u32 base, int hex) +{ + if (!hex) + return 0; + + /* if reg value exceeds linear scale use table */ + if (hex > SMPS_VOLT_LINEAR_HEX) + return tps80031_dcdc_voltages[hex - SMPS_VOLT_LINEAR_HEX]; + else + return base + hex * 12500; +} + +static int tps80031_smps_val(struct udevice *dev, int op, int *uV) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + struct tps80031_smps_priv *priv = dev_get_priv(dev); + u32 adr = uc_pdata->volt_reg; + int base, val, hex, ret; + + /* If offset flag was set then base voltage is higher */ + if (priv->flags & TPS80031_OFFSET_FLAG) + base = SMPS_VOLT_BASE_OFFSET; + else + base = SMPS_VOLT_BASE; + + val = pmic_reg_read(dev->parent, adr); + if (val < 0) + return val; + + if (op == PMIC_OP_GET) { + *uV = 0; + + ret = tps80031_smps_hex2volt(base, val & SMPS_VOLT_MASK); + if (ret < 0) + return ret; + + *uV = ret; + return 0; + } + + hex = tps80031_smps_volt2hex(base, *uV); + if (hex < 0) + return hex; + + val &= ~SMPS_VOLT_MASK; + + return pmic_reg_write(dev->parent, adr, val | hex); +} + +static int tps80031_smps_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata = + dev_get_uclass_plat(dev); + struct tps80031_smps_priv *priv = dev_get_priv(dev); + int idx = dev->driver_data - 1; + int val; + + uc_pdata->type = REGULATOR_TYPE_BUCK; + + uc_pdata->ctrl_reg = tps80031_smps_reg[CTRL][idx]; + uc_pdata->volt_reg = tps80031_smps_reg[VOLT][idx]; + + /* Determine if smps regulator uses higher voltage */ + val = pmic_reg_read(dev->parent, TPS80031_SMPS_OFFSET); + if (val & tps80031_smps_reg[OFFSET][idx]) + priv->flags |= TPS80031_OFFSET_FLAG; + + return 0; +} + +static int smps_get_value(struct udevice *dev) +{ + int uV; + int ret; + + ret = tps80031_smps_val(dev, PMIC_OP_GET, &uV); + if (ret) + return ret; + + return uV; +} + +static int smps_set_value(struct udevice *dev, int uV) +{ + return tps80031_smps_val(dev, PMIC_OP_SET, &uV); +} + +static const struct dm_regulator_ops tps80031_smps_ops = { + .get_value = smps_get_value, + .set_value = smps_set_value, + .get_enable = tps80031_get_enable, + .set_enable = tps80031_set_enable, +}; + +U_BOOT_DRIVER(tps80031_smps) = { + .name = TPS80031_SMPS_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &tps80031_smps_ops, + .probe = tps80031_smps_probe, + .priv_auto = sizeof(struct tps80031_smps_priv), +}; diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c index 4a8a6a90bfc..cff8ffc8929 100644 --- a/drivers/ram/k3-am654-ddrss.c +++ b/drivers/ram/k3-am654-ddrss.c @@ -2,7 +2,7 @@ /* * Texas Instruments' AM654 DDRSS driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/drivers/ram/k3-am654-ddrss.h b/drivers/ram/k3-am654-ddrss.h index c87f186291e..9d03ae10750 100644 --- a/drivers/ram/k3-am654-ddrss.h +++ b/drivers/ram/k3-am654-ddrss.h @@ -2,7 +2,7 @@ /* * AM654: DDRSS Register definitions and structures. * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> * */ diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile index ba5d9a2f4d3..823d1887178 100644 --- a/drivers/ram/k3-ddrss/Makefile +++ b/drivers/ram/k3-ddrss/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2019-2022 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ # obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 5b6089e8526..a5c9b82cf1d 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -2,7 +2,7 @@ /* * Texas Instruments' K3 DDRSS driver * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 27e4a60ff5b..781de530aff 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2015 -# Texas Instruments Incorporated - http://www.ti.com/ +# Texas Instruments Incorporated - https://www.ti.com/ # menu "Remote Processor drivers" diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index fbe9c172bc0..e09ed1aa4d4 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2015 -# Texas Instruments Incorporated - http://www.ti.com/ +# Texas Instruments Incorporated - https://www.ti.com/ # obj-$(CONFIG_$(SPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers/remoteproc/ipu_rproc.c index b4a06bc955a..996e658e871 100644 --- a/drivers/remoteproc/ipu_rproc.c +++ b/drivers/remoteproc/ipu_rproc.c @@ -2,7 +2,7 @@ /* * IPU remoteproc driver for various SoCs * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Angela Stegmaier <angelabaker@ti.com> * Venkateswara Rao Mandela <venkat.mandela@ti.com> * Keerthy <j-keerthy@ti.com> diff --git a/drivers/remoteproc/k3_system_controller.c b/drivers/remoteproc/k3_system_controller.c index e2affe69c67..071de40fbd6 100644 --- a/drivers/remoteproc/k3_system_controller.c +++ b/drivers/remoteproc/k3_system_controller.c @@ -2,7 +2,7 @@ /* * Texas Instruments' K3 System Controller Driver * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 924070a76b5..6ec55e27d9d 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -2,7 +2,7 @@ /* * PRU-RTU remoteproc driver for various SoCs * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Keerthy <j-keerthy@ti.com> */ diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index ece534c3c0e..28b362c887a 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2015 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #define LOG_CATEGORY UCLASS_REMOTEPROC diff --git a/drivers/remoteproc/sandbox_testproc.c b/drivers/remoteproc/sandbox_testproc.c index d360cf3169f..f76f68ebeb4 100644 --- a/drivers/remoteproc/sandbox_testproc.c +++ b/drivers/remoteproc/sandbox_testproc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2015 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #define pr_fmt(fmt) "%s: " fmt, __func__ #include <common.h> diff --git a/drivers/remoteproc/ti_k3_arm64_rproc.c b/drivers/remoteproc/ti_k3_arm64_rproc.c index 99f11000dfb..767493c1383 100644 --- a/drivers/remoteproc/ti_k3_arm64_rproc.c +++ b/drivers/remoteproc/ti_k3_arm64_rproc.c @@ -2,7 +2,7 @@ /* * Texas Instruments' K3 ARM64 Remoteproc driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> * */ diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c index 1a2e9dd1f58..576de4bb26e 100644 --- a/drivers/remoteproc/ti_k3_dsp_rproc.c +++ b/drivers/remoteproc/ti_k3_dsp_rproc.c @@ -2,7 +2,7 @@ /* * Texas Instruments' K3 DSP Remoteproc driver * - * Copyright (C) 2018-2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> * Suman Anna <s-anna@ti.com> */ diff --git a/drivers/remoteproc/ti_power_proc.c b/drivers/remoteproc/ti_power_proc.c index 6887a3c8541..f55df4a9119 100644 --- a/drivers/remoteproc/ti_power_proc.c +++ b/drivers/remoteproc/ti_power_proc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2015-2016 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #define pr_fmt(fmt) "%s: " fmt, __func__ #include <common.h> diff --git a/drivers/remoteproc/ti_sci_proc.h b/drivers/remoteproc/ti_sci_proc.h index 36351da63fc..167a7143e83 100644 --- a/drivers/remoteproc/ti_sci_proc.h +++ b/drivers/remoteproc/ti_sci_proc.h @@ -2,7 +2,7 @@ /* * Texas Instruments TI-SCI Processor Controller Helper Functions * - * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> * Suman Anna <s-anna@ti.com> */ diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c index a9589d448dc..05101a94f9b 100644 --- a/drivers/reset/reset-dra7.c +++ b/drivers/reset/reset-dra7.c @@ -2,7 +2,7 @@ /* * Texas Instruments DRA7 reset driver * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Author: Keerthy <j-keerthy@ti.com> */ diff --git a/drivers/reset/reset-ti-sci.c b/drivers/reset/reset-ti-sci.c index f35332767b2..fd654a08f13 100644 --- a/drivers/reset/reset-ti-sci.c +++ b/drivers/reset/reset-ti-sci.c @@ -2,7 +2,7 @@ /* * Texas Instruments System Control Interface (TI SCI) reset driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Andreas Dannenberg <dannenberg@ti.com> * * Loosely based on Linux kernel reset-ti-sci.c... diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig index 994cc35b274..a89c8995682 100644 --- a/drivers/rng/Kconfig +++ b/drivers/rng/Kconfig @@ -48,6 +48,14 @@ config RNG_OPTEE accessible to normal world but reserved and used by the OP-TEE to avoid the weakness of a software PRNG. +config RNG_RISCV_ZKR + bool "RISC-V Zkr random number generator" + depends on RISCV_SMODE + help + This driver provides a Random Number Generator based on the + Zkr RISC-V ISA extension which provides an interface to an + NIST SP 800-90B or BSI AIS-31 compliant physical entropy source. + config RNG_STM32 bool "Enable random number generator for STM32" depends on ARCH_STM32 || ARCH_STM32MP @@ -91,4 +99,10 @@ config TPM_RNG functionality. Enable random number generator on TPM devices. +config RNG_JH7110 + bool "StarFive JH7110 Random Number Generator support" + depends on DM_RNG && STARFIVE_JH7110 + help + Enable True Random Number Generator in StarFive JH7110 SoCs. + endif diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile index 47b323e61ee..7e64c4cdfc3 100644 --- a/drivers/rng/Makefile +++ b/drivers/rng/Makefile @@ -10,8 +10,10 @@ obj-$(CONFIG_RNG_MSM) += msm_rng.o obj-$(CONFIG_RNG_NPCM) += npcm_rng.o obj-$(CONFIG_RNG_OPTEE) += optee_rng.o obj-$(CONFIG_RNG_STM32) += stm32_rng.o +obj-$(CONFIG_RNG_RISCV_ZKR) += riscv_zkr_rng.o obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o obj-$(CONFIG_TPM_RNG) += tpm_rng.o +obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c new file mode 100644 index 00000000000..eb21afe4e7c --- /dev/null +++ b/drivers/rng/jh7110_rng.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * TRNG driver for the StarFive JH7110 SoC + * + */ + +#include <clk.h> +#include <dm.h> +#include <reset.h> +#include <rng.h> +#include <asm/io.h> +#include <linux/iopoll.h> + +/* trng register offset */ +#define STARFIVE_CTRL 0x00 +#define STARFIVE_STAT 0x04 +#define STARFIVE_MODE 0x08 +#define STARFIVE_SMODE 0x0C +#define STARFIVE_IE 0x10 +#define STARFIVE_ISTAT 0x14 +#define STARFIVE_RAND0 0x20 +#define STARFIVE_RAND1 0x24 +#define STARFIVE_RAND2 0x28 +#define STARFIVE_RAND3 0x2C +#define STARFIVE_RAND4 0x30 +#define STARFIVE_RAND5 0x34 +#define STARFIVE_RAND6 0x38 +#define STARFIVE_RAND7 0x3C +#define STARFIVE_AUTO_RQSTS 0x60 +#define STARFIVE_AUTO_AGE 0x64 + +/* CTRL CMD */ +#define STARFIVE_CTRL_EXEC_NOP 0x0 +#define STARFIVE_CTRL_GENE_RANDNUM 0x1 +#define STARFIVE_CTRL_EXEC_RANDRESEED 0x2 + +/* STAT */ +#define STARFIVE_STAT_NONCE_MODE BIT(2) +#define STARFIVE_STAT_R256 BIT(3) +#define STARFIVE_STAT_MISSION_MODE BIT(8) +#define STARFIVE_STAT_SEEDED BIT(9) +#define STARFIVE_STAT_LAST_RESEED(x) ((x) << 16) +#define STARFIVE_STAT_SRVC_RQST BIT(27) +#define STARFIVE_STAT_RAND_GENERATING BIT(30) +#define STARFIVE_STAT_RAND_SEEDING BIT(31) +#define STARFIVE_STAT_RUNNING (STARFIVE_STAT_RAND_GENERATING | \ + STARFIVE_STAT_RAND_SEEDING) + +/* MODE */ +#define STARFIVE_MODE_R256 BIT(3) + +/* SMODE */ +#define STARFIVE_SMODE_NONCE_MODE BIT(2) +#define STARFIVE_SMODE_MISSION_MODE BIT(8) +#define STARFIVE_SMODE_MAX_REJECTS(x) ((x) << 16) + +/* IE */ +#define STARFIVE_IE_RAND_RDY_EN BIT(0) +#define STARFIVE_IE_SEED_DONE_EN BIT(1) +#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4) +#define STARFIVE_IE_GLBL_EN BIT(31) + +#define STARFIVE_IE_ALL (STARFIVE_IE_GLBL_EN | \ + STARFIVE_IE_RAND_RDY_EN | \ + STARFIVE_IE_SEED_DONE_EN | \ + STARFIVE_IE_LFSR_LOCKUP_EN) + +/* ISTAT */ +#define STARFIVE_ISTAT_RAND_RDY BIT(0) +#define STARFIVE_ISTAT_SEED_DONE BIT(1) +#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4) + +#define STARFIVE_RAND_LEN sizeof(u32) + +enum mode { + PRNG_128BIT, + PRNG_256BIT, +}; + +struct starfive_trng_plat { + void *base; + struct clk *hclk; + struct clk *ahb; + struct reset_ctl *rst; + u32 mode; +}; + +static inline int starfive_trng_wait_idle(struct starfive_trng_plat *trng) +{ + u32 stat; + + return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat, + !(stat & STARFIVE_STAT_RUNNING), + 100000); +} + +static inline void starfive_trng_irq_mask_clear(struct starfive_trng_plat *trng) +{ + /* clear register: ISTAT */ + u32 data = readl(trng->base + STARFIVE_ISTAT); + + writel(data, trng->base + STARFIVE_ISTAT); +} + +static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd) +{ + u32 stat, flg; + int ret; + + switch (cmd) { + case STARFIVE_CTRL_GENE_RANDNUM: + writel(cmd, trng->base + STARFIVE_CTRL); + flg = STARFIVE_ISTAT_RAND_RDY; + break; + case STARFIVE_CTRL_EXEC_RANDRESEED: + writel(cmd, trng->base + STARFIVE_CTRL); + flg = STARFIVE_ISTAT_SEED_DONE; + break; + default: + return -EINVAL; + } + + ret = readl_relaxed_poll_timeout(trng->base + STARFIVE_ISTAT, stat, + (stat & flg), 1000); + writel(flg, trng->base + STARFIVE_ISTAT); + + return ret; +} + +static int starfive_trng_read(struct udevice *dev, void *data, size_t len) +{ + struct starfive_trng_plat *trng = dev_get_plat(dev); + u8 *buffer = data; + int iter_mask; + + if (trng->mode == PRNG_256BIT) + iter_mask = 7; + else + iter_mask = 3; + + for (int i = 0; len; ++i, i &= iter_mask) { + u32 val; + size_t step; + int ret; + + if (!i) { + ret = starfive_trng_cmd(trng, + STARFIVE_CTRL_GENE_RANDNUM); + if (ret) + return ret; + } + + val = readl(trng->base + STARFIVE_RAND0 + + (i * STARFIVE_RAND_LEN)); + step = min_t(size_t, len, STARFIVE_RAND_LEN); + memcpy(buffer, &val, step); + buffer += step; + len -= step; + } + + return 0; +} + +static int starfive_trng_init(struct starfive_trng_plat *trng) +{ + u32 mode, intr = 0; + + /* setup Auto Request/Age register */ + writel(0, trng->base + STARFIVE_AUTO_AGE); + writel(0, trng->base + STARFIVE_AUTO_RQSTS); + + /* clear register: ISTAT */ + starfive_trng_irq_mask_clear(trng); + + intr |= STARFIVE_IE_ALL; + writel(intr, trng->base + STARFIVE_IE); + + mode = readl(trng->base + STARFIVE_MODE); + + switch (trng->mode) { + case PRNG_128BIT: + mode &= ~STARFIVE_MODE_R256; + break; + case PRNG_256BIT: + mode |= STARFIVE_MODE_R256; + break; + default: + mode |= STARFIVE_MODE_R256; + break; + } + + writel(mode, trng->base + STARFIVE_MODE); + + return starfive_trng_cmd(trng, STARFIVE_CTRL_EXEC_RANDRESEED); +} + +static int starfive_trng_probe(struct udevice *dev) +{ + struct starfive_trng_plat *pdata = dev_get_plat(dev); + int err; + + err = clk_enable(pdata->hclk); + if (err) + return err; + + err = clk_enable(pdata->ahb); + if (err) + goto err_ahb; + + err = reset_deassert(pdata->rst); + if (err) + goto err_reset; + + pdata->mode = PRNG_256BIT; + + err = starfive_trng_init(pdata); + if (err) + goto err_trng_init; + + return 0; + +err_trng_init: + reset_assert(pdata->rst); +err_reset: + clk_disable(pdata->ahb); +err_ahb: + clk_disable(pdata->hclk); + + return err; +} + +static int starfive_trng_of_to_plat(struct udevice *dev) +{ + struct starfive_trng_plat *pdata = dev_get_plat(dev); + + pdata->base = (void *)dev_read_addr(dev); + if (!pdata->base) + return -ENODEV; + + pdata->hclk = devm_clk_get(dev, "hclk"); + if (IS_ERR(pdata->hclk)) + return -ENODEV; + + pdata->ahb = devm_clk_get(dev, "ahb"); + if (IS_ERR(pdata->ahb)) + return -ENODEV; + + pdata->rst = devm_reset_control_get(dev, NULL); + if (IS_ERR(pdata->rst)) + return -ENODEV; + + return 0; +} + +static const struct dm_rng_ops starfive_trng_ops = { + .read = starfive_trng_read, +}; + +static const struct udevice_id starfive_trng_match[] = { + { + .compatible = "starfive,jh7110-trng", + }, + {}, +}; + +U_BOOT_DRIVER(starfive_trng) = { + .name = "jh7110-trng", + .id = UCLASS_RNG, + .of_match = starfive_trng_match, + .probe = starfive_trng_probe, + .ops = &starfive_trng_ops, + .plat_auto = sizeof(struct starfive_trng_plat), + .of_to_plat = starfive_trng_of_to_plat, +}; diff --git a/drivers/rng/riscv_zkr_rng.c b/drivers/rng/riscv_zkr_rng.c new file mode 100644 index 00000000000..8c9e111e2e0 --- /dev/null +++ b/drivers/rng/riscv_zkr_rng.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * The RISC-V Zkr extension provides CSR seed which provides access to a + * random number generator. + */ + +#define LOG_CATEGORY UCLASS_RNG + +#include <dm.h> +#include <interrupt.h> +#include <log.h> +#include <rng.h> + +#define DRIVER_NAME "riscv_zkr" + +enum opst { + /** @BIST: built in self test running */ + BIST = 0b00, + /** @WAIT: sufficient amount of entropy is not yet available */ + WAIT = 0b01, + /** @ES16: 16bits of entropy available */ + ES16 = 0b10, + /** @DEAD: unrecoverable self-test error */ + DEAD = 0b11, +}; + +static unsigned long read_seed(void) +{ + unsigned long ret; + + __asm__ __volatile__("csrrw %0, seed, x0" : "=r" (ret) : : "memory"); + + return ret; +} + +static int riscv_zkr_read(struct udevice *dev, void *data, size_t len) +{ + u8 *ptr = data; + + while (len) { + u32 val; + + val = read_seed(); + + switch (val >> 30) { + case BIST: + continue; + case WAIT: + continue; + case ES16: + *ptr++ = val & 0xff; + if (--len) { + *ptr++ = val >> 8; + --len; + } + break; + case DEAD: + return -ENODEV; + } + } + + return 0; +} + +/** + * riscv_zkr_probe() - check if the seed register is available + * + * If the SBI software has not set mseccfg.sseed=1 or the Zkr + * extension is not available this probe function will result + * in an exception. Currently we cannot recover from this. + * + * @dev: RNG device + * Return: 0 if successfully probed + */ +static int riscv_zkr_probe(struct udevice *dev) +{ + struct resume_data resume; + int ret; + u32 val; + + /* Check if reading seed leads to interrupt */ + set_resume(&resume); + ret = setjmp(resume.jump); + if (ret) + log_debug("Exception %ld reading seed CSR\n", resume.code); + else + val = read_seed(); + set_resume(NULL); + if (ret) + return -ENODEV; + + do { + val = read_seed(); + val >>= 30; + } while (val == BIST || val == WAIT); + + if (val == DEAD) + return -ENODEV; + + return 0; +} + +static const struct dm_rng_ops riscv_zkr_ops = { + .read = riscv_zkr_read, +}; + +U_BOOT_DRIVER(riscv_zkr) = { + .name = DRIVER_NAME, + .id = UCLASS_RNG, + .ops = &riscv_zkr_ops, + .probe = riscv_zkr_probe, +}; + +U_BOOT_DRVINFO(cpu_riscv_zkr) = { + .name = DRIVER_NAME, +}; diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 7411660d465..b76aadb0653 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -450,15 +450,15 @@ static void scsi_setup_test_unit_ready(struct scsi_cmd *pccb) */ static void scsi_init_dev_desc_priv(struct blk_desc *dev_desc) { + memset(dev_desc, 0, sizeof(struct blk_desc)); dev_desc->target = 0xff; dev_desc->lun = 0xff; dev_desc->log2blksz = LOG2_INVALID(typeof(dev_desc->log2blksz)); dev_desc->type = DEV_TYPE_UNKNOWN; - dev_desc->vendor[0] = 0; - dev_desc->product[0] = 0; - dev_desc->revision[0] = 0; - dev_desc->removable = false; +#if IS_ENABLED(CONFIG_BOUNCE_BUFFER) + dev_desc->bb = true; +#endif /* CONFIG_BOUNCE_BUFFER */ } #if !defined(CONFIG_DM_SCSI) @@ -606,6 +606,7 @@ static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose) bdesc->lun = lun; bdesc->removable = bd.removable; bdesc->type = bd.type; + bdesc->bb = bd.bb; memcpy(&bdesc->vendor, &bd.vendor, sizeof(bd.vendor)); memcpy(&bdesc->product, &bd.product, sizeof(bd.product)); memcpy(&bdesc->revision, &bd.revision, sizeof(bd.revision)); diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9f0f84c9b42..6628a887de7 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -24,6 +24,21 @@ config BAUDRATE in the SPL stage (most drivers) or for choosing a default baudrate in the absence of an environment setting (serial_mxc.c). +config OF_SERIAL_BAUD + bool "Fetch serial baudrate from device tree" + depends on DM_SERIAL && SPL_ENV_SUPPORT + select DEFAULT_ENV_IS_RW + help + Select this to enable fetching and setting of the baudrate + configured in the DT. Replace the default baudrate with the DT + baudrate and also set it to the environment. + +config DEFAULT_ENV_IS_RW + bool "Make default environment as writable" + help + Select this to enable to make default environment writable. This + allows modifying the default environment. + config REQUIRE_SERIAL_CONSOLE bool "Require a serial port for console" # Running without a serial console is not supported by the diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 4a2da7a3317..e4fa3933bc8 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -155,12 +155,61 @@ static void serial_find_console_or_panic(void) } #endif /* CONFIG_SERIAL_PRESENT */ +/** + * check_valid_baudrate() - Check whether baudrate is valid or not + * + * @baud: baud rate to check + * Return: 0 if OK, -ve on error + */ +static int check_valid_baudrate(int baud) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) { + if (baud == baudrate_table[i]) + return 0; + } + + return -EINVAL; +} + +int fetch_baud_from_dtb(void) +{ + int baud_value, ret; + + baud_value = ofnode_read_baud(); + ret = check_valid_baudrate(baud_value); + if (ret) + return ret; + + return baud_value; +} + /* Called prior to relocation */ int serial_init(void) { #if CONFIG_IS_ENABLED(SERIAL_PRESENT) serial_find_console_or_panic(); gd->flags |= GD_FLG_SERIAL_READY; + + if (IS_ENABLED(CONFIG_OF_SERIAL_BAUD)) { + int ret = 0; + char *ptr = (char*)&default_environment[0]; + + /* + * Fetch the baudrate from the dtb and update the value in the + * default environment. + */ + ret = fetch_baud_from_dtb(); + if (ret != -EINVAL && ret != -EFAULT) { + gd->baudrate = ret; + + while (*ptr != '\0' && *(ptr + 1) != '\0') + ptr++; + ptr += 2; + sprintf(ptr, "baudrate=%d", gd->baudrate); + } + } serial_setbrg(); #endif @@ -182,6 +231,16 @@ int serial_initialize(void) return serial_init(); } +static void _serial_flush(struct udevice *dev) +{ + struct dm_serial_ops *ops = serial_get_ops(dev); + + if (!ops->pending) + return; + while (ops->pending(dev, false) > 0) + ; +} + static void _serial_putc(struct udevice *dev, char ch) { struct dm_serial_ops *ops = serial_get_ops(dev); @@ -193,6 +252,9 @@ static void _serial_putc(struct udevice *dev, char ch) do { err = ops->putc(dev, ch); } while (err == -EAGAIN); + + if (IS_ENABLED(CONFIG_CONSOLE_FLUSH_ON_NEWLINE) && ch == '\n') + _serial_flush(dev); } static int __serial_puts(struct udevice *dev, const char *str, size_t len) @@ -231,22 +293,13 @@ static void _serial_puts(struct udevice *dev, const char *str) if (*newline && __serial_puts(dev, "\r\n", 2)) return; + if (IS_ENABLED(CONFIG_CONSOLE_FLUSH_ON_NEWLINE) && *newline) + _serial_flush(dev); + str += len + !!*newline; } while (*str); } -#ifdef CONFIG_CONSOLE_FLUSH_SUPPORT -static void _serial_flush(struct udevice *dev) -{ - struct dm_serial_ops *ops = serial_get_ops(dev); - - if (!ops->pending) - return; - while (ops->pending(dev, false) > 0) - ; -} -#endif - static int __serial_getc(struct udevice *dev) { struct dm_serial_ops *ops = serial_get_ops(dev); diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index 26310b0b746..49ced8f9fae 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -2,7 +2,7 @@ /* * Texas Instruments' OMAP serial driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index c034ab54e15..e4cc4ee4260 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -6,7 +6,6 @@ * Copyright (C) 2002 - 2008 Paul Mundt */ -#include <common.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/processor.h> diff --git a/drivers/sm/Kconfig b/drivers/sm/Kconfig index f0987275d26..926af286330 100644 --- a/drivers/sm/Kconfig +++ b/drivers/sm/Kconfig @@ -4,6 +4,5 @@ config SM config MESON_SM bool "Amlogic Secure Monitor driver" select SM - default n help Say y here to enable the Amlogic secure monitor driver. diff --git a/drivers/sm/meson-sm.c b/drivers/sm/meson-sm.c index 25adaf45607..15b3b0e2672 100644 --- a/drivers/sm/meson-sm.c +++ b/drivers/sm/meson-sm.c @@ -193,6 +193,7 @@ U_BOOT_DRIVER(meson_sm) = { .id = UCLASS_SM, .of_match = meson_sm_ids, .probe = meson_sm_probe, + .bind = dm_scan_fdt_dev, .priv_auto = sizeof(struct meson_sm_priv), .ops = &sm_ops, }; diff --git a/drivers/soc/soc-uclass.c b/drivers/soc/soc-uclass.c index dfad32d80db..8b3044fed8d 100644 --- a/drivers/soc/soc-uclass.c +++ b/drivers/soc/soc-uclass.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/ + * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/ * Dave Gerlach <d-gerlach@ti.com> */ diff --git a/drivers/soc/soc_sandbox.c b/drivers/soc/soc_sandbox.c index 5c82ad84fc2..15fdd9930cb 100644 --- a/drivers/soc/soc_sandbox.c +++ b/drivers/soc/soc_sandbox.c @@ -2,7 +2,7 @@ /* * Sandbox driver for the SOC uclass * - * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/ + * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/ * Dave Gerlach <d-gerlach@ti.com> */ diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index b720131ae5d..355a5368dd4 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * Dave Gerlach <d-gerlach@ti.com> */ diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index e02889649b2..7a2fbb0db6e 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -2,7 +2,7 @@ /* * TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com */ #include <common.h> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 854b8b88daf..69b184b0d9e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -251,6 +251,15 @@ config MICROCHIP_COREQSPI Enable the QSPI driver for Microchip FPGA QSPI controllers. This driver can be used on Polarfire SoC. +config MESON_SPIFC_A1 + bool "Amlogic Meson A1 SPI Flash Controller driver" + depends on ARCH_MESON + help + Enable the Amlogic A1 SPI Flash Controller (SPIFC) driver. + This driver can be used to access the SPI NOR/NAND flash chips + with STR mode frequency up to 98MHz. Dual and quad modes are + supported by controller. + config MPC8XX_SPI bool "MPC8XX SPI Driver" depends on MPC8xx @@ -451,7 +460,6 @@ config SANDBOX_SPI_MAX_CS config SPI_ASPEED_SMC bool "ASPEED SPI flash controller driver" depends on DM_SPI && SPI_MEM - default n help Enable ASPEED SPI flash controller driver for AST2500 and AST2600 SoCs. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c27b3327c33..14bdb97f189 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o +obj-$(CONFIG_MESON_SPIFC_A1) += meson_spifc_a1.o obj-$(CONFIG_MICROCHIP_COREQSPI) += microchip_coreqspi.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a7685a2f512..e02a3b3de37 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -44,8 +44,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE); writel(CQSPI_DFLT_DMA_PERIPH_CFG, priv->regbase + CQSPI_REG_DMA_PERIPH_CFG); - writel((unsigned long)rxbuf, priv->regbase + + writel(lower_32_bits((unsigned long)rxbuf), priv->regbase + CQSPI_DMA_DST_ADDR_REG); + writel(upper_32_bits((unsigned long)rxbuf), priv->regbase + + CQSPI_DMA_DST_ADDR_MSB_REG); writel(priv->trigger_address, priv->regbase + CQSPI_DMA_SRC_RD_ADDR_REG); writel(bytes_to_dma, priv->regbase + diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 9ebc4ed48f0..25f5e9fdebd 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ * * Driver for SPI controller on DaVinci. Based on atmel_spi.c * by Atmel Corporation diff --git a/drivers/spi/meson_spifc_a1.c b/drivers/spi/meson_spifc_a1.c new file mode 100644 index 00000000000..099c4c037dd --- /dev/null +++ b/drivers/spi/meson_spifc_a1.c @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Amlogic A1 SPI flash controller (SPIFC) + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * + * Author: Martin Kurbanov <mmkurbanov@sberdevices.ru> + * + * Ported to u-boot: + * Author: Igor Prusov <ivprusov@sberdevices.ru> + */ + +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <spi-mem.h> +#include <asm/io.h> +#include <linux/log2.h> +#include <linux/iopoll.h> +#include <linux/bitfield.h> + +#define SPIFC_A1_AHB_CTRL_REG 0x0 +#define SPIFC_A1_AHB_BUS_EN BIT(31) + +#define SPIFC_A1_USER_CTRL0_REG 0x200 +#define SPIFC_A1_USER_REQUEST_ENABLE BIT(31) +#define SPIFC_A1_USER_REQUEST_FINISH BIT(30) +#define SPIFC_A1_USER_DATA_UPDATED BIT(0) + +#define SPIFC_A1_USER_CTRL1_REG 0x204 +#define SPIFC_A1_USER_CMD_ENABLE BIT(30) +#define SPIFC_A1_USER_CMD_MODE GENMASK(29, 28) +#define SPIFC_A1_USER_CMD_CODE GENMASK(27, 20) +#define SPIFC_A1_USER_ADDR_ENABLE BIT(19) +#define SPIFC_A1_USER_ADDR_MODE GENMASK(18, 17) +#define SPIFC_A1_USER_ADDR_BYTES GENMASK(16, 15) +#define SPIFC_A1_USER_DOUT_ENABLE BIT(14) +#define SPIFC_A1_USER_DOUT_MODE GENMASK(11, 10) +#define SPIFC_A1_USER_DOUT_BYTES GENMASK(9, 0) + +#define SPIFC_A1_USER_CTRL2_REG 0x208 +#define SPIFC_A1_USER_DUMMY_ENABLE BIT(31) +#define SPIFC_A1_USER_DUMMY_MODE GENMASK(30, 29) +#define SPIFC_A1_USER_DUMMY_CLK_SYCLES GENMASK(28, 23) + +#define SPIFC_A1_USER_CTRL3_REG 0x20c +#define SPIFC_A1_USER_DIN_ENABLE BIT(31) +#define SPIFC_A1_USER_DIN_MODE GENMASK(28, 27) +#define SPIFC_A1_USER_DIN_BYTES GENMASK(25, 16) + +#define SPIFC_A1_USER_ADDR_REG 0x210 + +#define SPIFC_A1_AHB_REQ_CTRL_REG 0x214 +#define SPIFC_A1_AHB_REQ_ENABLE BIT(31) + +#define SPIFC_A1_ACTIMING0_REG (0x0088 << 2) +#define SPIFC_A1_TSLCH GENMASK(31, 30) +#define SPIFC_A1_TCLSH GENMASK(29, 28) +#define SPIFC_A1_TSHWL GENMASK(20, 16) +#define SPIFC_A1_TSHSL2 GENMASK(15, 12) +#define SPIFC_A1_TSHSL1 GENMASK(11, 8) +#define SPIFC_A1_TWHSL GENMASK(7, 0) + +#define SPIFC_A1_DBUF_CTRL_REG 0x240 +#define SPIFC_A1_DBUF_DIR BIT(31) +#define SPIFC_A1_DBUF_AUTO_UPDATE_ADDR BIT(30) +#define SPIFC_A1_DBUF_ADDR GENMASK(7, 0) + +#define SPIFC_A1_DBUF_DATA_REG 0x244 + +#define SPIFC_A1_USER_DBUF_ADDR_REG 0x248 + +#define SPIFC_A1_BUFFER_SIZE 512U + +#define SPIFC_A1_MAX_HZ 200000000 +#define SPIFC_A1_MIN_HZ 1000000 + +#define SPIFC_A1_USER_CMD(op) ( \ + SPIFC_A1_USER_CMD_ENABLE | \ + FIELD_PREP(SPIFC_A1_USER_CMD_CODE, (op)->cmd.opcode) | \ + FIELD_PREP(SPIFC_A1_USER_CMD_MODE, ilog2((op)->cmd.buswidth))) + +#define SPIFC_A1_USER_ADDR(op) ( \ + SPIFC_A1_USER_ADDR_ENABLE | \ + FIELD_PREP(SPIFC_A1_USER_ADDR_MODE, ilog2((op)->addr.buswidth)) | \ + FIELD_PREP(SPIFC_A1_USER_ADDR_BYTES, (op)->addr.nbytes - 1)) + +#define SPIFC_A1_USER_DUMMY(op) ( \ + SPIFC_A1_USER_DUMMY_ENABLE | \ + FIELD_PREP(SPIFC_A1_USER_DUMMY_MODE, ilog2((op)->dummy.buswidth)) | \ + FIELD_PREP(SPIFC_A1_USER_DUMMY_CLK_SYCLES, (op)->dummy.nbytes << 3)) + +#define SPIFC_A1_TSLCH_VAL FIELD_PREP(SPIFC_A1_TSLCH, 1) +#define SPIFC_A1_TCLSH_VAL FIELD_PREP(SPIFC_A1_TCLSH, 1) +#define SPIFC_A1_TSHWL_VAL FIELD_PREP(SPIFC_A1_TSHWL, 7) +#define SPIFC_A1_TSHSL2_VAL FIELD_PREP(SPIFC_A1_TSHSL2, 7) +#define SPIFC_A1_TSHSL1_VAL FIELD_PREP(SPIFC_A1_TSHSL1, 7) +#define SPIFC_A1_TWHSL_VAL FIELD_PREP(SPIFC_A1_TWHSL, 2) +#define SPIFC_A1_ACTIMING0_VAL (SPIFC_A1_TSLCH_VAL | SPIFC_A1_TCLSH_VAL | \ + SPIFC_A1_TSHWL_VAL | SPIFC_A1_TSHSL2_VAL | \ + SPIFC_A1_TSHSL1_VAL | SPIFC_A1_TWHSL_VAL) + +struct amlogic_spifc_a1 { + struct clk clk; + void __iomem *base; + u32 curr_speed_hz; +}; + +static int amlogic_spifc_a1_request(struct amlogic_spifc_a1 *spifc, bool read) +{ + u32 mask = SPIFC_A1_USER_REQUEST_FINISH | + (read ? SPIFC_A1_USER_DATA_UPDATED : 0); + u32 val; + + writel(SPIFC_A1_USER_REQUEST_ENABLE, + spifc->base + SPIFC_A1_USER_CTRL0_REG); + + return readl_poll_timeout(spifc->base + SPIFC_A1_USER_CTRL0_REG, + val, (val & mask) == mask, + 200 * 1000); +} + +static void amlogic_spifc_a1_drain_buffer(struct amlogic_spifc_a1 *spifc, + char *buf, u32 len) +{ + u32 data; + const u32 count = len / sizeof(data); + const u32 pad = len % sizeof(data); + + writel(SPIFC_A1_DBUF_AUTO_UPDATE_ADDR, + spifc->base + SPIFC_A1_DBUF_CTRL_REG); + readsl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); + + if (pad) { + data = readl(spifc->base + SPIFC_A1_DBUF_DATA_REG); + memcpy(buf + len - pad, &data, pad); + } +} + +static void amlogic_spifc_a1_fill_buffer(struct amlogic_spifc_a1 *spifc, + const char *buf, u32 len) +{ + u32 data; + const u32 count = len / sizeof(data); + const u32 pad = len % sizeof(data); + + writel(SPIFC_A1_DBUF_DIR | SPIFC_A1_DBUF_AUTO_UPDATE_ADDR, + spifc->base + SPIFC_A1_DBUF_CTRL_REG); + writesl(spifc->base + SPIFC_A1_DBUF_DATA_REG, buf, count); + + if (pad) { + memcpy(&data, buf + len - pad, pad); + writel(data, spifc->base + SPIFC_A1_DBUF_DATA_REG); + } +} + +static void amlogic_spifc_a1_user_init(struct amlogic_spifc_a1 *spifc) +{ + writel(0, spifc->base + SPIFC_A1_USER_CTRL0_REG); + writel(0, spifc->base + SPIFC_A1_USER_CTRL1_REG); + writel(0, spifc->base + SPIFC_A1_USER_CTRL2_REG); + writel(0, spifc->base + SPIFC_A1_USER_CTRL3_REG); +} + +static void amlogic_spifc_a1_set_cmd(struct amlogic_spifc_a1 *spifc, + u32 cmd_cfg) +{ + u32 val; + + val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG); + val &= ~(SPIFC_A1_USER_CMD_MODE | SPIFC_A1_USER_CMD_CODE); + val |= cmd_cfg; + writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG); +} + +static void amlogic_spifc_a1_set_addr(struct amlogic_spifc_a1 *spifc, u32 addr, + u32 addr_cfg) +{ + u32 val; + + writel(addr, spifc->base + SPIFC_A1_USER_ADDR_REG); + + val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG); + val &= ~(SPIFC_A1_USER_ADDR_MODE | SPIFC_A1_USER_ADDR_BYTES); + val |= addr_cfg; + writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG); +} + +static void amlogic_spifc_a1_set_dummy(struct amlogic_spifc_a1 *spifc, + u32 dummy_cfg) +{ + u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL2_REG); + + val &= ~(SPIFC_A1_USER_DUMMY_MODE | SPIFC_A1_USER_DUMMY_CLK_SYCLES); + val |= dummy_cfg; + writel(val, spifc->base + SPIFC_A1_USER_CTRL2_REG); +} + +static int amlogic_spifc_a1_read(struct amlogic_spifc_a1 *spifc, void *buf, + u32 size, u32 mode) +{ + u32 val = readl(spifc->base + SPIFC_A1_USER_CTRL3_REG); + int ret; + + val &= ~(SPIFC_A1_USER_DIN_MODE | SPIFC_A1_USER_DIN_BYTES); + val |= SPIFC_A1_USER_DIN_ENABLE; + val |= FIELD_PREP(SPIFC_A1_USER_DIN_MODE, mode); + val |= FIELD_PREP(SPIFC_A1_USER_DIN_BYTES, size); + writel(val, spifc->base + SPIFC_A1_USER_CTRL3_REG); + + ret = amlogic_spifc_a1_request(spifc, true); + if (!ret) + amlogic_spifc_a1_drain_buffer(spifc, buf, size); + + return ret; +} + +static int amlogic_spifc_a1_write(struct amlogic_spifc_a1 *spifc, + const void *buf, u32 size, u32 mode) +{ + u32 val; + + amlogic_spifc_a1_fill_buffer(spifc, buf, size); + + val = readl(spifc->base + SPIFC_A1_USER_CTRL1_REG); + val &= ~(SPIFC_A1_USER_DOUT_MODE | SPIFC_A1_USER_DOUT_BYTES); + val |= FIELD_PREP(SPIFC_A1_USER_DOUT_MODE, mode); + val |= FIELD_PREP(SPIFC_A1_USER_DOUT_BYTES, size); + val |= SPIFC_A1_USER_DOUT_ENABLE; + writel(val, spifc->base + SPIFC_A1_USER_CTRL1_REG); + + return amlogic_spifc_a1_request(spifc, false); +} + +static int amlogic_spifc_a1_set_freq(struct amlogic_spifc_a1 *spifc, u32 freq) +{ + int ret; + + if (freq == spifc->curr_speed_hz) + return 0; + + ret = clk_set_rate(&spifc->clk, freq); + if (ret) + return ret; + + spifc->curr_speed_hz = freq; + return 0; +} + +static int amlogic_spifc_a1_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct amlogic_spifc_a1 *spifc = dev_get_priv(slave->dev->parent); + size_t data_size = op->data.nbytes; + int ret; + + ret = amlogic_spifc_a1_set_freq(spifc, slave->max_hz); + if (ret) + return ret; + + amlogic_spifc_a1_user_init(spifc); + amlogic_spifc_a1_set_cmd(spifc, SPIFC_A1_USER_CMD(op)); + + if (op->addr.nbytes) + amlogic_spifc_a1_set_addr(spifc, op->addr.val, + SPIFC_A1_USER_ADDR(op)); + + if (op->dummy.nbytes) + amlogic_spifc_a1_set_dummy(spifc, SPIFC_A1_USER_DUMMY(op)); + + if (data_size) { + u32 mode = ilog2(op->data.buswidth); + + writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG); + + if (op->data.dir == SPI_MEM_DATA_IN) + ret = amlogic_spifc_a1_read(spifc, op->data.buf.in, + data_size, mode); + else + ret = amlogic_spifc_a1_write(spifc, op->data.buf.out, + data_size, mode); + } else { + ret = amlogic_spifc_a1_request(spifc, false); + } + + return ret; +} + +static int amlogic_spifc_a1_adjust_op_size(struct spi_slave *slave, + struct spi_mem_op *op) +{ + op->data.nbytes = min(op->data.nbytes, SPIFC_A1_BUFFER_SIZE); + return 0; +} + +static void amlogic_spifc_a1_hw_init(struct amlogic_spifc_a1 *spifc) +{ + u32 regv; + + regv = readl(spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG); + regv &= ~(SPIFC_A1_AHB_REQ_ENABLE); + writel(regv, spifc->base + SPIFC_A1_AHB_REQ_CTRL_REG); + + regv = readl(spifc->base + SPIFC_A1_AHB_CTRL_REG); + regv &= ~(SPIFC_A1_AHB_BUS_EN); + writel(regv, spifc->base + SPIFC_A1_AHB_CTRL_REG); + + writel(SPIFC_A1_ACTIMING0_VAL, spifc->base + SPIFC_A1_ACTIMING0_REG); + + writel(0, spifc->base + SPIFC_A1_USER_DBUF_ADDR_REG); +} + +static const struct spi_controller_mem_ops amlogic_spifc_a1_mem_ops = { + .exec_op = amlogic_spifc_a1_exec_op, + .adjust_op_size = amlogic_spifc_a1_adjust_op_size, +}; + +static int amlogic_spifc_a1_probe(struct udevice *dev) +{ + struct amlogic_spifc_a1 *spifc = dev_get_priv(dev); + int ret; + struct udevice *bus = dev; + + spifc->base = dev_read_addr_ptr(dev); + if (!spifc->base) + return -EINVAL; + + ret = clk_get_by_index(bus, 0, &spifc->clk); + if (ret) { + pr_err("can't get clk spifc_gate!\n"); + return ret; + } + + ret = clk_enable(&spifc->clk); + if (ret) { + pr_err("enable clk fail\n"); + return ret; + } + + amlogic_spifc_a1_hw_init(spifc); + + return 0; +} + +static int amlogic_spifc_a1_remove(struct udevice *dev) +{ + struct amlogic_spifc_a1 *spifc = dev_get_priv(dev); + + clk_free(&spifc->clk); + + return 0; +} + +static const struct udevice_id meson_spifc_ids[] = { + { .compatible = "amlogic,a1-spifc", }, + { } +}; + +int amlogic_spifc_a1_set_speed(struct udevice *bus, uint hz) +{ + return 0; +} + +int amlogic_spifc_a1_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static const struct dm_spi_ops amlogic_spifc_a1_ops = { + .mem_ops = &amlogic_spifc_a1_mem_ops, + .set_speed = amlogic_spifc_a1_set_speed, + .set_mode = amlogic_spifc_a1_set_mode, +}; + +U_BOOT_DRIVER(meson_spifc_a1) = { + .name = "meson_spifc_a1", + .id = UCLASS_SPI, + .of_match = meson_spifc_ids, + .ops = &amlogic_spifc_a1_ops, + .probe = amlogic_spifc_a1_probe, + .remove = amlogic_spifc_a1_remove, + .priv_auto = sizeof(struct amlogic_spifc_a1), +}; diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index ff7b55f8707..5cce6baa621 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -6,7 +6,7 @@ * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com> * * Driver for McSPI controller on OMAP3. Based on davinci_spi.c - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ * * Copyright (C) 2007 Atmel Corporation * diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c index 77ddb19a9f3..6ee841358b3 100644 --- a/drivers/spi/spi-mem-nodm.c +++ b/drivers/spi/spi-mem-nodm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ */ #include <log.h> diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index ec59ef58044..a323994fb2d 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -5,6 +5,8 @@ * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only) */ +#define LOG_CATEGORY UCLASS_SPI + #include <common.h> #include <cpu_func.h> #include <log.h> @@ -192,8 +194,6 @@ static int zynqmp_qspi_of_to_plat(struct udevice *bus) { struct zynqmp_qspi_plat *plat = dev_get_plat(bus); - debug("%s\n", __func__); - plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) + GQSPI_REG_OFFSET); plat->dma_regs = (struct zynqmp_qspi_dma_regs *) @@ -250,7 +250,7 @@ static u32 zynqmp_qspi_genfifo_mode(u8 buswidth) case 4: return GQSPI_SPI_MODE_QSPI; default: - debug("Unsupported bus width %u\n", buswidth); + log_warning("Unsupported bus width %u\n", buswidth); return GQSPI_SPI_MODE_SPI; } } @@ -262,6 +262,8 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, u32 config_reg, ier; int ret = 0; + log_content("%s, GFIFO_CMD: 0x%X\n", __func__, gqspi_fifo_reg); + writel(gqspi_fifo_reg, ®s->genfifo); config_reg = readl(®s->confr); @@ -278,7 +280,7 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv, ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1, GQSPI_TIMEOUT, 1); if (ret) - printf("%s Timeout\n", __func__); + log_warning("%s, Timeout\n", __func__); } @@ -286,6 +288,8 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) { u32 gqspi_fifo_reg = 0; + log_debug("%s, assert: %d\r\n", __func__, is_on); + if (is_on) { gqspi_fifo_reg = zynqmp_qspi_bus_select(priv); gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI | @@ -295,8 +299,6 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on) gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT; } - debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg); - zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg); } @@ -311,8 +313,8 @@ static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) clk_rate = plat->frequency; reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval)); - debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n", - __func__, reqhz, clk_rate, baudrateval); + log_debug("%s, clk_rate:%d, baudrateval:%d, bus_clk: %d\n", + __func__, clk_rate, baudrateval, reqhz); if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) || IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) { @@ -362,7 +364,8 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) u32 confr; u8 baud_rate_val = 0; - debug("%s\n", __func__); + log_debug("%s, Speed: %d, Max: %d\n", __func__, speed, plat->frequency); + if (speed > plat->frequency) speed = plat->frequency; @@ -383,9 +386,8 @@ static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed) confr &= ~GQSPI_BAUD_DIV_MASK; confr |= (baud_rate_val << 3); writel(confr, ®s->confr); - zynqmp_qspi_set_tapdelay(bus, baud_rate_val); - debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz); + zynqmp_qspi_set_tapdelay(bus, baud_rate_val); } return 0; @@ -399,8 +401,6 @@ static int zynqmp_qspi_probe(struct udevice *bus) unsigned long clock; int ret; - debug("%s: bus:%p, priv:%p\n", __func__, bus, priv); - priv->regs = plat->regs; priv->dma_regs = plat->dma_regs; priv->io_mode = plat->io_mode; @@ -416,7 +416,6 @@ static int zynqmp_qspi_probe(struct udevice *bus) dev_err(bus, "failed to get rate\n"); return clock; } - debug("%s: CLK %ld\n", __func__, clock); ret = clk_enable(&clk); if (ret) { @@ -429,6 +428,8 @@ static int zynqmp_qspi_probe(struct udevice *bus) /* init the zynq spi hw */ zynqmp_qspi_init_hw(priv); + log_debug("%s, Rerence clock frequency: %ld\n", __func__, clock); + return 0; } @@ -438,7 +439,8 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode) struct zynqmp_qspi_regs *regs = priv->regs; u32 confr; - debug("%s\n", __func__); + log_debug("%s, 0x%X\n", __func__, mode); + /* Set the SPI Clock phase and polarities */ confr = readl(®s->confr); confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK); @@ -461,16 +463,11 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) u32 *buf = (u32 *)priv->tx_buf; u32 len = size; - debug("TxFIFO: 0x%x, size: 0x%x\n", readl(®s->isr), - size); - while (size) { ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXNFULL_MASK, 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("%s: Timeout\n", __func__); - return ret; - } + if (ret) + return log_msg_ret("Timeout\n", ret); if (size >= 4) { writel(*buf, ®s->txd0r); @@ -501,10 +498,8 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size) ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("%s: Timeout\n", __func__); - return ret; - } + if (ret) + return log_msg_ret("Timeout\n", ret); priv->tx_buf += len; return 0; @@ -516,6 +511,9 @@ static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) u32 gen_fifo_cmd; u8 i, dummy_cycles, addr; + log_debug("%s, opcode: 0x%0X, addr.nbytes: %d, dummy.mbytes: %d\r\n", + __func__, op->cmd.opcode, op->addr.nbytes, op->dummy.nbytes); + /* Send opcode */ gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(op->cmd.buswidth); @@ -532,8 +530,6 @@ static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv) gen_fifo_cmd |= GQSPI_GFIFO_TX; gen_fifo_cmd |= addr; - debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd); - zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); } @@ -583,6 +579,8 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) u32 len; int ret = 0; + log_debug("%s, length: %d\r\n", __func__, priv->len); + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK; @@ -591,8 +589,6 @@ static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv) len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); - debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd); - if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len); else @@ -608,7 +604,6 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, u32 gen_fifo_cmd, u32 *buf) { u32 len; - u32 actuallen = priv->len; u32 config_reg, ier, isr; u32 timeout = GQSPI_TIMEOUT; struct zynqmp_qspi_regs *regs = priv->regs; @@ -623,7 +618,7 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, else priv->bytes_to_receive = len; zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); - debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); + /* Manual start */ config_reg = readl(®s->confr); config_reg |= GQSPI_STRT_GEN_FIFO; @@ -652,13 +647,8 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv, } } - debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", - (unsigned long)buf, (unsigned long)priv->rx_buf, - *buf, actuallen); - if (!timeout) { - printf("IO timeout: %d\n", readl(®s->isr)); - return -1; - } + if (!timeout) + return log_msg_retz("Timeout\n", timeout); } return 0; @@ -695,26 +685,18 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv, while (priv->len) { zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd); zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd); - - debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd); } ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE, 1, GQSPI_TIMEOUT, 1); - if (ret) { - printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr)); - return -ETIMEDOUT; - } + if (ret) + return log_msg_ret("Timeout:\n", ret); invalidate_dcache_range(addr, addr + size); writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr); - debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n", - (unsigned long)buf, (unsigned long)priv->rx_buf, *buf, - actuallen); - if (buf != priv->rx_buf) memcpy(priv->rx_buf, buf, actuallen); @@ -731,6 +713,8 @@ static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv) u32 *buf; u32 actuallen = priv->len; + log_debug("%s, length: %d\r\n", __func__, priv->len); + gen_fifo_cmd = zynqmp_qspi_bus_select(priv); gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth); gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK; diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index bdbe2a95364..0e52f996283 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -74,6 +74,13 @@ config SYSRESET_GPIO example on Microblaze where reset logic can be controlled via GPIO pin which triggers cpu reset. +config SYSRESET_MAX77663 + bool "Enable support for MAX77663 PMIC System Reset" + depends on DM_PMIC_MAX77663 + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF + help + Enable system power management functions found in MAX77663 PMIC. + config SYSRESET_MICROBLAZE bool "Enable support for Microblaze soft reset" depends on MICROBLAZE @@ -102,6 +109,13 @@ config SYSRESET_SPL_AT91 This enables the system reset driver support for Microchip/Atmel SoCs in SPL. +config SYSRESET_PALMAS + bool "Enable support for PALMAS System Reset" + depends on PMIC_PALMAS + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF + help + Enable system power management functions found in PLAMAS PMIC family. + config SYSRESET_PSCI bool "Enable support for PSCI System Reset" depends on ARM_PSCI_FW @@ -137,6 +151,12 @@ config SYSRESET_SOCFPGA_SOC64 This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs. +config SYSRESET_TEGRA + bool "Tegra PMC system reset driver" + depends on ARCH_TEGRA + help + This enables the system reset ability of PMC used in Tegra SoCs. + config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" depends on TI_SCI_PROTOCOL @@ -144,6 +164,22 @@ config SYSRESET_TI_SCI This enables the system reset driver support over TI System Control Interface available on some new TI's SoCs. +config SYSRESET_TPS65910 + bool "Enable support for TPS65910/TPS65911 PMIC System Reset" + depends on DM_PMIC_TPS65910 + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF + help + Enable system power management functions found in TPS65910/TPS65911 + PMICs. + +config SYSRESET_TPS80031 + bool "Enable support for TPS80031/TPS80032 PMIC System Reset" + depends on DM_PMIC_TPS80031 + select SYSRESET_CMD_POWEROFF if CMD_POWEROFF + help + Enable system power management functions found in TPS80031/TPS80032 + PMICs. + config SYSRESET_SYSCON bool "Enable support for mfd syscon reboot driver" select REGMAP diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 40c876764af..c9f1c625aeb 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -9,14 +9,19 @@ obj-$(CONFIG_ARCH_STI) += sysreset_sti.o obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_POWEROFF_GPIO) += poweroff_gpio.o obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET_MAX77663) += sysreset_max77663.o obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET_PALMAS) += sysreset_palmas.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o +obj-$(CONFIG_SYSRESET_TEGRA) += sysreset_tegra.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET_TPS65910) += sysreset_tps65910.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET_TPS80031) += sysreset_tps80031.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o diff --git a/drivers/sysreset/sysreset-ti-sci.c b/drivers/sysreset/sysreset-ti-sci.c index 81bfd67ad99..5fc05c46cb0 100644 --- a/drivers/sysreset/sysreset-ti-sci.c +++ b/drivers/sysreset/sysreset-ti-sci.c @@ -2,7 +2,7 @@ /* * Texas Instruments System Control Interface (TI SCI) system reset driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Andreas Dannenberg <dannenberg@ti.com> */ diff --git a/drivers/sysreset/sysreset_max77663.c b/drivers/sysreset/sysreset_max77663.c new file mode 100644 index 00000000000..8febcf8de6c --- /dev/null +++ b/drivers/sysreset/sysreset_max77663.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <errno.h> +#include <sysreset.h> +#include <power/pmic.h> +#include <power/max77663.h> + +static int max77663_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + int val; + + val = pmic_reg_read(dev->parent, MAX77663_REG_ONOFF_CFG1); + if (val < 0) + return val; + + /* clear both bits */ + val &= ~ONOFF_SFT_RST; + val &= ~ONOFF_PWR_OFF; + + switch (type) { + case SYSRESET_POWER: + /* MAX77663: SFT_RST > ONOFF_CFG1 */ + pmic_reg_write(dev->parent, MAX77663_REG_ONOFF_CFG1, + val | ONOFF_SFT_RST); + break; + case SYSRESET_POWER_OFF: + /* MAX77663: PWR_OFF > ONOFF_CFG1 */ + pmic_reg_write(dev->parent, MAX77663_REG_ONOFF_CFG1, + val | ONOFF_PWR_OFF); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops max77663_sysreset = { + .request = max77663_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_max77663) = { + .id = UCLASS_SYSRESET, + .name = MAX77663_RST_DRIVER, + .ops = &max77663_sysreset, +}; diff --git a/drivers/sysreset/sysreset_palmas.c b/drivers/sysreset/sysreset_palmas.c new file mode 100644 index 00000000000..9e3aa403488 --- /dev/null +++ b/drivers/sysreset/sysreset_palmas.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <errno.h> +#include <sysreset.h> +#include <power/pmic.h> +#include <power/palmas.h> + +static int palmas_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + struct palmas_priv *priv = dev_get_priv(dev->parent); + int ret; + + /* + * Mask INT3 on second page which detects vbus + * or device will immediately turn on. + */ + ret = dm_i2c_reg_clrset(priv->chip2, PALMAS_INT3_MASK, + MASK_VBUS, MASK_VBUS); + if (ret < 0) + return ret; + + switch (type) { + case SYSRESET_POWER: + /* PALMAS: SW_RST > DEV_CTRL */ + pmic_reg_write(dev->parent, PALMAS_DEV_CTRL, SW_RST); + break; + case SYSRESET_POWER_OFF: + /* PALMAS: DEV_OFF > DEV_CTRL */ + pmic_reg_write(dev->parent, PALMAS_DEV_CTRL, DEV_OFF); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops palmas_sysreset = { + .request = palmas_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_palmas) = { + .id = UCLASS_SYSRESET, + .name = PALMAS_RST_DRIVER, + .ops = &palmas_sysreset, +}; diff --git a/drivers/sysreset/sysreset_tegra.c b/drivers/sysreset/sysreset_tegra.c new file mode 100644 index 00000000000..10bcd3a1873 --- /dev/null +++ b/drivers/sysreset/sysreset_tegra.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <linux/err.h> +#include <asm/arch-tegra/pmc.h> + +static int tegra_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + u32 value; + + switch (type) { + case SYSRESET_WARM: + case SYSRESET_COLD: + /* resets everything but scratch 0 and reset status */ + value = tegra_pmc_readl(PMC_CNTRL); + value |= PMC_CNTRL_MAIN_RST; + tegra_pmc_writel(value, PMC_CNTRL); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops tegra_sysreset = { + .request = tegra_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_tegra) = { + .id = UCLASS_SYSRESET, + .name = "sysreset_tegra", + .ops = &tegra_sysreset, +}; + +/* Link to Tegra PMC once there is a driver */ +U_BOOT_DRVINFO(sysreset_tegra) = { + .name = "sysreset_tegra" +}; diff --git a/drivers/sysreset/sysreset_tps65910.c b/drivers/sysreset/sysreset_tps65910.c new file mode 100644 index 00000000000..98da56661c0 --- /dev/null +++ b/drivers/sysreset/sysreset_tps65910.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <errno.h> +#include <sysreset.h> +#include <power/pmic.h> +#include <power/tps65910_pmic.h> + +static int tps65910_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + int val; + + val = pmic_reg_read(dev->parent, TPS65910_REG_DEVICE_CTRL); + if (val < 0) + return val; + + /* define power-off to be sequential */ + val |= PWR_OFF_SEQ; + pmic_reg_write(dev->parent, TPS65910_REG_DEVICE_CTRL, val); + + val &= ~DEV_ON; + + switch (type) { + case SYSRESET_POWER: + /* TPS65910: DEV_OFF_RST > DEVICE_CTRL */ + pmic_reg_write(dev->parent, TPS65910_REG_DEVICE_CTRL, + val | DEV_OFF_RST); + break; + case SYSRESET_POWER_OFF: + /* TPS65910: DEV_OFF > DEVICE_CTRL */ + pmic_reg_write(dev->parent, TPS65910_REG_DEVICE_CTRL, + val | DEV_OFF); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops tps65910_sysreset = { + .request = tps65910_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_tps65910) = { + .id = UCLASS_SYSRESET, + .name = TPS65910_RST_DRIVER, + .ops = &tps65910_sysreset, +}; diff --git a/drivers/sysreset/sysreset_tps80031.c b/drivers/sysreset/sysreset_tps80031.c new file mode 100644 index 00000000000..50024fe4e79 --- /dev/null +++ b/drivers/sysreset/sysreset_tps80031.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <dm.h> +#include <i2c.h> +#include <errno.h> +#include <sysreset.h> +#include <power/pmic.h> +#include <power/tps80031.h> + +static int tps80031_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + switch (type) { + case SYSRESET_POWER: + /* TPS80031: SW_RESET > PHOENIX_DEV_ON */ + pmic_reg_write(dev->parent, TPS80031_PHOENIX_DEV_ON, SW_RESET); + break; + case SYSRESET_POWER_OFF: + /* TPS80031: DEVOFF > PHOENIX_DEV_ON */ + pmic_reg_write(dev->parent, TPS80031_PHOENIX_DEV_ON, DEVOFF); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops tps80031_sysreset = { + .request = tps80031_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_tps80031) = { + .id = UCLASS_SYSRESET, + .name = TPS80031_RST_DRIVER, + .ops = &tps80031_sysreset, +}; diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c index 0b533d4c420..0ea17a909dd 100644 --- a/drivers/thermal/ti-bandgap.c +++ b/drivers/thermal/ti-bandgap.c @@ -1,7 +1,7 @@ /* * TI Bandgap temperature sensor driver * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/drivers/tpm/tpm2_tis_sandbox.c b/drivers/tpm/tpm2_tis_sandbox.c index e4004cfcca3..d15a28d9fc8 100644 --- a/drivers/tpm/tpm2_tis_sandbox.c +++ b/drivers/tpm/tpm2_tis_sandbox.c @@ -22,11 +22,6 @@ enum tpm2_hierarchy { TPM2_HIERARCHY_NB, }; -/* Subset of supported capabilities */ -enum tpm2_capability { - TPM_CAP_TPM_PROPERTIES = 0x6, -}; - /* Subset of supported properties */ #define TPM2_PROPERTIES_OFFSET 0x0000020E @@ -38,7 +33,8 @@ enum tpm2_cap_tpm_property { TPM2_PROPERTY_NB, }; -#define SANDBOX_TPM_PCR_NB 1 +#define SANDBOX_TPM_PCR_NB TPM2_MAX_PCRS +#define SANDBOX_TPM_PCR_SELECT_MAX ((SANDBOX_TPM_PCR_NB + 7) / 8) /* * Information about our TPM emulation. This is preserved in the sandbox @@ -433,7 +429,7 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8 *sendbuf, int i, j; /* TPM2_GetProperty */ - u32 capability, property, property_count; + u32 capability, property, property_count, val; /* TPM2_PCR_Read/Extend variables */ int pcr_index = 0; @@ -542,19 +538,32 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8 *sendbuf, case TPM2_CC_GET_CAPABILITY: capability = get_unaligned_be32(sent); sent += sizeof(capability); - if (capability != TPM_CAP_TPM_PROPERTIES) { - printf("Sandbox TPM only support TPM_CAPABILITIES\n"); - return TPM2_RC_HANDLE; - } - property = get_unaligned_be32(sent); sent += sizeof(property); - property -= TPM2_PROPERTIES_OFFSET; - property_count = get_unaligned_be32(sent); sent += sizeof(property_count); - if (!property_count || - property + property_count > TPM2_PROPERTY_NB) { + + switch (capability) { + case TPM2_CAP_PCRS: + break; + case TPM2_CAP_TPM_PROPERTIES: + if (!property_count) { + rc = TPM2_RC_HANDLE; + return sandbox_tpm2_fill_buf(recv, recv_len, + tag, rc); + } + + if (property >= TPM2_PROPERTIES_OFFSET && + ((property - TPM2_PROPERTIES_OFFSET) + + property_count > TPM2_PROPERTY_NB)) { + rc = TPM2_RC_HANDLE; + return sandbox_tpm2_fill_buf(recv, recv_len, + tag, rc); + } + break; + default: + printf("Sandbox TPM2 only supports TPM2_CAP_PCRS or " + "TPM2_CAP_TPM_PROPERTIES\n"); rc = TPM2_RC_HANDLE; return sandbox_tpm2_fill_buf(recv, recv_len, tag, rc); } @@ -578,18 +587,53 @@ static int sandbox_tpm2_xfer(struct udevice *dev, const u8 *sendbuf, put_unaligned_be32(capability, recv); recv += sizeof(capability); - /* Give the number of properties that follow */ - put_unaligned_be32(property_count, recv); - recv += sizeof(property_count); - - /* Fill with the properties */ - for (i = 0; i < property_count; i++) { - put_unaligned_be32(TPM2_PROPERTIES_OFFSET + property + - i, recv); - recv += sizeof(property); - put_unaligned_be32(tpm->properties[property + i], - recv); - recv += sizeof(property); + switch (capability) { + case TPM2_CAP_PCRS: + /* Give the number of algorithms supported - just SHA256 */ + put_unaligned_be32(1, recv); + recv += sizeof(u32); + + /* Give SHA256 algorithm */ + put_unaligned_be16(TPM2_ALG_SHA256, recv); + recv += sizeof(u16); + + /* Select the PCRs supported */ + *recv = SANDBOX_TPM_PCR_SELECT_MAX; + recv++; + + /* Activate all the PCR bits */ + for (i = 0; i < SANDBOX_TPM_PCR_SELECT_MAX; ++i) { + *recv = 0xff; + recv++; + } + break; + case TPM2_CAP_TPM_PROPERTIES: + /* Give the number of properties that follow */ + put_unaligned_be32(property_count, recv); + recv += sizeof(property_count); + + /* Fill with the properties */ + for (i = 0; i < property_count; i++) { + put_unaligned_be32(property + i, recv); + recv += sizeof(property); + if (property >= TPM2_PROPERTIES_OFFSET) { + val = tpm->properties[(property - + TPM2_PROPERTIES_OFFSET) + i]; + } else { + switch (property) { + case TPM2_PT_PCR_COUNT: + val = SANDBOX_TPM_PCR_NB; + break; + default: + val = 0xffffffff; + break; + } + } + + put_unaligned_be32(val, recv); + recv += sizeof(property); + } + break; } /* Add trailing \0 */ diff --git a/drivers/ufs/Makefile b/drivers/ufs/Makefile index 4f3344fd4e4..56a4b0776d3 100644 --- a/drivers/ufs/Makefile +++ b/drivers/ufs/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # -# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com +# Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com # obj-$(CONFIG_UFS) += ufs.o ufs-uclass.o diff --git a/drivers/ufs/cdns-platform.c b/drivers/ufs/cdns-platform.c index 1e62e252e7a..9202b53989d 100644 --- a/drivers/ufs/cdns-platform.c +++ b/drivers/ufs/cdns-platform.c @@ -2,7 +2,7 @@ /** * cdns-platform.c - Platform driver for Cadence UFSHCI device * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com */ #include <clk.h> diff --git a/drivers/ufs/ti-j721e-ufs.c b/drivers/ufs/ti-j721e-ufs.c index d875269760c..1860e0dca29 100644 --- a/drivers/ufs/ti-j721e-ufs.c +++ b/drivers/ufs/ti-j721e-ufs.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ #include <asm/io.h> diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c index ceea30c4a95..e6478a9209b 100644 --- a/drivers/ufs/ufs-uclass.c +++ b/drivers/ufs/ufs-uclass.c @@ -2,7 +2,7 @@ /** * ufs-uclass.c - Universal Flash Subsystem (UFS) Uclass driver * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com */ #define LOG_CATEGORY UCLASS_UFS diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index 7c48d57f99d..346f0fd916f 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c @@ -5,7 +5,7 @@ * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported * to u-boot. * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com */ #include <bouncebuf.h> diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c index 8958f0166bd..92a7941ed15 100644 --- a/drivers/usb/cdns3/cdns3-ti.c +++ b/drivers/usb/cdns3/cdns3-ti.c @@ -2,7 +2,7 @@ /** * cdns_ti-ti.c - TI specific Glue layer for Cadence USB Controller * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com */ #include <common.h> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 7ca9d09824e..3aec8b0d941 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -2,7 +2,7 @@ /** * core.c - DesignWare USB3 DRD Controller Core file * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com * * Authors: Felipe Balbi <balbi@ti.com>, * Sebastian Andrzej Siewior <bigeasy@linutronix.de> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 532746dd88d..4162a682298 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -2,7 +2,7 @@ /** * core.h - DesignWare USB3 DRD Core Header * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com * * Authors: Felipe Balbi <balbi@ti.com>, * Sebastian Andrzej Siewior <bigeasy@linutronix.de> diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index ff4ebfb4447..4fadb4a3e20 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -2,7 +2,7 @@ /** * dwc3-omap.c - OMAP Specific Glue layer * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com * * Authors: Felipe Balbi <balbi@ti.com>, * Sebastian Andrzej Siewior <bigeasy@linutronix.de> diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 75ac993bc64..1133cf82b1a 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -2,7 +2,7 @@ /** * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com * * Authors: Felipe Balbi <balbi@ti.com>, * Sebastian Andrzej Siewior <bigeasy@linutronix.de> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 68cf32cd189..406d36ceafe 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2,7 +2,7 @@ /** * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com * * Authors: Felipe Balbi <balbi@ti.com>, * Sebastian Andrzej Siewior <bigeasy@linutronix.de> diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h index 7806ce59a27..f28a9755dcb 100644 --- a/drivers/usb/dwc3/gadget.h +++ b/drivers/usb/dwc3/gadget.h @@ -2,7 +2,7 @@ /** * gadget.h - DesignWare USB3 DRD Gadget Header * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com * * Authors: Felipe Balbi <balbi@ti.com>, * Sebastian Andrzej Siewior <bigeasy@linutronix.de> diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 2407f826c16..04791d4c9be 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -2,7 +2,7 @@ /** * io.h - DesignWare USB3 DRD IO Header * - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com * * Authors: Felipe Balbi <balbi@ti.com>, * Sebastian Andrzej Siewior <bigeasy@linutronix.de> diff --git a/drivers/usb/dwc3/linux-compat.h b/drivers/usb/dwc3/linux-compat.h index 3bb0bda5a6b..563f8727cdd 100644 --- a/drivers/usb/dwc3/linux-compat.h +++ b/drivers/usb/dwc3/linux-compat.h @@ -2,7 +2,7 @@ /** * linux-compat.h - DesignWare USB3 Linux Compatibiltiy Adapter Header * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com * * Authors: Kishon Vijay Abraham I <kishon@ti.com> * diff --git a/drivers/usb/dwc3/ti_usb_phy.c b/drivers/usb/dwc3/ti_usb_phy.c index f476810763d..8ae130860f7 100644 --- a/drivers/usb/dwc3/ti_usb_phy.c +++ b/drivers/usb/dwc3/ti_usb_phy.c @@ -2,7 +2,7 @@ /** * ti_usb_phy.c - USB3 and USB3 PHY programming for dwc3 * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com * * Author: Kishon Vijay Abraham I <kishon@ti.com> * diff --git a/drivers/usb/gadget/udc/udc-core.c b/drivers/usb/gadget/udc/udc-core.c index 7f73926cb3e..eb0b35969ce 100644 --- a/drivers/usb/gadget/udc/udc-core.c +++ b/drivers/usb/gadget/udc/udc-core.c @@ -2,7 +2,7 @@ /** * udc-core.c - Core UDC Framework * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com * * Author: Felipe Balbi <balbi@ti.com> * diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c index 3e433129ace..30ee1cab066 100644 --- a/drivers/usb/gadget/udc/udc-uclass.c +++ b/drivers/usb/gadget/udc/udc-uclass.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com * Written by Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 1a883babf4c..b501ea514bc 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -231,7 +231,6 @@ config USB_EHCI_MXS config USB_EHCI_NPCM bool "Support for Nuvoton NPCM on-chip EHCI USB controller" depends on ARCH_NPCM - default n ---help--- Enables support for the on-chip EHCI controller on Nuvoton NPCM chips. @@ -368,7 +367,6 @@ config USB_OHCI_DA8XX config USB_OHCI_NPCM bool "Support for Nuvoton NPCM on-chip OHCI USB controller" depends on ARCH_NPCM - default n ---help--- Enables support for the on-chip OHCI controller on Nuvoton NPCM chips. diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index 66b3e96b007..f9df59d2e5d 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -2,7 +2,7 @@ /* * dwc3-of-simple.c - OF glue layer for simple integrations * - * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com * * Author: Felipe Balbi <balbi@ti.com> * diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c b/drivers/usb/ulpi/omap-ulpi-viewport.c index 8d71db04a2d..1b01cd4c559 100644 --- a/drivers/usb/ulpi/omap-ulpi-viewport.c +++ b/drivers/usb/ulpi/omap-ulpi-viewport.c @@ -3,7 +3,7 @@ * OMAP ulpi viewport support * Based on drivers/usb/ulpi/ulpi-viewport.c * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com * Author: Govindraj R <govindraj.raja@ti.com> */ diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig index 949b2884119..690e77ef8dc 100644 --- a/fs/ubifs/Kconfig +++ b/fs/ubifs/Kconfig @@ -8,7 +8,6 @@ config UBIFS_SILENCE_MSG config UBIFS_SILENCE_DEBUG_DUMP bool "UBIFS silence debug dumps" default y if UBIFS_SILENCE_MSG - default n help Make the debug dumps from UBIFS stop printing. This decreases size of U-Boot binary. diff --git a/include/blk.h b/include/blk.h index 76bd5baf995..7c7cf7f2b10 100644 --- a/include/blk.h +++ b/include/blk.h @@ -68,6 +68,7 @@ struct blk_desc { /* device can use 48bit addr (ATA/ATAPI v7) */ bool lba48; unsigned char atapi; /* Use ATAPI protocol */ + unsigned char bb; /* Use bounce buffer */ lbaint_t lba; /* number of blocks */ unsigned long blksz; /* block size */ int log2blksz; /* for convenience: log2(blksz) */ diff --git a/include/bootdev.h b/include/bootdev.h index b079a91b5b7..35fa25aff1d 100644 --- a/include/bootdev.h +++ b/include/bootdev.h @@ -65,7 +65,7 @@ struct bootdev_hunter; * * @info: Info structure describing this hunter * @show: true to show information from the hunter - * Returns: 0 if OK, -ve on error + * Returns: 0 if OK, -ENOENT on device not found, otherwise -ve on error */ typedef int (*bootdev_hunter_func)(struct bootdev_hunter *info, bool show); diff --git a/include/bootm.h b/include/bootm.h index c3c7336207b..10a1bd65a75 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -56,6 +56,17 @@ ulong bootm_disable_interrupts(void); int bootm_find_images(int flag, int argc, char *const argv[], ulong start, ulong size); +/* + * Measure the boot images. Measurement is the process of hashing some binary + * data and storing it into secure memory, i.e. TPM PCRs. In addition, each + * measurement is logged into the platform event log such that the operating + * system can access it and perform attestation of the boot. + * + * @images: The structure containing the various images to boot (linux, + * initrd, dts, etc.) + */ +int bootm_measure(struct bootm_headers *images); + int do_bootm_states(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[], int states, struct bootm_headers *images, int boot_progress); diff --git a/include/bootstage.h b/include/bootstage.h index f9376c320c9..affb0e5c6a6 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -11,6 +11,7 @@ #ifndef _BOOTSTAGE_H #define _BOOTSTAGE_H +#include <linux/types.h> #include <linux/kconfig.h> /* Flags for each bootstage record */ diff --git a/include/cache.h b/include/cache.h index b12fec25915..296ae3c8b48 100644 --- a/include/cache.h +++ b/include/cache.h @@ -6,6 +6,8 @@ #ifndef __CACHE_H #define __CACHE_H +#include <linux/types.h> + struct udevice; /* diff --git a/include/cbfs.h b/include/cbfs.h index 38efb1d2b02..2bc5de2297e 100644 --- a/include/cbfs.h +++ b/include/cbfs.h @@ -22,7 +22,7 @@ enum cbfs_result { enum cbfs_filetype { CBFS_TYPE_BOOTBLOCK = 0x01, CBFS_TYPE_CBFSHEADER = 0x02, - CBFS_TYPE_STAGE = 0x10, + CBFS_TYPE_LEGACY_STAGE = 0x10, CBFS_TYPE_PAYLOAD = 0x20, CBFS_TYPE_SELF = CBFS_TYPE_PAYLOAD, diff --git a/include/clk.h b/include/clk.h index d91285235f7..249c0e0ab42 100644 --- a/include/clk.h +++ b/include/clk.h @@ -223,9 +223,11 @@ struct clk *devm_clk_get(struct udevice *dev, const char *id); static inline struct clk *devm_clk_get_optional(struct udevice *dev, const char *id) { + int ret; struct clk *clk = devm_clk_get(dev, id); - if (PTR_ERR(clk) == -ENODATA) + ret = PTR_ERR(clk); + if (ret == -ENODATA || ret == -ENOENT) return NULL; return clk; @@ -243,7 +245,7 @@ static inline struct clk *devm_clk_get_optional(struct udevice *dev, * * Return: zero on success, or -ve error code. */ -int clk_release_all(struct clk *clk, int count); +int clk_release_all(struct clk *clk, unsigned int count); /** * devm_clk_put - "free" a managed clock source @@ -307,7 +309,7 @@ clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) return -ENOSYS; } -static inline int clk_release_all(struct clk *clk, int count) +static inline int clk_release_all(struct clk *clk, unsigned int count) { return -ENOSYS; } @@ -335,7 +337,7 @@ static inline int clk_get_by_name_optional(struct udevice *dev, int ret; ret = clk_get_by_name(dev, name, clk); - if (ret == -ENODATA) + if (ret == -ENODATA || ret == -ENOENT) return 0; return ret; @@ -359,7 +361,7 @@ static inline int clk_get_by_name_nodev_optional(ofnode node, const char *name, int ret; ret = clk_get_by_name_nodev(node, name, clk); - if (ret == -ENODATA) + if (ret == -ENODATA || ret == -ENOENT) return 0; return ret; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 504b1f02283..67f46562539 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -1,7 +1,7 @@ /* * am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index ee6f62275a8..dedef91ba59 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -6,7 +6,7 @@ * Based on: * am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_AM335X_SHC_H diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 7ee7b7e4f4f..983428920fa 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -2,7 +2,7 @@ /* * am43xx_evm.h * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_AM43XX_EVM_H diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 9e90239a1c1..811dc0ff1a8 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -2,7 +2,7 @@ /* * Configuration header file for K3 AM654 EVM * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/include/configs/arbel.h b/include/configs/arbel.h index 891257bc93a..576ee37ee4a 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -7,11 +7,15 @@ #define __CONFIG_ARBEL_H #define CFG_SYS_SDRAM_BASE 0x0 -#define CFG_SYS_BOOTMAPSZ (30 << 20) +#define CFG_SYS_BOOTMAPSZ (128 << 20) #define CFG_SYS_BOOTM_LEN (20 << 20) #define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE #define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_BAUDRATE_TABLE \ + { 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 } + + /* Default environemnt variables */ #define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \ "stdin=serial\0" \ diff --git a/include/configs/baltos.h b/include/configs/baltos.h index e7946389eff..cc54b514fff 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -1,7 +1,7 @@ /* * am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h index 3347c11792d..3ada21cbba1 100644 --- a/include/configs/corstone1000.h +++ b/include/configs/corstone1000.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2022 ARM Limited + * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> * (C) Copyright 2022 Linaro * Rui Miguel Silva <rui.silva@linaro.org> * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> @@ -29,5 +29,6 @@ #include <config_distro_bootcmd.h> +#define CFG_EXTRA_ENV_SETTINGS BOOTENV #endif diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index cef404218ed..416aa96366c 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * * Based on davinci_dvevm.h. Original Copyrights follow: * diff --git a/include/configs/draco.h b/include/configs/draco.h index 4c67174572f..8f993cee0a3 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -6,7 +6,7 @@ * Based on: * U-Boot file:/include/configs/am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_DRACO_H diff --git a/include/configs/etamin.h b/include/configs/etamin.h index d07b4e95364..97585a4fd12 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -6,7 +6,7 @@ * Based on: * U-Boot file:/include/configs/am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_ETAMIN_H diff --git a/include/configs/inteno_xg6846.h b/include/configs/inteno_xg6846.h new file mode 100644 index 00000000000..4f2a2f84010 --- /dev/null +++ b/include/configs/inteno_xg6846.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023 Linus Walleij <linusw@kernel.org> + */ + +#include <configs/bmips_common.h> +#include <configs/bmips_bcm6328.h> + diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 4968722d18f..94a9c767882 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -15,6 +15,15 @@ #include <configs/ti_armv7_common.h> +/* allow up to 3 USB storage devices */ +#ifdef CONFIG_CMD_USB +#undef BOOT_TARGET_USB +#define BOOT_TARGET_USB(func) \ + func(USB, usb, 0) \ + func(USB, usb, 1) \ + func(USB, usb, 2) +#endif + /* * This defines all MMC devices, even if the basic variant has no mmc1. * The non-supported device will be removed from the boot targets during diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index ff966586ba6..a50f9480dd9 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -4,7 +4,7 @@ * * Based on da850evm.h * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * * Based on davinci_dvevm.h. Original Copyrights follow: * diff --git a/include/configs/libretech-ac.h b/include/configs/libretech-ac.h index bf20d315430..16239f25202 100644 --- a/include/configs/libretech-ac.h +++ b/include/configs/libretech-ac.h @@ -11,6 +11,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(ROMUSB, romusb, na) \ + func(USB_DFU, usbdfu, na) \ func(MMC, mmc, 0) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \ diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 801cdae4708..efab9a624dc 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -53,6 +53,30 @@ #define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance) \ "romusb " +/* + * Fallback to "USB DFU" boot if script is not at scriptaddr + * + * DFU will expose the kernel_addr_r memory range as DFU entry, + * then with `dfu-util --detach`, booting the uploaded image + * will be attempted: + * $ dfu-util -a 0 -D fitImage + * $ dfu-util -a 0 -e + */ +#if CONFIG_IS_ENABLED(USB_GADGET) && CONFIG_IS_ENABLED(DFU_RAM) + #define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \ + "bootcmd_usbdfu=" \ + "if test \"${boot_source}\" = \"usb\"; then " \ + "dfu 0 ram 0 60;" \ + "bootm ${kernel_addr_r};" \ + "fi\0" + + #define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) \ + "usbdfu " +#else + #define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) + #define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) +#endif + #ifdef CONFIG_CMD_USB #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) #else @@ -74,6 +98,7 @@ #ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(ROMUSB, romusb, na) \ + func(USB_DFU, usbdfu, na) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ @@ -84,6 +109,15 @@ func(DHCP, dhcp, na) #endif +#define BOOTM_SIZE __stringify(0x1700000) +#define KERNEL_ADDR_R __stringify(0x08080000) +#define KERNEL_COMP_ADDR_R __stringify(0x0d080000) +#define FDT_ADDR_R __stringify(0x08008000) +#define SCRIPT_ADDR_R __stringify(0x08000000) +#define PXEFILE_ADDR_R __stringify(0x01080000) +#define FDTOVERLAY_ADDR_R __stringify(0x01000000) +#define RAMDISK_ADDR_R __stringify(0x13000000) + #include <config_distro_bootcmd.h> #ifndef CFG_EXTRA_ENV_SETTINGS @@ -91,15 +125,16 @@ "stdin=" STDIN_CFG "\0" \ "stdout=" STDOUT_CFG "\0" \ "stderr=" STDOUT_CFG "\0" \ - "kernel_comp_addr_r=0x0d080000\0" \ + "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ "kernel_comp_size=0x2000000\0" \ - "fdt_addr_r=0x08008000\0" \ - "scriptaddr=0x08000000\0" \ - "kernel_addr_r=0x08080000\0" \ - "pxefile_addr_r=0x01080000\0" \ - "fdtoverlay_addr_r=0x01000000\0" \ - "ramdisk_addr_r=0x13000000\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ + "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "dfu_alt_info=fitimage ram " KERNEL_ADDR_R " 0x4000000 \0" \ BOOTENV #endif diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 76e148f55eb..18b55be0d8c 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -30,7 +30,6 @@ /* * Environment */ -#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */ #ifdef CONFIG_MMC #define BOOT_TARGET_DEVICES_MMC(func, i) func(MMC, mmc, i) diff --git a/include/configs/nanopc-t6-rk3588.h b/include/configs/nanopc-t6-rk3588.h new file mode 100644 index 00000000000..1ece6f9383f --- /dev/null +++ b/include/configs/nanopc-t6-rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#ifndef __NANOPCT6_RK3588_H +#define __NANOPCT6_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __NANOPCT6_RK3588_H */ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index fa029a176bd..8c4d03553d3 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi@gmail.com> + * Copyright (C) 2015, 2021-2023 Tony Dinh <mibodhi@gmail.com> * Copyright (C) 2015 * Gerald Kerma <dreagle@doukki.net> * Luka Perkov <luka.perkov@sartura.hr> @@ -15,14 +15,6 @@ */ #include "mv-common.h" -/* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(SATA, sata, 0) \ - func(DHCP, dhcp, na) - #define KERNEL_ADDR_R __stringify(0x800000) #define FDT_ADDR_R __stringify(0x2c00000) #define RAMDISK_ADDR_R __stringify(0x01100000) @@ -34,16 +26,11 @@ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ "scriptaddr=" SCRIPT_ADDR_R "\0" -#include <config_distro_bootcmd.h> - #define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/zImage\0" \ "fdt=/boot/nsa310s.dtb\0" \ "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" \ - LOAD_ADDRESS_ENV_SETTINGS \ - BOOTENV - -#endif /* CONFIG_SPL_BUILD */ + LOAD_ADDRESS_ENV_SETTINGS #endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index f44967787c9..2cb2e52ad25 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -2,7 +2,7 @@ /* * Configuration settings for the TI OMAP3 EVM board. * - * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2006-2011 Texas Instruments Incorporated - https://www.ti.com/ * * Author : * Manikandan Pillai <mani.pillai@ti.com> diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index fc2655a17b9..5b7eb0b6946 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * * Based on davinci_dvevm.h. Original Copyrights follow: * diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index 80b14b002a9..24d7dcd427c 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -4,7 +4,7 @@ * * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_PDU001_H diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index 8668da6eba5..060a1509657 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -4,7 +4,7 @@ * * Phytec phyCORE-AM335x R2 (PCL060 / PCM060) boards information header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH * Copyright (C) 2019 DENX Software Engineering GmbH */ diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h index 33715790233..d5003538da3 100644 --- a/include/configs/pogo_v4.h +++ b/include/configs/pogo_v4.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014-2022 Tony Dinh <mibodhi@gmail.com> + * Copyright (C) 2014-2023 Tony Dinh <mibodhi@gmail.com> * * Based on * Copyright (C) 2012 @@ -21,33 +21,6 @@ */ #include "mv-common.h" -/* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - -#ifdef CONFIG_MMC -#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) -#else -#define BOOT_TARGET_DEVICES_MMC(func) -#endif - -#ifdef CONFIG_SATA -#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0) -#else -#define BOOT_TARGET_DEVICES_SATA(func) -#endif - -#ifdef CONFIG_USB_STORAGE -#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_DEVICES_USB(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_DEVICES_MMC(func) \ - BOOT_TARGET_DEVICES_USB(func) \ - BOOT_TARGET_DEVICES_SATA(func) \ - func(DHCP, dhcp, na) - #define KERNEL_ADDR_R __stringify(0x800000) #define FDT_ADDR_R __stringify(0x2c00000) #define RAMDISK_ADDR_R __stringify(0x01100000) @@ -59,14 +32,10 @@ "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ "scriptaddr=" SCRIPT_ADDR_R "\0" -#include <config_distro_bootcmd.h> - #define CFG_EXTRA_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "console=ttyS0,115200\0" \ - BOOTENV -#endif /* CONFIG_SPL_BUILD */ + "console=ttyS0,115200\0" #endif /* _CONFIG_POGO_V4_H */ diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 1e96e838be4..2a2d85c8ec6 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -13,6 +13,8 @@ #define CFG_SYS_BOOTMAPSZ (0x30 << 20) #define CFG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_BAUDRATE_TABLE { 57600, 115200, 230400, 460800 } + /* Default environemnt variables */ #define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ "stdin=serial\0" \ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index b701e52076d..040178baf84 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -7,7 +7,7 @@ * Based on: * U-Boot file:/include/configs/am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_PXM2_H diff --git a/include/configs/quartzpro64-rk3588.h b/include/configs/quartzpro64-rk3588.h new file mode 100644 index 00000000000..a1faa2aad85 --- /dev/null +++ b/include/configs/quartzpro64-rk3588.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * Copyright 2023 Google, Inc + */ + +#ifndef __QUARTZPRO64_RK3588_H +#define __QUARTZPRO64_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __QUARTZPRO64_RK3588_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 2efb4d23cdd..0991ebfd00c 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -6,7 +6,7 @@ * Based on: * U-Boot file:/include/configs/am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_RASTABAN_H diff --git a/include/configs/rut.h b/include/configs/rut.h index 4002bc4b6c8..7cc2bd5a341 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -7,7 +7,7 @@ * Based on: * U-Boot file:/include/configs/am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_RUT_H diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 7def657bcd1..6b1d5caafb1 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -7,7 +7,7 @@ * Based on: * U-Boot file:/include/configs/am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_SIEMENS_AM33X_COMMON_H diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 74150b7d4b0..de8bfc1123b 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -36,7 +36,7 @@ "name=system,size=-,bootable,type=${type_guid_gpt_system};" #define CFG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x84000000\0" \ + "kernel_addr_r=0x80200000\0" \ "kernel_comp_addr_r=0x88000000\0" \ "kernel_comp_size=0x4000000\0" \ "fdt_addr_r=0x8c000000\0" \ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index cd7359c2f8a..e36e63e81e4 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -41,20 +41,6 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ #ifdef CONFIG_FWU_MULTI_BANK_UPDATE -#define DEFAULT_DFU_ALT_INFO -#else -#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ - "mtd nor1=u-boot.bin raw 200000 100000;" \ - "fip.bin raw 180000 78000;" \ - "optee.bin raw 500000 100000\0" -#endif - -/* GUIDs for capsule updatable firmware images */ -#define DEVELOPERBOX_UBOOT_IMAGE_GUID \ - EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \ - 0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00) - -#ifdef CONFIG_FWU_MULTI_BANK_UPDATE #define DEVELOPERBOX_FIP_IMAGE_GUID \ EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \ 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08) @@ -64,10 +50,6 @@ 0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98) #endif -#define DEVELOPERBOX_OPTEE_IMAGE_GUID \ - EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \ - 0xf0, 0xa3, 0x83, 0x87, 0xe6, 0x30) - /* Distro boot settings */ #ifdef CONFIG_CMD_USB #define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) @@ -107,7 +89,6 @@ "ramdisk_addr_r=0xa0000000\0" \ "scriptaddr=0x88000000\0" \ "pxefile_addr_r=0x88100000\0" \ - DEFAULT_DFU_ALT_INFO \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index a5913e1e7d2..f4c04c55ebf 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -6,7 +6,7 @@ * Based on: * U-Boot file:/include/configs/am335x_evm.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __CONFIG_THUBAN_H diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 20f8643771d..c827a9cace9 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -2,10 +2,10 @@ /* * ti_am335x_common.h * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * For more details, please see the technical documents listed at - * http://www.ti.com/product/am3359#technicaldocuments + * https://www.ti.com/product/am3359#technicaldocuments */ #ifndef __CONFIG_TI_AM335X_COMMON_H__ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 4e30d0d2ddf..3def7b1027e 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -2,7 +2,7 @@ /* * ti_armv7_common.h * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * The various ARMv7 SoCs from TI all share a number of IP blocks when * implementing a given feature. Rather than define these in every diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h index d34042af468..0b8b1ac8f9a 100644 --- a/include/configs/ti_armv7_omap.h +++ b/include/configs/ti_armv7_omap.h @@ -2,7 +2,7 @@ /* * ti_armv7_omap.h * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/ * * The various ARMv7 SoCs from TI all share a number of IP blocks when * implementing a given feature. This is meant to isolate the features diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 36a05b6896e..45f7179f035 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -2,12 +2,12 @@ /* * ti_omap3_common.h * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * For more details, please see the technical documents listed at - * http://www.ti.com/product/omap3530 - * http://www.ti.com/product/omap3630 - * http://www.ti.com/product/dm3730 + * https://www.ti.com/product/omap3530 + * https://www.ti.com/product/omap3630 + * https://www.ti.com/product/dm3730 */ #ifndef __CONFIG_TI_OMAP3_COMMON_H__ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 4e5aa74147d..26494ae9801 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -10,7 +10,7 @@ * TI OMAP5 AND DRA7XX common configuration settings * * For more details, please see the technical documents listed at - * http://www.ti.com/product/omap5432 + * https://www.ti.com/product/omap5432 */ #ifndef __CONFIG_TI_OMAP5_COMMON_H diff --git a/include/configs/transformer-common.h b/include/configs/transformer-common.h index dcdda1ec5b4..3b7db0ab142 100644 --- a/include/configs/transformer-common.h +++ b/include/configs/transformer-common.h @@ -64,19 +64,14 @@ "else echo SPI flash backup FAILED! Aborting ...;" \ "poweroff; fi\0" -#define TRANSFORMER_REFRESH_USB \ - "refresh_usb=usb start; usb reset; usb tree; usb info;" \ - "pause 'Press ANY key to return to bootmenu...'; bootmenu\0" - #define TRANSFORMER_BOOTMENU \ TRANSFORMER_FLASH_UBOOT \ TRANSFORMER_FLASH_SPI \ - TRANSFORMER_REFRESH_USB \ "bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu\0" \ "bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu\0" \ "bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu\0" \ "bootmenu_3=update bootloader=run flash_uboot\0" \ - "bootmenu_4=refresh USB=run refresh_usb\0" \ + "bootmenu_4=enter console=usb start; setenv skip_boot 1; exit\0" \ "bootmenu_5=reboot RCM=enterrcm\0" \ "bootmenu_6=reboot=reset\0" \ "bootmenu_7=power off=poweroff\0" \ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 43f7e454d81..24d8ca08665 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -148,6 +148,12 @@ #define FUNC_VIRTIO(func) #endif +#ifdef CONFIG_CMD_MMC +#define FUNC_MMC(func) func(MMC, mmc, 0) +#else +#define FUNC_MMC(func) +#endif + /* * Boot by loading an Android image, or kernel, initrd and FDT through * semihosting into DRAM. @@ -204,6 +210,7 @@ func(SMH, smh, na) \ func(MEM, mem, na) \ FUNC_VIRTIO(func) \ + FUNC_MMC(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/cpsw.h b/include/cpsw.h index 786f8b385b7..5e0509923b5 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -1,7 +1,7 @@ /* * CPSW Ethernet Switch Driver * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/include/cpu.h b/include/cpu.h index be02a167129..2077ff30634 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -7,6 +7,8 @@ #ifndef __CPU_H #define __CPU_H +#include <linux/types.h> + struct udevice; /** diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 19e97a90327..5795115c490 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -977,12 +977,22 @@ const char *ofnode_read_chosen_string(const char *propname); ofnode ofnode_get_chosen_node(const char *propname); /** - * ofnode_read_aliases_prop() - get the value of a aliases property + * ofnode_read_baud() - get the baudrate from string value of chosen property * - * This looks for a property within the /aliases node and returns its value + * This looks for stdout-path property within the /chosen node and parses its + * value to return baudrate. * * This only works with the control FDT. * + * Return: baudrate value if found, else -ve error code + */ +int ofnode_read_baud(void); + +/** + * ofnode_read_aliases_prop() - get the value of a aliases property + * + * This looks for a property within the /aliases node and returns its value + * * @propname: Property name to look for * @sizep: Returns size of property, or `FDT_ERR_...` error code if function * returns NULL diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index a6045f5cc8c..5271e646bb1 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -121,6 +121,7 @@ enum uclass_id { UCLASS_REGULATOR, /* Regulator device */ UCLASS_REMOTEPROC, /* Remote Processor device */ UCLASS_RESET, /* Reset controller device */ + UCLASS_RKMTD, /* Rockchip MTD device */ UCLASS_RNG, /* Random Number Generator */ UCLASS_RTC, /* Real time clock device */ UCLASS_SCMI_AGENT, /* Interface with an SCMI server */ diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h index 3be89a7c20a..9a0d33d027f 100644 --- a/include/dt-bindings/leds/common.h +++ b/include/dt-bindings/leds/common.h @@ -33,7 +33,12 @@ #define LED_COLOR_ID_MULTI 8 /* For multicolor LEDs */ #define LED_COLOR_ID_RGB 9 /* For multicolor LEDs that can do arbitrary color, so this would include RGBW and similar */ -#define LED_COLOR_ID_MAX 10 +#define LED_COLOR_ID_PURPLE 10 +#define LED_COLOR_ID_ORANGE 11 +#define LED_COLOR_ID_PINK 12 +#define LED_COLOR_ID_CYAN 13 +#define LED_COLOR_ID_LIME 14 +#define LED_COLOR_ID_MAX 15 /* Standard LED functions */ /* Keyboard LEDs, usually it would be input4::capslock etc. */ diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h index 61f5287d752..c340437414f 100644 --- a/include/dt-bindings/net/mscc-phy-vsc8531.h +++ b/include/dt-bindings/net/mscc-phy-vsc8531.h @@ -28,13 +28,4 @@ #define VSC8531_FORCE_LED_OFF 14 #define VSC8531_FORCE_LED_ON 15 -#define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 -#define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 -#define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 -#define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 -#define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 -#define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 -#define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 -#define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 - #endif diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h index b543eebd2f0..765c385f7b2 100644 --- a/include/dt-bindings/pinctrl/dra.h +++ b/include/dt-bindings/pinctrl/dra.h @@ -1,7 +1,7 @@ /* * This header provides constants for DRA pinctrl bindings. * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Author: Rajendra Nayak <rnayak@ti.com> * * This program is free software; you can redistribute it and/or modify diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h index 884fd91df8e..1427ff140f1 100644 --- a/include/dt-bindings/reset/ti-syscon.h +++ b/include/dt-bindings/reset/ti-syscon.h @@ -1,7 +1,7 @@ /* * TI Syscon Reset definitions * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/include/dwc3-omap-uboot.h b/include/dwc3-omap-uboot.h index 9e0e717dc98..ed92bfc5a97 100644 --- a/include/dwc3-omap-uboot.h +++ b/include/dwc3-omap-uboot.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* include/dwc3_omap_uboot.h * - * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com * * Designware SuperSpeed OMAP Glue uboot init */ diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index bb0436c0973..35cfbb93b29 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* include/dwc3-uboot.h * - * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com * * Designware SuperSpeed USB uboot init */ diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index b1c3abd0975..b21c5cb3dd6 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -129,50 +129,6 @@ struct efi_tcg2_boot_service_capability { #define BOOT_SERVICE_CAPABILITY_MIN \ offsetof(struct efi_tcg2_boot_service_capability, number_of_pcr_banks) -#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03" -#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2 -#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0 -#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2 - -/** - * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information - * - * @algorithm_id: algorithm defined in enum tpm2_algorithms - * @digest_size: size of the algorithm - */ -struct tcg_efi_spec_id_event_algorithm_size { - u16 algorithm_id; - u16 digest_size; -} __packed; - -/** - * struct TCG_EfiSpecIDEventStruct - content of the event log header - * - * @signature: signature, set to Spec ID Event03 - * @platform_class: class defined in TCG ACPI Specification - * Client Common Header. - * @spec_version_minor: minor version - * @spec_version_major: major version - * @spec_version_errata: major version - * @uintn_size: size of the efi_uintn_t fields used in various - * data structures used in this specification. - * 0x01 indicates u32 and 0x02 indicates u64 - * @number_of_algorithms: hashing algorithms used in this event log - * @digest_sizes: array of number_of_algorithms pairs - * 1st member defines the algorithm id - * 2nd member defines the algorithm size - */ -struct tcg_efi_spec_id_event { - u8 signature[16]; - u32 platform_class; - u8 spec_version_minor; - u8 spec_version_major; - u8 spec_errata; - u8 uintn_size; - u32 number_of_algorithms; - struct tcg_efi_spec_id_event_algorithm_size digest_sizes[]; -} __packed; - /** * struct tdEFI_TCG2_FINAL_EVENTS_TABLE - log entries after Get Event Log * @version: version number for this structure diff --git a/include/env/ti/dfu.h b/include/env/ti/dfu.h index 3c90570107e..10bcf33c630 100644 --- a/include/env/ti/dfu.h +++ b/include/env/ti/dfu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com * * Environment variable definitions for DFU on TI boards. */ diff --git a/include/env/ti/k3_dfu.h b/include/env/ti/k3_dfu.h index a16a3adecaf..098f5f5dabd 100644 --- a/include/env/ti/k3_dfu.h +++ b/include/env/ti/k3_dfu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * * Environment variable definitions for DFU on TI K3 SoCs. * diff --git a/include/env/ti/k3_rproc.h b/include/env/ti/k3_rproc.h index 3418cb42be5..a467d751e2d 100644 --- a/include/env/ti/k3_rproc.h +++ b/include/env/ti/k3_rproc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * * rproc environment variable definitions for various TI K3 SoCs. */ diff --git a/include/env/ti/mmc.h b/include/env/ti/mmc.h index 769ea9d5ef7..d07189baaf4 100644 --- a/include/env/ti/mmc.h +++ b/include/env/ti/mmc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com * * Environment variable definitions for MMC/SD on TI boards. */ diff --git a/include/env/ti/nand.h b/include/env/ti/nand.h index 7d00afa2b10..0e0da458b90 100644 --- a/include/env/ti/nand.h +++ b/include/env/ti/nand.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * * Environment variable definitions for NAND on TI boards. */ diff --git a/include/env/ti/ufs.h b/include/env/ti/ufs.h index 6619ec9c88e..c192f3aee18 100644 --- a/include/env/ti/ufs.h +++ b/include/env/ti/ufs.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com * * Environment variable definitions for UFS on TI boards. */ diff --git a/include/env_default.h b/include/env_default.h index b16c22d5a28..2ca4a087d3b 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -21,7 +21,7 @@ env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = { { #elif defined(DEFAULT_ENV_INSTANCE_STATIC) static char default_environment[] = { -#elif defined(DEFAULT_ENV_IS_RW) +#elif defined(CONFIG_DEFAULT_ENV_IS_RW) char default_environment[] = { #else const char default_environment[] = { @@ -42,7 +42,7 @@ const char default_environment[] = { #if defined(CONFIG_BOOTDELAY) "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0" #endif -#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) +#if !defined(CONFIG_OF_SERIAL_BAUD) && defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0) "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" #endif #ifdef CONFIG_LOADS_ECHO @@ -119,6 +119,10 @@ const char default_environment[] = { #ifdef CFG_EXTRA_ENV_SETTINGS CFG_EXTRA_ENV_SETTINGS #endif +#ifdef CONFIG_OF_SERIAL_BAUD + /* Padding for baudrate at the end when environment is writable */ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" +#endif "\0" #else /* CONFIG_USE_DEFAULT_ENV_FILE */ #include "generated/defaultenv_autogenerated.h" diff --git a/include/env_internal.h b/include/env_internal.h index 6a694946468..fcb464263f0 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -89,7 +89,7 @@ typedef struct environment_s { extern env_t embedded_environment; #endif /* ENV_IS_EMBEDDED */ -#ifdef DEFAULT_ENV_IS_RW +#ifdef CONFIG_DEFAULT_ENV_IS_RW extern char default_environment[]; #else extern const char default_environment[]; diff --git a/include/generic-phy.h b/include/generic-phy.h index bee4de8a0ba..eaab7491660 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/include/i2c.h b/include/i2c.h index ef3820eaba7..4e59009cd93 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -538,6 +538,18 @@ int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, struct udevice **devp); /** + * i2c_get_chip_by_phandle() - get a device to use to access a chip + * based on a phandle property pointing to it + * + * @parent: Parent device containing the phandle pointer + * @name: Name of phandle property in the parent device node + * @devp: Returns pointer to new device or NULL if not found + * Return: 0 on success, -ve on failure + */ +int i2c_get_chip_by_phandle(const struct udevice *parent, const char *prop_name, + struct udevice **devp); + +/** * i2c_chip_of_to_plat() - Decode standard I2C platform data * * This decodes the chip address from a device tree node and puts it into diff --git a/include/image.h b/include/image.h index 5f85bf84a2d..2e3cf839ee3 100644 --- a/include/image.h +++ b/include/image.h @@ -409,6 +409,7 @@ struct bootm_headers { #define BOOTM_STATE_OS_FAKE_GO 0x00000200 /* 'Almost' run the OS */ #define BOOTM_STATE_OS_GO 0x00000400 #define BOOTM_STATE_PRE_LOAD 0x00000800 +#define BOOTM_STATE_MEASURE 0x00001000 int state; #if defined(CONFIG_LMB) && !defined(USE_HOSTCC) diff --git a/include/interrupt.h b/include/interrupt.h new file mode 100644 index 00000000000..46ef2e196d4 --- /dev/null +++ b/include/interrupt.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <asm/setjmp.h> + +/** + * struct resume_data - data for resume after interrupt + */ +struct resume_data { + /** @jump: longjmp buffer */ + jmp_buf jump; + /** @code: exception code */ + ulong code; +}; + +/** + * set_resume() - set longjmp buffer for resuming after exception + * + * By calling this function it is possible to use a long jump to catch an + * exception. The caller sets the long jump buffer with set_resume() and then + * executes setjmp(). If an exception occurs, the code will return to the + * setjmp caller(). The exception code will be returned in @data->code. + * + * After the critical operation call set_resume(NULL) so that an exception in + * another part of the code will not accidently invoke the long jump. + * + * .. code-block:: c + * + * // This example shows how to use set_resume(). + * + * struct resume_data resume; + * int ret; + * + * set_resume(&resume); + * ret = setjmp(resume.jump); + * if (ret) { + * printf("An exception %ld occurred\n", resume.code); + * } else { + * // Do what might raise an exception here. + * } + * set_resume(NULL); + * + * @data: pointer to structure with longjmp address + * Return: 0 before an exception, 1 after an exception occurred + */ +void set_resume(struct resume_data *data); diff --git a/include/k3-avs.h b/include/k3-avs.h index e3c3cafbb9d..1014d5d114d 100644 --- a/include/k3-avs.h +++ b/include/k3-avs.h @@ -2,7 +2,7 @@ /* * Texas Instruments' K3 Adaptive Voltage Scaling driver * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * Tero Kristo <t-kristo@ti.com> * */ diff --git a/include/k3-clk.h b/include/k3-clk.h index 49ba53d20f7..1b6ab8fe654 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2020-2021 Texas Instruments Incorporated - http://www.ti.com + * (C) Copyright 2020-2021 Texas Instruments Incorporated - https://www.ti.com * Tero Kristo <t-kristo@ti.com> */ diff --git a/include/k3-dev.h b/include/k3-dev.h index d288ae3be73..072e10ba632 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -2,7 +2,7 @@ /* * Texas Instruments K3 Device Platform Data * - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef __K3_DEV_H__ #define __K3_DEV_H__ diff --git a/include/linux/soc/ti/cppi5.h b/include/linux/soc/ti/cppi5.h index 3a55c3ec46f..c5d7ebd05d7 100644 --- a/include/linux/soc/ti/cppi5.h +++ b/include/linux/soc/ti/cppi5.h @@ -2,7 +2,7 @@ /* * CPPI5 descriptors interface * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com */ #ifndef __TI_CPPI5_H__ diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h index 0ad8f203da1..30fb903d972 100644 --- a/include/linux/soc/ti/k3-navss-ringacc.h +++ b/include/linux/soc/ti/k3-navss-ringacc.h @@ -2,7 +2,7 @@ /* * TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com */ #ifndef __SOC_TI_K3_NAVSS_RINGACC_API_H_ diff --git a/include/linux/soc/ti/k3-sec-proxy.h b/include/linux/soc/ti/k3-sec-proxy.h index f34854ceebc..c3a83f163d7 100644 --- a/include/linux/soc/ti/k3-sec-proxy.h +++ b/include/linux/soc/ti/k3-sec-proxy.h @@ -2,7 +2,7 @@ /* * Texas Instruments' K3 Secure proxy * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> * */ diff --git a/include/linux/soc/ti/ti-udma.h b/include/linux/soc/ti/ti-udma.h index 04e354fb2d6..89faf69242f 100644 --- a/include/linux/soc/ti/ti-udma.h +++ b/include/linux/soc/ti/ti-udma.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> */ diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 7f9941894cd..8e4c43cef31 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -3,7 +3,7 @@ * Texas Instruments System Control Interface Protocol * Based on include/linux/soc/ti/ti_sci_protocol.h from Linux. * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ * Nishanth Menon * Lokesh Vutla <lokeshvutla@ti.com> */ diff --git a/include/linux/usb/dwc3-omap.h b/include/linux/usb/dwc3-omap.h index 62180e3973b..d5737ed7e88 100644 --- a/include/linux/usb/dwc3-omap.h +++ b/include/linux/usb/dwc3-omap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* include/linux/usb/dwc3-omap.h * - * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2014 Texas Instruments Incorporated - https://www.ti.com * * Designware SuperSpeed Glue */ diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h index 5d0dac950ef..e7e3d259cae 100644 --- a/include/linux/usb/otg.h +++ b/include/linux/usb/otg.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* include/linux/usb/otg.h * - * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com * * USB OTG (On The Go) defines */ diff --git a/include/mux-internal.h b/include/mux-internal.h index 93e3a5cdd74..67fa28933c7 100644 --- a/include/mux-internal.h +++ b/include/mux-internal.h @@ -5,7 +5,7 @@ * Copyright (C) 2017 Axentia Technologies AB * Author: Peter Rosin <peda@axentia.se> * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/include/mux.h b/include/mux.h index c92d887591e..e5deaba66f4 100644 --- a/include/mux.h +++ b/include/mux.h @@ -10,7 +10,7 @@ * Copyright (C) 2017 Axentia Technologies AB * Author: Peter Rosin <peda@axentia.se> * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/include/net.h b/include/net.h index e254df7d7f4..e63a946002d 100644 --- a/include/net.h +++ b/include/net.h @@ -16,6 +16,7 @@ #include <asm/cache.h> #include <asm/byteorder.h> /* for nton* / ntoh* stuff */ #include <env.h> +#include <hexdump.h> #include <log.h> #include <time.h> #include <linux/if_ether.h> @@ -29,6 +30,7 @@ struct udevice; #define DEBUG_DEV_PKT 0 /* Packets or info directed to the device */ #define DEBUG_NET_PKT 0 /* Packets on info on the network at large */ #define DEBUG_INT_STATE 0 /* Internal network state changes */ +#define DEBUG_NET_PKT_TRACE 0 /* Trace all packet data */ /* * The number of receive packet buffers, and the required packet buffer @@ -640,6 +642,8 @@ uchar * net_get_async_tx_pkt_buf(void); /* Transmit a packet */ static inline void net_send_packet(uchar *pkt, int len) { + if (DEBUG_NET_PKT_TRACE) + print_hex_dump_bytes("tx: ", DUMP_PREFIX_OFFSET, pkt, len); /* Currently no way to return errors from eth_send() */ (void) eth_send(pkt, len); } diff --git a/include/power/max77663.h b/include/power/max77663.h new file mode 100644 index 00000000000..b3ae3dabf46 --- /dev/null +++ b/include/power/max77663.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef _MAX77663_H_ +#define _MAX77663_H_ + +#define MAX77663_LDO_NUM 9 +#define MAX77663_SD_NUM 5 + +/* Drivers name */ +#define MAX77663_LDO_DRIVER "max77663_ldo" +#define MAX77663_SD_DRIVER "max77663_sd" +#define MAX77663_RST_DRIVER "max77663_rst" + +/* Step-Down (SD) Regulator calculations */ +#define SD_STATUS_MASK 0x30 + +#define SD0_VOLT_MAX_HEX 0x40 +#define SD1_VOLT_MAX_HEX 0x4c +#define SD_VOLT_MAX_HEX 0xff +#define SD_VOLT_MIN_HEX 0x02 + +#define SD0_VOLT_MAX 1400000 +#define SD1_VOLT_MAX 1550000 +#define SD_VOLT_MAX 3787500 +#define SD_VOLT_MIN 625000 + +#define SD_VOLT_BASE 600000 + +/* Low-Dropout Linear (LDO) Regulator calculations */ +#define LDO_STATUS_MASK 0xc0 +#define LDO_VOLT_MASK 0x3f +#define LDO_VOLT_MAX_HEX 0x3f + +#define LDO01_VOLT_MAX 2375000 +#define LDO4_VOLT_MAX 1587500 +#define LDO_VOLT_MAX 3950000 + +#define LDO_VOLT_BASE 800000 + +#define MAX77663_REG_ONOFF_CFG1 0x41 +#define ONOFF_SFT_RST BIT(7) +#define ONOFF_PWR_OFF BIT(1) + +#endif /* _MAX77663_H_ */ diff --git a/include/power/palmas.h b/include/power/palmas.h index df5f15c5bd6..0a612052f01 100644 --- a/include/power/palmas.h +++ b/include/power/palmas.h @@ -2,6 +2,10 @@ #define TPS659038 0x1 #define TPS65917 0x2 +struct palmas_priv { + struct udevice *chip2; +}; + /* I2C device address for pmic palmas */ #define PALMAS_I2C_ADDR (0x12 >> 1) #define PALMAS_LDO_NUM 11 @@ -10,6 +14,7 @@ /* Drivers name */ #define PALMAS_LDO_DRIVER "palmas_ldo" #define PALMAS_SMPS_DRIVER "palmas_smps" +#define PALMAS_RST_DRIVER "palmas_rst" #define PALMAS_SMPS_VOLT_MASK 0x7F #define PALMAS_SMPS_RANGE_MASK 0x80 @@ -24,3 +29,9 @@ #define PALMAS_LDO_MODE_MASK 0x1 #define PALMAS_LDO_STATUS_MASK 0x10 #define PALMAS_LDO_BYPASS_EN 0x40 + +#define PALMAS_DEV_CTRL 0xA0 +#define SW_RST BIT(1) +#define DEV_OFF 0x00 +#define PALMAS_INT3_MASK 0x1B +#define MASK_VBUS BIT(7) diff --git a/include/power/tps62362.h b/include/power/tps62362.h index f0fc538463c..df06c28fed6 100644 --- a/include/power/tps62362.h +++ b/include/power/tps62362.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com + * (C) Copyright 2014 Texas Instruments Incorporated - https://www.ti.com * Author: Felipe Balbi <balbi@ti.com> */ diff --git a/include/power/tps65217.h b/include/power/tps65217.h index 669a94a6c87..7862b31bfb9 100644 --- a/include/power/tps65217.h +++ b/include/power/tps65217.h @@ -3,7 +3,7 @@ * (C) Copyright 2011-2013 * Texas Instruments, <www.ti.com> * - * For more details, please see the TRM at http://www.ti.com/product/tps65217a + * For more details, please see the TRM at https://www.ti.com/product/tps65217a */ #ifndef __POWER_TPS65217_H__ diff --git a/include/power/tps65910.h b/include/power/tps65910.h index 21b2a21ee04..ccc759acf66 100644 --- a/include/power/tps65910.h +++ b/include/power/tps65910.h @@ -3,7 +3,7 @@ * (C) Copyright 2011-2013 * Texas Instruments, <www.ti.com> * - * For more details, please see the TRM at http://www.ti.com/product/tps65910 + * For more details, please see the TRM at https://www.ti.com/product/tps65910 */ #ifndef __POWER_TPS65910_H__ #define __POWER_TPS65910_H__ diff --git a/include/power/tps65910_pmic.h b/include/power/tps65910_pmic.h index 66214786d3e..2026ec2f426 100644 --- a/include/power/tps65910_pmic.h +++ b/include/power/tps65910_pmic.h @@ -17,6 +17,12 @@ #define TPS65910_SUPPLY_STATE_OFF 0x0 #define TPS65910_SUPPLY_STATE_ON 0x1 +/* TPS65910 DEVICE_CTRL bits */ +#define PWR_OFF_SEQ BIT(7) +#define DEV_OFF_RST BIT(3) +#define DEV_ON BIT(2) +#define DEV_OFF BIT(0) + /* i2c registers */ enum { TPS65910_REG_RTC_SEC = 0x00, @@ -125,5 +131,50 @@ struct tps65910_regulator_pdata { #define TPS65910_BUCK_DRIVER "tps65910_buck" #define TPS65910_BOOST_DRIVER "tps65910_boost" #define TPS65910_LDO_DRIVER "tps65910_ldo" +#define TPS65910_RST_DRIVER "tps65910_rst" + +/* tps65911 i2c registers */ +enum { + TPS65911_REG_VIO = 0x20, + TPS65911_REG_VDD1, + TPS65911_REG_VDD1_OP, + TPS65911_REG_VDD1_SR, + TPS65911_REG_VDD2, + TPS65911_REG_VDD2_OP, + TPS65911_REG_VDD2_SR, + TPS65911_REG_VDDCTRL, + TPS65911_REG_VDDCTRL_OP, + TPS65911_REG_VDDCTRL_SR, + TPS65911_REG_LDO1 = 0x30, + TPS65911_REG_LDO2, + TPS65911_REG_LDO5, + TPS65911_REG_LDO8, + TPS65911_REG_LDO7, + TPS65911_REG_LDO6, + TPS65911_REG_LDO4, + TPS65911_REG_LDO3, +}; + +#define TPS65911_VDD_NUM 4 +#define TPS65911_LDO_NUM 8 + +#define TPS65911_VDD_VOLT_MAX 1500000 +#define TPS65911_VDD_VOLT_MIN 600000 +#define TPS65911_VDD_VOLT_BASE 562500 + +#define TPS65911_LDO_VOLT_MAX 3300000 +#define TPS65911_LDO_VOLT_BASE 800000 + +#define TPS65911_LDO_SEL_MASK (0x3f << 2) + +#define TPS65911_LDO124_VOLT_MAX_HEX 0x32 +#define TPS65911_LDO358_VOLT_MAX_HEX 0x19 +#define TPS65911_LDO358_VOLT_MIN_HEX 0x02 + +#define TPS65911_LDO124_VOLT_STEP 50000 +#define TPS65911_LDO358_VOLT_STEP 100000 + +#define TPS65911_VDD_DRIVER "tps65911_vdd" +#define TPS65911_LDO_DRIVER "tps65911_ldo" #endif /* __TPS65910_PMIC_H_ */ diff --git a/include/power/tps80031.h b/include/power/tps80031.h new file mode 100644 index 00000000000..983c841bfe3 --- /dev/null +++ b/include/power/tps80031.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef _TPS80031_H_ +#define _TPS80031_H_ + +#define TPS80031_LDO_NUM 9 +#define TPS80031_SMPS_NUM 5 + +/* Drivers name */ +#define TPS80031_LDO_DRIVER "tps80031_ldo" +#define TPS80031_SMPS_DRIVER "tps80031_smps" +#define TPS80031_RST_DRIVER "tps80031_rst" + +#define TPS80031_SMPS_OFFSET 0xe0 +#define TPS80031_OFFSET_FLAG BIT(0) + +#define REGULATOR_STATUS_MASK 0x3 +#define REGULATOR_MODE_ON 0x1 + +/* Switched-Mode Power Supply Regulator calculations */ +#define SMPS_VOLT_MASK 0x3f +#define SMPS_VOLT_LINEAR_HEX 0x39 +#define SMPS_VOLT_NLINEAR_HEX 0x3a +#define SMPS_VOLT_LINEAR 1300000 +#define SMPS_VOLT_BASE 600000 +#define SMPS_VOLT_BASE_OFFSET 700000 + +/* Low-Dropout Linear (LDO) Regulator calculations */ +#define LDO_VOLT_MASK 0x3f +#define LDO_VOLT_MAX_HEX 0x18 +#define LDO_VOLT_MIN_HEX 0x01 +#define LDO_VOLT_MAX 3360000 +#define LDO_VOLT_MIN 1018000 +#define LDO_VOLT_BASE 916000 + +#define TPS80031_PHOENIX_DEV_ON 0x25 +#define SW_RESET BIT(6) +#define DEVOFF BIT(0) + +/* register groups */ +enum { + CTRL, + VOLT, + OFFSET, +}; + +#endif /* _TPS80031_H_ */ diff --git a/include/remoteproc.h b/include/remoteproc.h index f48054de6ba..a11dc8a9b6c 100644 --- a/include/remoteproc.h +++ b/include/remoteproc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * (C) Copyright 2015 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _RPROC_H_ diff --git a/include/rkmtd.h b/include/rkmtd.h new file mode 100644 index 00000000000..145fede6c84 --- /dev/null +++ b/include/rkmtd.h @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Driver interface derived from: + * /include/sandbox_host.h + * Copyright 2022 Google LLC + * + * Copyright 2023 Johan Jonker <jbx6244@gmail.com> + */ + +#ifndef __RKMTD__ +#define __RKMTD__ + +#include <part_efi.h> +#include <uuid.h> + +#define LBA 64 + 512 + 33 + +#define RK_TAG 0xFCDC8C3B +#define NFC_SYS_DATA_SIZE 4 +#define BLK_SIZE 2048 +#define STEP_SIZE 1024 +#define BUF_SIZE 512 * 512 + +struct nand_para_info { + u8 id_bytes; + u8 nand_id[6]; + u8 vendor; + u8 die_per_chip; + u8 sec_per_page; + u16 page_per_blk; + u8 cell; + u8 plane_per_die; + u16 blk_per_plane; + u16 operation_opt; + u8 lsb_mode; + u8 read_retry_mode; + u8 ecc_bits; + u8 access_freq; + u8 opt_mode; + u8 die_gap; + u8 bad_block_mode; + u8 multi_plane_mode; + u8 slc_mode; + u8 reserved[5]; +}; + +struct bootblk { + int blk; + int boot_size; + int offset; +}; + +struct rkmtd_dev { + struct udevice *dev; + struct blk_desc *desc; + char *label; + legacy_mbr *mbr; + gpt_header *gpt_h; + gpt_header *gpt_h2; + gpt_entry *gpt_e; + char *check; + char *idb; + char *str; + char uuid_part_str[UUID_STR_LEN + 1]; + char uuid_disk_str[UUID_STR_LEN + 1]; + char *datbuf; + char *oobbuf; + struct mtd_info *mtd; + struct nand_para_info *info; + u16 page_table[512]; + u32 idb_need_write_back; + struct bootblk idblock[5]; + u32 blk_counter; + u32 boot_blks; + u32 offset; + u32 boot_size; + u32 lsb_mode; +}; + +struct sector0 { + u32 magic; + u8 reserved[4]; + u32 rc4_flag; + u16 boot_code1_offset; + u16 boot_code2_offset; + u8 reserved1[490]; + u16 flash_data_size; + u16 flash_boot_size; + u8 reserved2[2]; +} __packed; + +/** + * rkmtd_rc4() - Rockchip specific RC4 Encryption Algorithm + * + * Encrypt Rockchip boot block header version 1 and data + * + * @buf: Pointer to data buffer + * @len: Data buffer size + */ +void rkmtd_rc4(u8 *buf, u32 len); + +/** + * struct rkmtd_ops - operations supported by UCLASS_RKMTD + */ +struct rkmtd_ops { + /** + * @attach_mtd: - Attach a new rkmtd driver to the device structure + * + * @attach_mtd.dev: Device to update + * @attach_mtd.Returns: 0 if OK, -EEXIST if a driver is already attached, + * other -ve on other error + */ + int (*attach_mtd)(struct udevice *dev); + + /** + * @detach_mtd: - Detach a rkmtd driver from the device structure + * + * @detach_mtd.dev: Device to detach from + * @detach_mtd.Returns: 0 if OK, -ENOENT if no driver is attached, + * other -ve on other error + */ + int (*detach_mtd)(struct udevice *dev); +}; + +#define rkmtd_get_ops(dev) ((struct rkmtd_ops *)(dev)->driver->ops) + +/** + * rkmtd_get_cur_dev() - Get the current device + * + * Returns current device, or NULL if none + */ +struct udevice *rkmtd_get_cur_dev(void); + +/** + * rkmtd_set_cur_dev() - Set the current device + * + * Sets the current device, or clears it if @dev is NULL + * + * @dev: Device to set as the current one + */ +void rkmtd_set_cur_dev(struct udevice *dev); + +/** + * rkmtd_find_by_label() - Find a rkmtd device by label + * + * Searches all rkmtd devices to find one with the given label + * + * @label: Label to find + * Returns: associated device, or NULL if not found + */ +struct udevice *rkmtd_find_by_label(const char *label); + +/** + * rkmtd_attach() - Attach a new rkmtd driver to the device structure + * + * @dev: Device to update + * Returns: 0 if OK, -EEXIST if a file is already attached, other -ve on + * other error + */ +int rkmtd_attach(struct udevice *dev); + +/** + * rkmtd_detach() - Detach a rkmtd driver from the device structure + * + * @dev: Device to detach from + * Returns: 0 if OK, -ENOENT if no file is attached, other -ve on other + * error + */ +int rkmtd_detach(struct udevice *dev); + +/** + * rkmtd_create_device() - Create a new rkmtd device + * + * Any existing device with the same label is removed and unbound first + * + * @label: Label of the attachment, e.g. "test1" + * @devp: Returns the device created, on success + * Returns: 0 if OK, -ve on error + */ +int rkmtd_create_device(const char *label, struct udevice **devp); + +/** + * rkmtd_create_attach_mtd() - Create a new rkmtd device and attach driver + * + * @label: Label of the attachment, e.g. "test1" + * @devp: Returns the device created, on success + * Returns: 0 if OK, -ve on error + */ +int rkmtd_create_attach_mtd(const char *label, struct udevice **devp); + +#endif /* __RKMTD__ */ diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index 35d96069645..33e0e18c30d 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -23,6 +23,7 @@ struct scmi_channel; * @agent_name: Agent name * @agent_id: Identifier of agent * @base_dev: SCMI base protocol device + * @pwdom_dev: SCMI power domain management protocol device * @clock_dev: SCMI clock protocol device * @resetdom_dev: SCMI reset domain protocol device * @voltagedom_dev: SCMI voltage domain protocol device @@ -38,6 +39,7 @@ struct scmi_agent_priv { u8 *agent_name; u32 agent_id; struct udevice *base_dev; + struct udevice *pwdom_dev; struct udevice *clock_dev; struct udevice *resetdom_dev; struct udevice *voltagedom_dev; diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 163647a57b9..7abb2a6f36b 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -545,6 +545,184 @@ int scmi_base_reset_agent_configuration(struct udevice *dev, u32 agent_id, u32 flags); /* + * SCMI Power Domain Management Protocol + */ + +#define SCMI_PWD_PROTOCOL_VERSION 0x30000 +#define SCMI_PWD_PSTATE_TYPE_LOST BIT(30) +#define SCMI_PWD_PSTATE_ID GENMASK(27, 0) + +enum scmi_power_domain_message_id { + SCMI_PWD_ATTRIBUTES = 0x3, + SCMI_PWD_STATE_SET = 0x4, + SCMI_PWD_STATE_GET = 0x5, + SCMI_PWD_STATE_NOTIFY = 0x6, + SCMI_PWD_STATE_CHANGE_REQUESTED_NOTIFY = 0x7, + SCMI_PWD_NAME_GET = 0x8, +}; + +/** + * struct scmi_pwd_protocol_attrs_out + * @status: SCMI command status + * @attributes: Protocol attributes + * @stats_addr_low: Lower 32 bits of address of statistics memory region + * @stats_addr_high: Higher 32 bits of address of statistics memory region + * @stats_len: Length of statistics memory region + */ +struct scmi_pwd_protocol_attrs_out { + s32 status; + u32 attributes; + u32 stats_addr_low; + u32 stats_addr_high; + u32 stats_len; +}; + +#define SCMI_PWD_PROTO_ATTRS_NUM_PWD(attributes) ((attributes) & GENMASK(15, 0)) + +/** + * struct scmi_pwd_protocol_msg_attrs_out + * @status: SCMI command status + * @attributes: Message-specific attributes + */ +struct scmi_pwd_protocol_msg_attrs_out { + s32 status; + u32 attributes; +}; + +#define SCMI_PWD_NAME_LENGTH_MAX 16 + +/** + * struct scmi_pwd_attrs_out + * @status: SCMI command status + * @attributes: Power domain attributes + * @name: Name of power domain + */ +struct scmi_pwd_attrs_out { + s32 status; + u32 attributes; + u8 name[SCMI_PWD_NAME_LENGTH_MAX]; +}; + +#define SCMI_PWD_ATTR_PSTATE_CHANGE_NOTIFY BIT(31) +#define SCMI_PWD_ATTR_PSTATE_ASYNC BIT(30) +#define SCMI_PWD_ATTR_PSTATE_SYNC BIT(29) +#define SCMI_PWD_ATTR_PSTATE_CHANGE_RQ_NOTIFY BIT(28) +#define SCMI_PWD_ATTR_EXTENDED_NAME BIT(27) + +/** + * struct scmi_pwd_state_set_in + * @flags: Flags + * @domain_id: Identifier of power domain + * @pstate: Power state of the domain + */ +struct scmi_pwd_state_set_in { + u32 flags; + u32 domain_id; + u32 pstate; +}; + +#define SCMI_PWD_SET_FLAGS_ASYNC BIT(0) + +/** + * struct scmi_pwd_state_get_out + * @status: SCMI command status + * @pstate: Power state of the domain + */ +struct scmi_pwd_state_get_out { + s32 status; + u32 pstate; +}; + +#define SCMI_PWD_EXTENDED_NAME_MAX 64 +/** + * struct scmi_pwd_name_get_out + * @status: SCMI command status + * @flags: Parameter flags + * @extended_name: Extended name of power domain + */ +struct scmi_pwd_name_get_out { + s32 status; + u32 flags; + u8 extended_name[SCMI_PWD_EXTENDED_NAME_MAX]; +}; + +/** + * scmi_pwd_protocol_attrs - get protocol attributes + * @dev: SCMI protocol device + * @num_pwdoms: Number of power domains + * @stats_addr: Address of statistics memory region + * @stats_len: Length of statistics memory region + * + * Obtain the protocol attributes, the number of power domains and + * the information of statistics memory region. + * + * Return: 0 on success, error code on failure + */ +int scmi_pwd_protocol_attrs(struct udevice *dev, int *num_pwdoms, + u64 *stats_addr, size_t *stats_len); +/** + * scmi_pwd_protocol_message_attrs - get message-specific attributes + * @dev: SCMI protocol device + * @message_id: SCMI message ID + * @attributes: Message-specific attributes + * + * Obtain the message-specific attributes in @attributes. + * + * Return: 0 on success, error code on failure + */ +int scmi_pwd_protocol_message_attrs(struct udevice *dev, s32 message_id, + u32 *attributes); +/** + * scmi_pwd_attrs - get power domain attributes + * @dev: SCMI protocol device + * @domain_id: Identifier of power domain + * @attributes: Power domain attributes + * @name: Name of power domain + * + * Obtain the attributes of the given power domain, @domain_id, in @attributes + * as well as its name in @name. + * + * Return: 0 on success, error code on failure + */ +int scmi_pwd_attrs(struct udevice *dev, u32 message_id, u32 *attributes, + u8 **name); +/** + * scmi_pwd_state_set - set power state + * @dev: SCMI protocol device + * @flags: Parameter flags + * @domain_id: Identifier of power domain + * @pstate: Power state + * + * Change the power state of the given power domain, @domain_id. + * + * Return: 0 on success, error code on failure + */ +int scmi_pwd_state_set(struct udevice *dev, u32 flags, u32 domain_id, + u32 pstate); +/** + * scmi_pwd_state_get - get power state + * @dev: SCMI protocol device + * @domain_id: Identifier of power domain + * @pstate: Power state + * + * Obtain the power state of the given power domain, @domain_id. + * + * Return: 0 on success, error code on failure + */ +int scmi_pwd_state_get(struct udevice *dev, u32 domain_id, u32 *pstate); +/** + * scmi_pwd_name_get - get extended name + * @dev: SCMI protocol device + * @domain_id: Identifier of power domain + * @name: Extended name of the domain + * + * Obtain the extended name of the given power domain, @domain_id, in @name. + * + * Return: 0 on success, error code on failure + */ +int scmi_pwd_name_get(struct udevice *dev, u32 domain_id, u8 **name); + +/* * SCMI Clock Protocol */ diff --git a/include/sdhci.h b/include/sdhci.h index 70fefca2a97..a1b74e3bd79 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -57,6 +57,7 @@ #define SDHCI_PRESENT_STATE 0x24 #define SDHCI_CMD_INHIBIT BIT(0) #define SDHCI_DATA_INHIBIT BIT(1) +#define SDHCI_DAT_ACTIVE BIT(2) #define SDHCI_DOING_WRITE BIT(8) #define SDHCI_DOING_READ BIT(9) #define SDHCI_SPACE_AVAILABLE BIT(10) diff --git a/include/serial.h b/include/serial.h index 205889d28be..d129dc3253c 100644 --- a/include/serial.h +++ b/include/serial.h @@ -339,6 +339,13 @@ int serial_setconfig(struct udevice *dev, uint config); */ int serial_getinfo(struct udevice *dev, struct serial_device_info *info); +/** + * fetch_baud_from_dtb() - Fetch the baudrate value from DT + * + * Return: baudrate if OK, -ve on error + */ +int fetch_baud_from_dtb(void); + void atmel_serial_initialize(void); void mcf_serial_initialize(void); void mpc85xx_serial_initialize(void); diff --git a/include/soc.h b/include/soc.h index a52a300a84a..850db28b76a 100644 --- a/include/soc.h +++ b/include/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/ + * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/ * Dave Gerlach <d-gerlach@ti.com> */ diff --git a/include/spl.h b/include/spl.h index 0d49e4a454c..8ff20adc28e 100644 --- a/include/spl.h +++ b/include/spl.h @@ -497,6 +497,32 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc); void spl_set_bd(void); /** + * spl_mmc_get_uboot_raw_sector() - Provide raw sector of the start of U-Boot (architecture override) + * + * This is a weak function which by default will provide the raw sector that is + * where the start of the U-Boot image has been written to. + * + * @mmc: struct mmc that describes the devie where U-Boot resides + * @raw_sect: The raw sector number where U-Boot is by default. + * Return: The raw sector location that U-Boot resides at + */ +unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect); + +/** + * spl_mmc_get_uboot_raw_sector() - Provide raw sector of the start of U-Boot (board override) + * + * This is a weak function which by default will provide the raw sector that is + * where the start of the U-Boot image has been written to. + * + * @mmc: struct mmc that describes the devie where U-Boot resides + * @raw_sect: The raw sector number where U-Boot is by default. + * Return: The raw sector location that U-Boot resides at + */ +unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, + unsigned long raw_sect); + +/** * spl_mmc_get_uboot_raw_sector() - Provide raw sector of the start of U-Boot * * This is a weak function which by default will provide the raw sector that is diff --git a/include/test/suites.h b/include/test/suites.h index 1c7dc65966a..ad4fc926f48 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -45,6 +45,8 @@ int do_ut_font(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_lib(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_loadm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_log(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); +int do_ut_mbr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_measurement(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); int do_ut_mem(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_overlay(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/include/ti-usb-phy-uboot.h b/include/ti-usb-phy-uboot.h index cd2ba404774..feeddb86529 100644 --- a/include/ti-usb-phy-uboot.h +++ b/include/ti-usb-phy-uboot.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* include/ti_usb_phy_uboot.h * - * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com + * Copyright (c) 2014 Texas Instruments Incorporated - https://www.ti.com * * USB2 and USB3 PHY uboot init */ diff --git a/include/tpm-v2.h b/include/tpm-v2.h index 2b6980e441d..33dd103767c 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -169,7 +169,7 @@ struct tcg_pcr_event { /** * Definition of TPMU_HA Union */ -union tmpu_ha { +union tpmu_ha { u8 sha1[TPM2_SHA1_DIGEST_SIZE]; u8 sha256[TPM2_SHA256_DIGEST_SIZE]; u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE]; @@ -185,7 +185,7 @@ union tmpu_ha { */ struct tpmt_ha { u16 hash_alg; - union tmpu_ha digest; + union tpmu_ha digest; } __packed; /** @@ -217,6 +217,50 @@ struct tcg_pcr_event2 { } __packed; /** + * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information + * + * @algorithm_id: algorithm defined in enum tpm2_algorithms + * @digest_size: size of the algorithm + */ +struct tcg_efi_spec_id_event_algorithm_size { + u16 algorithm_id; + u16 digest_size; +} __packed; + +#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03" +#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2 +#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0 +#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2 + +/** + * struct TCG_EfiSpecIDEventStruct - content of the event log header + * + * @signature: signature, set to Spec ID Event03 + * @platform_class: class defined in TCG ACPI Specification + * Client Common Header. + * @spec_version_minor: minor version + * @spec_version_major: major version + * @spec_version_errata: major version + * @uintn_size: size of the efi_uintn_t fields used in various + * data structures used in this specification. + * 0x01 indicates u32 and 0x02 indicates u64 + * @number_of_algorithms: hashing algorithms used in this event log + * @digest_sizes: array of number_of_algorithms pairs + * 1st member defines the algorithm id + * 2nd member defines the algorithm size + */ +struct tcg_efi_spec_id_event { + u8 signature[16]; + u32 platform_class; + u8 spec_version_minor; + u8 spec_version_major; + u8 spec_errata; + u8 uintn_size; + u32 number_of_algorithms; + struct tcg_efi_spec_id_event_algorithm_size digest_sizes[]; +} __packed; + +/** * TPM2 Structure Tags for command/response buffers. * * @TPM2_ST_NO_SESSIONS: the command does not need an authentication. @@ -342,6 +386,26 @@ enum tpm2_algorithms { TPM2_ALG_SM3_256 = 0x12, }; +extern const enum tpm2_algorithms tpm2_supported_algorithms[4]; + +static inline u16 tpm2_algorithm_to_len(enum tpm2_algorithms a) +{ + switch (a) { + case TPM2_ALG_SHA1: + return TPM2_SHA1_DIGEST_SIZE; + case TPM2_ALG_SHA256: + return TPM2_SHA256_DIGEST_SIZE; + case TPM2_ALG_SHA384: + return TPM2_SHA384_DIGEST_SIZE; + case TPM2_ALG_SHA512: + return TPM2_SHA512_DIGEST_SIZE; + default: + return 0; + } +} + +#define tpm2_algorithm_to_mask(a) (1 << (a)) + /* NV index attributes */ enum tpm_index_attrs { TPMA_NV_PPWRITE = 1UL << 0, @@ -422,6 +486,188 @@ enum { }; /** + * struct tcg2_event_log - Container for managing the platform event log + * + * @log: Address of the log + * @log_position: Current entry position + * @log_size: Log space available + * @found: Boolean indicating if an existing log was discovered + */ +struct tcg2_event_log { + u8 *log; + u32 log_position; + u32 log_size; + bool found; +}; + +/** + * Create a list of digests of the supported PCR banks for a given input data + * + * @dev TPM device + * @input Data + * @length Length of the data to calculate the digest + * @digest_list List of digests to fill in + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, + struct tpml_digest_values *digest_list); + +/** + * Get the event size of the specified digests + * + * @digest_list List of digests for the event + * + * Return: Size in bytes of the event + */ +u32 tcg2_event_get_size(struct tpml_digest_values *digest_list); + +/** + * tcg2_get_active_pcr_banks + * + * @dev TPM device + * @active_pcr_banks Bitmask of PCR algorithms supported + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks); + +/** + * tcg2_log_append - Append an event to an event log + * + * @pcr_index Index of the PCR + * @event_type Type of event + * @digest_list List of digests to add + * @size Size of event + * @event Event data + * @log Log buffer to append the event to + */ +void tcg2_log_append(u32 pcr_index, u32 event_type, + struct tpml_digest_values *digest_list, u32 size, + const u8 *event, u8 *log); + +/** + * Extend the PCR with specified digests + * + * @dev TPM device + * @pcr_index Index of the PCR + * @digest_list List of digests to extend + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index, + struct tpml_digest_values *digest_list); + +/** + * Read the PCR into a list of digests + * + * @dev TPM device + * @pcr_index Index of the PCR + * @digest_list List of digests to extend + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_pcr_read(struct udevice *dev, u32 pcr_index, + struct tpml_digest_values *digest_list); + +/** + * Measure data into the TPM PCRs and the platform event log. + * + * @dev TPM device + * @log Platform event log + * @pcr_index Index of the PCR + * @size Size of the data or 0 for event only + * @data Pointer to the data or NULL for event only + * @event_type Event log type + * @event_size Size of the event + * @event Pointer to the event + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog, + u32 pcr_index, u32 size, const u8 *data, u32 event_type, + u32 event_size, const u8 *event); + +#define tcg2_measure_event(dev, elog, pcr_index, event_type, size, event) \ + tcg2_measure_data(dev, elog, pcr_index, 0, NULL, event_type, size, \ + event) + +/** + * Prepare the event log buffer. This function tries to discover an existing + * event log in memory from a previous bootloader stage. If such a log exists + * and the PCRs are not extended, the log is "replayed" to extend the PCRs. + * If no log is discovered, create the log header. + * + * @dev TPM device + * @elog Platform event log. The log pointer and log_size + * members must be initialized to either 0 or to a valid + * memory region, in which case any existing log + * discovered will be copied to the specified memory + * region. + * @ignore_existing_log Boolean to indicate whether or not to ignore an + * existing platform log in memory + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, + bool ignore_existing_log); + +/** + * Begin measurements. + * + * @dev TPM device + * @elog Platform event log. The log pointer and log_size + * members must be initialized to either 0 or to a valid + * memory region, in which case any existing log + * discovered will be copied to the specified memory + * region. + * @ignore_existing_log Boolean to indicate whether or not to ignore an + * existing platform log in memory + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog, + bool ignore_existing_log); + +/** + * Stop measurements and record separator events. + * + * @dev TPM device + * @elog Platform event log + * @error Boolean to indicate whether an error ocurred or not + */ +void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog, + bool error); + +/** + * Get the platform event log address and size. + * + * @dev TPM device + * @addr Address of the log + * @size Size of the log + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size); + +/** + * Get the first TPM2 device found. + * + * @dev TPM device + * + * Return: zero on success, negative errno otherwise + */ +int tcg2_platform_get_tpm2(struct udevice **dev); + +/** + * Platform-specific function for handling TPM startup errors + * + * @dev TPM device + * @rc The TPM response code + */ +void tcg2_platform_startup_error(struct udevice *dev, int rc); + +/** * Issue a TPM2_Startup command. * * @dev TPM device @@ -541,6 +787,19 @@ u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property, void *buf, size_t prop_count); /** + * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks + * + * @dev: TPM device + * @supported_pcr: bitmask with the algorithms supported + * @active_pcr: bitmask with the active algorithms + * @pcr_banks: number of PCR banks + * + * @return 0 on success, code of operation or negative errno on failure + */ +int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, + u32 *pcr_banks); + +/** * Issue a TPM2_DictionaryAttackLockReset command. * * @dev TPM device diff --git a/lib/Kconfig b/lib/Kconfig index f6ca559897e..19649517a39 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -431,6 +431,10 @@ config TPM bool "Trusted Platform Module (TPM) Support" depends on DM imply DM_RNG + select SHA1 + select SHA256 + select SHA384 + select SHA512 help This enables support for TPMs which can be used to provide security features for your board. The TPM can be connected via LPC or I2C diff --git a/lib/addr_map.c b/lib/addr_map.c index 9b3e0a544e4..86e932e4b56 100644 --- a/lib/addr_map.c +++ b/lib/addr_map.c @@ -59,7 +59,7 @@ void *addrmap_phys_to_virt(phys_addr_t paddr) void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr, phys_size_t size, int idx) { - if (idx > CONFIG_SYS_NUM_ADDR_MAP) + if (idx >= CONFIG_SYS_NUM_ADDR_MAP) return; address_map[idx].vaddr = vaddr; diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index d20aaab6dba..4ccd26f94a9 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -379,8 +379,6 @@ config EFI_TCG2_PROTOCOL bool "EFI_TCG2_PROTOCOL support" default y depends on TPM_V2 - # Sandbox TPM currently fails on GetCapabilities needed for TCG2 - depends on !SANDBOX select SHA1 select SHA256 select SHA384 diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 7b7926a0d46..2eaa12b83b1 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -66,35 +66,6 @@ static bool tcg2_efi_app_invoked; static const efi_guid_t efi_guid_tcg2_protocol = EFI_TCG2_PROTOCOL_GUID; static const efi_guid_t efi_guid_final_events = EFI_TCG2_FINAL_EVENTS_TABLE_GUID; -struct digest_info { - u16 hash_alg; - u32 hash_mask; - u16 hash_len; -}; - -static const struct digest_info hash_algo_list[] = { - { - TPM2_ALG_SHA1, - EFI_TCG2_BOOT_HASH_ALG_SHA1, - TPM2_SHA1_DIGEST_SIZE, - }, - { - TPM2_ALG_SHA256, - EFI_TCG2_BOOT_HASH_ALG_SHA256, - TPM2_SHA256_DIGEST_SIZE, - }, - { - TPM2_ALG_SHA384, - EFI_TCG2_BOOT_HASH_ALG_SHA384, - TPM2_SHA384_DIGEST_SIZE, - }, - { - TPM2_ALG_SHA512, - EFI_TCG2_BOOT_HASH_ALG_SHA512, - TPM2_SHA512_DIGEST_SIZE, - }, -}; - struct variable_info { const u16 *name; bool accept_empty; @@ -113,46 +84,6 @@ static struct variable_info secure_variables[] = { {u"AuditMode", false, 1}, }; -#define MAX_HASH_COUNT ARRAY_SIZE(hash_algo_list) - -/** - * alg_to_mask - Get a TCG hash mask for algorithms - * - * @hash_alg: TCG defined algorithm - * - * @Return: TCG hashing algorithm bitmaps, 0 if the algorithm is not supported - */ -static u32 alg_to_mask(u16 hash_alg) -{ - size_t i; - - for (i = 0; i < MAX_HASH_COUNT; i++) { - if (hash_algo_list[i].hash_alg == hash_alg) - return hash_algo_list[i].hash_mask; - } - - return 0; -} - -/** - * alg_to_len - Get a TCG hash len for algorithms - * - * @hash_alg: TCG defined algorithm - * - * @Return: len of chosen algorithm, 0 if the algorithm is not supported - */ -static u16 alg_to_len(u16 hash_alg) -{ - size_t i; - - for (i = 0; i < MAX_HASH_COUNT; i++) { - if (hash_algo_list[i].hash_alg == hash_alg) - return hash_algo_list[i].hash_len; - } - - return 0; -} - static bool is_tcg2_protocol_installed(void) { struct efi_handler *handler; @@ -162,145 +93,6 @@ static bool is_tcg2_protocol_installed(void) return ret == EFI_SUCCESS; } -static u32 tcg_event_final_size(struct tpml_digest_values *digest_list) -{ - u32 len; - size_t i; - - len = offsetof(struct tcg_pcr_event2, digests); - len += offsetof(struct tpml_digest_values, digests); - for (i = 0; i < digest_list->count; i++) { - u16 hash_alg = digest_list->digests[i].hash_alg; - - len += offsetof(struct tpmt_ha, digest); - len += alg_to_len(hash_alg); - } - len += sizeof(u32); /* tcg_pcr_event2 event_size*/ - - return len; -} - -/* tcg2_pcr_extend - Extend PCRs for a TPM2 device for a given tpml_digest_values - * - * @dev: device - * @digest_list: list of digest algorithms to extend - * - * @Return: status code - */ -static efi_status_t tcg2_pcr_extend(struct udevice *dev, u32 pcr_index, - struct tpml_digest_values *digest_list) -{ - u32 rc; - size_t i; - - for (i = 0; i < digest_list->count; i++) { - u32 alg = digest_list->digests[i].hash_alg; - - rc = tpm2_pcr_extend(dev, pcr_index, alg, - (u8 *)&digest_list->digests[i].digest, - alg_to_len(alg)); - if (rc) { - EFI_PRINT("Failed to extend PCR\n"); - return EFI_DEVICE_ERROR; - } - } - - return EFI_SUCCESS; -} - -/* tcg2_pcr_read - Read PCRs for a TPM2 device for a given tpml_digest_values - * - * @dev: device - * @pcr_index: PCR index - * @digest_list: list of digest algorithms to extend - * - * @Return: status code - */ -static efi_status_t tcg2_pcr_read(struct udevice *dev, u32 pcr_index, - struct tpml_digest_values *digest_list) -{ - struct tpm_chip_priv *priv; - unsigned int updates, pcr_select_min; - u32 rc; - size_t i; - - priv = dev_get_uclass_priv(dev); - if (!priv) - return EFI_DEVICE_ERROR; - - pcr_select_min = priv->pcr_select_min; - - for (i = 0; i < digest_list->count; i++) { - u16 hash_alg = digest_list->digests[i].hash_alg; - u8 *digest = (u8 *)&digest_list->digests[i].digest; - - rc = tpm2_pcr_read(dev, pcr_index, pcr_select_min, - hash_alg, digest, alg_to_len(hash_alg), - &updates); - if (rc) { - EFI_PRINT("Failed to read PCR\n"); - return EFI_DEVICE_ERROR; - } - } - - return EFI_SUCCESS; -} - -/* put_event - Append an agile event to an eventlog - * - * @pcr_index: PCR index - * @event_type: type of event added - * @digest_list: list of digest algorithms to add - * @size: size of event - * @event: event to add - * @log: log buffer to append the event - * - */ -static void put_event(u32 pcr_index, u32 event_type, - struct tpml_digest_values *digest_list, u32 size, - u8 event[], void *log) -{ - size_t pos; - size_t i; - u32 event_size; - - /* - * size refers to the length of event[] only, we need to check against - * the final tcg_pcr_event2 size - */ - event_size = size + tcg_event_final_size(digest_list); - - put_unaligned_le32(pcr_index, log); - pos = offsetof(struct tcg_pcr_event2, event_type); - put_unaligned_le32(event_type, (void *)((uintptr_t)log + pos)); - pos = offsetof(struct tcg_pcr_event2, digests); /* count */ - put_unaligned_le32(digest_list->count, (void *)((uintptr_t)log + pos)); - - pos += offsetof(struct tpml_digest_values, digests); - for (i = 0; i < digest_list->count; i++) { - u16 hash_alg = digest_list->digests[i].hash_alg; - u8 *digest = (u8 *)&digest_list->digests[i].digest; - - put_unaligned_le16(hash_alg, (void *)((uintptr_t)log + pos)); - pos += offsetof(struct tpmt_ha, digest); - memcpy((void *)((uintptr_t)log + pos), digest, alg_to_len(hash_alg)); - pos += alg_to_len(hash_alg); - } - - put_unaligned_le32(size, (void *)((uintptr_t)log + pos)); - pos += sizeof(u32); /* tcg_pcr_event2 event_size*/ - memcpy((void *)((uintptr_t)log + pos), event, size); - pos += size; - - /* - * make sure the calculated buffer is what we checked against - * This check should never fail. It checks the code above is - * calculating the right length for the event we are adding - */ - if (pos != event_size) - log_err("Appending to the EventLog failed\n"); -} - /* tcg2_agile_log_append - Append an agile event to an eventlog * * @pcr_index: PCR index @@ -317,7 +109,7 @@ static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type, u32 size, u8 event[]) { void *log = (void *)((uintptr_t)event_log.buffer + event_log.pos); - u32 event_size = size + tcg_event_final_size(digest_list); + u32 event_size = size + tcg2_event_get_size(digest_list); struct efi_tcg2_final_events_table *final_event; efi_status_t ret = EFI_SUCCESS; @@ -328,7 +120,7 @@ static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type, event_log.truncated = true; return EFI_VOLUME_FULL; } - put_event(pcr_index, event_type, digest_list, size, event, log); + tcg2_log_append(pcr_index, event_type, digest_list, size, event, log); event_log.pos += event_size; event_log.last_event_size = event_size; } @@ -341,7 +133,7 @@ static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type, return EFI_VOLUME_FULL; log = (void *)((uintptr_t)event_log.final_buffer + event_log.final_pos); - put_event(pcr_index, event_type, digest_list, size, event, log); + tcg2_log_append(pcr_index, event_type, digest_list, size, event, log); final_event = event_log.final_buffer; final_event->number_of_events++; @@ -351,66 +143,6 @@ static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type, } /** - * platform_get_tpm_device() - retrieve TPM device - * - * This function retrieves the udevice implementing a TPM - * - * This function may be overridden if special initialization is needed. - * - * @dev: udevice - * Return: status code - */ -__weak efi_status_t platform_get_tpm2_device(struct udevice **dev) -{ - for_each_tpm_device(*dev) { - /* Only support TPMv2 devices */ - if (tpm_get_version(*dev) == TPM_V2) - return EFI_SUCCESS; - } - - return EFI_NOT_FOUND; -} - -/** - * platform_get_eventlog() - retrieve the eventlog address and size - * - * This function retrieves the eventlog address and size if the underlying - * firmware has done some measurements and passed them. - * - * This function may be overridden based on platform specific method of - * passing the eventlog address and size. - * - * @dev: udevice - * @addr: eventlog address - * @sz: eventlog size - * Return: status code - */ -__weak efi_status_t platform_get_eventlog(struct udevice *dev, u64 *addr, - u32 *sz) -{ - const u64 *basep; - const u32 *sizep; - - basep = dev_read_prop(dev, "tpm_event_log_addr", NULL); - if (!basep) - return EFI_NOT_FOUND; - - *addr = be64_to_cpup((__force __be64 *)basep); - - sizep = dev_read_prop(dev, "tpm_event_log_size", NULL); - if (!sizep) - return EFI_NOT_FOUND; - - *sz = be32_to_cpup((__force __be32 *)sizep); - if (*sz == 0) { - log_debug("event log empty\n"); - return EFI_NOT_FOUND; - } - - return EFI_SUCCESS; -} - -/** * tpm2_get_max_command_size() - get the supported max command size * * @dev: TPM device @@ -486,238 +218,6 @@ static int tpm2_get_manufacturer_id(struct udevice *dev, u32 *manufacturer_id) } /** - * tpm2_get_num_pcr() - get the number of PCRs - * - * @dev: TPM device - * @manufacturer_id: output buffer for the number - * - * Return: 0 on success, -1 on error - */ -static int tpm2_get_num_pcr(struct udevice *dev, u32 *num_pcr) -{ - u8 response[TPM2_RESPONSE_BUFFER_SIZE]; - u32 ret; - - memset(response, 0, sizeof(response)); - ret = tpm2_get_capability(dev, TPM2_CAP_TPM_PROPERTIES, - TPM2_PT_PCR_COUNT, response, 1); - if (ret) - return -1; - - *num_pcr = get_unaligned_be32(response + properties_offset); - if (*num_pcr > TPM2_MAX_PCRS) - return -1; - - return 0; -} - -/** - * is_active_pcr() - Check if a supported algorithm is active - * - * @dev: TPM device - * @selection: struct of PCR information - * - * Return: true if PCR is active - */ -static bool is_active_pcr(struct tpms_pcr_selection *selection) -{ - int i; - /* - * check the pcr_select. If at least one of the PCRs supports the - * algorithm add it on the active ones - */ - for (i = 0; i < selection->size_of_select; i++) { - if (selection->pcr_select[i]) - return true; - } - - return false; -} - -/** - * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks - * - * @dev: TPM device - * @supported_pcr: bitmask with the algorithms supported - * @active_pcr: bitmask with the active algorithms - * @pcr_banks: number of PCR banks - * - * Return: 0 on success, -1 on error - */ -static int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, - u32 *active_pcr, u32 *pcr_banks) -{ - u8 response[TPM2_RESPONSE_BUFFER_SIZE]; - struct tpml_pcr_selection pcrs; - u32 ret, num_pcr; - size_t i; - int tpm_ret; - - *supported_pcr = 0; - *active_pcr = 0; - *pcr_banks = 0; - memset(response, 0, sizeof(response)); - ret = tpm2_get_capability(dev, TPM2_CAP_PCRS, 0, response, 1); - if (ret) - goto out; - - pcrs.count = get_unaligned_be32(response); - /* - * We only support 5 algorithms for now so check against that - * instead of TPM2_NUM_PCR_BANKS - */ - if (pcrs.count > MAX_HASH_COUNT || pcrs.count < 1) - goto out; - - tpm_ret = tpm2_get_num_pcr(dev, &num_pcr); - if (tpm_ret) - goto out; - - for (i = 0; i < pcrs.count; i++) { - /* - * Definition of TPMS_PCR_SELECTION Structure - * hash: u16 - * size_of_select: u8 - * pcr_select: u8 array - * - * The offsets depend on the number of the device PCRs - * so we have to calculate them based on that - */ - u32 hash_offset = offsetof(struct tpml_pcr_selection, selection) + - i * offsetof(struct tpms_pcr_selection, pcr_select) + - i * ((num_pcr + 7) / 8); - u32 size_select_offset = - hash_offset + offsetof(struct tpms_pcr_selection, - size_of_select); - u32 pcr_select_offset = - hash_offset + offsetof(struct tpms_pcr_selection, - pcr_select); - - pcrs.selection[i].hash = - get_unaligned_be16(response + hash_offset); - pcrs.selection[i].size_of_select = - __get_unaligned_be(response + size_select_offset); - if (pcrs.selection[i].size_of_select > TPM2_PCR_SELECT_MAX) - goto out; - /* copy the array of pcr_select */ - memcpy(pcrs.selection[i].pcr_select, response + pcr_select_offset, - pcrs.selection[i].size_of_select); - } - - for (i = 0; i < pcrs.count; i++) { - u32 hash_mask = alg_to_mask(pcrs.selection[i].hash); - - if (hash_mask) { - *supported_pcr |= hash_mask; - if (is_active_pcr(&pcrs.selection[i])) - *active_pcr |= hash_mask; - } else { - EFI_PRINT("Unknown algorithm %x\n", pcrs.selection[i].hash); - } - } - - *pcr_banks = pcrs.count; - - return 0; -out: - return -1; -} - -/** - * __get_active_pcr_banks() - returns the currently active PCR banks - * - * @active_pcr_banks: pointer for receiving the bitmap of currently - * active PCR banks - * - * Return: status code - */ -static efi_status_t __get_active_pcr_banks(u32 *active_pcr_banks) -{ - struct udevice *dev; - u32 active = 0, supported = 0, pcr_banks = 0; - efi_status_t ret; - int err; - - ret = platform_get_tpm2_device(&dev); - if (ret != EFI_SUCCESS) - goto out; - - err = tpm2_get_pcr_info(dev, &supported, &active, &pcr_banks); - if (err) { - ret = EFI_DEVICE_ERROR; - goto out; - } - - *active_pcr_banks = active; - -out: - return ret; -} - -/* tcg2_create_digest - create a list of digests of the supported PCR banks - * for a given memory range - * - * @input: input memory - * @length: length of buffer to calculate the digest - * @digest_list: list of digests to fill in - * - * Return: status code - */ -static efi_status_t tcg2_create_digest(const u8 *input, u32 length, - struct tpml_digest_values *digest_list) -{ - sha1_context ctx; - sha256_context ctx_256; - sha512_context ctx_512; - u8 final[TPM2_SHA512_DIGEST_SIZE]; - efi_status_t ret; - u32 active; - size_t i; - - ret = __get_active_pcr_banks(&active); - if (ret != EFI_SUCCESS) - return ret; - - digest_list->count = 0; - for (i = 0; i < MAX_HASH_COUNT; i++) { - u16 hash_alg = hash_algo_list[i].hash_alg; - - if (!(active & alg_to_mask(hash_alg))) - continue; - switch (hash_alg) { - case TPM2_ALG_SHA1: - sha1_starts(&ctx); - sha1_update(&ctx, input, length); - sha1_finish(&ctx, final); - break; - case TPM2_ALG_SHA256: - sha256_starts(&ctx_256); - sha256_update(&ctx_256, input, length); - sha256_finish(&ctx_256, final); - break; - case TPM2_ALG_SHA384: - sha384_starts(&ctx_512); - sha384_update(&ctx_512, input, length); - sha384_finish(&ctx_512, final); - break; - case TPM2_ALG_SHA512: - sha512_starts(&ctx_512); - sha512_update(&ctx_512, input, length); - sha512_finish(&ctx_512, final); - break; - default: - continue; - } - digest_list->digests[digest_list->count].hash_alg = hash_alg; - memcpy(&digest_list->digests[digest_list->count].digest, final, - (u32)alg_to_len(hash_alg)); - digest_list->count++; - } - - return EFI_SUCCESS; -} - -/** * efi_tcg2_get_capability() - protocol capability information and state information * * @this: TCG2 protocol instance @@ -758,7 +258,7 @@ efi_tcg2_get_capability(struct efi_tcg2_protocol *this, capability->protocol_version.major = 1; capability->protocol_version.minor = 1; - efi_ret = platform_get_tpm2_device(&dev); + efi_ret = tcg2_platform_get_tpm2(&dev); if (efi_ret != EFI_SUCCESS) { capability->supported_event_logs = 0; capability->hash_algorithm_bitmap = 0; @@ -854,7 +354,7 @@ efi_tcg2_get_eventlog(struct efi_tcg2_protocol *this, goto out; } - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) { event_log_location = NULL; event_log_last_entry = NULL; @@ -889,6 +389,7 @@ static efi_status_t tcg2_hash_pe_image(void *efi, u64 efi_size, struct efi_image_regions *regs = NULL; void *new_efi = NULL; u8 hash[TPM2_SHA512_DIGEST_SIZE]; + struct udevice *dev; efi_status_t ret; u32 active; int i; @@ -904,16 +405,20 @@ static efi_status_t tcg2_hash_pe_image(void *efi, u64 efi_size, goto out; } - ret = __get_active_pcr_banks(&active); + ret = tcg2_platform_get_tpm2(&dev); + if (ret != EFI_SUCCESS) + goto out; + + ret = tcg2_get_active_pcr_banks(dev, &active); if (ret != EFI_SUCCESS) { goto out; } digest_list->count = 0; - for (i = 0; i < MAX_HASH_COUNT; i++) { - u16 hash_alg = hash_algo_list[i].hash_alg; + for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); i++) { + u16 hash_alg = tpm2_supported_algorithms[i]; - if (!(active & alg_to_mask(hash_alg))) + if (!(active & tpm2_algorithm_to_mask(hash_alg))) continue; switch (hash_alg) { case TPM2_ALG_SHA1: @@ -933,7 +438,7 @@ static efi_status_t tcg2_hash_pe_image(void *efi, u64 efi_size, } digest_list->digests[digest_list->count].hash_alg = hash_alg; memcpy(&digest_list->digests[digest_list->count].digest, hash, - (u32)alg_to_len(hash_alg)); + (u32)tpm2_algorithm_to_len(hash_alg)); digest_list->count++; } @@ -973,7 +478,7 @@ efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size, if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) return EFI_SECURITY_VIOLATION; @@ -1082,7 +587,7 @@ efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, goto out; } - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) goto out; @@ -1117,7 +622,7 @@ efi_tcg2_hash_log_extend_event(struct efi_tcg2_protocol *this, u64 flags, ret = tcg2_hash_pe_image((void *)(uintptr_t)data_to_hash, data_to_hash_len, &digest_list); } else { - ret = tcg2_create_digest((u8 *)(uintptr_t)data_to_hash, + ret = tcg2_create_digest(dev, (u8 *)(uintptr_t)data_to_hash, data_to_hash_len, &digest_list); } @@ -1180,7 +685,7 @@ efi_tcg2_submit_command(struct efi_tcg2_protocol *this, goto out; } - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) goto out; @@ -1209,15 +714,20 @@ static efi_status_t EFIAPI efi_tcg2_get_active_pcr_banks(struct efi_tcg2_protocol *this, u32 *active_pcr_banks) { + struct udevice *dev; efi_status_t ret; + EFI_ENTRY("%p, %p", this, active_pcr_banks); + if (!this || !active_pcr_banks) { ret = EFI_INVALID_PARAMETER; goto out; } + ret = tcg2_platform_get_tpm2(&dev); + if (ret != EFI_SUCCESS) + goto out; - EFI_ENTRY("%p, %p", this, active_pcr_banks); - ret = __get_active_pcr_banks(active_pcr_banks); + ret = tcg2_get_active_pcr_banks(dev, active_pcr_banks); out: return EFI_EXIT(ret); @@ -1269,397 +779,6 @@ static const struct efi_tcg2_protocol efi_tcg2_protocol = { }; /** - * parse_event_log_header() - Parse and verify the event log header fields - * - * @buffer: Pointer to the start of the eventlog - * @size: Size of the eventlog - * @pos: Return offset of the next event in buffer right - * after the event header i.e specID - * - * Return: status code - */ -static efi_status_t parse_event_log_header(void *buffer, u32 size, u32 *pos) -{ - struct tcg_pcr_event *event_header = (struct tcg_pcr_event *)buffer; - int i = 0; - - if (size < sizeof(*event_header)) - return EFI_COMPROMISED_DATA; - - if (get_unaligned_le32(&event_header->pcr_index) != 0 || - get_unaligned_le32(&event_header->event_type) != EV_NO_ACTION) - return EFI_COMPROMISED_DATA; - - for (i = 0; i < sizeof(event_header->digest); i++) { - if (event_header->digest[i]) - return EFI_COMPROMISED_DATA; - } - - *pos += sizeof(*event_header); - - return EFI_SUCCESS; -} - -/** - * parse_specid_event() - Parse and verify the specID Event in the eventlog - * - * @dev: udevice - * @buffer: Pointer to the start of the eventlog - * @log_size: Size of the eventlog - * @pos: [in] Offset of specID event in the eventlog buffer - * [out] Return offset of the next event in the buffer - * after the specID - * @digest_list: list of digests in the event - * - * Return: status code - * @pos Offset in the eventlog where the specID event ends - * @digest_list: list of digests in the event - */ -static efi_status_t parse_specid_event(struct udevice *dev, void *buffer, - u32 log_size, u32 *pos, - struct tpml_digest_values *digest_list) -{ - struct tcg_efi_spec_id_event *spec_event; - struct tcg_pcr_event *event_header = (struct tcg_pcr_event *)buffer; - size_t spec_event_size; - u32 active = 0, supported = 0, pcr_count = 0, alg_count = 0; - u32 spec_active = 0; - u16 hash_alg; - u8 vendor_sz; - int err, i; - - if (*pos >= log_size || (*pos + sizeof(*spec_event)) > log_size) - return EFI_COMPROMISED_DATA; - - /* Check specID event data */ - spec_event = (struct tcg_efi_spec_id_event *)((uintptr_t)buffer + *pos); - /* Check for signature */ - if (memcmp(spec_event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03, - sizeof(TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03))) { - log_err("specID Event: Signature mismatch\n"); - return EFI_COMPROMISED_DATA; - } - - if (spec_event->spec_version_minor != - TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 || - spec_event->spec_version_major != - TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2) - return EFI_COMPROMISED_DATA; - - if (spec_event->number_of_algorithms > MAX_HASH_COUNT || - spec_event->number_of_algorithms < 1) { - log_err("specID Event: Number of algorithms incorrect\n"); - return EFI_COMPROMISED_DATA; - } - - alg_count = spec_event->number_of_algorithms; - - err = tpm2_get_pcr_info(dev, &supported, &active, &pcr_count); - if (err) - return EFI_DEVICE_ERROR; - - digest_list->count = 0; - /* - * We have to take care that the sequence of algorithms that we record - * in digest_list matches the sequence in eventlog. - */ - for (i = 0; i < alg_count; i++) { - hash_alg = - get_unaligned_le16(&spec_event->digest_sizes[i].algorithm_id); - - if (!(supported & alg_to_mask(hash_alg))) { - log_err("specID Event: Unsupported algorithm\n"); - return EFI_COMPROMISED_DATA; - } - digest_list->digests[digest_list->count++].hash_alg = hash_alg; - - spec_active |= alg_to_mask(hash_alg); - } - - /* - * TCG specification expects the event log to have hashes for all - * active PCR's - */ - if (spec_active != active) { - /* - * Previous stage bootloader should know all the active PCR's - * and use them in the Eventlog. - */ - log_err("specID Event: All active hash alg not present\n"); - return EFI_COMPROMISED_DATA; - } - - /* - * the size of the spec event and placement of vendor_info_size - * depends on supported algoriths - */ - spec_event_size = - offsetof(struct tcg_efi_spec_id_event, digest_sizes) + - alg_count * sizeof(spec_event->digest_sizes[0]); - - if (*pos + spec_event_size >= log_size) - return EFI_COMPROMISED_DATA; - - vendor_sz = *(uint8_t *)((uintptr_t)buffer + *pos + spec_event_size); - - spec_event_size += sizeof(vendor_sz) + vendor_sz; - *pos += spec_event_size; - - if (get_unaligned_le32(&event_header->event_size) != spec_event_size) { - log_err("specID event: header event size mismatch\n"); - /* Right way to handle this can be to call SetActive PCR's */ - return EFI_COMPROMISED_DATA; - } - - return EFI_SUCCESS; -} - -/** - * tcg2_parse_event() - Parse the event in the eventlog - * - * @dev: udevice - * @buffer: Pointer to the start of the eventlog - * @log_size: Size of the eventlog - * @offset: [in] Offset of the event in the eventlog buffer - * [out] Return offset of the next event in the buffer - * @digest_list: list of digests in the event - * @pcr Index of the PCR in the event - * - * Return: status code - */ -static efi_status_t tcg2_parse_event(struct udevice *dev, void *buffer, - u32 log_size, u32 *offset, - struct tpml_digest_values *digest_list, - u32 *pcr) -{ - struct tcg_pcr_event2 *event = NULL; - u32 count, size, event_size; - size_t pos; - - event_size = tcg_event_final_size(digest_list); - if (*offset >= log_size || *offset + event_size > log_size) { - log_err("Event exceeds log size\n"); - return EFI_COMPROMISED_DATA; - } - - event = (struct tcg_pcr_event2 *)((uintptr_t)buffer + *offset); - *pcr = get_unaligned_le32(&event->pcr_index); - - /* get the count */ - count = get_unaligned_le32(&event->digests.count); - if (count != digest_list->count) - return EFI_COMPROMISED_DATA; - - pos = offsetof(struct tcg_pcr_event2, digests); - pos += offsetof(struct tpml_digest_values, digests); - - for (int i = 0; i < digest_list->count; i++) { - u16 alg; - u16 hash_alg = digest_list->digests[i].hash_alg; - u8 *digest = (u8 *)&digest_list->digests[i].digest; - - alg = get_unaligned_le16((void *)((uintptr_t)event + pos)); - - if (alg != hash_alg) - return EFI_COMPROMISED_DATA; - - pos += offsetof(struct tpmt_ha, digest); - memcpy(digest, (void *)((uintptr_t)event + pos), alg_to_len(hash_alg)); - pos += alg_to_len(hash_alg); - } - - size = get_unaligned_le32((void *)((uintptr_t)event + pos)); - event_size += size; - pos += sizeof(u32); /* tcg_pcr_event2 event_size*/ - pos += size; - - /* make sure the calculated buffer is what we checked against */ - if (pos != event_size) - return EFI_COMPROMISED_DATA; - - if (pos > log_size) - return EFI_COMPROMISED_DATA; - - *offset += pos; - - return EFI_SUCCESS; -} - -/** - * tcg2_get_fw_eventlog() - Get the eventlog address and size - * - * If the previous firmware has passed some eventlog, this function get it's - * location and check for it's validity. - * - * @dev: udevice - * @log_buffer: eventlog address - * @log_sz: eventlog size - * - * Return: status code - */ -static efi_status_t tcg2_get_fw_eventlog(struct udevice *dev, void *log_buffer, - size_t *log_sz) -{ - struct tpml_digest_values digest_list; - void *buffer; - efi_status_t ret; - u32 pcr, pos; - u64 base; - u32 sz; - bool extend_pcr = false; - int i; - - ret = platform_get_eventlog(dev, &base, &sz); - if (ret != EFI_SUCCESS) - return ret; - - if (sz > TPM2_EVENT_LOG_SIZE) - return EFI_VOLUME_FULL; - - buffer = (void *)(uintptr_t)base; - pos = 0; - /* Parse the eventlog to check for its validity */ - ret = parse_event_log_header(buffer, sz, &pos); - if (ret) - return ret; - - ret = parse_specid_event(dev, buffer, sz, &pos, &digest_list); - if (ret) { - log_err("Error parsing SPEC ID Event\n"); - return ret; - } - - ret = tcg2_pcr_read(dev, 0, &digest_list); - if (ret) { - log_err("Error reading PCR 0\n"); - return ret; - } - - /* - * If PCR0 is 0, previous firmware didn't have the capability - * to extend the PCR. In this scenario, extend the PCR as - * the eventlog is parsed. - */ - for (i = 0; i < digest_list.count; i++) { - u8 hash_buf[TPM2_SHA512_DIGEST_SIZE] = { 0 }; - u16 hash_alg = digest_list.digests[i].hash_alg; - - if (!memcmp((u8 *)&digest_list.digests[i].digest, hash_buf, - alg_to_len(hash_alg))) - extend_pcr = true; - } - - while (pos < sz) { - ret = tcg2_parse_event(dev, buffer, sz, &pos, &digest_list, - &pcr); - if (ret) { - log_err("Error parsing event\n"); - return ret; - } - if (extend_pcr) { - ret = tcg2_pcr_extend(dev, pcr, &digest_list); - if (ret != EFI_SUCCESS) { - log_err("Error in extending PCR\n"); - return ret; - } - - /* Clear the digest for next event */ - for (i = 0; i < digest_list.count; i++) { - u16 hash_alg = digest_list.digests[i].hash_alg; - u8 *digest = - (u8 *)&digest_list.digests[i].digest; - - memset(digest, 0, alg_to_len(hash_alg)); - } - } - } - - memcpy(log_buffer, buffer, sz); - *log_sz = sz; - - return ret; -} - -/** - * create_specid_event() - Create the first event in the eventlog - * - * @dev: tpm device - * @event_header: Pointer to the final event header - * @event_size: final spec event size - * - * Return: status code - */ -static efi_status_t create_specid_event(struct udevice *dev, void *buffer, - size_t *event_size) -{ - struct tcg_efi_spec_id_event *spec_event; - size_t spec_event_size; - efi_status_t ret = EFI_DEVICE_ERROR; - u32 active = 0, supported = 0, pcr_count = 0, alg_count = 0; - int err; - size_t i; - - /* - * Create Spec event. This needs to be the first event in the log - * according to the TCG EFI protocol spec - */ - - /* Setup specID event data */ - spec_event = (struct tcg_efi_spec_id_event *)buffer; - memcpy(spec_event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03, - sizeof(spec_event->signature)); - put_unaligned_le32(0, &spec_event->platform_class); /* type client */ - spec_event->spec_version_minor = - TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2; - spec_event->spec_version_major = - TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2; - spec_event->spec_errata = - TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2; - spec_event->uintn_size = sizeof(efi_uintn_t) / sizeof(u32); - - err = tpm2_get_pcr_info(dev, &supported, &active, &pcr_count); - - if (err) - goto out; - - for (i = 0; i < pcr_count; i++) { - u16 hash_alg = hash_algo_list[i].hash_alg; - u16 hash_len = hash_algo_list[i].hash_len; - - if (active & alg_to_mask(hash_alg)) { - put_unaligned_le16(hash_alg, - &spec_event->digest_sizes[alg_count].algorithm_id); - put_unaligned_le16(hash_len, - &spec_event->digest_sizes[alg_count].digest_size); - alg_count++; - } - } - - spec_event->number_of_algorithms = alg_count; - if (spec_event->number_of_algorithms > MAX_HASH_COUNT || - spec_event->number_of_algorithms < 1) - goto out; - - /* - * the size of the spec event and placement of vendor_info_size - * depends on supported algoriths - */ - spec_event_size = - offsetof(struct tcg_efi_spec_id_event, digest_sizes) + - spec_event->number_of_algorithms * sizeof(spec_event->digest_sizes[0]); - /* no vendor info for us */ - memset(buffer + spec_event_size, 0, 1); - /* add a byte for vendor_info_size in the spec event */ - spec_event_size += 1; - *event_size = spec_event_size; - - return EFI_SUCCESS; - -out: - return ret; -} - -/** * tcg2_uninit - remove the final event table and free efi memory on failures */ void tcg2_uninit(void) @@ -1720,7 +839,7 @@ out: } /** - * tcg2_measure_event() - common function to add event log and extend PCR + * measure_event() - common function to add event log and extend PCR * * @dev: TPM device * @pcr_index: PCR index @@ -1730,14 +849,13 @@ out: * * Return: status code */ -static efi_status_t -tcg2_measure_event(struct udevice *dev, u32 pcr_index, u32 event_type, - u32 size, u8 event[]) +static efi_status_t measure_event(struct udevice *dev, u32 pcr_index, + u32 event_type, u32 size, u8 event[]) { struct tpml_digest_values digest_list; efi_status_t ret; - ret = tcg2_create_digest(event, size, &digest_list); + ret = tcg2_create_digest(dev, event, size, &digest_list); if (ret != EFI_SUCCESS) goto out; @@ -1764,9 +882,8 @@ static efi_status_t efi_append_scrtm_version(struct udevice *dev) { efi_status_t ret; - ret = tcg2_measure_event(dev, 0, EV_S_CRTM_VERSION, - strlen(version_string) + 1, - (u8 *)version_string); + ret = measure_event(dev, 0, EV_S_CRTM_VERSION, + strlen(version_string) + 1, (u8 *)version_string); return ret; } @@ -1782,12 +899,11 @@ static efi_status_t efi_init_event_log(void) * vendor_info_size is currently set to 0, we need to change the length * and allocate the flexible array member if this changes */ - struct tcg_pcr_event *event_header = NULL; + struct tcg2_event_log elog; struct udevice *dev; - size_t spec_event_size; efi_status_t ret; - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) return ret; @@ -1806,7 +922,6 @@ static efi_status_t efi_init_event_log(void) * The log header is defined to be in SHA1 event log entry format. * Setup event header */ - event_header = (struct tcg_pcr_event *)event_log.buffer; event_log.pos = 0; event_log.last_event_size = 0; event_log.get_event_called = false; @@ -1817,34 +932,20 @@ static efi_status_t efi_init_event_log(void) * Check if earlier firmware have passed any eventlog. Different * platforms can use different ways to do so. */ - ret = tcg2_get_fw_eventlog(dev, event_log.buffer, &event_log.pos); + elog.log = event_log.buffer; + elog.log_size = TPM2_EVENT_LOG_SIZE; + ret = tcg2_log_prepare_buffer(dev, &elog, false); + if (ret != EFI_SUCCESS) + goto free_pool; + + event_log.pos = elog.log_position; + /* - * If earlier firmware hasn't passed any eventlog, go ahead and - * create the eventlog header. + * Add SCRTM version to the log if previous firmmware + * doesn't pass an eventlog. */ - if (ret == EFI_NOT_FOUND) { - put_unaligned_le32(0, &event_header->pcr_index); - put_unaligned_le32(EV_NO_ACTION, &event_header->event_type); - memset(&event_header->digest, 0, sizeof(event_header->digest)); - ret = create_specid_event(dev, - (void *)((uintptr_t)event_log.buffer + - sizeof(*event_header)), - &spec_event_size); - if (ret != EFI_SUCCESS) - goto free_pool; - put_unaligned_le32(spec_event_size, &event_header->event_size); - event_log.pos = spec_event_size + sizeof(*event_header); - event_log.last_event_size = event_log.pos; - - /* - * Add SCRTM version to the log if previous firmmware - * doesn't pass an eventlog. - */ + if (!elog.found) ret = efi_append_scrtm_version(dev); - } - - if (ret != EFI_SUCCESS) - goto free_pool; ret = create_final_event(); if (ret != EFI_SUCCESS) @@ -1897,8 +998,8 @@ static efi_status_t tcg2_measure_variable(struct udevice *dev, u32 pcr_index, memcpy((u16 *)event->unicode_name + event->unicode_name_length, data, data_size); } - ret = tcg2_measure_event(dev, pcr_index, event_type, event_size, - (u8 *)event); + ret = measure_event(dev, pcr_index, event_type, event_size, + (u8 *)event); free(event); return ret; } @@ -2009,8 +1110,8 @@ tcg2_measure_smbios(struct udevice *dev, smbios_prepare_measurement(entry, smbios_copy); - ret = tcg2_measure_event(dev, 1, EV_EFI_HANDOFF_TABLES2, event_size, - (u8 *)event); + ret = measure_event(dev, 1, EV_EFI_HANDOFF_TABLES2, event_size, + (u8 *)event); if (ret != EFI_SUCCESS) goto out; @@ -2161,7 +1262,7 @@ tcg2_measure_gpt_data(struct udevice *dev, gpt_e = (gpt_entry *)((u8 *)gpt_e + gpt_h->sizeof_partition_entry); } - ret = tcg2_measure_event(dev, 5, EV_EFI_GPT_EVENT, event_size, (u8 *)event); + ret = measure_event(dev, 5, EV_EFI_GPT_EVENT, event_size, (u8 *)event); out2: free(gpt_h); @@ -2215,7 +1316,7 @@ efi_status_t efi_tcg2_measure_dtb(void *dtb) if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) return EFI_SECURITY_VIOLATION; @@ -2240,7 +1341,7 @@ efi_status_t efi_tcg2_measure_dtb(void *dtb) sha256_update(&hash_ctx, (u8 *)dtb + fdt_off_mem_rsvmap(dtb), rsvmap_size); sha256_finish(&hash_ctx, blob->data + blob->blob_description_size); - ret = tcg2_measure_event(dev, 0, EV_POST_CODE, event_size, (u8 *)blob); + ret = measure_event(dev, 0, EV_POST_CODE, event_size, (u8 *)blob); free(blob); return ret; @@ -2265,7 +1366,7 @@ efi_status_t efi_tcg2_measure_efi_app_invocation(struct efi_loaded_image_obj *ha if (tcg2_efi_app_invoked) return EFI_SUCCESS; - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) return EFI_SECURITY_VIOLATION; @@ -2273,9 +1374,9 @@ efi_status_t efi_tcg2_measure_efi_app_invocation(struct efi_loaded_image_obj *ha if (ret != EFI_SUCCESS) goto out; - ret = tcg2_measure_event(dev, 4, EV_EFI_ACTION, - strlen(EFI_CALLING_EFI_APPLICATION), - (u8 *)EFI_CALLING_EFI_APPLICATION); + ret = measure_event(dev, 4, EV_EFI_ACTION, + strlen(EFI_CALLING_EFI_APPLICATION), + (u8 *)EFI_CALLING_EFI_APPLICATION); if (ret != EFI_SUCCESS) goto out; @@ -2291,8 +1392,8 @@ efi_status_t efi_tcg2_measure_efi_app_invocation(struct efi_loaded_image_obj *ha goto out; for (pcr_index = 0; pcr_index <= 7; pcr_index++) { - ret = tcg2_measure_event(dev, pcr_index, EV_SEPARATOR, - sizeof(event), (u8 *)&event); + ret = measure_event(dev, pcr_index, EV_SEPARATOR, + sizeof(event), (u8 *)&event); if (ret != EFI_SUCCESS) goto out; } @@ -2315,13 +1416,13 @@ efi_status_t efi_tcg2_measure_efi_app_exit(void) if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) return ret; - ret = tcg2_measure_event(dev, 4, EV_EFI_ACTION, - strlen(EFI_RETURNING_FROM_EFI_APPLICATION), - (u8 *)EFI_RETURNING_FROM_EFI_APPLICATION); + ret = measure_event(dev, 4, EV_EFI_ACTION, + strlen(EFI_RETURNING_FROM_EFI_APPLICATION), + (u8 *)EFI_RETURNING_FROM_EFI_APPLICATION); return ret; } @@ -2346,19 +1447,19 @@ efi_tcg2_notify_exit_boot_services(struct efi_event *event, void *context) goto out; } - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) goto out; - ret = tcg2_measure_event(dev, 5, EV_EFI_ACTION, - strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION), - (u8 *)EFI_EXIT_BOOT_SERVICES_INVOCATION); + ret = measure_event(dev, 5, EV_EFI_ACTION, + strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION), + (u8 *)EFI_EXIT_BOOT_SERVICES_INVOCATION); if (ret != EFI_SUCCESS) goto out; - ret = tcg2_measure_event(dev, 5, EV_EFI_ACTION, - strlen(EFI_EXIT_BOOT_SERVICES_SUCCEEDED), - (u8 *)EFI_EXIT_BOOT_SERVICES_SUCCEEDED); + ret = measure_event(dev, 5, EV_EFI_ACTION, + strlen(EFI_EXIT_BOOT_SERVICES_SUCCEEDED), + (u8 *)EFI_EXIT_BOOT_SERVICES_SUCCEEDED); out: EFI_EXIT(ret); @@ -2378,19 +1479,19 @@ efi_status_t efi_tcg2_notify_exit_boot_services_failed(void) if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) goto out; - ret = tcg2_measure_event(dev, 5, EV_EFI_ACTION, - strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION), - (u8 *)EFI_EXIT_BOOT_SERVICES_INVOCATION); + ret = measure_event(dev, 5, EV_EFI_ACTION, + strlen(EFI_EXIT_BOOT_SERVICES_INVOCATION), + (u8 *)EFI_EXIT_BOOT_SERVICES_INVOCATION); if (ret != EFI_SUCCESS) goto out; - ret = tcg2_measure_event(dev, 5, EV_EFI_ACTION, - strlen(EFI_EXIT_BOOT_SERVICES_FAILED), - (u8 *)EFI_EXIT_BOOT_SERVICES_FAILED); + ret = measure_event(dev, 5, EV_EFI_ACTION, + strlen(EFI_EXIT_BOOT_SERVICES_FAILED), + (u8 *)EFI_EXIT_BOOT_SERVICES_FAILED); out: return ret; @@ -2460,7 +1561,7 @@ efi_status_t efi_tcg2_do_initial_measurement(void) if (!is_tcg2_protocol_installed()) return EFI_SUCCESS; - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) return EFI_SECURITY_VIOLATION; @@ -2486,7 +1587,7 @@ efi_status_t efi_tcg2_register(void) struct efi_event *event; u32 err; - ret = platform_get_tpm2_device(&dev); + ret = tcg2_platform_get_tpm2(&dev); if (ret != EFI_SUCCESS) { log_warning("Missing TPMv2 device for EFI_TCG_PROTOCOL\n"); return EFI_SUCCESS; diff --git a/lib/image-sparse.c b/lib/image-sparse.c index 8f8a67e1580..323aad981c6 100644 --- a/lib/image-sparse.c +++ b/lib/image-sparse.c @@ -289,8 +289,8 @@ int write_sparse_image(struct sparse_storage *info, case CHUNK_TYPE_CRC32: if (chunk_header->total_sz != - sparse_header->chunk_hdr_sz) { - info->mssg("Bogus chunk size for chunk type Dont Care", + sparse_header->chunk_hdr_sz + sizeof(uint32_t)) { + info->mssg("Bogus chunk size for chunk type CRC32", response); return -1; } diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c index 9ab5b46df17..bd0fb078dc3 100644 --- a/lib/tpm-v2.c +++ b/lib/tpm-v2.c @@ -1,16 +1,705 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (c) 2023 Linaro Limited * Copyright (c) 2018 Bootlin * Author: Miquel Raynal <miquel.raynal@bootlin.com> */ #include <common.h> #include <dm.h> +#include <dm/of_access.h> +#include <tpm_api.h> #include <tpm-common.h> #include <tpm-v2.h> +#include <u-boot/sha1.h> +#include <u-boot/sha256.h> +#include <u-boot/sha512.h> +#include <version_string.h> +#include <asm/io.h> #include <linux/bitops.h> +#include <linux/unaligned/be_byteshift.h> +#include <linux/unaligned/generic.h> +#include <linux/unaligned/le_byteshift.h> + #include "tpm-utils.h" +const enum tpm2_algorithms tpm2_supported_algorithms[4] = { + TPM2_ALG_SHA1, + TPM2_ALG_SHA256, + TPM2_ALG_SHA384, + TPM2_ALG_SHA512, +}; + +int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks) +{ + u32 supported = 0; + u32 pcr_banks = 0; + u32 active = 0; + int rc; + + rc = tpm2_get_pcr_info(dev, &supported, &active, &pcr_banks); + if (rc) + return rc; + + *active_pcr_banks = active; + + return 0; +} + +u32 tcg2_event_get_size(struct tpml_digest_values *digest_list) +{ + u32 len; + size_t i; + + len = offsetof(struct tcg_pcr_event2, digests); + len += offsetof(struct tpml_digest_values, digests); + for (i = 0; i < digest_list->count; ++i) { + u16 l = tpm2_algorithm_to_len(digest_list->digests[i].hash_alg); + + if (!l) + continue; + + len += l + offsetof(struct tpmt_ha, digest); + } + len += sizeof(u32); + + return len; +} + +int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length, + struct tpml_digest_values *digest_list) +{ + u8 final[sizeof(union tpmu_ha)]; + sha256_context ctx_256; + sha512_context ctx_512; + sha1_context ctx; + u32 active; + size_t i; + u32 len; + int rc; + + rc = tcg2_get_active_pcr_banks(dev, &active); + if (rc) + return rc; + + digest_list->count = 0; + for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) { + u32 mask = + tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]); + + if (!(active & mask)) + continue; + + switch (tpm2_supported_algorithms[i]) { + case TPM2_ALG_SHA1: + sha1_starts(&ctx); + sha1_update(&ctx, input, length); + sha1_finish(&ctx, final); + len = TPM2_SHA1_DIGEST_SIZE; + break; + case TPM2_ALG_SHA256: + sha256_starts(&ctx_256); + sha256_update(&ctx_256, input, length); + sha256_finish(&ctx_256, final); + len = TPM2_SHA256_DIGEST_SIZE; + break; + case TPM2_ALG_SHA384: + sha384_starts(&ctx_512); + sha384_update(&ctx_512, input, length); + sha384_finish(&ctx_512, final); + len = TPM2_SHA384_DIGEST_SIZE; + break; + case TPM2_ALG_SHA512: + sha512_starts(&ctx_512); + sha512_update(&ctx_512, input, length); + sha512_finish(&ctx_512, final); + len = TPM2_SHA512_DIGEST_SIZE; + break; + default: + printf("%s: unsupported algorithm %x\n", __func__, + tpm2_supported_algorithms[i]); + continue; + } + + digest_list->digests[digest_list->count].hash_alg = + tpm2_supported_algorithms[i]; + memcpy(&digest_list->digests[digest_list->count].digest, final, + len); + digest_list->count++; + } + + return 0; +} + +void tcg2_log_append(u32 pcr_index, u32 event_type, + struct tpml_digest_values *digest_list, u32 size, + const u8 *event, u8 *log) +{ + size_t len; + size_t pos; + u32 i; + + pos = offsetof(struct tcg_pcr_event2, pcr_index); + put_unaligned_le32(pcr_index, log); + pos = offsetof(struct tcg_pcr_event2, event_type); + put_unaligned_le32(event_type, log + pos); + pos = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, count); + put_unaligned_le32(digest_list->count, log + pos); + + pos = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, digests); + for (i = 0; i < digest_list->count; ++i) { + u16 hash_alg = digest_list->digests[i].hash_alg; + + len = tpm2_algorithm_to_len(hash_alg); + if (!len) + continue; + + pos += offsetof(struct tpmt_ha, hash_alg); + put_unaligned_le16(hash_alg, log + pos); + pos += offsetof(struct tpmt_ha, digest); + memcpy(log + pos, (u8 *)&digest_list->digests[i].digest, len); + pos += len; + } + + put_unaligned_le32(size, log + pos); + pos += sizeof(u32); + memcpy(log + pos, event, size); +} + +static int tcg2_log_append_check(struct tcg2_event_log *elog, u32 pcr_index, + u32 event_type, + struct tpml_digest_values *digest_list, + u32 size, const u8 *event) +{ + u32 event_size; + u8 *log; + + event_size = size + tcg2_event_get_size(digest_list); + if (elog->log_position + event_size > elog->log_size) { + printf("%s: log too large: %u + %u > %u\n", __func__, + elog->log_position, event_size, elog->log_size); + return -ENOBUFS; + } + + log = elog->log + elog->log_position; + elog->log_position += event_size; + + tcg2_log_append(pcr_index, event_type, digest_list, size, event, log); + + return 0; +} + +static int tcg2_log_init(struct udevice *dev, struct tcg2_event_log *elog) +{ + struct tcg_efi_spec_id_event *ev; + struct tcg_pcr_event *log; + u32 event_size; + u32 count = 0; + u32 log_size; + u32 active; + u32 mask; + size_t i; + u16 len; + int rc; + + rc = tcg2_get_active_pcr_banks(dev, &active); + if (rc) + return rc; + + event_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes); + for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) { + mask = tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]); + + if (!(active & mask)) + continue; + + switch (tpm2_supported_algorithms[i]) { + case TPM2_ALG_SHA1: + case TPM2_ALG_SHA256: + case TPM2_ALG_SHA384: + case TPM2_ALG_SHA512: + count++; + break; + default: + continue; + } + } + + event_size += 1 + + (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count); + log_size = offsetof(struct tcg_pcr_event, event) + event_size; + + if (log_size > elog->log_size) { + printf("%s: log too large: %u > %u\n", __func__, log_size, + elog->log_size); + return -ENOBUFS; + } + + log = (struct tcg_pcr_event *)elog->log; + put_unaligned_le32(0, &log->pcr_index); + put_unaligned_le32(EV_NO_ACTION, &log->event_type); + memset(&log->digest, 0, sizeof(log->digest)); + put_unaligned_le32(event_size, &log->event_size); + + ev = (struct tcg_efi_spec_id_event *)log->event; + strlcpy((char *)ev->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03, + sizeof(ev->signature)); + put_unaligned_le32(0, &ev->platform_class); + ev->spec_version_minor = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2; + ev->spec_version_major = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2; + ev->spec_errata = TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2; + ev->uintn_size = sizeof(size_t) / sizeof(u32); + put_unaligned_le32(count, &ev->number_of_algorithms); + + count = 0; + for (i = 0; i < ARRAY_SIZE(tpm2_supported_algorithms); ++i) { + mask = tpm2_algorithm_to_mask(tpm2_supported_algorithms[i]); + + if (!(active & mask)) + continue; + + len = tpm2_algorithm_to_len(tpm2_supported_algorithms[i]); + if (!len) + continue; + + put_unaligned_le16(tpm2_supported_algorithms[i], + &ev->digest_sizes[count].algorithm_id); + put_unaligned_le16(len, &ev->digest_sizes[count].digest_size); + count++; + } + + *((u8 *)ev + (event_size - 1)) = 0; + elog->log_position = log_size; + + return 0; +} + +static int tcg2_replay_eventlog(struct tcg2_event_log *elog, + struct udevice *dev, + struct tpml_digest_values *digest_list, + u32 log_position) +{ + const u32 offset = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, digests); + u32 event_size; + u32 count; + u16 algo; + u32 pcr; + u32 pos; + u16 len; + u8 *log; + int rc; + u32 i; + + while (log_position + offset < elog->log_size) { + log = elog->log + log_position; + + pos = offsetof(struct tcg_pcr_event2, pcr_index); + pcr = get_unaligned_le32(log + pos); + pos = offsetof(struct tcg_pcr_event2, event_type); + if (!get_unaligned_le32(log + pos)) + return 0; + + pos = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, count); + count = get_unaligned_le32(log + pos); + if (count > ARRAY_SIZE(tpm2_supported_algorithms) || + (digest_list->count && digest_list->count != count)) + return 0; + + pos = offsetof(struct tcg_pcr_event2, digests) + + offsetof(struct tpml_digest_values, digests); + for (i = 0; i < count; ++i) { + pos += offsetof(struct tpmt_ha, hash_alg); + if (log_position + pos + sizeof(u16) >= elog->log_size) + return 0; + + algo = get_unaligned_le16(log + pos); + pos += offsetof(struct tpmt_ha, digest); + switch (algo) { + case TPM2_ALG_SHA1: + case TPM2_ALG_SHA256: + case TPM2_ALG_SHA384: + case TPM2_ALG_SHA512: + len = tpm2_algorithm_to_len(algo); + break; + default: + return 0; + } + + if (digest_list->count) { + if (algo != digest_list->digests[i].hash_alg || + log_position + pos + len >= elog->log_size) + return 0; + + memcpy(digest_list->digests[i].digest.sha512, + log + pos, len); + } + + pos += len; + } + + if (log_position + pos + sizeof(u32) >= elog->log_size) + return 0; + + event_size = get_unaligned_le32(log + pos); + pos += event_size + sizeof(u32); + if (log_position + pos > elog->log_size) + return 0; + + if (digest_list->count) { + rc = tcg2_pcr_extend(dev, pcr, digest_list); + if (rc) + return rc; + } + + log_position += pos; + } + + elog->log_position = log_position; + elog->found = true; + return 0; +} + +static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) +{ + struct tpml_digest_values digest_list; + struct tcg_efi_spec_id_event *event; + struct tcg_pcr_event *log; + u32 log_active; + u32 calc_size; + u32 active; + u32 count; + u32 evsz; + u32 mask; + u16 algo; + u16 len; + int rc; + u32 i; + u16 j; + + if (elog->log_size <= offsetof(struct tcg_pcr_event, event)) + return 0; + + log = (struct tcg_pcr_event *)elog->log; + if (get_unaligned_le32(&log->pcr_index) != 0 || + get_unaligned_le32(&log->event_type) != EV_NO_ACTION) + return 0; + + for (i = 0; i < sizeof(log->digest); i++) { + if (log->digest[i]) + return 0; + } + + evsz = get_unaligned_le32(&log->event_size); + if (evsz < offsetof(struct tcg_efi_spec_id_event, digest_sizes) || + evsz + offsetof(struct tcg_pcr_event, event) > elog->log_size) + return 0; + + event = (struct tcg_efi_spec_id_event *)log->event; + if (memcmp(event->signature, TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03, + sizeof(TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03))) + return 0; + + if (event->spec_version_minor != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 || + event->spec_version_major != TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2) + return 0; + + count = get_unaligned_le32(&event->number_of_algorithms); + if (count > ARRAY_SIZE(tpm2_supported_algorithms)) + return 0; + + calc_size = offsetof(struct tcg_efi_spec_id_event, digest_sizes) + + (sizeof(struct tcg_efi_spec_id_event_algorithm_size) * count) + + 1; + if (evsz != calc_size) + return 0; + + rc = tcg2_get_active_pcr_banks(dev, &active); + if (rc) + return rc; + + digest_list.count = 0; + log_active = 0; + + for (i = 0; i < count; ++i) { + algo = get_unaligned_le16(&event->digest_sizes[i].algorithm_id); + mask = tpm2_algorithm_to_mask(algo); + + if (!(active & mask)) + return 0; + + switch (algo) { + case TPM2_ALG_SHA1: + case TPM2_ALG_SHA256: + case TPM2_ALG_SHA384: + case TPM2_ALG_SHA512: + len = get_unaligned_le16(&event->digest_sizes[i].digest_size); + if (tpm2_algorithm_to_len(algo) != len) + return 0; + digest_list.digests[digest_list.count++].hash_alg = algo; + break; + default: + return 0; + } + + log_active |= mask; + } + + /* Ensure the previous firmware extended all the PCRs. */ + if (log_active != active) + return 0; + + /* Read PCR0 to check if previous firmware extended the PCRs or not. */ + rc = tcg2_pcr_read(dev, 0, &digest_list); + if (rc) + return rc; + + for (i = 0; i < digest_list.count; ++i) { + len = tpm2_algorithm_to_len(digest_list.digests[i].hash_alg); + for (j = 0; j < len; ++j) { + if (digest_list.digests[i].digest.sha512[j]) + break; + } + + /* PCR is non-zero; it has been extended, so skip extending. */ + if (j != len) { + digest_list.count = 0; + break; + } + } + + return tcg2_replay_eventlog(elog, dev, &digest_list, + offsetof(struct tcg_pcr_event, event) + + evsz); +} + +int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index, + struct tpml_digest_values *digest_list) +{ + u32 rc; + u32 i; + + for (i = 0; i < digest_list->count; i++) { + u32 alg = digest_list->digests[i].hash_alg; + + rc = tpm2_pcr_extend(dev, pcr_index, alg, + (u8 *)&digest_list->digests[i].digest, + tpm2_algorithm_to_len(alg)); + if (rc) { + printf("%s: error pcr:%u alg:%08x\n", __func__, + pcr_index, alg); + return rc; + } + } + + return 0; +} + +int tcg2_pcr_read(struct udevice *dev, u32 pcr_index, + struct tpml_digest_values *digest_list) +{ + struct tpm_chip_priv *priv; + u32 rc; + u32 i; + + priv = dev_get_uclass_priv(dev); + if (!priv) + return -ENODEV; + + for (i = 0; i < digest_list->count; i++) { + u32 alg = digest_list->digests[i].hash_alg; + u8 *digest = (u8 *)&digest_list->digests[i].digest; + + rc = tpm2_pcr_read(dev, pcr_index, priv->pcr_select_min, alg, + digest, tpm2_algorithm_to_len(alg), NULL); + if (rc) { + printf("%s: error pcr:%u alg:%08x\n", __func__, + pcr_index, alg); + return rc; + } + } + + return 0; +} + +int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog, + u32 pcr_index, u32 size, const u8 *data, u32 event_type, + u32 event_size, const u8 *event) +{ + struct tpml_digest_values digest_list; + int rc; + + if (data) + rc = tcg2_create_digest(dev, data, size, &digest_list); + else + rc = tcg2_create_digest(dev, event, event_size, &digest_list); + if (rc) + return rc; + + rc = tcg2_pcr_extend(dev, pcr_index, &digest_list); + if (rc) + return rc; + + return tcg2_log_append_check(elog, pcr_index, event_type, &digest_list, + event_size, event); +} + +int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, + bool ignore_existing_log) +{ + struct tcg2_event_log log; + int rc; + + elog->log_position = 0; + elog->found = false; + + rc = tcg2_platform_get_log(dev, (void **)&log.log, &log.log_size); + if (!rc) { + log.log_position = 0; + log.found = false; + + if (!ignore_existing_log) { + rc = tcg2_log_parse(dev, &log); + if (rc) + return rc; + } + + if (elog->log_size) { + if (log.found) { + if (elog->log_size < log.log_position) + return -ENOSPC; + + /* + * Copy the discovered log into the user buffer + * if there's enough space. + */ + memcpy(elog->log, log.log, log.log_position); + } + + unmap_physmem(log.log, MAP_NOCACHE); + } else { + elog->log = log.log; + elog->log_size = log.log_size; + } + + elog->log_position = log.log_position; + elog->found = log.found; + } + + /* + * Initialize the log buffer if no log was discovered and the buffer is + * valid. User's can pass in their own buffer as a fallback if no + * memory region is found. + */ + if (!elog->found && elog->log_size) + rc = tcg2_log_init(dev, elog); + + return rc; +} + +int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog, + bool ignore_existing_log) +{ + int rc; + + rc = tcg2_platform_get_tpm2(dev); + if (rc) + return rc; + + rc = tpm_auto_start(*dev); + if (rc) + return rc; + + rc = tcg2_log_prepare_buffer(*dev, elog, ignore_existing_log); + if (rc) { + tcg2_measurement_term(*dev, elog, true); + return rc; + } + + rc = tcg2_measure_event(*dev, elog, 0, EV_S_CRTM_VERSION, + strlen(version_string) + 1, + (u8 *)version_string); + if (rc) { + tcg2_measurement_term(*dev, elog, true); + return rc; + } + + return 0; +} + +void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog, + bool error) +{ + u32 event = error ? 0x1 : 0xffffffff; + int i; + + for (i = 0; i < 8; ++i) + tcg2_measure_event(dev, elog, i, EV_SEPARATOR, sizeof(event), + (const u8 *)&event); + + if (elog->log) + unmap_physmem(elog->log, MAP_NOCACHE); +} + +__weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size) +{ + const __be32 *addr_prop; + const __be32 *size_prop; + int asize; + int ssize; + + *addr = NULL; + *size = 0; + + addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize); + if (!addr_prop) + addr_prop = dev_read_prop(dev, "linux,sml-base", &asize); + + size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize); + if (!size_prop) + size_prop = dev_read_prop(dev, "linux,sml-size", &ssize); + + if (addr_prop && size_prop) { + u64 a = of_read_number(addr_prop, asize / sizeof(__be32)); + u64 s = of_read_number(size_prop, ssize / sizeof(__be32)); + + *addr = map_physmem(a, s, MAP_NOCACHE); + *size = (u32)s; + } else { + struct ofnode_phandle_args args; + phys_addr_t a; + fdt_size_t s; + + if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0, + 0, &args)) + return -ENODEV; + + a = ofnode_get_addr_size(args.node, "reg", &s); + if (a == FDT_ADDR_T_NONE) + return -ENOMEM; + + *addr = map_physmem(a, s, MAP_NOCACHE); + *size = (u32)s; + } + + return 0; +} + +__weak int tcg2_platform_get_tpm2(struct udevice **dev) +{ + for_each_tpm_device(*dev) { + if (tpm_get_version(*dev) == TPM_V2) + return 0; + } + + return -ENODEV; +} + +__weak void tcg2_platform_startup_error(struct udevice *dev, int rc) {} + u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode) { const u8 command_v2[12] = { @@ -359,6 +1048,131 @@ u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property, return 0; } +static int tpm2_get_num_pcr(struct udevice *dev, u32 *num_pcr) +{ + u8 response[(sizeof(struct tpms_capability_data) - + offsetof(struct tpms_capability_data, data))]; + u32 properties_offset = + offsetof(struct tpml_tagged_tpm_property, tpm_property) + + offsetof(struct tpms_tagged_property, value); + u32 ret; + + memset(response, 0, sizeof(response)); + ret = tpm2_get_capability(dev, TPM2_CAP_TPM_PROPERTIES, + TPM2_PT_PCR_COUNT, response, 1); + if (ret) + return ret; + + *num_pcr = get_unaligned_be32(response + properties_offset); + if (*num_pcr > TPM2_MAX_PCRS) { + printf("%s: too many pcrs: %u\n", __func__, *num_pcr); + return -E2BIG; + } + + return 0; +} + +static bool tpm2_is_active_pcr(struct tpms_pcr_selection *selection) +{ + int i; + + /* + * check the pcr_select. If at least one of the PCRs supports the + * algorithm add it on the active ones + */ + for (i = 0; i < selection->size_of_select; i++) { + if (selection->pcr_select[i]) + return true; + } + + return false; +} + +int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr, + u32 *pcr_banks) +{ + u8 response[(sizeof(struct tpms_capability_data) - + offsetof(struct tpms_capability_data, data))]; + struct tpml_pcr_selection pcrs; + u32 num_pcr; + size_t i; + u32 ret; + + *supported_pcr = 0; + *active_pcr = 0; + *pcr_banks = 0; + memset(response, 0, sizeof(response)); + ret = tpm2_get_capability(dev, TPM2_CAP_PCRS, 0, response, 1); + if (ret) + return ret; + + pcrs.count = get_unaligned_be32(response); + /* + * We only support 5 algorithms for now so check against that + * instead of TPM2_NUM_PCR_BANKS + */ + if (pcrs.count > ARRAY_SIZE(tpm2_supported_algorithms) || + pcrs.count < 1) { + printf("%s: too many pcrs: %u\n", __func__, pcrs.count); + return -EMSGSIZE; + } + + ret = tpm2_get_num_pcr(dev, &num_pcr); + if (ret) + return ret; + + for (i = 0; i < pcrs.count; i++) { + /* + * Definition of TPMS_PCR_SELECTION Structure + * hash: u16 + * size_of_select: u8 + * pcr_select: u8 array + * + * The offsets depend on the number of the device PCRs + * so we have to calculate them based on that + */ + u32 hash_offset = offsetof(struct tpml_pcr_selection, selection) + + i * offsetof(struct tpms_pcr_selection, pcr_select) + + i * ((num_pcr + 7) / 8); + u32 size_select_offset = + hash_offset + offsetof(struct tpms_pcr_selection, + size_of_select); + u32 pcr_select_offset = + hash_offset + offsetof(struct tpms_pcr_selection, + pcr_select); + + pcrs.selection[i].hash = + get_unaligned_be16(response + hash_offset); + pcrs.selection[i].size_of_select = + __get_unaligned_be(response + size_select_offset); + if (pcrs.selection[i].size_of_select > TPM2_PCR_SELECT_MAX) { + printf("%s: pcrs selection too large: %u\n", __func__, + pcrs.selection[i].size_of_select); + return -ENOBUFS; + } + /* copy the array of pcr_select */ + memcpy(pcrs.selection[i].pcr_select, response + pcr_select_offset, + pcrs.selection[i].size_of_select); + } + + for (i = 0; i < pcrs.count; i++) { + u32 hash_mask = tpm2_algorithm_to_mask(pcrs.selection[i].hash); + + if (hash_mask) { + *supported_pcr |= hash_mask; + if (tpm2_is_active_pcr(&pcrs.selection[i])) + *active_pcr |= hash_mask; + } else { + printf("%s: unknown algorithm %x\n", __func__, + pcrs.selection[i].hash); + } + } + + *pcr_banks = pcrs.count; + + return 0; +} + u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz) { u8 command_v2[COMMAND_BUFFER_SIZE] = { diff --git a/net/bootp.c b/net/bootp.c index 7b0f45e18a9..68002909634 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -26,6 +26,7 @@ #ifdef CONFIG_BOOTP_RANDOM_DELAY #include "net_rand.h" #endif +#include <malloc.h> #define BOOTP_VENDOR_MAGIC 0x63825363 /* RFC1048 Magic Cookie */ @@ -601,6 +602,10 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip, *e++ = 42; *cnt += 1; #endif + if (IS_ENABLED(CONFIG_BOOTP_PXE_DHCP_OPTION)) { + *e++ = 209; /* PXELINUX Config File */ + *cnt += 1; + } /* no options, so back up to avoid sending an empty request list */ if (*cnt == 0) e -= 2; @@ -909,6 +914,22 @@ static void dhcp_process_options(uchar *popt, uchar *end) net_boot_file_name[size] = 0; } break; + case 209: /* PXELINUX Config File */ + if (IS_ENABLED(CONFIG_BOOTP_PXE_DHCP_OPTION)) { + /* In case it has already been allocated when get DHCP Offer packet, + * free first to avoid memory leak. + */ + if (pxelinux_configfile) + free(pxelinux_configfile); + + pxelinux_configfile = (char *)malloc((oplen + 1) * sizeof(char)); + + if (pxelinux_configfile) + strlcpy(pxelinux_configfile, popt + 2, oplen + 1); + else + printf("Error: Failed to allocate pxelinux_configfile\n"); + } + break; default: #if defined(CONFIG_BOOTP_VENDOREX) if (dhcp_vendorex_proc(popt)) diff --git a/net/dhcpv6.c b/net/dhcpv6.c index 73a1067877c..4aea779f6f2 100644 --- a/net/dhcpv6.c +++ b/net/dhcpv6.c @@ -304,7 +304,7 @@ static void dhcp6_parse_ia_options(struct dhcp6_option_hdr *ia_ptr, uchar *ia_op static void dhcp6_parse_options(uchar *rx_pkt, unsigned int len) { uchar *option_ptr; - int sol_max_rt_sec, option_len; + int sol_max_rt_sec, option_len, param_len_1; char *s, *e; struct dhcp6_option_hdr *option_hdr; @@ -390,14 +390,23 @@ static void dhcp6_parse_options(uchar *rx_pkt, unsigned int len) case DHCP6_OPTION_OPT_BOOTFILE_PARAM: if (IS_ENABLED(CONFIG_DHCP6_PXE_DHCP_OPTION)) { debug("DHCP6_OPTION_OPT_BOOTFILE_PARAM FOUND\n"); + /* if CONFIG_DHCP6_PXE_DHCP_OPTION is set the PXE config file path + * is contained in the first OPT_BOOTFILE_PARAM argument + */ + param_len_1 = ntohs(*((u16 *)option_ptr)); + option_ptr += sizeof(u16); + if (param_len_1 + sizeof(u16) > option_len) { + debug("Invalid BOOTFILE_PARAM param_len_1. Skipping\n"); + break; + } if (pxelinux_configfile) free(pxelinux_configfile); - pxelinux_configfile = (char *)malloc((option_len + 1) * + pxelinux_configfile = (char *)malloc((param_len_1 + 1) * sizeof(char)); if (pxelinux_configfile) - strlcpy(pxelinux_configfile, option_ptr, option_len + 1); + strlcpy(pxelinux_configfile, option_ptr, param_len_1 + 1); else printf("Error: Failed to allocate pxelinux_configfile\n"); diff --git a/net/eth-uclass.c b/net/eth-uclass.c index 4311f3fe6e8..3d0ec91dfa4 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -562,10 +562,14 @@ static int eth_post_probe(struct udevice *dev) /* Check if the device has a valid MAC address in device tree */ if (!eth_dev_get_mac_address(dev, pdata->enetaddr) || !is_valid_ethaddr(pdata->enetaddr)) { - source = "ROM"; /* Check if the device has a MAC address in ROM */ - if (eth_get_ops(dev)->read_rom_hwaddr) - eth_get_ops(dev)->read_rom_hwaddr(dev); + if (eth_get_ops(dev)->read_rom_hwaddr) { + int ret; + + ret = eth_get_ops(dev)->read_rom_hwaddr(dev); + if (!ret) + source = "ROM"; + } } eth_env_get_enetaddr_by_index("eth", dev_seq(dev), env_enetaddr); @@ -594,7 +598,7 @@ static int eth_post_probe(struct udevice *dev) eth_env_set_enetaddr_by_index("eth", dev_seq(dev), pdata->enetaddr); #else - printf("\nError: %s address not set.\n", + printf("\nError: %s No valid MAC address found.\n", dev->name); return -EINVAL; #endif diff --git a/net/net.c b/net/net.c index 8357f084101..0fb2d250773 100644 --- a/net/net.c +++ b/net/net.c @@ -1201,6 +1201,9 @@ void net_process_received_packet(uchar *in_packet, int len) ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid; debug_cond(DEBUG_NET_PKT, "packet received\n"); + if (DEBUG_NET_PKT_TRACE) + print_hex_dump_bytes("rx: ", DUMP_PREFIX_OFFSET, in_packet, + len); #if defined(CONFIG_CMD_PCAP) pcap_post(in_packet, len, false); diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 32f4384657b..e450ffd5d5e 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -7,7 +7,7 @@ # Daniel Schwierzeck, daniel.schwierzeck@googlemail.com. # # (C) Copyright 2011 -# Texas Instruments Incorporated - http://www.ti.com/ +# Texas Instruments Incorporated - https://www.ti.com/ # Aneesh V <aneesh@ti.com> # Based on top-level Makefile. # diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 488d73a0ed7..b8eb57f38c7 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -2636,12 +2636,18 @@ sub u_boot_line { "All CONFIG symbols are managed by Kconfig\n" . $herecurr); } - # Don't put common.h and dm.h in header files - if ($realfile =~ /\.h$/ && $rawline =~ /^\+#include\s*<(common|dm)\.h>*/) { + # Don't put dm.h in header files + if ($realfile =~ /\.h$/ && $rawline =~ /^\+#include\s*<dm\.h>*/) { ERROR("BARRED_INCLUDE_IN_HDR", "Avoid including common.h and dm.h in header files\n" . $herecurr); } + # Don't add common.h to files + if ($rawline =~ /^\+#include\s*<common\.h>*/) { + ERROR("BARRED_INCLUDE_COMMON_H", + "Do not add common.h to files\n" . $herecurr); + } + # Do not disable fdt / initrd relocation if ($rawline =~ /^\+.*(fdt|initrd)_high=0xffffffff/) { ERROR("DISABLE_FDT_OR_INITRD_RELOC", diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl index 81116e215e5..6c58578e988 100755 --- a/scripts/get_maintainer.pl +++ b/scripts/get_maintainer.pl @@ -981,6 +981,7 @@ sub get_maintainers { } foreach my $email (@file_emails) { + $email = mailmap_email($email); my ($name, $address) = parse_email($email); my $tmp_email = format_email($name, $address, $email_usename); @@ -1718,7 +1719,7 @@ sub vcs_exists { %VCS_cmds = %VCS_cmds_hg; return 2 if eval $VCS_cmds{"available"}; %VCS_cmds = (); - if (!$printed_novcs) { + if (!$printed_novcs && $email_git) { warn("$P: No supported VCS found. Add --nogit to options?\n"); warn("Using a git repository produces better results.\n"); warn("Try Linus Torvalds' latest git repository using:\n"); diff --git a/test/boot/Makefile b/test/boot/Makefile index 52947580ae6..068522cb9e0 100644 --- a/test/boot/Makefile +++ b/test/boot/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_BOOTSTD) += bootdev.o bootstd_common.o bootflow.o bootmeth.o obj-$(CONFIG_FIT) += image.o +obj-$(CONFIG_MEASURED_BOOT) += measurement.o obj-$(CONFIG_EXPO) += expo.o obj-$(CONFIG_CEDIT) += cedit.o diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index f5b2059140a..f640db8a241 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -973,6 +973,26 @@ static int bootflow_cmdline(struct unit_test_state *uts) } BOOTSTD_TEST(bootflow_cmdline, 0); +/* test a few special changes to a long command line */ +static int bootflow_cmdline_special(struct unit_test_state *uts) +{ + char buf[500]; + int pos; + + /* + * check handling of an argument which has an embedded '=', as well as + * handling of a argument which partially matches ("ro" and "root") + */ + ut_asserteq(32, cmdline_set_arg( + buf, sizeof(buf), + "loglevel=7 root=PARTUUID=d68352e3 rootwait ro noinitrd", + "root", NULL, &pos)); + ut_asserteq_str("loglevel=7 rootwait ro noinitrd", buf); + + return 0; +} +BOOTSTD_TEST(bootflow_cmdline_special, 0); + /* Test ChromiumOS bootmeth */ static int bootflow_cros(struct unit_test_state *uts) { diff --git a/test/boot/measurement.c b/test/boot/measurement.c new file mode 100644 index 00000000000..9db2ed324c2 --- /dev/null +++ b/test/boot/measurement.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for measured boot functions + * + * Copyright 2023 IBM Corp. + * Written by Eddie James <eajames@linux.ibm.com> + */ + +#include <common.h> +#include <bootm.h> +#include <malloc.h> +#include <test/suites.h> +#include <test/test.h> +#include <test/ut.h> +#include <asm/io.h> + +#define MEASUREMENT_TEST(_name, _flags) \ + UNIT_TEST(_name, _flags, measurement_test) + +static int measure(struct unit_test_state *uts) +{ + struct bootm_headers images; + const size_t size = 1024; + u8 *kernel; + u8 *initrd; + size_t i; + + kernel = malloc(size); + initrd = malloc(size); + + images.os.image_start = map_to_sysmem(kernel); + images.os.image_len = size; + + images.rd_start = map_to_sysmem(initrd); + images.rd_end = images.rd_start + size; + + images.ft_addr = malloc(size); + images.ft_len = size; + + env_set("bootargs", "measurement testing"); + + for (i = 0; i < size; ++i) { + kernel[i] = 0xf0 | (i & 0xf); + initrd[i] = (i & 0xf0) | 0xf; + images.ft_addr[i] = i & 0xff; + } + + ut_assertok(bootm_measure(&images)); + + free(images.ft_addr); + free(initrd); + free(kernel); + + return 0; +} +MEASUREMENT_TEST(measure, 0); + +int do_ut_measurement(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct unit_test *tests = UNIT_TEST_SUITE_START(measurement_test); + const int n_ents = UNIT_TEST_SUITE_COUNT(measurement_test); + + return cmd_ut_category("measurement", "measurement_test_", tests, + n_ents, argc, argv); +} diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 8d70ac510a5..e296ba1192b 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CMD_PINMUX) += pinmux.o obj-$(CONFIG_CMD_PWM) += pwm.o obj-$(CONFIG_CMD_SEAMA) += seama.o ifdef CONFIG_SANDBOX +obj-$(CONFIG_CMD_MBR) += mbr.o obj-$(CONFIG_CMD_READ) += rw.o obj-$(CONFIG_CMD_SETEXPR) += setexpr.o obj-$(CONFIG_ARM_FFA_TRANSPORT) += armffa.o diff --git a/test/cmd/mbr.c b/test/cmd/mbr.c new file mode 100644 index 00000000000..46b78e706ca --- /dev/null +++ b/test/cmd/mbr.c @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Tests for mbr command + * + * Copyright 2023 Matrox Video + * Written by Alex Gendin <agendin@matrox.com> + */ + +#include <dm.h> +#include <console.h> +#include <dm/test.h> +#include <mapmem.h> +#include <part.h> +#include <asm/global_data.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <test/suites.h> +#include <test/ut.h> + +DECLARE_GLOBAL_DATA_PTR; +/* + * Requirements for running test manually: + * mmc6.img - File size needs to be at least 12 MiB + * + * Command to create mmc6.img: + * $ dd if=/dev/zero of=mmc6.img bs=12M count=1 + * + * To run this test manually, place mmc6.img into the same directory as u-boot, + * then run: + * $ ./u-boot -Tc 'ut mbr' + * + * To run this test as part of U-Boot test: + * $ ./test/py/test.py --bd sandbox --build -k ut_dm -v + * Note: mmc6.img will be created by the test suit. + */ + +static char * mbr_parts_header = "setenv mbr_parts '"; +static char * mbr_parts_p1 = "uuid_disk=0x12345678;name=p1,start=8M,bootable,size=1M,id=0x0e"; +static char * mbr_parts_p2 = ";name=p2,size=1M,id=0x0e"; +static char * mbr_parts_p3 = ";name=p3,size=1M,id=0x0e"; +static char * mbr_parts_p4 = ";name=p4,size=1M,id=0x0e"; +static char * mbr_parts_p5 = ";name=[ext],size=2M,id=0x05;name=p5,size=1M,id=0x0e"; +static char * mbr_parts_tail = "'"; + +/* + * One MBR partition +000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| +000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 00 |...%$..@........| +000001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.| +*/ +static unsigned mbr_cmp_start = 0x1B8; +static unsigned mbr_cmp_size = 0x48; +static unsigned char mbr_parts_ref_p1[] = { + 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05, +0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa +}; + +/* + * Two MBR partitions +000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| +000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| +000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 00 |%..F...H........| +000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.| +*/ +static unsigned char mbr_parts_ref_p2[] = { + 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05, +0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x25, +0x25, 0x01, 0x0e, 0x46, 0x05, 0x01, 0x00, 0x48, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa +}; + +/* + * Three MBR partitions +000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| +000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| +000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F| +000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 00 |...f%..P........| +000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.| +*/ +static unsigned char mbr_parts_ref_p3[] = { + 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05, +0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x25, +0x25, 0x01, 0x0e, 0x46, 0x05, 0x01, 0x00, 0x48, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x46, +0x06, 0x01, 0x0e, 0x66, 0x25, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa +}; + +/* + * Four MBR partitions +000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| +000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| +000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F| +000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f| +000001f0 26 01 0e 87 06 01 00 58 00 00 00 08 00 00 55 aa |&......X......U.| +*/ +static unsigned char mbr_parts_ref_p4[] = { + 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05, +0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x25, +0x25, 0x01, 0x0e, 0x46, 0x05, 0x01, 0x00, 0x48, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x46, +0x06, 0x01, 0x0e, 0x66, 0x25, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x66, +0x26, 0x01, 0x0e, 0x87, 0x06, 0x01, 0x00, 0x58, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x55, 0xaa +}; + +/* + * Five MBR partitions +000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| +000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| +000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F| +000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f| +000001f0 26 01 05 a7 26 01 00 58 00 00 00 10 00 00 55 aa |&...&..X......U.| +*/ +static unsigned char mbr_parts_ref_p5[] = { + 0x78, 0x56, 0x34, 0x12, 0x00, 0x00, 0x80, 0x05, +0x05, 0x01, 0x0e, 0x25, 0x24, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x25, +0x25, 0x01, 0x0e, 0x46, 0x05, 0x01, 0x00, 0x48, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x46, +0x06, 0x01, 0x0e, 0x66, 0x25, 0x01, 0x00, 0x50, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x66, +0x26, 0x01, 0x05, 0xa7, 0x26, 0x01, 0x00, 0x58, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x55, 0xaa +}; +static unsigned ebr_cmp_start = 0x1B8; +static unsigned ebr_cmp_size = 0x48; +/* + * EBR +00b001b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 87 |................| +00b001c0 07 01 0e a7 26 01 00 08 00 00 00 08 00 00 00 00 |....&...........| +00b001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00b001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| +00b001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.| +*/ +static unsigned char ebr_parts_ref_p5[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87, +0x07, 0x01, 0x0e, 0xa7, 0x26, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xaa +}; + +/* Fill write buffers with pseudo-random data */ +static void init_write_buffers(char *mbr_wb, size_t mbr_wb_size, + char *ebr_wb, size_t ebr_wb_size, unsigned seed) +{ + while (mbr_wb_size--) { + *mbr_wb++ = seed; + seed *= 43; + seed += 17 + mbr_wb_size/4; + } + while (ebr_wb_size--) { + *ebr_wb++ = seed; + seed *= 43; + seed += 17 + ebr_wb_size/4; + } +} + +/* Build string with MBR partition(s) layout */ +static unsigned build_mbr_parts(char *buf, size_t buf_size, unsigned num_parts) +{ + size_t bytes_remaining, cur_str_size; + char * cur_buf; + + if (!num_parts || num_parts > 5 || !buf) + return 1; + + cur_buf = buf; + *cur_buf = '\0'; + bytes_remaining = buf_size; + + cur_str_size = sizeof(mbr_parts_header); + if (cur_str_size + 1 > bytes_remaining) + return 1; + strcat(cur_buf, mbr_parts_header); + bytes_remaining -= cur_str_size; + + if (num_parts >= 1) { + cur_str_size = sizeof(mbr_parts_p1); + if (cur_str_size + 1 > bytes_remaining) + return 1; + strcat(cur_buf, mbr_parts_p1); + bytes_remaining -= cur_str_size; + + if (num_parts >= 2) { + cur_str_size = sizeof(mbr_parts_p2); + if (cur_str_size + 1 > bytes_remaining) + return 1; + strcat(cur_buf, mbr_parts_p2); + bytes_remaining -= cur_str_size; + + if (num_parts >= 3) { + cur_str_size = sizeof(mbr_parts_p3); + if (cur_str_size + 1 > bytes_remaining) + return 1; + strcat(cur_buf, mbr_parts_p3); + bytes_remaining -= cur_str_size; + + if (num_parts == 4) { + cur_str_size = sizeof(mbr_parts_p4); + if (cur_str_size + 1 > bytes_remaining) + return 1; + strcat(cur_buf, mbr_parts_p4); + bytes_remaining -= cur_str_size; + + } + else if (num_parts == 5) { + cur_str_size = sizeof(mbr_parts_p5); + if (cur_str_size + 1 > bytes_remaining) + return 1; + strcat(cur_buf, mbr_parts_p5); + bytes_remaining -= cur_str_size; + + } + } + } + } + + cur_str_size = sizeof(mbr_parts_tail); + if (cur_str_size + 1 > bytes_remaining) + return 1; + strcat(cur_buf, mbr_parts_tail); + + return 0; +} + +static int mbr_test_run(struct unit_test_state *uts) +{ + struct blk_desc *mmc_dev_desc; + unsigned char mbr_wbuf[512], ebr_wbuf[512], rbuf[512]; + char mbr_parts_buf[256]; + ulong mbr_wa, ebr_wa, ra, ebr_blk, mbr_parts_max; + struct udevice *dev; + ofnode root, node; + + /* Enable the mmc6 node for this test */ + root = oftree_root(oftree_default()); + node = ofnode_find_subnode(root, "mmc6"); + ut_assert(ofnode_valid(node)); + ut_assertok(lists_bind_fdt(gd->dm_root, node, &dev, NULL, false)); + + mbr_parts_max = sizeof('\0') + 2 + + strlen(mbr_parts_header) + + strlen(mbr_parts_p1) + + strlen(mbr_parts_p2) + + strlen(mbr_parts_p3) + + max(strlen(mbr_parts_p4), strlen(mbr_parts_p5)) + + strlen(mbr_parts_tail); + ut_assertf(sizeof(mbr_parts_buf) >= mbr_parts_max, "Buffer avail: %ld; buffer req: %ld\n", + sizeof(mbr_parts_buf), mbr_parts_max); + + mbr_wa = map_to_sysmem(mbr_wbuf); + ebr_wa = map_to_sysmem(ebr_wbuf); + ra = map_to_sysmem(rbuf); + ebr_blk = (ulong)0xB00000 / 0x200; + + /* Make sure mmc6 exists */ + ut_asserteq(6, blk_get_device_by_str("mmc", "6", &mmc_dev_desc)); + ut_assertok(console_record_reset_enable()); + ut_assertok(run_commandf("mmc dev 6")); + ut_assert_nextline("switch to partitions #0, OK"); + ut_assert_nextline("mmc6 is current device"); + ut_assertok(ut_check_console_end(uts)); + + /* Make sure mmc6 is 12+ MiB in size */ + ut_assertok(run_commandf("mmc read 0x%lx 0x%lx 1", ra, (ulong)0xBFFE00 / 0x200)); + + /* Test one MBR partition */ + init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__); + ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 1)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + ut_assertok(memcmp(mbr_wbuf, rbuf, 512)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); + ut_assertok(console_record_reset_enable()); + ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf); + ut_assertok(run_commandf("mbr write mmc 6")); + ut_assert_nextline("MBR: write success!"); + ut_assertok(run_commandf("mbr verify mmc 6")); + ut_assert_nextline("MBR: verify success!"); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); + ut_assertok(ut_check_console_end(uts)); + /* + 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| + 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 00 |...%$..@........| + 000001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| + 000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| + 000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.| + */ + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + for (unsigned i = 0; i < mbr_cmp_size; i++) { + ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p1[i], + "1P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n", + mbr_cmp_start + i, mbr_parts_ref_p1[i], rbuf[mbr_cmp_start + i]); + } + + /* Test two MBR partitions */ + init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__); + ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 2)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + ut_assertok(memcmp(mbr_wbuf, rbuf, 512)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); + ut_assertok(console_record_reset_enable()); + ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf); + ut_assertok(run_commandf("mbr write mmc 6")); + ut_assert_nextline("MBR: write success!"); + ut_assertok(run_commandf("mbr verify mmc 6")); + ut_assert_nextline("MBR: verify success!"); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); + ut_assertok(ut_check_console_end(uts)); + /* + 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| + 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| + 000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 00 |%..F...H........| + 000001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| + 000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.| + */ + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + for (unsigned i = 0; i < mbr_cmp_size; i++) { + ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p2[i], + "2P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n", + mbr_cmp_start + i, mbr_parts_ref_p2[i], rbuf[mbr_cmp_start + i]); + } + + /* Test three MBR partitions */ + init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__); + ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 3)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + ut_assertok(memcmp(mbr_wbuf, rbuf, 512)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); + ut_assertok(console_record_reset_enable()); + ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf); + ut_assertok(run_commandf("mbr write mmc 6")); + ut_assert_nextline("MBR: write success!"); + ut_assertok(run_commandf("mbr verify mmc 6")); + ut_assert_nextline("MBR: verify success!"); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); + ut_assertok(ut_check_console_end(uts)); + /* + 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| + 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| + 000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F| + 000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 00 |...f%..P........| + 000001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.| + */ + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + for (unsigned i = 0; i < mbr_cmp_size; i++) { + ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p3[i], + "3P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n", + mbr_cmp_start + i, mbr_parts_ref_p3[i], rbuf[mbr_cmp_start + i]); + } + + /* Test four MBR partitions */ + init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__); + ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 4)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + ut_assertok(memcmp(mbr_wbuf, rbuf, 512)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); + ut_assertok(console_record_reset_enable()); + ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf); + ut_assertok(run_commandf("mbr write mmc 6")); + ut_assert_nextline("MBR: write success!"); + ut_assertok(run_commandf("mbr verify mmc 6")); + ut_assert_nextline("MBR: verify success!"); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); + ut_assertok(ut_check_console_end(uts)); + /* + 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| + 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| + 000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F| + 000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f| + 000001f0 26 01 0e 87 06 01 00 58 00 00 00 08 00 00 55 aa |&......X......U.| + */ + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + for (unsigned i = 0; i < mbr_cmp_size; i++) { + ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p4[i], + "4P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n", + mbr_cmp_start + i, mbr_parts_ref_p4[i], rbuf[mbr_cmp_start + i]); + } + + /* Test five MBR partitions */ + init_write_buffers(mbr_wbuf, sizeof(mbr_wbuf), ebr_wbuf, sizeof(ebr_wbuf), __LINE__); + ut_assertok(build_mbr_parts(mbr_parts_buf, sizeof(mbr_parts_buf), 5)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0 1", mbr_wa)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + ut_assertok(memcmp(mbr_wbuf, rbuf, 512)); + ut_assertok(run_commandf("write mmc 6:0 0x%lx 0x%lx 1", ebr_wa, ebr_blk)); + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + ut_assertok(memcmp(ebr_wbuf, rbuf, 512)); + ut_assertok(console_record_reset_enable()); + ut_assertf(0 == run_commandf(mbr_parts_buf), "Invalid partitions string: %s\n", mbr_parts_buf); + ut_assertf(0 == run_commandf("mbr write mmc 6"), "Invalid partitions string: %s\n", mbr_parts_buf); + ut_assert_nextline("MBR: write success!"); + ut_assertok(run_commandf("mbr verify mmc 6")); + ut_assert_nextline("MBR: verify success!"); + ut_assertok(ut_check_console_end(uts)); + /* + 000001b0 00 00 00 00 00 00 00 00 78 56 34 12 00 00 80 05 |........xV4.....| + 000001c0 05 01 0e 25 24 01 00 40 00 00 00 08 00 00 00 25 |...%$..@.......%| + 000001d0 25 01 0e 46 05 01 00 48 00 00 00 08 00 00 00 46 |%..F...H.......F| + 000001e0 06 01 0e 66 25 01 00 50 00 00 00 08 00 00 00 66 |...f%..P.......f| + 000001f0 26 01 05 a7 26 01 00 58 00 00 00 10 00 00 55 aa |&...&..X......U.| + */ + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0 1", ra)); + for (unsigned i = 0; i < mbr_cmp_size; i++) { + ut_assertf(rbuf[mbr_cmp_start + i] == mbr_parts_ref_p5[i], + "5P MBR+0x%04X: expected 0x%02X, actual: 0x%02X\n", + mbr_cmp_start + i, mbr_parts_ref_p5[i], rbuf[mbr_cmp_start + i]); + } + /* + 00b001b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 87 |................| + 00b001c0 07 01 0e a7 26 01 00 08 00 00 00 08 00 00 00 00 |....&...........| + 00b001d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| + 00b001e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................| + 00b001f0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 aa |..............U.| + */ + memset(rbuf, 0, sizeof(rbuf)); + ut_assertok(run_commandf("read mmc 6:0 0x%lx 0x%lx 1", ra, ebr_blk)); + for (unsigned i = 0; i < ebr_cmp_size; i++) { + ut_assertf(rbuf[ebr_cmp_start + i] == ebr_parts_ref_p5[i], + "5P EBR+0x%04X: expected 0x%02X, actual: 0x%02X\n", + ebr_cmp_start + i, ebr_parts_ref_p5[i], rbuf[ebr_cmp_start + i]); + } + + return 0; +} + +/* Declare mbr test */ +UNIT_TEST(mbr_test_run, UT_TESTF_CONSOLE_REC, mbr_test); + +int do_ut_mbr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct unit_test *tests = UNIT_TEST_SUITE_START(mbr_test); + const int n_ents = UNIT_TEST_SUITE_COUNT(mbr_test); + + return cmd_ut_category("mbr", "mbr_test_", tests, n_ents, argc, argv); +} + +static int dm_test_cmd_mbr(struct unit_test_state *uts) +{ + return mbr_test_run(uts); +} + +DM_TEST(dm_test_cmd_mbr, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC); diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 477d4759521..2d5b80f992e 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -87,6 +87,10 @@ static struct cmd_tbl cmd_ut_sub[] = { #ifdef CONFIG_UT_LOG U_BOOT_CMD_MKENT(log, CONFIG_SYS_MAXARGS, 1, do_ut_log, "", ""), #endif +#if defined(CONFIG_SANDBOX) && defined(CONFIG_CMD_MBR) && defined(CONFIG_CMD_MMC) \ + && defined(CONFIG_MMC_SANDBOX) && defined(CONFIG_MMC_WRITE) + U_BOOT_CMD_MKENT(mbr, CONFIG_SYS_MAXARGS, 1, do_ut_mbr, "", ""), +#endif U_BOOT_CMD_MKENT(mem, CONFIG_SYS_MAXARGS, 1, do_ut_mem, "", ""), #if defined(CONFIG_SANDBOX) && defined(CONFIG_CMD_SETEXPR) U_BOOT_CMD_MKENT(setexpr, CONFIG_SYS_MAXARGS, 1, do_ut_setexpr, "", @@ -99,6 +103,10 @@ static struct cmd_tbl cmd_ut_sub[] = { #if CONFIG_IS_ENABLED(UT_UNICODE) && !defined(API_BUILD) U_BOOT_CMD_MKENT(unicode, CONFIG_SYS_MAXARGS, 1, do_ut_unicode, "", ""), #endif +#ifdef CONFIG_MEASURED_BOOT + U_BOOT_CMD_MKENT(measurement, CONFIG_SYS_MAXARGS, 1, do_ut_measurement, + "", ""), +#endif #ifdef CONFIG_SANDBOX U_BOOT_CMD_MKENT(compression, CONFIG_SYS_MAXARGS, 1, do_ut_compression, "", ""), diff --git a/test/common/cread.c b/test/common/cread.c index 2fdd29a265f..4edc7739604 100644 --- a/test/common/cread.c +++ b/test/common/cread.c @@ -43,6 +43,12 @@ static int cli_ch_test(struct unit_test_state *uts) ut_asserteq('a', cli_ch_process(cch, 'a')); ut_asserteq(0, cli_ch_process(cch, 0)); + /* unexpected 'Esc' */ + ut_asserteq('a', cli_ch_process(cch, 'a')); + ut_asserteq(0, cli_ch_process(cch, '\e')); + ut_asserteq('b', cli_ch_process(cch, 'b')); + ut_asserteq(0, cli_ch_process(cch, 0)); + return 0; } COMMON_TEST(cli_ch_test, 0); @@ -80,6 +86,12 @@ static int cread_test(struct unit_test_state *uts) ut_asserteq(7, cli_readline_into_buffer("-> ", buf, 1)); ut_asserteq_str("abc\e[Xx", buf); + /* unexpected 'Esc' */ + *buf = '\0'; + ut_asserteq(7, console_in_puts("abc\eXx\n")); + ut_asserteq(5, cli_readline_into_buffer("-> ", buf, 1)); + ut_asserteq_str("abcXx", buf); + /* check timeout, should be between 1000 and 1050ms */ start = get_timer(0); *buf = '\0'; diff --git a/test/dm/Makefile b/test/dm/Makefile index 02c651a7862..cb82d839f8a 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_REMOTEPROC) += remoteproc.o obj-$(CONFIG_DM_RESET) += reset.o obj-$(CONFIG_SYSRESET) += sysreset.o obj-$(CONFIG_DM_REGULATOR) += regulator.o +obj-$(CONFIG_CMD_RKMTD) += rkmtd.o obj-$(CONFIG_DM_RNG) += rng.o obj-$(CONFIG_DM_RTC) += rtc.o obj-$(CONFIG_SCMI_FIRMWARE) += scmi.o diff --git a/test/dm/mux-emul.c b/test/dm/mux-emul.c index 58233edc9b2..c6aeeb7e1f1 100644 --- a/test/dm/mux-emul.c +++ b/test/dm/mux-emul.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ * Pratyush Yadav <p.yadav@ti.com> */ #include <common.h> diff --git a/test/dm/mux-mmio.c b/test/dm/mux-mmio.c index fd353d8b155..27c881dabde 100644 --- a/test/dm/mux-mmio.c +++ b/test/dm/mux-mmio.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017-2018 Texas Instruments Incorporated - https://www.ti.com/ * Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/test/dm/nop.c b/test/dm/nop.c index 75b9e7b6cc0..f7d9a0f3df3 100644 --- a/test/dm/nop.c +++ b/test/dm/nop.c @@ -2,7 +2,7 @@ /* * Test for the NOP uclass * - * (C) Copyright 2019 - Texas Instruments Incorporated - http://www.ti.com/ + * (C) Copyright 2019 - Texas Instruments Incorporated - https://www.ti.com/ * Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/test/dm/phy.c b/test/dm/phy.c index 4f91abca3a0..0cf3689fdec 100644 --- a/test/dm/phy.c +++ b/test/dm/phy.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ * Written by Jean-Jacques Hiblot <jjhiblot@ti.com> */ diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c index 7a8ff47fa14..f6f9e509e27 100644 --- a/test/dm/remoteproc.c +++ b/test/dm/remoteproc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2015 - * Texas Instruments Incorporated - http://www.ti.com/ + * Texas Instruments Incorporated - https://www.ti.com/ */ #include <common.h> #include <dm.h> diff --git a/test/dm/rkmtd.c b/test/dm/rkmtd.c new file mode 100644 index 00000000000..3c3e8efa92f --- /dev/null +++ b/test/dm/rkmtd.c @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Test derived from: + * /test/dm/host.c + * Copyright 2022 Google LLC + * Written by Simon Glass <sjg@chromium.org> + * + * Copyright (C) 2023 Johan Jonker <jbx6244@gmail.com> + */ + +#include <common.h> +#include <blk.h> +#include <dm.h> +#include <fs.h> +#include <rkmtd.h> +#include <asm/test.h> +#include <dm/device-internal.h> +#include <dm/test.h> +#include <test/test.h> +#include <test/ut.h> + +#define RW_BUF_SIZE 12 * 512 + +/* Basic test of the RKMTD interface */ +static int dm_test_rkmtd(struct unit_test_state *uts) +{ + struct udevice *dev, *part, *chk, *blk; + char write[RW_BUF_SIZE], read[RW_BUF_SIZE]; + static const char label[] = "test"; + struct rkmtd_dev *plat; + struct blk_desc *desc; + struct sector0 *sec0; + int i; + + ut_asserteq(-ENODEV, uclass_first_device_err(UCLASS_RKMTD, &dev)); + ut_asserteq(-ENODEV, uclass_first_device_err(UCLASS_PARTITION, &part)); + + ut_assertok(rkmtd_create_device(label, &dev)); + + /* Check that the plat data has been allocated */ + plat = dev_get_plat(dev); + ut_asserteq_str("test", plat->label); + ut_assert(label != plat->label); + + /* Attach RKMTD driver */ + ut_assertok(rkmtd_attach(dev)); + ut_assertok(uclass_first_device_err(UCLASS_RKMTD, &chk)); + ut_asserteq_ptr(chk, dev); + + /* Get RKMTD block device */ + ut_assertok(blk_get_from_parent(dev, &blk)); + ut_assertok(device_probe(blk)); + + /* There should be a GPT partition table in this device */ + ut_asserteq(0, uclass_first_device_err(UCLASS_PARTITION, &part)); + + /* Write a boot block and verify that we get the same data back */ + desc = dev_get_uclass_plat(blk); + ut_asserteq(true, desc->removable); + ut_asserteq(LBA, desc->lba); + + memset(write, '\0', BLK_SIZE); + + for (i = BLK_SIZE; i < sizeof(write); i++) + write[i] = i; + + sec0 = (struct sector0 *)write; + sec0->magic = 0x0FF0AA55; + sec0->rc4_flag = 0; + sec0->boot_code1_offset = 4; + sec0->boot_code2_offset = 4; + sec0->flash_data_size = 4; + sec0->flash_boot_size = 8; + + rkmtd_rc4(write, 512); + ut_asserteq(RK_TAG, sec0->magic); + + ut_asserteq(12, blk_dwrite(desc, 64, 12, write)); + ut_asserteq(12, blk_dread(desc, 64, 12, read)); + ut_asserteq_mem(write, read, RW_BUF_SIZE); + + ut_assertok(rkmtd_detach(dev)); + + ut_asserteq(-ENODEV, blk_get_from_parent(dev, &blk)); + ut_assertok(device_unbind(dev)); + + return 0; +} +DM_TEST(dm_test_rkmtd, UT_TESTF_SCAN_FDT); + +/* Reusing the same label should work */ +static int dm_test_rkmtd_dup(struct unit_test_state *uts) +{ + static const char label[] = "test"; + struct udevice *dev, *chk; + + /* Create a RKMTD device with label "test" */ + ut_asserteq(0, uclass_id_count(UCLASS_RKMTD)); + ut_assertok(rkmtd_create_device(label, &dev)); + ut_assertok(rkmtd_attach(dev)); + ut_assertok(uclass_first_device_err(UCLASS_RKMTD, &chk)); + ut_asserteq_ptr(chk, dev); + ut_asserteq(1, uclass_id_count(UCLASS_RKMTD)); + + /* Create another device with the same label (should remove old one) */ + ut_assertok(rkmtd_create_device(label, &dev)); + ut_assertok(rkmtd_attach(dev)); + ut_assertok(uclass_first_device_err(UCLASS_RKMTD, &chk)); + ut_asserteq_ptr(chk, dev); + + /* Make sure there is still only one device */ + ut_asserteq(1, uclass_id_count(UCLASS_RKMTD)); + + return 0; +} +DM_TEST(dm_test_rkmtd_dup, UT_TESTF_SCAN_FDT); + +/* Basic test of the 'rkmtd' command */ +static int dm_test_rkmtd_cmd(struct unit_test_state *uts) +{ + struct udevice *dev, *blk; + struct blk_desc *desc; + + /* First check 'rkmtd info' with binding */ + ut_assertok(run_command("rkmtd info", 0)); + ut_assert_nextline("dev blocks label "); + ut_assert_console_end(); + + /* Bind device 1 */ + ut_assertok(run_commandf("rkmtd bind test1")); + ut_assertok(uclass_first_device_err(UCLASS_RKMTD, &dev)); + ut_assertok(blk_get_from_parent(dev, &blk)); + desc = dev_get_uclass_plat(blk); + + ut_assertok(run_command("rkmtd info", 0)); + ut_assert_nextline("dev blocks label "); + ut_assert_nextline(" 0 609 test1 "); + ut_assert_console_end(); + + /* Bind device 2 */ + ut_assertok(run_commandf("rkmtd bind test2")); + ut_assertok(uclass_next_device_err(&dev)); + ut_assertok(blk_get_from_parent(dev, &blk)); + desc = dev_get_uclass_plat(blk); + + ut_assertok(run_command("rkmtd info", 0)); + ut_assert_nextline("dev blocks label "); + ut_assert_nextline(" 0 609 test1 "); + ut_assert_nextline(" 1 609 test2 "); + ut_assert_console_end(); + + ut_asserteq(1, run_command("rkmtd info test", 0)); + ut_assert_nextline("No such device 'test'"); + ut_assert_console_end(); + + ut_assertok(run_command("rkmtd info test2", 0)); + ut_assert_nextline("dev blocks label "); + ut_assert_nextline(" 1 609 test2 "); + ut_assert_console_end(); + + /* Check 'rkmtd dev' */ + ut_asserteq(1, run_command("rkmtd dev", 0)); + ut_assert_nextline("No current rkmtd device"); + ut_assert_console_end(); + + ut_asserteq(1, run_command("rkmtd dev missing", 0)); + ut_assert_nextline("No such device 'missing'"); + ut_assert_console_end(); + + ut_assertok(run_command("rkmtd dev test2", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("rkmtd dev", 0)); + ut_assert_nextline("Current rkmtd device: 1: test2"); + ut_assert_console_end(); + + /* Try a numerical label */ + ut_assertok(run_command("rkmtd dev 0", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("rkmtd dev", 0)); + ut_assert_nextline("Current rkmtd device: 0: test1"); + ut_assert_console_end(); + + /* Remove one of the bindings */ + ut_assertok(run_commandf("rkmtd unbind test1")); + + /* There should now be no current device */ + ut_asserteq(1, run_command("rkmtd dev", 0)); + ut_assert_nextline("No current rkmtd device"); + ut_assert_console_end(); + + ut_assertok(run_command("rkmtd info", 0)); + ut_assert_nextline("dev blocks label "); + ut_assert_nextline(" 1 609 test2 "); + ut_assert_console_end(); + + return 0; +} +DM_TEST(dm_test_rkmtd_cmd, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC); diff --git a/test/dm/scmi.c b/test/dm/scmi.c index d4ff60e0006..da45314f2e4 100644 --- a/test/dm/scmi.c +++ b/test/dm/scmi.c @@ -206,6 +206,109 @@ static int dm_test_scmi_base(struct unit_test_state *uts) DM_TEST(dm_test_scmi_base, UT_TESTF_SCAN_FDT); +static int dm_test_scmi_power_domains(struct unit_test_state *uts) +{ + struct sandbox_scmi_agent *agent; + struct sandbox_scmi_devices *scmi_devices; + struct udevice *agent_dev, *pwd, *dev; + u32 version, count, attributes, pstate; + u64 stats_addr; + size_t stats_len; + u8 *name; + int ret; + + /* preparation */ + ut_assertok(load_sandbox_scmi_test_devices(uts, &agent, &dev)); + ut_assertnonnull(agent); + scmi_devices = sandbox_scmi_devices_ctx(dev); + ut_assertnonnull(scmi_devices); + ut_asserteq(2, scmi_devices->pwdom->id); /* in test.dts */ + + ut_assertok(uclass_get_device_by_name(UCLASS_SCMI_AGENT, "scmi", + &agent_dev)); + ut_assertnonnull(agent_dev); + pwd = scmi_get_protocol(agent_dev, SCMI_PROTOCOL_ID_POWER_DOMAIN); + ut_assertnonnull(pwd); + + /* + * SCMI Power domain management protocol interfaces + */ + /* version */ + ret = scmi_generic_protocol_version(pwd, SCMI_PROTOCOL_ID_POWER_DOMAIN, + &version); + ut_assertok(ret); + ut_asserteq(agent->pwdom_version, version); + + /* protocol attributes */ + ret = scmi_pwd_protocol_attrs(pwd, &count, &stats_addr, &stats_len); + ut_assertok(ret); + ut_asserteq(agent->pwdom_count, count); + ut_asserteq(0, stats_len); + + /* protocol message attributes */ + ret = scmi_pwd_protocol_message_attrs(pwd, SCMI_PWD_STATE_SET, + &attributes); + ut_assertok(ret); + ret = scmi_pwd_protocol_message_attrs(pwd, SCMI_PWD_STATE_NOTIFY, + &attributes); + ut_asserteq(-ENOENT, ret); /* the protocol not supported */ + + /* power domain attributes */ + ret = scmi_pwd_attrs(pwd, 0, &attributes, &name); + ut_assertok(ret); + ut_asserteq_str("power-domain--0", name); + free(name); + + ret = scmi_pwd_attrs(pwd, 10, &attributes, &name); + ut_asserteq(-ENOENT, ret); /* domain-10 doesn't exist */ + + /* power domain state set/get */ + ret = scmi_pwd_state_set(pwd, 0, 0, 0); + ut_assertok(ret); + ret = scmi_pwd_state_get(pwd, 0, &pstate); + ut_assertok(ret); + ut_asserteq(0, pstate); /* ON */ + + ret = scmi_pwd_state_set(pwd, 0, 0, SCMI_PWD_PSTATE_TYPE_LOST); + ut_assertok(ret); + ret = scmi_pwd_state_get(pwd, 0, &pstate); + ut_assertok(ret); + ut_asserteq(SCMI_PWD_PSTATE_TYPE_LOST, pstate); /* OFF */ + + ret = scmi_pwd_state_set(pwd, 0, 10, 0); + ut_asserteq(-ENOENT, ret); + + /* power domain name get */ + ret = scmi_pwd_name_get(pwd, 0, &name); + ut_assertok(ret); + ut_asserteq_str("power-domain--0-extended", name); + free(name); + + ret = scmi_pwd_name_get(pwd, 10, &name); + ut_asserteq(-ENOENT, ret); /* domain-10 doesn't exist */ + + /* + * U-Boot driver model interfaces + */ + /* power_domain_on */ + ret = power_domain_on(scmi_devices->pwdom); + ut_assertok(ret); + ret = scmi_pwd_state_get(pwd, scmi_devices->pwdom->id, &pstate); + ut_assertok(ret); + ut_asserteq(0, pstate); /* ON */ + + /* power_domain_off */ + ret = power_domain_off(scmi_devices->pwdom); + ut_assertok(ret); + ret = scmi_pwd_state_get(pwd, scmi_devices->pwdom->id, &pstate); + ut_assertok(ret); + ut_asserteq(SCMI_PWD_PSTATE_TYPE_LOST, pstate); /* OFF */ + + return release_sandbox_scmi_test_devices(uts, dev); +} + +DM_TEST(dm_test_scmi_power_domains, UT_TESTF_SCAN_FDT); + static int dm_test_scmi_clocks(struct unit_test_state *uts) { struct sandbox_scmi_agent *agent; diff --git a/test/dm/serial.c b/test/dm/serial.c index 37d17a65f16..34b783e062e 100644 --- a/test/dm/serial.c +++ b/test/dm/serial.c @@ -29,6 +29,7 @@ static int dm_test_serial(struct unit_test_state *uts) &dev_serial)); ut_assertok(serial_tstc()); + ut_asserteq(115200, fetch_baud_from_dtb()); /* * test with default config which is the only one supported by * sandbox_serial driver diff --git a/test/dm/soc.c b/test/dm/soc.c index 17e1b5ba012..8f6c97fa790 100644 --- a/test/dm/soc.c +++ b/test/dm/soc.c @@ -2,7 +2,7 @@ /* * Test for the SOC uclass * - * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com/ + * (C) Copyright 2020 - Texas Instruments Incorporated - https://www.ti.com/ * Dave Gerlach <d-gerlach@ti.com> */ diff --git a/test/py/tests/test_tpm2.py b/test/py/tests/test_tpm2.py index c2579fa02c5..1d654cd4a23 100644 --- a/test/py/tests/test_tpm2.py +++ b/test/py/tests/test_tpm2.py @@ -61,7 +61,7 @@ def test_tpm2_init(u_boot_console): skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) if skip_test: pytest.skip('skip TPM device test') - u_boot_console.run_command('tpm2 init') + u_boot_console.run_command('tpm2 autostart') output = u_boot_console.run_command('echo $?') assert output.endswith('0') @@ -100,7 +100,7 @@ def test_tpm2_sandbox_self_test_full(u_boot_console): """ if is_sandbox(u_boot_console): u_boot_console.restart_uboot() - u_boot_console.run_command('tpm2 init') + u_boot_console.run_command('tpm2 autostart') output = u_boot_console.run_command('echo $?') assert output.endswith('0') @@ -239,7 +239,7 @@ def test_tpm2_dam_parameters(u_boot_console): def test_tpm2_pcr_read(u_boot_console): """Execute a TPM2_PCR_Read command. - Perform a PCR read of the 0th PCR. Must be zero. + Perform a PCR read of the 10th PCR. Must be zero. """ if is_sandbox(u_boot_console): tpm2_sandbox_init(u_boot_console) @@ -247,7 +247,7 @@ def test_tpm2_pcr_read(u_boot_console): force_init(u_boot_console) ram = u_boot_utils.find_ram_base(u_boot_console) - read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % ram) + read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % ram) output = u_boot_console.run_command('echo $?') assert output.endswith('0') @@ -257,7 +257,7 @@ def test_tpm2_pcr_read(u_boot_console): updates = int(re.findall(r'\d+', str)[0]) # Check the output value - assert 'PCR #0 content' in read_pcr + assert 'PCR #10 content' in read_pcr assert '00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00' in read_pcr @pytest.mark.buildconfigspec('cmd_tpm_v2') @@ -275,19 +275,19 @@ def test_tpm2_pcr_extend(u_boot_console): force_init(u_boot_console) ram = u_boot_utils.find_ram_base(u_boot_console) - read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % (ram + 0x20)) + read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20)) output = u_boot_console.run_command('echo $?') assert output.endswith('0') str = re.findall(r'\d+ known updates', read_pcr)[0] updates = int(re.findall(r'\d+', str)[0]) - u_boot_console.run_command('tpm2 pcr_extend 0 0x%x' % ram) + u_boot_console.run_command('tpm2 pcr_extend 10 0x%x' % ram) output = u_boot_console.run_command('echo $?') assert output.endswith('0') # Read the value back into a different place so we can still use 'ram' as # our zero bytes - read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % (ram + 0x20)) + read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20)) output = u_boot_console.run_command('echo $?') assert output.endswith('0') assert 'f5 a5 fd 42 d1 6a 20 30 27 98 ef 6e d3 09 97 9b' in read_pcr @@ -297,11 +297,11 @@ def test_tpm2_pcr_extend(u_boot_console): new_updates = int(re.findall(r'\d+', str)[0]) assert (updates + 1) == new_updates - u_boot_console.run_command('tpm2 pcr_extend 0 0x%x' % ram) + u_boot_console.run_command('tpm2 pcr_extend 10 0x%x' % ram) output = u_boot_console.run_command('echo $?') assert output.endswith('0') - read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % (ram + 0x20)) + read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20)) output = u_boot_console.run_command('echo $?') assert output.endswith('0') assert '7a 05 01 f5 95 7b df 9c b3 a8 ff 49 66 f0 22 65' in read_pcr diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py index 82932a662bf..1d9149a3f68 100644 --- a/test/py/tests/test_ut.py +++ b/test/py/tests/test_ut.py @@ -433,7 +433,6 @@ def setup_cedit_file(cons): u_boot_utils.run_and_log( cons, f'{expo_tool} -e {inhname} -l {infname} -o {outfname}') - @pytest.mark.buildconfigspec('ut_dm') def test_ut_dm_init(u_boot_console): """Initialize data for ut dm tests.""" @@ -463,6 +462,12 @@ def test_ut_dm_init(u_boot_console): fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB') fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB') + mmc_dev = 6 + fn = os.path.join(u_boot_console.config.source_dir, f'mmc{mmc_dev}.img') + data = b'\x00' * (12 * 1024 * 1024) + with open(fn, 'wb') as fh: + fh.write(data) + @pytest.mark.buildconfigspec('cmd_bootflow') def test_ut_dm_init_bootstd(u_boot_console): """Initialise data for bootflow tests""" diff --git a/tools/.gitignore b/tools/.gitignore index 941d38de212..0108c567309 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -34,7 +34,7 @@ /relocate-rela /spl_size_limit /sunxi-spl-image-builder -/tools/generated/**/*.c +/generated/**/*.c /update_octeon_header /version.h /xway-swap-bytes diff --git a/tools/binman/btool/openssl.py b/tools/binman/btool/openssl.py index aad3b61ae27..7ee2683ab23 100644 --- a/tools/binman/btool/openssl.py +++ b/tools/binman/btool/openssl.py @@ -155,6 +155,7 @@ authInPlace = INTEGER:2 C, ST, L, O, OU, CN and emailAddress cert_type (int): Certification type bootcore (int): Booting core + bootcore_opts(int): Booting core option, lockstep (0) or split (2) mode load_addr (int): Load address of image sha (int): Hash function @@ -225,7 +226,7 @@ emailAddress = {req_dist_name_dict['emailAddress']} imagesize_sbl, hashval_sbl, load_addr_sysfw, imagesize_sysfw, hashval_sysfw, load_addr_sysfw_data, imagesize_sysfw_data, hashval_sysfw_data, sysfw_inner_cert_ext_boot_block, - dm_data_ext_boot_block): + dm_data_ext_boot_block, bootcore_opts): """Create a certificate Args: @@ -241,6 +242,7 @@ emailAddress = {req_dist_name_dict['emailAddress']} bootcore (int): Booting core load_addr (int): Load address of image sha (int): Hash function + bootcore_opts (int): Booting core option, lockstep (0) or split (2) mode Returns: str: Tool output @@ -285,7 +287,7 @@ sysfw_data=SEQUENCE:sysfw_data [sbl] compType = INTEGER:1 bootCore = INTEGER:16 -compOpts = INTEGER:0 +compOpts = INTEGER:{bootcore_opts} destAddr = FORMAT:HEX,OCT:{load_addr:08x} compSize = INTEGER:{imagesize_sbl} shaType = OID:{sha_type} diff --git a/tools/binman/cbfs_util.py b/tools/binman/cbfs_util.py index fc56b40b753..671cafa34c0 100644 --- a/tools/binman/cbfs_util.py +++ b/tools/binman/cbfs_util.py @@ -42,27 +42,24 @@ HEADER_VERSION2 = 0x31313132 FILE_HEADER_FORMAT = b'>8sIIII' FILE_HEADER_LEN = 0x18 FILE_MAGIC = b'LARCHIVE' -FILENAME_ALIGN = 16 # Filename lengths are aligned to this +ATTRIBUTE_ALIGN = 4 # All attribute sizes must be divisible by this -# A stage header containing information about 'stage' files +# A stage-header attribute containing information about 'stage' files # Yes this is correct: this header is in litte-endian format -STAGE_FORMAT = '<IQQII' -STAGE_LEN = 0x1c +ATTR_STAGE_FORMAT = '>IIQII' +ATTR_STAGE_LEN = 0x18 # An attribute describring the compression used in a file ATTR_COMPRESSION_FORMAT = '>IIII' ATTR_COMPRESSION_LEN = 0x10 # Attribute tags -# Depending on how the header was initialised, it may be backed with 0x00 or -# 0xff. Support both. -FILE_ATTR_TAG_UNUSED = 0 -FILE_ATTR_TAG_UNUSED2 = 0xffffffff FILE_ATTR_TAG_COMPRESSION = 0x42435a4c FILE_ATTR_TAG_HASH = 0x68736148 FILE_ATTR_TAG_POSITION = 0x42435350 # PSCB FILE_ATTR_TAG_ALIGNMENT = 0x42434c41 # ALCB FILE_ATTR_TAG_PADDING = 0x47444150 # PDNG +FILE_ATTR_TAG_STAGEHEADER = 0x53746748 # StgH # This is 'the size of bootblock reserved in firmware image (cbfs.txt)' # Not much more info is available, but we set it to 4, due to this comment in @@ -100,7 +97,8 @@ ARCH_NAMES = { # File types. Only supported ones are included here TYPE_CBFSHEADER = 0x02 # Master header, HEADER_FORMAT -TYPE_STAGE = 0x10 # Stage, holding an executable, see STAGE_FORMAT +TYPE_LEGACY_STAGE = 0x10 # Stage, holding an executable +TYPE_STAGE = 0x11 # New-type stage with ATTR_STAGE_FORMAT TYPE_RAW = 0x50 # Raw file, possibly compressed TYPE_EMPTY = 0xffffffff # Empty data @@ -190,7 +188,7 @@ def _pack_string(instr): String with required padding (at least one 0x00 byte) at the end """ val = tools.to_bytes(instr) - pad_len = align_int(len(val) + 1, FILENAME_ALIGN) + pad_len = align_int(len(val) + 1, ATTRIBUTE_ALIGN) return val + tools.get_bytes(0, pad_len - len(val)) @@ -304,7 +302,7 @@ class CbfsFile(object): CbfsFile object containing the file information """ cfile = CbfsFile('', TYPE_EMPTY, b'', None) - cfile.size = space_to_use - FILE_HEADER_LEN - FILENAME_ALIGN + cfile.size = space_to_use - FILE_HEADER_LEN - ATTRIBUTE_ALIGN cfile.erase_byte = erase_byte return cfile @@ -331,9 +329,10 @@ class CbfsFile(object): name = _pack_string(self.name) hdr_len = len(name) + FILE_HEADER_LEN if self.ftype == TYPE_STAGE: - pass + hdr_len += ATTR_STAGE_LEN elif self.ftype == TYPE_RAW: - hdr_len += ATTR_COMPRESSION_LEN + if self.compress: + hdr_len += ATTR_COMPRESSION_LEN elif self.ftype == TYPE_EMPTY: pass else: @@ -359,9 +358,9 @@ class CbfsFile(object): data = self.data if self.ftype == TYPE_STAGE: elf_data = elf.DecodeElf(data, self.base_address) - content = struct.pack(STAGE_FORMAT, self.compress, - elf_data.entry, elf_data.load, - len(elf_data.data), elf_data.memsize) + attr = struct.pack(ATTR_STAGE_FORMAT, FILE_ATTR_TAG_STAGEHEADER, + ATTR_STAGE_LEN, elf_data.load, + elf_data.entry - elf_data.load, elf_data.memsize) data = elf_data.data elif self.ftype == TYPE_RAW: orig_data = data @@ -369,9 +368,11 @@ class CbfsFile(object): data = self.comp_bintool.compress(orig_data) self.memlen = len(orig_data) self.data_len = len(data) - attr = struct.pack(ATTR_COMPRESSION_FORMAT, - FILE_ATTR_TAG_COMPRESSION, ATTR_COMPRESSION_LEN, - self.compress, self.memlen) + if self.compress: + attr = struct.pack(ATTR_COMPRESSION_FORMAT, + FILE_ATTR_TAG_COMPRESSION, + ATTR_COMPRESSION_LEN, self.compress, + self.memlen) elif self.ftype == TYPE_EMPTY: data = tools.get_bytes(self.erase_byte, self.size) else: @@ -391,6 +392,8 @@ class CbfsFile(object): raise ValueError("Internal error: CBFS file '%s': Requested offset %#x but current output position is %#x" % (self.name, self.cbfs_offset, offset)) pad = tools.get_bytes(pad_byte, pad_len) + if attr_pos: + attr_pos += pad_len hdr_len += pad_len # This is the offset of the start of the file's data, @@ -405,9 +408,9 @@ class CbfsFile(object): if expected_len != actual_len: # pragma: no cover # Test coverage of this is not available since this should never # happen. It probably indicates that get_header_len() is broken. - raise ValueError("Internal error: CBFS file '%s': Expected headers of %#x bytes, got %#d" % + raise ValueError("Internal error: CBFS file '%s': Expected headers of %#x bytes, got %#x" % (self.name, expected_len, actual_len)) - return hdr + name + attr + pad + content + data, hdr_len + return hdr + name + pad + attr + content + data, hdr_len class CbfsWriter(object): @@ -453,6 +456,9 @@ class CbfsWriter(object): self._arch = arch self._bootblock_size = 0 self._erase_byte = 0xff + + # Small padding to align a file uses 0 + self._small_pad_byte = 0 self._align = ENTRY_ALIGN self._add_fileheader = False if self._arch == ARCHITECTURE_X86: @@ -474,7 +480,7 @@ class CbfsWriter(object): self._bootblock_size, self._align) self._hdr_at_start = True - def _skip_to(self, fd, offset): + def _skip_to(self, fd, offset, pad_byte): """Write out pad bytes until a given offset Args: @@ -484,16 +490,16 @@ class CbfsWriter(object): if fd.tell() > offset: raise ValueError('No space for data before offset %#x (current offset %#x)' % (offset, fd.tell())) - fd.write(tools.get_bytes(self._erase_byte, offset - fd.tell())) + fd.write(tools.get_bytes(pad_byte, offset - fd.tell())) - def _pad_to(self, fd, offset): + def _pad_to(self, fd, offset, pad_byte): """Write out pad bytes and/or an empty file until a given offset Args: fd: File objext to write to offset: Offset to write to """ - self._align_to(fd, self._align) + self._align_to(fd, self._align, pad_byte) upto = fd.tell() if upto > offset: raise ValueError('No space for data before pad offset %#x (current offset %#x)' % @@ -502,9 +508,9 @@ class CbfsWriter(object): if todo: cbf = CbfsFile.empty(todo, self._erase_byte) fd.write(cbf.get_data_and_offset()[0]) - self._skip_to(fd, offset) + self._skip_to(fd, offset, pad_byte) - def _align_to(self, fd, align): + def _align_to(self, fd, align, pad_byte): """Write out pad bytes until a given alignment is reached This only aligns if the resulting output would not reach the end of the @@ -518,7 +524,7 @@ class CbfsWriter(object): """ offset = align_int(fd.tell(), align) if offset < self._size: - self._skip_to(fd, offset) + self._skip_to(fd, offset, pad_byte) def add_file_stage(self, name, data, cbfs_offset=None): """Add a new stage file to the CBFS @@ -568,7 +574,7 @@ class CbfsWriter(object): raise ValueError('No space for header at offset %#x (current offset %#x)' % (self._header_offset, fd.tell())) if not add_fileheader: - self._pad_to(fd, self._header_offset) + self._pad_to(fd, self._header_offset, self._erase_byte) hdr = struct.pack(HEADER_FORMAT, HEADER_MAGIC, HEADER_VERSION2, self._size, self._bootblock_size, self._align, self._contents_offset, self._arch, 0xffffffff) @@ -580,7 +586,7 @@ class CbfsWriter(object): fd.write(name) self._header_offset = fd.tell() fd.write(hdr) - self._align_to(fd, self._align) + self._align_to(fd, self._align, self._erase_byte) else: fd.write(hdr) @@ -597,24 +603,26 @@ class CbfsWriter(object): # THe header can go at the start in some cases if self._hdr_at_start: self._write_header(fd, add_fileheader=self._add_fileheader) - self._skip_to(fd, self._contents_offset) + self._skip_to(fd, self._contents_offset, self._erase_byte) # Write out each file for cbf in self._files.values(): # Place the file at its requested place, if any offset = cbf.calc_start_offset() if offset is not None: - self._pad_to(fd, align_int_down(offset, self._align)) + self._pad_to(fd, align_int_down(offset, self._align), + self._erase_byte) pos = fd.tell() - data, data_offset = cbf.get_data_and_offset(pos, self._erase_byte) + data, data_offset = cbf.get_data_and_offset(pos, + self._small_pad_byte) fd.write(data) - self._align_to(fd, self._align) + self._align_to(fd, self._align, self._erase_byte) cbf.calced_cbfs_offset = pos + data_offset if not self._hdr_at_start: self._write_header(fd, add_fileheader=self._add_fileheader) # Pad to the end and write a pointer to the CBFS master header - self._pad_to(fd, self._base_address or self._size - 4) + self._pad_to(fd, self._base_address or self._size - 4, self._erase_byte) rel_offset = self._header_offset - self._size fd.write(struct.pack('<I', rel_offset & 0xffffffff)) @@ -734,26 +742,28 @@ class CbfsReader(object): print('name', name) # If there are attribute headers present, read those - compress = self._read_attr(fd, file_pos, attr, offset) - if compress is None: + attrs = self._read_attr(fd, file_pos, attr, offset) + if attrs is None: return False # Create the correct CbfsFile object depending on the type cfile = None cbfs_offset = file_pos + offset fd.seek(cbfs_offset, io.SEEK_SET) + if DEBUG: + print(f'ftype {ftype:x}') if ftype == TYPE_CBFSHEADER: self._read_header(fd) elif ftype == TYPE_STAGE: - data = fd.read(STAGE_LEN) cfile = CbfsFile.stage(self.stage_base_address, name, b'', cbfs_offset) - (cfile.compress, cfile.entry, cfile.load, cfile.data_len, - cfile.memlen) = struct.unpack(STAGE_FORMAT, data) - cfile.data = fd.read(cfile.data_len) + cfile.load, entry_offset, cfile.memlen = attrs + cfile.entry = cfile.load + entry_offset + cfile.data = fd.read(cfile.memlen) + cfile.data_len = cfile.memlen elif ftype == TYPE_RAW: data = fd.read(size) - cfile = CbfsFile.raw(name, data, cbfs_offset, compress) + cfile = CbfsFile.raw(name, data, cbfs_offset, attrs) cfile.decompress() if DEBUG: print('data', data) @@ -777,8 +787,8 @@ class CbfsReader(object): """Read attributes from the file CBFS files can have attributes which are things that cannot fit into the - header. The only attributes currently supported are compression and the - unused tag. + header. The only attributes currently supported are compression, stage + header and the unused tag Args: fd: File to read from @@ -788,11 +798,16 @@ class CbfsReader(object): attributes) Returns: - Compression to use for the file (COMPRESS_...) + Either: + Compression to use for the file (COMPRESS_...) + tuple containing stage info: + load address + entry offset + memory size """ - compress = COMPRESS_NONE + attrs = None if not attr: - return compress + return COMPRESS_NONE attr_size = offset - attr fd.seek(file_pos + attr, io.SEEK_SET) while attr_size: @@ -807,12 +822,15 @@ class CbfsReader(object): # We don't currently use this information atag, alen, compress, _decomp_size = struct.unpack( ATTR_COMPRESSION_FORMAT, data) - elif atag == FILE_ATTR_TAG_UNUSED2: - break + attrs = compress + elif atag == FILE_ATTR_TAG_STAGEHEADER: + atag, alen, load, entry_offset, memsize = struct.unpack( + ATTR_STAGE_FORMAT, data) + attrs = (load, entry_offset, memsize) else: print('Unknown attribute tag %x' % atag) attr_size -= len(data) - return compress + return attrs def _read_header(self, fd): """Read the master header @@ -843,7 +861,8 @@ class CbfsReader(object): def _read_string(cls, fd): """Read a string from a file - This reads a string and aligns the data to the next alignment boundary + This reads a string and aligns the data to the next alignment boundary. + The string must be nul-terminated Args: fd: File to read from @@ -854,8 +873,8 @@ class CbfsReader(object): """ val = b'' while True: - data = fd.read(FILENAME_ALIGN) - if len(data) < FILENAME_ALIGN: + data = fd.read(ATTRIBUTE_ALIGN) + if len(data) < ATTRIBUTE_ALIGN: return None pos = data.find(b'\0') if pos == -1: diff --git a/tools/binman/cbfs_util_test.py b/tools/binman/cbfs_util_test.py index ee951d10cf3..4c415b7ce94 100755 --- a/tools/binman/cbfs_util_test.py +++ b/tools/binman/cbfs_util_test.py @@ -96,7 +96,7 @@ class TestCbfs(unittest.TestCase): self.assertEqual(arch, cbfs.arch) return cbfs - def _check_uboot(self, cbfs, ftype=cbfs_util.TYPE_RAW, offset=0x38, + def _check_uboot(self, cbfs, ftype=cbfs_util.TYPE_RAW, offset=0x20, data=U_BOOT_DATA, cbfs_offset=None): """Check that the U-Boot file is as expected @@ -122,7 +122,7 @@ class TestCbfs(unittest.TestCase): self.assertEqual(len(data), cfile.memlen) return cfile - def _check_dtb(self, cbfs, offset=0x38, data=U_BOOT_DTB_DATA, + def _check_dtb(self, cbfs, offset=0x24, data=U_BOOT_DTB_DATA, cbfs_offset=None): """Check that the U-Boot dtb file is as expected @@ -391,7 +391,7 @@ class TestCbfs(unittest.TestCase): cbfs_util.DEBUG = True with test_util.capture_sys_output() as (stdout, _stderr): cbfs_util.CbfsReader(data) - self.assertEqual('name u-boot\ndata %s\n' % U_BOOT_DATA, + self.assertEqual('name u-boot\nftype 50\ndata %s\n' % U_BOOT_DATA, stdout.getvalue()) finally: cbfs_util.DEBUG = False @@ -437,8 +437,9 @@ class TestCbfs(unittest.TestCase): pos = fd.tell() # Create a new CBFS with only the first 4 bytes of the compression tag, - # then try to read the file - tag_pos = pos + cbfs_util.FILE_HEADER_LEN + cbfs_util.FILENAME_ALIGN + # then try to read the file. Note that the tag gets pushed out 4 bytes + tag_pos = (4 + pos + cbfs_util.FILE_HEADER_LEN + + cbfs_util.ATTRIBUTE_ALIGN) newdata = data[:tag_pos + 4] with test_util.capture_sys_output() as (stdout, _stderr): with io.BytesIO(newdata) as fd: @@ -474,7 +475,7 @@ class TestCbfs(unittest.TestCase): self._compare_expected_cbfs(data, cbfs_fname) def test_cbfs_stage(self): - """Tests handling of a Coreboot Filesystem (CBFS)""" + """Tests handling of a CBFS stage""" if not elf.ELF_TOOLS: self.skipTest('Python elftools not available') elf_fname = os.path.join(self._indir, 'cbfs-stage.elf') @@ -489,7 +490,7 @@ class TestCbfs(unittest.TestCase): load = 0xfef20000 entry = load + 2 - cfile = self._check_uboot(cbfs, cbfs_util.TYPE_STAGE, offset=0x28, + cfile = self._check_uboot(cbfs, cbfs_util.TYPE_STAGE, offset=0x38, data=U_BOOT_DATA + U_BOOT_DTB_DATA) self.assertEqual(entry, cfile.entry) @@ -520,7 +521,7 @@ class TestCbfs(unittest.TestCase): self.assertIn('u-boot', cbfs.files) cfile = cbfs.files['u-boot'] self.assertEqual(cfile.name, 'u-boot') - self.assertEqual(cfile.offset, 56) + self.assertEqual(cfile.offset, 0x30) self.assertEqual(cfile.data, COMPRESS_DATA) self.assertEqual(cfile.ftype, cbfs_util.TYPE_RAW) self.assertEqual(cfile.compress, cbfs_util.COMPRESS_LZ4) @@ -529,7 +530,7 @@ class TestCbfs(unittest.TestCase): self.assertIn('u-boot-dtb', cbfs.files) cfile = cbfs.files['u-boot-dtb'] self.assertEqual(cfile.name, 'u-boot-dtb') - self.assertEqual(cfile.offset, 56) + self.assertEqual(cfile.offset, 0x34) self.assertEqual(cfile.data, COMPRESS_DATA) self.assertEqual(cfile.ftype, cbfs_util.TYPE_RAW) self.assertEqual(cfile.compress, cbfs_util.COMPRESS_LZMA) @@ -598,8 +599,8 @@ class TestCbfs(unittest.TestCase): data = cbw.get_data() cbfs = cbfs_util.CbfsReader(data) - self.assertEqual(0x38, cbfs.files['u-boot'].cbfs_offset) - self.assertEqual(0x78, cbfs.files['u-boot-dtb'].cbfs_offset) + self.assertEqual(0x20, cbfs.files['u-boot'].cbfs_offset) + self.assertEqual(0x64, cbfs.files['u-boot-dtb'].cbfs_offset) if __name__ == '__main__': diff --git a/tools/binman/control.py b/tools/binman/control.py index c6d3205b8c2..2f00279232b 100644 --- a/tools/binman/control.py +++ b/tools/binman/control.py @@ -858,6 +858,8 @@ def Binman(args): data = state.GetFdtForEtype('u-boot-dtb').GetContents() elf.UpdateFile(*elf_params, data) + bintool.Bintool.set_missing_list(None) + # This can only be True if -M is provided, since otherwise binman # would have raised an error already if invalid: diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index e7b4e9380e2..2402adb3d96 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -1944,6 +1944,7 @@ Properties / Entry arguments: - core: core on which bootloader runs, valid cores are 'secure' and 'public' - content: phandle of SPL in case of legacy bootflow or phandles of component binaries in case of combined bootflow + - core-opts (optional): lockstep (0) or split (2) mode set to 0 by default The following properties are only for generating a combined bootflow binary: - sysfw-inner-cert: boolean if binary contains sysfw inner certificate diff --git a/tools/binman/etype/ti_secure_rom.py b/tools/binman/etype/ti_secure_rom.py index 9a7ac9e9e0a..f6fc3f90f84 100644 --- a/tools/binman/etype/ti_secure_rom.py +++ b/tools/binman/etype/ti_secure_rom.py @@ -32,6 +32,7 @@ class Entry_ti_secure_rom(Entry_x509_cert): - core: core on which bootloader runs, valid cores are 'secure' and 'public' - content: phandle of SPL in case of legacy bootflow or phandles of component binaries in case of combined bootflow + - core-opts (optional): lockstep (0) or split (2) mode set to 0 by default The following properties are only for generating a combined bootflow binary: - sysfw-inner-cert: boolean if binary contains sysfw inner certificate @@ -69,6 +70,7 @@ class Entry_ti_secure_rom(Entry_x509_cert): self.sw_rev = fdt_util.GetInt(self._node, 'sw-rev', 1) self.sha = fdt_util.GetInt(self._node, 'sha', 512) self.core = fdt_util.GetString(self._node, 'core', 'secure') + self.bootcore_opts = fdt_util.GetInt(self._node, 'core-opts') self.key_fname = self.GetEntryArgsOrProps([ EntryArg('keyfile', str)], required=True)[0] if self.combined: @@ -97,17 +99,19 @@ class Entry_ti_secure_rom(Entry_x509_cert): bytes content of the entry, which is the certificate binary for the provided data """ + if self.bootcore_opts is None: + self.bootcore_opts = 0 + if self.core == 'secure': if self.countersign: self.cert_type = 3 else: self.cert_type = 2 self.bootcore = 0 - self.bootcore_opts = 32 else: self.cert_type = 1 self.bootcore = 16 - self.bootcore_opts = 0 + return super().GetCertificate(required=required, type='rom') def CombinedGetCertificate(self, required): @@ -126,6 +130,9 @@ class Entry_ti_secure_rom(Entry_x509_cert): self.num_comps = 3 self.sha_type = SHA_OIDS[self.sha] + if self.bootcore_opts is None: + self.bootcore_opts = 0 + # sbl self.content = fdt_util.GetPhandleList(self._node, 'content-sbl') input_data_sbl = self.GetContents(required) diff --git a/tools/binman/etype/x509_cert.py b/tools/binman/etype/x509_cert.py index d028cfe38cd..fc0bb122786 100644 --- a/tools/binman/etype/x509_cert.py +++ b/tools/binman/etype/x509_cert.py @@ -136,7 +136,8 @@ class Entry_x509_cert(Entry_collection): imagesize_sysfw_data=self.imagesize_sysfw_data, hashval_sysfw_data=self.hashval_sysfw_data, sysfw_inner_cert_ext_boot_block=self.sysfw_inner_cert_ext_boot_block, - dm_data_ext_boot_block=self.dm_data_ext_boot_block + dm_data_ext_boot_block=self.dm_data_ext_boot_block, + bootcore_opts=self.bootcore_opts ) if stdout is not None: data = tools.read_file(output_fname) diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index 16156b74105..5ace2a825dc 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -2667,12 +2667,12 @@ class TestFunctional(unittest.TestCase): 'cbfs:offset': 0, 'cbfs:size': len(data), 'cbfs:image-pos': 0, - 'cbfs/u-boot:offset': 0x38, + 'cbfs/u-boot:offset': 0x30, 'cbfs/u-boot:uncomp-size': len(U_BOOT_DATA), - 'cbfs/u-boot:image-pos': 0x38, - 'cbfs/u-boot-dtb:offset': 0xb8, + 'cbfs/u-boot:image-pos': 0x30, + 'cbfs/u-boot-dtb:offset': 0xa4, 'cbfs/u-boot-dtb:size': len(U_BOOT_DATA), - 'cbfs/u-boot-dtb:image-pos': 0xb8, + 'cbfs/u-boot-dtb:image-pos': 0xa4, }, props) def testCbfsBadType(self): @@ -2854,7 +2854,7 @@ class TestFunctional(unittest.TestCase): ' u-boot 0 4 u-boot 0', ' section 100 %x section 100' % section_size, ' cbfs 100 400 cbfs 0', -' u-boot 138 4 u-boot 38', +' u-boot 120 4 u-boot 20', ' u-boot-dtb 180 105 u-boot-dtb 80 3c9', ' u-boot-dtb 500 %x u-boot-dtb 400 3c9' % fdt_size, ' fdtmap %x 3bd fdtmap %x' % diff --git a/tools/binman/test/297_ti_secure_rom.dts b/tools/binman/test/297_ti_secure_rom.dts index d1313769f43..1a3eca94255 100644 --- a/tools/binman/test/297_ti_secure_rom.dts +++ b/tools/binman/test/297_ti_secure_rom.dts @@ -9,6 +9,7 @@ binman { ti-secure-rom { content = <&unsecure_binary>; + core-opts = <2>; }; unsecure_binary: blob-ext { filename = "ti_unsecure.bin"; diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index 5305477c5be..3e42c987d1c 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -35,6 +35,10 @@ from u_boot_pylib.terminal import tprint # which indicates that BREAK_ME has an empty default RE_NO_DEFAULT = re.compile(b'\((\w+)\) \[] \(NEW\)') +# Symbol types which appear in the bloat feature (-B). Others are silently +# dropped when reading in the 'nm' output +NM_SYMBOL_TYPES = 'tTdDbBr' + """ Theory of Operation @@ -693,7 +697,7 @@ class Builder: parts = line.split() if line and len(parts) == 3: size, type, name = line.split() - if type in 'tTdDbB': + if type in NM_SYMBOL_TYPES: # function names begin with '.' on 64-bit powerpc if '.' in name[1:]: name = 'static.' + name.split('.')[0] diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py index 8eba5d34864..197ac1aad10 100755 --- a/tools/patman/__main__.py +++ b/tools/patman/__main__.py @@ -103,6 +103,8 @@ send.add_argument('--no-signoff', action='store_false', dest='add_signoff', default=True, help="Don't add Signed-off-by to patches") send.add_argument('--smtp-server', type=str, help="Specify the SMTP server to 'git send-email'") +send.add_argument('--keep-change-id', action='store_true', + help='Preserve Change-Id tags in patches to send.') send.add_argument('patchfiles', nargs='*') diff --git a/tools/patman/control.py b/tools/patman/control.py index 916ddf8fcff..b292da9dc27 100644 --- a/tools/patman/control.py +++ b/tools/patman/control.py @@ -16,11 +16,14 @@ from patman import gitutil from patman import patchstream from u_boot_pylib import terminal + def setup(): """Do required setup before doing anything""" gitutil.setup() -def prepare_patches(col, branch, count, start, end, ignore_binary, signoff): + +def prepare_patches(col, branch, count, start, end, ignore_binary, signoff, + keep_change_id=False): """Figure out what patches to generate, then generate them The patch files are written to the current directory, e.g. 0001_xxx.patch @@ -35,6 +38,7 @@ def prepare_patches(col, branch, count, start, end, ignore_binary, signoff): end (int): End patch to use (0=last one in series, 1=one before that, etc.) ignore_binary (bool): Don't generate patches for binary files + keep_change_id (bool): Preserve the Change-Id tag. Returns: Tuple: @@ -59,11 +63,12 @@ def prepare_patches(col, branch, count, start, end, ignore_binary, signoff): branch, start, to_do, ignore_binary, series, signoff) # Fix up the patch files to our liking, and insert the cover letter - patchstream.fix_patches(series, patch_files) + patchstream.fix_patches(series, patch_files, keep_change_id) if cover_fname and series.get('cover'): patchstream.insert_cover_letter(cover_fname, series, to_do) return series, cover_fname, patch_files + def check_patches(series, patch_files, run_checkpatch, verbose, use_tree): """Run some checks on a set of patches @@ -166,7 +171,8 @@ def send(args): col = terminal.Color() series, cover_fname, patch_files = prepare_patches( col, args.branch, args.count, args.start, args.end, - args.ignore_binary, args.add_signoff) + args.ignore_binary, args.add_signoff, + keep_change_id=args.keep_change_id) ok = check_patches(series, patch_files, args.check_patch, args.verbose, args.check_patch_use_tree) diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index b0a12f2e8c0..10ea5ff39f5 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -147,8 +147,9 @@ def get_upstream(git_dir, branch): if remote == '.': return merge, None elif remote and merge: - leaf = merge.split('/')[-1] - return '%s/%s' % (remote, leaf), None + # Drop the initial refs/heads from merge + leaf = merge.split('/', maxsplit=2)[2:] + return '%s/%s' % (remote, '/'.join(leaf)), None else: raise ValueError("Cannot determine upstream branch for branch " "'%s' remote='%s', merge='%s'" diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index f91669a9404..e2e2a83e677 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -68,6 +68,7 @@ STATE_PATCH_SUBJECT = 1 # In patch subject (first line of log for a commit) STATE_PATCH_HEADER = 2 # In patch header (after the subject) STATE_DIFFS = 3 # In the diff part (past --- line) + class PatchStream: """Class for detecting/injecting tags in a patch or series of patches @@ -76,7 +77,7 @@ class PatchStream: unwanted tags or inject additional ones. These correspond to the two phases of processing. """ - def __init__(self, series, is_log=False): + def __init__(self, series, is_log=False, keep_change_id=False): self.skip_blank = False # True to skip a single blank line self.found_test = False # Found a TEST= line self.lines_after_test = 0 # Number of lines found after TEST= @@ -86,6 +87,7 @@ class PatchStream: self.section = [] # The current section...END section self.series = series # Info about the patch series self.is_log = is_log # True if indent like git log + self.keep_change_id = keep_change_id # True to keep Change-Id tags self.in_change = None # Name of the change list we are in self.change_version = 0 # Non-zero if we are in a change list self.change_lines = [] # Lines of the current change @@ -452,6 +454,8 @@ class PatchStream: # Detect Change-Id tags elif change_id_match: + if self.keep_change_id: + out = [line] value = change_id_match.group(1) if self.is_log: if self.commit.change_id: @@ -763,7 +767,7 @@ def get_metadata_for_test(text): pst.finalise() return series -def fix_patch(backup_dir, fname, series, cmt): +def fix_patch(backup_dir, fname, series, cmt, keep_change_id=False): """Fix up a patch file, by adding/removing as required. We remove our tags from the patch file, insert changes lists, etc. @@ -776,6 +780,7 @@ def fix_patch(backup_dir, fname, series, cmt): fname (str): Filename to patch file to process series (Series): Series information about this patch set cmt (Commit): Commit object for this patch file + keep_change_id (bool): Keep the Change-Id tag. Return: list: A list of errors, each str, or [] if all ok. @@ -783,7 +788,7 @@ def fix_patch(backup_dir, fname, series, cmt): handle, tmpname = tempfile.mkstemp() outfd = os.fdopen(handle, 'w', encoding='utf-8') infd = open(fname, 'r', encoding='utf-8') - pst = PatchStream(series) + pst = PatchStream(series, keep_change_id=keep_change_id) pst.commit = cmt pst.process_stream(infd, outfd) infd.close() @@ -795,7 +800,7 @@ def fix_patch(backup_dir, fname, series, cmt): shutil.move(tmpname, fname) return cmt.warn -def fix_patches(series, fnames): +def fix_patches(series, fnames, keep_change_id=False): """Fix up a list of patches identified by filenames The patch files are processed in place, and overwritten. @@ -803,6 +808,7 @@ def fix_patches(series, fnames): Args: series (Series): The Series object fnames (:type: list of str): List of patch files to process + keep_change_id (bool): Keep the Change-Id tag. """ # Current workflow creates patches, so we shouldn't need a backup backup_dir = None #tempfile.mkdtemp('clean-patch') @@ -811,7 +817,8 @@ def fix_patches(series, fnames): cmt = series.commits[count] cmt.patch = fname cmt.count = count - result = fix_patch(backup_dir, fname, series, cmt) + result = fix_patch(backup_dir, fname, series, cmt, + keep_change_id=keep_change_id) if result: print('%d warning%s for %s:' % (len(result), 's' if len(result) > 1 else '', fname)) diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst index 038b651ee87..a8b317eed63 100644 --- a/tools/patman/patman.rst +++ b/tools/patman/patman.rst @@ -371,11 +371,12 @@ Series-process-log: sort, uniq Separate each tag with a comma. Change-Id: - This tag is stripped out but is used to generate the Message-Id - of the emails that will be sent. When you keep the Change-Id the - same you are asserting that this is a slightly different version - (but logically the same patch) as other patches that have been - sent out with the same Change-Id. + This tag is used to generate the Message-Id of the emails that + will be sent. When you keep the Change-Id the same you are + asserting that this is a slightly different version (but logically + the same patch) as other patches that have been sent out with the + same Change-Id. The Change-Id tag line is removed from outgoing + patches, unless the `keep_change_id` settings is set to `True`. Various other tags are silently removed, like these Chrome OS and Gerrit tags:: diff --git a/tools/patman/test_checkpatch.py b/tools/patman/test_checkpatch.py index a8bb364e42b..db7860f551d 100644 --- a/tools/patman/test_checkpatch.py +++ b/tools/patman/test_checkpatch.py @@ -18,19 +18,47 @@ from patman import commit class Line: + """Single changed line in one file in a patch + + Args: + fname (str): Filename containing the added line + text (str): Text of the added line + """ def __init__(self, fname, text): self.fname = fname self.text = text class PatchMaker: + """Makes a patch for checking with checkpatch.pl + + The idea here is to create a patch which adds one line in one file, + intended to provoke a checkpatch error or warning. The base patch is empty + (i.e. invalid), so you should call add_line() to add at least one line. + """ def __init__(self): + """Set up the PatchMaker object + + Properties: + lines (list of Line): List of lines to add to the patch. Note that + each line has both a file and some text associated with it, + since for simplicity we just add a single line for each file + """ self.lines = [] def add_line(self, fname, text): + """Add to the list of filename/line pairs""" self.lines.append(Line(fname, text)) def get_patch_text(self): + """Build the patch text + + Takes a base patch and adds a diffstat and patch for each filename/line + pair in the list. + + Returns: + str: Patch text ready for submission to checkpatch + """ base = '''From 125b77450f4c66b8fd9654319520bbe795c9ef31 Mon Sep 17 00:00:00 2001 From: Simon Glass <sjg@chromium.org> Date: Sun, 14 Jun 2020 09:45:14 -0600 @@ -75,6 +103,11 @@ Signed-off-by: Simon Glass <sjg@chromium.org> return '\n'.join(lines) def get_patch(self): + """Get the patch text and write it into a temporary file + + Returns: + str: Filename containing the patch + """ inhandle, inname = tempfile.mkstemp() infd = os.fdopen(inhandle, 'w') infd.write(self.get_patch_text()) @@ -82,6 +115,22 @@ Signed-off-by: Simon Glass <sjg@chromium.org> return inname def run_checkpatch(self): + """Run checkpatch on the patch file + + Returns: + namedtuple containing: + ok: False=failure, True=ok + problems: List of problems, each a dict: + 'type'; error or warning + 'msg': text message + 'file' : filename + 'line': line number + errors: Number of errors + warnings: Number of warnings + checks: Number of checks + lines: Number of lines + stdout: Full output of checkpatch + """ return checkpatch.check_patch(self.get_patch(), show_types=True) @@ -160,6 +209,22 @@ Signed-off-by: Simon Glass <sjg@chromium.org> rc = os.system('diff -u %s %s' % (inname, expname)) self.assertEqual(rc, 0) + os.remove(inname) + + # Test whether the keep_change_id settings works. + inhandle, inname = tempfile.mkstemp() + infd = os.fdopen(inhandle, 'w', encoding='utf-8') + infd.write(data) + infd.close() + + patchstream.fix_patch(None, inname, series.Series(), com, + keep_change_id=True) + + with open(inname, 'r') as f: + content = f.read() + self.assertIn( + 'Change-Id: I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413', + content) os.remove(inname) os.remove(expname) @@ -238,7 +303,7 @@ index 0000000..2234c87 + * passed to kernel in the ATAGs + */ + -+#include <common.h> ++#include <config.h> + +struct bootstage_record { + u32 time_us; @@ -401,10 +466,15 @@ index 0000000..2234c87 def test_barred_include_in_hdr(self): """Test for using a barred include in a header file""" pm = PatchMaker() - #pm.add_line('include/myfile.h', '#include <common.h>') pm.add_line('include/myfile.h', '#include <dm.h>') self.check_single_message(pm, 'BARRED_INCLUDE_IN_HDR', 'error') + def test_barred_include_common_h(self): + """Test for adding common.h to a file""" + pm = PatchMaker() + pm.add_line('include/myfile.h', '#include <common.h>') + self.check_single_message(pm, 'BARRED_INCLUDE_COMMON_H', 'error') + def test_config_is_enabled_config(self): """Test for accidental CONFIG_IS_ENABLED(CONFIG_*) calls""" pm = PatchMaker() diff --git a/tools/sfspl.c b/tools/sfspl.c index ec18a0a77e7..c76420ce21b 100644 --- a/tools/sfspl.c +++ b/tools/sfspl.c @@ -99,7 +99,7 @@ static int sfspl_image_extract_subimage(void *ptr, { struct spl_hdr *hdr = (void *)ptr; unsigned char *buf = ptr; - int fd; + int fd, ret = EXIT_SUCCESS; unsigned int hdr_size = le32_to_cpu(hdr->hdr_size); unsigned int file_size = le32_to_cpu(hdr->file_size); @@ -110,16 +110,16 @@ static int sfspl_image_extract_subimage(void *ptr, fd = open(params->outfile, O_WRONLY | O_CREAT | O_TRUNC, 0644); if (fd == -1) { - perror("Can write file"); + perror("Cannot open file"); return EXIT_FAILURE; } if (write(fd, &buf[hdr_size], file_size) != file_size) { perror("Cannot write file"); - return EXIT_FAILURE; + ret = EXIT_FAILURE; } close(fd); - return EXIT_SUCCESS; + return ret; } static int sfspl_check_image_type(uint8_t type) diff --git a/tools/u_boot_pylib/command.py b/tools/u_boot_pylib/command.py index 9bbfc5bdd83..bbe95d86122 100644 --- a/tools/u_boot_pylib/command.py +++ b/tools/u_boot_pylib/command.py @@ -105,9 +105,7 @@ def run_pipe(pipe_list, infile=None, outfile=None, last_pipe.communicate_filter(output_func)) if result.stdout and oneline: result.output = result.stdout.rstrip(b'\r\n') - result.return_code = last_pipe.wait() - else: - result.return_code = os.waitpid(last_pipe.pid, 0)[1] + result.return_code = last_pipe.wait() if raise_on_error and result.return_code: raise Exception("Error running '%s'" % user_pipestr) return result.to_output(binary) |