diff options
Diffstat (limited to 'arch/arm')
36 files changed, 755 insertions, 50 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8b9ced128b6..03ed3cbeb79 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -327,6 +327,7 @@ zynqmp-sc-vpk120-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk120-revB.dtbo zynqmp-sc-vpk180-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revA.dtbo zynqmp-sc-vpk180-revB-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vpk180-revB.dtbo zynqmp-sc-vn-p-b2197-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vn-p-b2197-00-revA.dtbo +zynqmp-sc-vm-p-b1369-00-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vm-p-m1369-00-revA.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vek280-revB.dtb @@ -335,6 +336,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk120-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vpk180-revB.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vn-p-b2197-00-revA.dtb +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sc-vm-p-b1369-00-revA.dtb zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index 6e5379e53c5..38925d53065 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -7,18 +7,48 @@ &{/imx8qm-pm} { + bootph-some-ram; bootph-pre-ram; }; &mu { + bootph-some-ram; bootph-pre-ram; }; &clk { + bootph-some-ram; bootph-pre-ram; }; &iomuxc { + bootph-some-ram; + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&{/mu@5d1c0000/iomuxc/imx8qm-mek} { + bootph-some-ram; + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_lpuart0 { + bootph-some-ram; + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { bootph-pre-ram; }; @@ -75,10 +105,12 @@ }; &pd_dma { + bootph-some-ram; bootph-pre-ram; }; &pd_dma_lpuart0 { + bootph-some-ram; bootph-pre-ram; }; @@ -131,6 +163,7 @@ }; &lpuart0 { + bootph-some-ram; bootph-pre-ram; }; diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts index 63908ba6bf1..6cf7ce3d5e0 100644 --- a/arch/arm/dts/fsl-imx8qm-mek.dts +++ b/arch/arm/dts/fsl-imx8qm-mek.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "fsl-imx8qm.dtsi" -#include "fsl-imx8qm-mek-u-boot.dtsi" / { model = "Freescale i.MX8QM MEK"; diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index 591eb66604b..e670214b5fc 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -6,19 +6,32 @@ #include "imx8qxp-u-boot.dtsi" &{/imx8qx-pm} { - + bootph-some-ram; bootph-pre-ram; }; &mu { + bootph-some-ram; bootph-pre-ram; }; &clk { + bootph-some-ram; bootph-pre-ram; }; &iomuxc { + bootph-some-ram; + bootph-pre-ram; +}; + +&{/mu@5d1c0000/iomuxc/imx8qxp-mek} { + bootph-some-ram; + bootph-pre-ram; +}; + +&pinctrl_lpuart0 { + bootph-some-ram; bootph-pre-ram; }; @@ -75,10 +88,12 @@ }; &pd_dma { + bootph-some-ram; bootph-pre-ram; }; &pd_dma_lpuart0 { + bootph-some-ram; bootph-pre-ram; }; @@ -131,6 +146,7 @@ }; &lpuart0 { + bootph-some-ram; bootph-pre-ram; }; diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts index 6a987f0dbb3..983b918dc7d 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek.dts +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-mek-u-boot.dtsi" / { model = "Freescale i.MX8QXP MEK"; diff --git a/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi new file mode 100644 index 00000000000..27b4b2ed84a --- /dev/null +++ b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include "imx93-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + bootph-pre-ram; + bootph-some-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index 03e6a858a7b..a25eae9bd38 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -87,7 +87,7 @@ reg = <0x402c0000 0x4000>; interrupts = <110>; clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, - <&clks IMXRT1050_CLK_OSC>, + <&clks IMXRT1050_CLK_AHB_PODF>, <&clks IMXRT1050_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts index c2fd0c0392c..0d8e7016860 100644 --- a/arch/arm/dts/imxrt1170-evk.dts +++ b/arch/arm/dts/imxrt1170-evk.dts @@ -20,6 +20,8 @@ }; memory { + #address-cells = <1>; + #size-cells = <1>; device_type = "memory"; reg = <0x20240000 0xf0000 0x80000000 0x4000000>; diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index b98ed16bc5f..179060c56ee 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -40,6 +40,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index e6a5c2b699e..ffcc3334529 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -40,6 +40,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/versal-net-mini-emmc.dts b/arch/arm/dts/versal-net-mini-emmc.dts index e200fb694c6..20e4e299404 100644 --- a/arch/arm/dts/versal-net-mini-emmc.dts +++ b/arch/arm/dts/versal-net-mini-emmc.dts @@ -54,6 +54,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0 0xf1050000 0 0x10000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/versal-net-mini.dts b/arch/arm/dts/versal-net-mini.dts index 9365efbe9fe..f98f95a5c2f 100644 --- a/arch/arm/dts/versal-net-mini.dts +++ b/arch/arm/dts/versal-net-mini.dts @@ -60,7 +60,6 @@ clock-names = "uartclk", "apb_pclk"; clocks = <&clk1>, <&clk1>; clock = <1000000>; - current-speed = <115200>; skip-init; }; }; diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts index 8d007378033..8031488d17a 100644 --- a/arch/arm/dts/zynq-dlc20-rev1.0.dts +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -83,6 +83,9 @@ bootph-all; status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */ non-removable; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <4>; }; diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts index 96d2937de8b..a8f345032ea 100644 --- a/arch/arm/dts/zynq-minized.dts +++ b/arch/arm/dts/zynq-minized.dts @@ -92,6 +92,9 @@ &sdhci1 { status = "okay"; non-removable; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <4>; max-frequency = <12000000>; diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index 293d8e97b63..d540f334f51 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -60,6 +60,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index c439f778ca4..6ef8b1462eb 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -68,6 +68,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index d6cd193a449..c597adb80cb 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -88,6 +88,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 902fdd4de6c..eefe5ab61e7 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -84,6 +84,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index f3994bca4a0..7ea4eab6a37 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -84,6 +84,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index cf2219797a5..ad4b3c5f8b1 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -52,6 +52,9 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; non-removable; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 4c9f56a8076..fd421b4fe7e 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -52,6 +52,9 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; non-removable; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index ae52e8e996a..fce0d8d5ca1 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -60,6 +60,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; @@ -155,7 +158,7 @@ reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; @@ -163,15 +166,15 @@ /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ @@ -212,75 +215,75 @@ reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ - compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ + compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus.rst - wiring is missing */ reg = <0x1f>; }; }; diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 1fcb5bfb928..1af3f643567 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -288,6 +288,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso new file mode 100644 index 00000000000..8412aecd726 --- /dev/null +++ b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso @@ -0,0 +1,400 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP VM-P-M1369-00 + * + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sc-vm-p-m1369-revA", + "xlnx,zynqmp-sc-vm-p-m1369", "xlnx,zynqmp"; + + ina226-u19 { + compatible = "iio-hwmon"; + io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>; + }; + ina226-u287 { + compatible = "iio-hwmon"; + io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; + }; + ina226-u288 { + compatible = "iio-hwmon"; + io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>; + }; + ina226-u289 { + compatible = "iio-hwmon"; + io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; + }; + ina226-u290 { + compatible = "iio-hwmon"; + io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>; + }; + ina226-u291 { + compatible = "iio-hwmon"; + io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; + }; + ina226-u292 { + compatible = "iio-hwmon"; + io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; + }; + ina226-u293 { + compatible = "iio-hwmon"; + io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; + }; + ina226-u294 { + compatible = "iio-hwmon"; + io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; + }; + ina226-u295 { + compatible = "iio-hwmon"; + io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>; + }; + ina226-u298 { + compatible = "iio-hwmon"; + io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>; + }; + ina226-u296 { + compatible = "iio-hwmon"; + io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>; + }; + ina226-u299 { + compatible = "iio-hwmon"; + io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; + }; + ina226-u300 { + compatible = "iio-hwmon"; + io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; + }; + ina226-u301 { + compatible = "iio-hwmon"; + io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; + }; + ina226-u297 { + compatible = "iio-hwmon"; + io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>; + }; +}; + +&i2c1 { /* i2c_main bus */ + #address-cells = <1>; + #size-cells = <0>; + + /* u97 eeprom at 0x54 described in sc-revB - WP protection via BOARD_EEPROM_WP - J1801 */ + + /* i2c_main_1 - u72 - j108 - disable translation, add 8 */ + /* J133 - OE for u91@55 + 8 - 161,132813MHz - QSFP56G_0 */ + qsfp56g_0_clk: clock-controller@5d { + compatible = "renesas,proxo-xp"; + reg = <0x5d>; + #clock-cells = <0>; + clock-output-names = "qsfp56g_0_clk"; + }; + + /* J134 - OE for u92@57 + 8 - 322,265625MHz - QSFP56G_1 */ + qsfp56g_1_clk: clock-controller@5f { + compatible = "renesas,proxo-xp"; + reg = <0x5f>; + #clock-cells = <0>; + clock-output-names = "qsfp56g_1_clk"; + }; + + /* i2c_main_2 - u74 - j110 - disable translation, add 9 */ + /* J210 - OE for u164@50 + 9 - 320MHz - CH2_LP5 */ + ch2_lpddr5_refclk: clock-controller@59 { + compatible = "renesas,proxo-xp"; + reg = <0x59>; + #clock-cells = <0>; + clock-output-names = "ch2_lpddr5_refclk"; + }; + + /* i2c_main_3 - u76 - j112 - disable translation, add 6 */ + /* J231 - OE for u165@50 + 6 - 320MHz - _RDIMM */ + ddr5_dimm1_refclk: clock-controller@56 { + compatible = "renesas,proxo-xp"; + reg = <0x56>; + #clock-cells = <0>; + clock-output-names = "ddr5_udimm_refclk"; + }; + + /* i2c_main_4 - u73 - j109 - disable translation, add 5 */ + /* J117 - OE for u82@50 + 5 - 33,3333MHz - PS_REFCLK */ + ps_refclk: clock-controller@55 { + compatible = "renesas,proxo-xp"; + reg = <0x55>; + #clock-cells = <0>; + clock-output-names = "ps_refclk"; + }; + + /* J71 - selection to LP_I2C_SCL_J or LP_I2C_PMC_SCL_J */ + /* J70 - selection to LP_I2C_SDA_J or LP_I2C_PMC_SDA_J */ + /* this should be SW controlable too */ +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + /* u134 tps544b25 but connected to J178 connector */ + /* u48/IMx3112/0x77 - 1:2 multiplexer - also accessed from Versal NET */ + /* Connection DDR5_UDIMM - SPD can be from 0x50-0x57 */ + /* FIXME gpio should handle SYSCTLR_PMBUS_ALERT and also INA226_PMBUS_ALERT */ + /* Access to i2c_pmc bus via u49 with OE j100 or via SYSCTLR_I2C_PMC_EN */ + + /* ina226_pmbus - J103 - disable INA226_PMBUS */ + vcc_soc_ina: power-monitor@40 { /* u19 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x40>; + shunt-resistor = <1000>; /* R222 */ + }; + + vcc_ram_ina: power-monitor@41 { /* u287 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x41>; + shunt-resistor = <1000>; /* R32981 */ + }; + + vcc_pslp_ina: power-monitor@42 { /* u288 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x42>; + shunt-resistor = <1000>; /* R32984 */ + }; + + vccaux_ina: power-monitor@43 { /* u289 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x43>; + shunt-resistor = <1000>; /* R32987 */ + }; + + vccaux_pmc_ina: power-monitor@44 { /* u290 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x44>; + shunt-resistor = <1000>; /* R32990 */ + }; + + vcco_500_ina: power-monitor@45 { /* u291 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x45>; + shunt-resistor = <1000>; /* R32993 */ + }; + + vcco_501_ina: power-monitor@46 { /* u292 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x46>; + shunt-resistor = <1000>; /* R32996 */ + }; + + vcco_502_ina: power-monitor@47 { /* u293 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x47>; + shunt-resistor = <1000>; /* R32999 */ + }; + + vcco_503_ina: power-monitor@48 { /* u294 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x48>; + shunt-resistor = <1000>; /* R33002 */ + }; + + vcc_ddr5_rdimm_ina: power-monitor@49 { /* u295 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x49>; + shunt-resistor = <1000>; /* R33005 */ + }; + + lp5_1v0_ina: power-monitor@4a { /* u298 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4a>; + shunt-resistor = <1000>; /* R33014 */ + }; + + vcc_fmc_ina: power-monitor@4b { /* u296 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4b>; + shunt-resistor = <1000>; /* R33008 */ + }; + + gtm_avcc_ina: power-monitor@4c { /* u299 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4c>; + shunt-resistor = <1000>; /* R33017 */ + }; + + gtm_avtt_ina: power-monitor@4d { /* u300 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4d>; + shunt-resistor = <1000>; /* R33020 */ + }; + + gtm_avccaux_ina: power-monitor@4e { /* u301 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4e>; + shunt-resistor = <1000>; /* R33023 */ + }; + + vcc_mipi_ina: power-monitor@4f { /* u297 */ + compatible = "ti,ina226"; + #io-channel-cells = <1>; + reg = <0x4f>; + shunt-resistor = <1000>; /* R33011 */ + }; + + /* pmbus - j105 - disable main PMBUS - also going to j102 connector */ + vcc_pslp: regulator@15 { /* u24 */ + compatible = "ti,tps546b24a"; + reg = <0x15>; + }; + + vccaux_pmc: regulator@17 { /* u26 */ + compatible = "ti,tps546b24a"; + reg = <0x17>; + }; + + vcco_500: regulator@18 { /* u27 */ + compatible = "ti,tps546b24a"; + reg = <0x18>; + }; + + vcco_501: regulator@19 { /* u28 */ + compatible = "ti,tps546b24a"; + reg = <0x19>; + }; + + vcco_502: regulator@1a { /* u29 */ + compatible = "ti,tps546b24a"; + reg = <0x1a>; + }; + + vcco_503: regulator@1b { /* u30 */ + compatible = "ti,tps546b24a"; + reg = <0x1b>; + }; + + vcc_ddr5_rdimm: regulator@1c { /* u31 */ + compatible = "ti,tps546b24a"; + reg = <0x1c>; + }; + + gtm_avcc: regulator@22 { /* u37 */ + compatible = "ti,tps546b24a"; + reg = <0x22>; + }; + + gtm_avtt: regulator@20 { /* u38 */ + compatible = "ti,tps546b24a"; + reg = <0x20>; + }; + + gtm_avccaux: regulator@21 { /* u39 */ + compatible = "ti,tps546b24a"; + reg = <0x21>; + }; + + vccint_gt: regulator@2a { /* u44 */ + compatible = "ti,tps546b24a"; + reg = <0x2a>; + }; + + util_1v8: regulator@2b { /* u1839 */ + compatible = "ti,tps546b24a"; + reg = <0x2b>; + }; + + vcc_pmc: regulator@2c { /* u46 */ + compatible = "ti,tps546b24a"; + reg = <0x2c>; + }; + + /* pmbus via U62 as ext_pmbus - disable via j104 */ + vccint: regulator@10 { /* u18 */ + compatible = "ti,tps546b24"; + reg = <0x10>; + }; + + vccsoc: regulator@11 { /* u20 */ + compatible = "ti,tps546b24"; + reg = <0x11>; + }; + + vcc_io: regulator@12 { /* u21 */ + compatible = "ti,tps546b24"; + reg = <0x12>; + }; + + vcc_psfp: regulator@13 { /* u22 */ + compatible = "ti,tps546b24"; + reg = <0x13>; + }; + + vcc_ram: regulator@14 { /* u23 */ + compatible = "ti,tps546b24"; + reg = <0x14>; + }; + + vccaux: regulator@16 { /* u25 */ + compatible = "ti,tps546b24"; + reg = <0x16>; + }; + + lp5_1v0: regulator@1d { /* u32 */ + compatible = "ti,tps546b24"; + reg = <0x1d>; + }; + + vcc_fmc: regulator@1e { /* u33 */ + compatible = "ti,tps546b24"; + reg = <0x1e>; + }; + + lp5_vdd1: regulator@25 { /* u40 */ + compatible = "ti,tps546b24"; + reg = <0x25>; + }; + + lp5_vdd2: regulator@26 { /* u41 */ + compatible = "ti,tps546b24"; + reg = <0x26>; + }; + + lp5_vddq: regulator@27 { /* u42 */ + compatible = "ti,tps546b24"; + reg = <0x27>; + }; + + vcco_hdio: regulator@29 { /* u43 */ + compatible = "ti,tps546b24"; + reg = <0x29>; + }; + + vcc_mipi: regulator@1f { /* u47 */ + compatible = "ti,tps546b24"; + reg = <0x1f>; + }; + + /* connected via J425 connector + ucd90320: power-sequencer@73 { // u16 + compatible = "ti,ucd90320"; + reg = <0x73>; + };*/ +}; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index d95a05e2159..8056f6b176e 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -247,6 +247,9 @@ pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index 0d96c6f9f04..2037686b9b4 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -93,6 +93,9 @@ status = "okay"; non-removable; disable-wp; /* We don't have a write-protect detection */ + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index 4768fac71d0..f281c7fb9fd 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -105,6 +105,9 @@ status = "okay"; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index c5945067cd5..c9051360931 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -509,6 +509,9 @@ xlnx,mio-bank = <0>; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 4d32c28670d..5c1054138fc 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -23,6 +23,13 @@ choice prompt "NXP i.MX9 board select" optional +config TARGET_IMX93_9X9_QSB + bool "imx93_qsb" + select OF_BOARD_FIXUP + select IMX93 + select IMX9_LPDDR4X + imply OF_UPSTREAM + config TARGET_IMX93_11X11_EVK bool "imx93_11x11_evk" select OF_BOARD_FIXUP @@ -42,6 +49,7 @@ config TARGET_PHYCORE_IMX93 endchoice source "board/freescale/imx93_evk/Kconfig" +source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index dda57ed7f55..c00be19c4fa 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -35,6 +35,7 @@ static struct imx_intpll_rate_table imx9_intpll_tbl[] = { static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */ FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */ + FRAC_PLL_RATE(800000000U, 1, 200, 6, 0, 1), /* 800Mhz */ FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */ FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1), FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1), diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c index 47106fffefb..5dbc398e97f 100644 --- a/arch/arm/mach-imx/imx9/clock_root.c +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -7,9 +7,10 @@ #include <config.h> #include <command.h> +#include <asm/arch/ccm_regs.h> #include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/ccm_regs.h> #include <asm/global_data.h> #include <linux/iopoll.h> diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 2e68557d6a9..4e0e8ed0582 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -17,13 +17,6 @@ config MX7D select ROM_UNIFIED_SECTIONS imply CMD_FUSE -config TEXT_BASE - default 0x87800000 - -config SPL_TEXT_BASE - depends on SPL - default 0x00912000 - choice prompt "MX7 board select" optional diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 24fd5751216..960ffac2105 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -112,19 +112,32 @@ u64 get_page_table_size(void) return 0x14000; } -#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) void tcm_init(u8 mode) { - puts("WARNING: Initializing TCM overwrites TCM content\n"); - initialize_tcm(mode); - memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); + int ret; + + ret = check_tcm_mode(mode); + if (!ret) { + puts("WARNING: Initializing TCM overwrites TCM content\n"); + initialize_tcm(mode); + memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); + } + + if (ret == -EACCES) + printf("ERROR: Split to lockstep mode required reset/disable cpu\n"); + + /* Ignore if ret is -EAGAIN, trying to initialize same mode again */ } #endif #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU int arm_reserve_mmu(void) { - tcm_init(TCM_LOCK); + puts("WARNING: Initializing TCM overwrites TCM content\n"); + initialize_tcm(TCM_LOCK); + memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); + gd->arch.tlb_size = PGTABLE_SIZE; gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index 15b69e77712..9af3ab5d6b6 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -48,9 +48,10 @@ enum { unsigned int zynqmp_get_silicon_version(void); +int check_tcm_mode(bool mode); void initialize_tcm(bool mode); void mem_map_fill(void); -#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) void tcm_init(u8 mode); #endif diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 9b46a25a1cb..6e6da8008f4 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -12,7 +12,9 @@ #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <linux/bitfield.h> #include <linux/delay.h> +#include <linux/errno.h> #include <linux/string.h> #define LOCK 0 @@ -264,6 +266,28 @@ void initialize_tcm(bool mode) } } +int check_tcm_mode(bool mode) +{ + u32 tmp, cpu_state; + bool mode_prev; + + tmp = readl(&rpu_base->rpu_glbl_ctrl); + mode_prev = FIELD_GET(ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK, tmp); + + tmp = readl(&crlapb_base->rst_lpd_top); + cpu_state = FIELD_GET(ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK, tmp); + cpu_state = cpu_state ? false : true; + + if ((mode_prev == SPLIT && mode == LOCK) && cpu_state) + return -EACCES; + + if (mode_prev == mode) + return -EAGAIN; + + return 0; +} + static void mark_r5_used(u32 nr, u8 mode) { u32 mask = 0; diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c index 3b4d9c60e5c..8ee25e4c316 100644 --- a/arch/arm/mach-zynqmp/zynqmp.c +++ b/arch/arm/mach-zynqmp/zynqmp.c @@ -151,14 +151,12 @@ static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, if (argc != cmdtp->maxargs) return CMD_RET_USAGE; - if (strcmp(argv[2], "lockstep") && strcmp(argv[2], "split")) { - printf("mode param should be lockstep or split\n"); - return CMD_RET_FAILURE; - } - - mode = hextoul(argv[2], NULL); - if (mode != TCM_LOCK && mode != TCM_SPLIT) { - printf("Mode should be either 0(lock)/1(split)\n"); + if (!strcmp(argv[2], "lockstep") || !strcmp(argv[2], "0")) { + mode = TCM_LOCK; + } else if (!strcmp(argv[2], "split") || !strcmp(argv[2], "1")) { + mode = TCM_SPLIT; + } else { + printf("Mode should be either lockstep/split\n"); return CMD_RET_FAILURE; } @@ -429,7 +427,7 @@ U_BOOT_LONGHELP(zynqmp, " initialized before accessing to avoid ECC\n" " errors. mode specifies in which mode TCM has\n" " to be initialized. Supported modes will be\n" - " lock(0)/split(1)\n" + " lockstep(0)/split(1)\n" #endif "zynqmp pmufw address size - load PMU FW configuration object\n" "zynqmp pmufw node <id> - load PMU FW configuration object, <id> in dec\n" |