diff options
Diffstat (limited to 'arch')
173 files changed, 0 insertions, 303 deletions
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index c818b8bdaec..39f361293fd 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -77,7 +77,6 @@ static inline void sync(void) #define __arch_putl(v, a) ({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); }) #define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); }) - /* * We add memory barriers for __raw_readX / __raw_writeX accessors same way as * it is done for readX and writeX accessors as lots of U-Boot driver uses @@ -93,7 +92,6 @@ static inline void sync(void) #define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) #define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) - static inline void __raw_writesb(unsigned long addr, const void *data, int bytelen) { diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index 07ab04b7b08..0e100e6f13d 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -44,7 +44,6 @@ int cleanup_before_linux (void) disable_interrupts(); - /* turn off I/D-cache */ icache_disable(); dcache_disable(); diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index f25a8674dea..36c557d4a8f 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -49,7 +49,6 @@ unsigned long long get_ticks(void) return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; } - ulong timer_get_boot_us(void) { if (!gd->arch.timer_rate_hz) diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c index b769c451105..fa8af1b6941 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c @@ -84,7 +84,6 @@ static int peri_clk_enable(struct clk *c, int enable) struct bcm_clk_gate *gate = &cd->gate; void *base = (void *)c->ccu_clk_mgr_base; - debug("%s: %s\n", __func__, c->name); clk_get_rate(c); /* Make sure rate and sel are filled in */ diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c index 3f2e021a307..71b3a9277b1 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -84,7 +84,6 @@ static int peri_clk_enable(struct clk *c, int enable) struct bcm_clk_gate *gate = &cd->gate; void *base = (void *)c->ccu_clk_mgr_base; - debug("%s: %s\n", __func__, c->name); clk_get_rate(c); /* Make sure rate and sel are filled in */ diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 74a2dcbc116..dccf2fb3eb1 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -224,7 +224,6 @@ void enable_caches(void) } #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ - uint get_svr(void) { struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/dts/vf610-pinfunc.h b/arch/arm/dts/vf610-pinfunc.h index b7b7322a2d1..6775e4e3371 100644 --- a/arch/arm/dts/vf610-pinfunc.h +++ b/arch/arm/dts/vf610-pinfunc.h @@ -20,7 +20,6 @@ #define ALT6 0x6 #define ALT7 0x7 - #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 #define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ca5e33379ba..306f797f7a8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -190,7 +190,6 @@ #define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_USFCFG_MASK 0x00000400 - /* PCIe */ #define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h index c18c51ed2c7..b08274e361b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -37,7 +37,6 @@ * */ - #define FSL_INVALID_STREAM_ID 0 /* legacy devices */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 140849d4e1f..09199dfad25 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -97,7 +97,6 @@ #define FSL_PEX_STREAM_ID_END (0x100) #endif - /* DPAA2 - set in MC DPC and alloced by MC */ #define FSL_DPAA2_STREAM_ID_START 23 #define FSL_DPAA2_STREAM_ID_END 63 diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h index b98b45cc817..bcde48e4737 100644 --- a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -49,5 +49,4 @@ #define USB2_PHY01_REFCLK_SEL (1 << 12) #define USB2_PHY2_REFCLK_SEL (1 << 14) - #endif diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h b/arch/arm/include/asm/arch-hi6220/hi6220.h index 55729e306e4..6d8bba6f7eb 100644 --- a/arch/arm/include/asm/arch-hi6220/hi6220.h +++ b/arch/arm/include/asm/arch-hi6220/hi6220.h @@ -133,7 +133,6 @@ struct peri_sc_periph_regs { u32 reserved8_addr; /*0xd04*/ }; - /* CTRL1 bit definitions */ #define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) @@ -143,7 +142,6 @@ struct peri_sc_periph_regs { #define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) #define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) - /* CTRL2 bit definitions */ #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) diff --git a/arch/arm/include/asm/arch-hi6220/pinmux.h b/arch/arm/include/asm/arch-hi6220/pinmux.h index d18d2142f6a..7ee51000d69 100644 --- a/arch/arm/include/asm/arch-hi6220/pinmux.h +++ b/arch/arm/include/asm/arch-hi6220/pinmux.h @@ -9,7 +9,6 @@ #include "periph.h" - /* iomg bit definition */ #define MUX_M0 0 #define MUX_M1 1 diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 41160384a4d..b2d87524f70 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -8,7 +8,6 @@ #ifndef _LPC32XX_CONFIG_H #define _LPC32XX_CONFIG_H - /* Basic CPU architecture */ #if !defined(CFG_SYS_NS16550_CLK) diff --git a/arch/arm/include/asm/arch-meson/gpio.h b/arch/arm/include/asm/arch-meson/gpio.h index d0142f16ef1..9eb42211579 100644 --- a/arch/arm/include/asm/arch-meson/gpio.h +++ b/arch/arm/include/asm/arch-meson/gpio.h @@ -6,5 +6,4 @@ #ifndef __ASM_ARCH_MESON_GPIO_H #define __ASM_ARCH_MESON_GPIO_H - #endif /* __ASM_ARCH_MESON_GPIO_H */ diff --git a/arch/arm/include/asm/arch-mx27/gpio.h b/arch/arm/include/asm/arch-mx27/gpio.h index 9f342eb7f71..af05d1eb887 100644 --- a/arch/arm/include/asm/arch-mx27/gpio.h +++ b/arch/arm/include/asm/arch-mx27/gpio.h @@ -4,7 +4,6 @@ * Philippe Reynes <tremyfr@yahoo.fr> */ - #ifndef __ASM_ARCH_MX27_GPIO_H #define __ASM_ARCH_MX27_GPIO_H diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 77794d7d03d..60499189b2c 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -236,7 +236,6 @@ struct fuse_bank0_regs { #define SDCS1_SEL (1 << 1) #define SDCS0_SEL (1 << 0) - /* important definition of some bits of WCR */ #define WCR_WDE 0x04 diff --git a/arch/arm/include/asm/arch-mx31/gpio.h b/arch/arm/include/asm/arch-mx31/gpio.h index 45e9fc61937..1bfe28f95c9 100644 --- a/arch/arm/include/asm/arch-mx31/gpio.h +++ b/arch/arm/include/asm/arch-mx31/gpio.h @@ -4,7 +4,6 @@ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> */ - #ifndef __ASM_ARCH_MX31_GPIO_H #define __ASM_ARCH_MX31_GPIO_H diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index a0ab3a0e665..a608732f765 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -585,7 +585,6 @@ struct esdc_regs { #define GET_PLL_MFI(x) (((x) >> 10) & 0xf) #define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff) - #define WEIM_ESDCTL0 0xB8001000 #define WEIM_ESDCFG0 0xB8001004 #define WEIM_ESDCTL1 0xB8001008 @@ -777,7 +776,6 @@ struct esdc_regs { #define MUX_CTL_NFC_ALE 0xD6 #define MUX_CTL_NFC_CLE 0xD7 - #define MUX_CTL_CAPTURE 0x150 #define MUX_CTL_COMPARE 0x151 diff --git a/arch/arm/include/asm/arch-mx5/gpio.h b/arch/arm/include/asm/arch-mx5/gpio.h index dad40bd3d7e..98f9d63e9a8 100644 --- a/arch/arm/include/asm/arch-mx5/gpio.h +++ b/arch/arm/include/asm/arch-mx5/gpio.h @@ -4,7 +4,6 @@ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> */ - #ifndef __ASM_ARCH_MX5_GPIO_H #define __ASM_ARCH_MX5_GPIO_H diff --git a/arch/arm/include/asm/arch-mx6/gpio.h b/arch/arm/include/asm/arch-mx6/gpio.h index b3913199337..f5c8d336991 100644 --- a/arch/arm/include/asm/arch-mx6/gpio.h +++ b/arch/arm/include/asm/arch-mx6/gpio.h @@ -4,7 +4,6 @@ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> */ - #ifndef __ASM_ARCH_MX6_GPIO_H #define __ASM_ARCH_MX6_GPIO_H diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 8fd3dd2df3a..7f216c70e8b 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -385,7 +385,6 @@ ((is_mx6ull()) ? \ MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) - extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); #define SRC_SCR_CORE_1_RESET_OFFSET 14 diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index bfa68a9d2a0..bb2642d46c8 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -229,7 +229,6 @@ struct mxc_ccm_anatop_reg { #define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) #define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) - #define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f #define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B #define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 @@ -1784,7 +1783,6 @@ struct mxc_ccm_anatop_reg { #define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 #define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK) - /* HW_ANADIG_TEMPSENSE0 Bit Fields */ #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 @@ -1998,7 +1996,6 @@ struct mxc_ccm_anatop_reg { #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK) - #define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i)) #define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i)) #define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i)) @@ -2091,7 +2088,6 @@ struct mxc_ccm_anatop_reg { #define CLK_ROOT_ALT6 0x06000000 #define CLK_ROOT_ALT7 0x07000000 - #define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007 #define CLK_ROOT_POST_DIV_MASK 0x0000003f #define CLK_ROOT_POST_DIV_SHIFT 0 diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 6f5ae5173c0..849c5482241 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -71,7 +71,6 @@ #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) - /* Defines for Blocks connected via AIPS (SkyBlue) */ #define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR #define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR @@ -1162,7 +1161,6 @@ struct rdc_sema_regs { #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 - extern void check_cpu_temperature(void); extern void pcie_power_up(void); diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 33a699ff71a..02e434f2e65 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -124,7 +124,6 @@ #define IOMUXC_PSMI_IMUX_ALT6 (0x6) #define IOMUXC_PSMI_IMUX_ALT7 (0x7) - #define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8) #define SIM_SOPT1_PMIC_STBY_REQ (1<<2) #define SIM_SOPT1_A7_SW_RESET (1<<0) @@ -240,7 +239,6 @@ #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) #define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35))) - #define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0))) #define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1))) #define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2))) diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h b/arch/arm/include/asm/arch-mx7ulp/iomux.h index f067c02062f..3eec2c78e56 100644 --- a/arch/arm/include/asm/arch-mx7ulp/iomux.h +++ b/arch/arm/include/asm/arch-mx7ulp/iomux.h @@ -69,7 +69,6 @@ typedef u64 iomux_cfg_t; #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ MUX_PAD_CTRL(pad)) - #define IOMUX_CONFIG_MPORTS 0x20 #define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ MUX_MODE_SHIFT) @@ -87,7 +86,6 @@ typedef u64 iomux_cfg_t; #define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) #define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) - void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, unsigned count); diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h index 8f0d7006286..09b9b9b8f34 100644 --- a/arch/arm/include/asm/arch-mx7ulp/pcc.h +++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h @@ -278,7 +278,6 @@ enum pcc3_entry { RSVD127_PCC3_SLOT = 127, }; - /* PCC registers */ #define PCC_PR_OFFSET 31 #define PCC_PR_MASK (0x1 << PCC_PR_OFFSET) @@ -293,7 +292,6 @@ enum pcc3_entry { #define PCC_PCD_OFFSET 0 #define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET) - enum pcc_clksrc_type { CLKSRC_PER_PLAT = 0, CLKSRC_PER_BUS = 1, @@ -353,7 +351,6 @@ enum pcc_clk { PER_CLK_GPU2D, }; - /* This structure keeps info for each pcc slot */ struct pcc_entry { u32 pcc_base; diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h index 3b5b7f6803c..57e9fb2a27c 100644 --- a/arch/arm/include/asm/arch-mx7ulp/scg.h +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -145,7 +145,6 @@ #define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000) - #define SCG_PLL_PFD3_GATE_MASK (0x80000000) #define SCG_PLL_PFD2_GATE_MASK (0x00800000) #define SCG_PLL_PFD1_GATE_MASK (0x00008000) diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index fce3568eca1..2b6cfde4114 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -463,7 +463,6 @@ enum { #define NET_LAN9221_GPMC_CONFIG6 0x87030000 #define NET_LAN9221_GPMC_CONFIG7 0x00000f6c - /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h index 39a7cba0f6b..2e34989ef9f 100644 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -63,5 +63,4 @@ typedef struct t2 { #define OMAP_HSMMC2_BASE 0x480B4000 #define OMAP_HSMMC3_BASE 0x480AD000 - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index 4054dd8edcb..50436e828b0 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -100,7 +100,6 @@ #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - /* CM_<clock_domain>_<module>_CLKCTRL */ #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index b18ef459dec..eeb3c6f2a6c 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -111,7 +111,6 @@ #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - /* CM_<clock_domain>_<module>_CLKCTRL */ #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h index 1e44fb5ae97..efd816be2c6 100644 --- a/arch/arm/include/asm/arch-omap5/gpio.h +++ b/arch/arm/include/asm/arch-omap5/gpio.h @@ -33,7 +33,6 @@ #define OMAP54XX_GPIO7_BASE 0x48051000 #define OMAP54XX_GPIO8_BASE 0x48053000 - /* Get the GPIO index from the given bank number and bank gpio */ #define GPIO_TO_PIN(bank, bank_gpio) (32 * (bank - 1) + (bank_gpio)) diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h index 9559813e520..edacf102852 100644 --- a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h @@ -532,7 +532,6 @@ check_member(rk3288_edp, pll_reg_5, 0xa00); #define EDID_HEADER 0x00 #define EDID_EXTENSION_FLAG 0x7e - enum dpcd_request { DPCD_READ, DPCD_WRITE, diff --git a/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h index fb25504b12b..f4da391ba51 100644 --- a/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h @@ -96,5 +96,4 @@ #define LVDS_24BIT (0 << 1) #define LVDS_18BIT (1 << 1) - #endif diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 14df3cc8f46..35ca0491ac9 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -262,7 +262,6 @@ struct sunxi_ccm_reg { #define CCM_DRAM_GATE_OFFSET_DE_BE0 26 #define CCM_DRAM_GATE_OFFSET_DE_BE1 27 - #define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */ #define MBUS_CLK_GATE (0x1 << 31) @@ -295,7 +294,6 @@ struct sunxi_ccm_reg { #define APB2_RESET_TWI_SHIFT (0) #define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) - #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int hz); void clock_set_pll5(unsigned int clk); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 0264bfe1c50..006f7761fc6 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -217,7 +217,6 @@ struct sunxi_ccm_reg { #define APB1_RESET_TWI_SHIFT 0 #define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) - #ifndef __ASSEMBLY__ void clock_set_pll1(unsigned int clk); void clock_set_pll6(unsigned int clk); diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index be02655cdd5..f0caecc807d 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -323,7 +323,6 @@ struct dram_para { const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; }; - static inline int ns_to_t(int nanoseconds) { const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h index 2a879963547..28b6560ff5b 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h @@ -146,7 +146,6 @@ struct sunxi_mctl_ctl_reg { u32 perfwr1; /* 0x1d8 */ }; - #define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x) #define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x) #define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h index 41df5fe5b6f..a77daecb107 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h @@ -40,7 +40,6 @@ struct sunxi_mctl_com_reg { u32 mdfstcr; /* 0x14c */ }; - struct sunxi_mctl_ctl_reg { u32 mstr; /* 0x00 master register */ u32 stat; /* 0x04 operating mode status register */ @@ -92,7 +91,6 @@ struct sunxi_mctl_ctl_reg { u32 perfwr1; /* 0x26c write CAM register 1 */ }; - struct sunxi_mctl_phy_reg { u8 res0[0x04]; /* 0x00 revision id ??? */ u32 pir; /* 0x04 PHY initialisation register */ diff --git a/arch/arm/include/asm/arch-tegra/bpmp_abi.h b/arch/arm/include/asm/arch-tegra/bpmp_abi.h index 373da526ed6..924361bab8d 100644 --- a/arch/arm/include/asm/arch-tegra/bpmp_abi.h +++ b/arch/arm/include/asm/arch-tegra/bpmp_abi.h @@ -29,7 +29,6 @@ * @file */ - /** * @defgroup MRQ MRQ Messages * @brief Messages sent to/from BPMP via IPC @@ -167,7 +166,6 @@ struct mrq_response { * @} */ - /** * @ingroup MRQ_Codes * @def MRQ_PING @@ -616,7 +614,6 @@ struct mrq_debugfs_response { #define DEBUGFS_S_IWUSR (1 << 7) /** @} */ - /** * @ingroup MRQ_Codes * @def MRQ_RESET diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 61ef81e7fe4..2957b97e6a5 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -130,7 +130,6 @@ void reset_periph(enum periph_id periph_id, int us_delay); */ void reset_set_enable(enum periph_id periph_id, int enable); - /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ enum crc_reset_id { /* Things we can hold in reset for each CPU */ diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h index bfde4c30ac0..9a53456370f 100644 --- a/arch/arm/include/asm/arch-tegra/warmboot.h +++ b/arch/arm/include/asm/arch-tegra/warmboot.h @@ -117,7 +117,6 @@ union scratch3_reg { u32 word; }; - /** * Save warmboot memory settings for a later resume * diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h index 20cce7657e1..6a80be57506 100644 --- a/arch/arm/include/asm/byteorder.h +++ b/arch/arm/include/asm/byteorder.h @@ -15,7 +15,6 @@ #ifndef __ASM_ARM_BYTEORDER_H #define __ASM_ARM_BYTEORDER_H - #include <asm/types.h> #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 2141a4581c7..4a9e26f634d 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -880,7 +880,6 @@ struct dmm_lisa_map_regs { #define RL_FINAL 6 #endif - /* Interleaving policies at EMIF level- between banks and Chip Selects */ #define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 #define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 @@ -913,7 +912,6 @@ struct dmm_lisa_map_regs { */ #define READ_IDLE_INTERVAL_NORMAL (50*1000) - /* * Unless voltage is changing due to DVFS one ZQCS command every 50ms should * be enough. This shoule be enough also in the case when voltage is changing @@ -961,7 +959,6 @@ struct dmm_lisa_map_regs { #define REG_SR_TIM 0xF #define REG_PD_TIM 0xF - /* EMIF_PWR_MGMT_CTRL register */ #define EMIF_PWR_MGMT_CTRL (\ ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ diff --git a/arch/arm/include/asm/mach-imx/gpio.h b/arch/arm/include/asm/mach-imx/gpio.h index 25763526f5f..f7d751f4024 100644 --- a/arch/arm/include/asm/mach-imx/gpio.h +++ b/arch/arm/include/asm/mach-imx/gpio.h @@ -4,7 +4,6 @@ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de> */ - #ifndef __ASM_ARCH_IMX_GPIO_H #define __ASM_ARCH_IMX_GPIO_H diff --git a/arch/arm/include/asm/mach-imx/mxc_i2c.h b/arch/arm/include/asm/mach-imx/mxc_i2c.h index e8b330f33d1..cf694de4970 100644 --- a/arch/arm/include/asm/mach-imx/mxc_i2c.h +++ b/arch/arm/include/asm/mach-imx/mxc_i2c.h @@ -91,7 +91,6 @@ struct mxc_i2c_bus { } \ }; - #define I2C_PADS_INFO(name) \ (is_mx6dq() || is_mx6dqp()) ? &mx6q_##name : &mx6s_##name #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 17fdfbcffb7..9945eeb66b8 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -814,7 +814,6 @@ static inline u8 is_dra76x_acd(void) #define HS_DEVICE 0x2 #define GP_DEVICE 0x3 - /* * SRAM scratch space entries */ diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h index 21b33442989..bc2f9e70810 100644 --- a/arch/arm/include/asm/opcodes.h +++ b/arch/arm/include/asm/opcodes.h @@ -15,7 +15,6 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); #define ARM_OPCODE_CONDTEST_PASS 1 #define ARM_OPCODE_CONDTEST_UNCOND 2 - /* * Assembler opcode byteswap helpers. * These are only intended for use by this header: don't use them directly, @@ -42,7 +41,6 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); #define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) #define ___asm_opcode_identity16(x) ((x) & 0xFFFF) - /* * Opcode byteswap helpers * @@ -94,7 +92,6 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); #endif /* ! __ASSEMBLY__ */ - #ifdef CONFIG_CPU_ENDIAN_BE8 #define __opcode_to_mem_arm(x) ___opcode_swab32(x) diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index e0e2d7e3606..b8ca50a6401 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -75,7 +75,6 @@ struct param_struct { char commandline[COMMAND_LINE_SIZE]; }; - /* * The new way of passing information: a list of tagged entries */ diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h index f51e47e55d5..6ca2c4ae6ff 100644 --- a/arch/arm/mach-at91/include/mach/at91_pio.h +++ b/arch/arm/mach-at91/include/mach/at91_pio.h @@ -13,7 +13,6 @@ #ifndef AT91_PIO_H #define AT91_PIO_H - #define AT91_ASM_PIO_RANGE 0x200 #define AT91_ASM_PIOC_ASR \ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h index 40ec87e2ff9..6beab397ae1 100644 --- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h @@ -59,7 +59,6 @@ struct atmel_mpddr { u32 version; /* 0xfc: IP version */ }; - int ddr2_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value); diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index ac6a719d9c0..acd7cc9301b 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -35,7 +35,6 @@ static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr) return 1; } - int ddr2_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value) diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 936b5e11667..78d50d4e719 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -146,7 +146,6 @@ static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult) */ setbits_le32(®->pllctl, PLLCTL_PLLEN); - /* * clear EMIFA and EMIFB clock source settings, let them * run off SYSCLK diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h index 4f56160ee50..a3fc7d9fbeb 100644 --- a/arch/arm/mach-exynos/common_setup.h +++ b/arch/arm/mach-exynos/common_setup.h @@ -61,7 +61,6 @@ enum l2_cache_params { CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27) }; - #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420) /* * Configure L2CTLR to get timings that keep us from hanging/crashing. diff --git a/arch/arm/mach-exynos/exynos4_setup.h b/arch/arm/mach-exynos/exynos4_setup.h index 23c9011fbc6..1a287a4ef6a 100644 --- a/arch/arm/mach-exynos/exynos4_setup.h +++ b/arch/arm/mach-exynos/exynos4_setup.h @@ -284,7 +284,6 @@ #define MFC_0_SEL MFC_SEL_MPLL #define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL)) - /* CLK_DIV_MFC */ #define MFC_RATIO 3 #define CLK_DIV_MFC_VAL (MFC_RATIO) @@ -498,7 +497,6 @@ struct mem_timings { | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\ | NUM_CHIP_2 | BL_8) - #define CHIP_BANK_8 (0x3 << 0) #define CHIP_ROW_14 (0x2 << 4) #define CHIP_COL_10 (0x3 << 8) diff --git a/arch/arm/mach-exynos/exynos5_setup.h b/arch/arm/mach-exynos/exynos5_setup.h index 4e508edba0c..6fa80221c8d 100644 --- a/arch/arm/mach-exynos/exynos5_setup.h +++ b/arch/arm/mach-exynos/exynos5_setup.h @@ -685,7 +685,6 @@ #define PWM_RATIO 8 #define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0) - /* CLK_DIV_PERIC4 */ #define CLK_DIV_PERIC4_VAL NOT_AVAILABLE @@ -710,7 +709,6 @@ /* MPLL_CON1 */ #define MPLL_CON1_VAL (0x0020F300) - /* CPLL_CON1 */ #define CPLL_CON1_VAL 0x0020f300 @@ -720,7 +718,6 @@ /* GPLL_CON1 */ #define GPLL_CON1_VAL (NOT_AVAILABLE) - /* EPLL_CON1, CON2 */ #define EPLL_CON1_VAL 0x00000000 #define EPLL_CON2_VAL 0x00000080 @@ -750,7 +747,6 @@ #define CLK_DIV_ISP0_VAL 0x13131300 #define CLK_DIV_ISP1_VAL 0xbb110202 - /* CLK_FSYS */ #define CLK_SRC_FSYS0_VAL 0x33033300 #define CLK_DIV_FSYS0_VAL 0x0 diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h index dab148e3320..cf4580be189 100644 --- a/arch/arm/mach-exynos/include/mach/cpu.h +++ b/arch/arm/mach-exynos/include/mach/cpu.h @@ -190,7 +190,6 @@ #define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE - #ifndef __ASSEMBLY__ #include <asm/io.h> /* CPU detection macros */ diff --git a/arch/arm/mach-exynos/include/mach/dp_info.h b/arch/arm/mach-exynos/include/mach/dp_info.h index 3226eb95f01..a7f7667afd6 100644 --- a/arch/arm/mach-exynos/include/mach/dp_info.h +++ b/arch/arm/mach-exynos/include/mach/dp_info.h @@ -183,7 +183,6 @@ enum { VIDEO_TIMING_FROM_REGISTER }; - struct exynos_dp_platform_data { struct exynos_dp_priv *edp_dev_info; }; diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h index 757e1586bde..32534116cf8 100644 --- a/arch/arm/mach-exynos/include/mach/power.h +++ b/arch/arm/mach-exynos/include/mach/power.h @@ -1752,7 +1752,6 @@ void set_xclkout(void); */ uint32_t get_reset_status(void); - /* Read the resume function and call it */ void power_exit_wakeup(void); diff --git a/arch/arm/mach-exynos/include/mach/sound.h b/arch/arm/mach-exynos/include/mach/sound.h index 1a40e35f0b5..9672e977f07 100644 --- a/arch/arm/mach-exynos/include/mach/sound.h +++ b/arch/arm/mach-exynos/include/mach/sound.h @@ -4,7 +4,6 @@ * Rajeshwari Shinde <rajeshwari.s@samsung.com> */ - #ifndef __SOUND_ARCH_H__ #define __SOUND_ARCH_H__ diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 4061dd4aafa..07d19fd17ba 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -391,7 +391,6 @@ static void exynos5420_i2s_config(int peripheral) } } - void exynos5_spi_config(int peripheral) { int cfg = 0, pin = 0, i; diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c index 599d3ccff60..1b61da6dc1a 100644 --- a/arch/arm/mach-exynos/power.c +++ b/arch/arm/mach-exynos/power.c @@ -20,7 +20,6 @@ static void exynos4_mipi_phy_control(unsigned int dev_index, else addr = (unsigned int)&pmu->mipi_phy1_control; - cfg = readl(addr); if (enable) cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE); @@ -174,7 +173,6 @@ void set_ps_hold_ctrl(void) exynos5_set_ps_hold_ctrl(); } - static void exynos5_set_xclkout(void) { struct exynos5_power *power = diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index b368db49fce..7b3eacb43ed 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -86,7 +86,6 @@ void v7_outer_cache_enable(void) struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; unsigned int val, cache_id; - /* * Must disable the L2 before changing the latency parameters * and auxiliary control register. diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 627baa1d83f..accba502e49 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -519,7 +519,6 @@ phys_size_t get_effective_memsize(void) board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, &phys_sdram_2_start, &phys_sdram_2_size); - end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); @@ -699,7 +698,6 @@ static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end) board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size, &phys_sdram_2_start, &phys_sdram_2_size); - end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 7e6c3748716..43e677deae2 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -733,7 +733,6 @@ static int frac_pll_init(u32 pll, enum frac_pll_out_val val) return 0; } - int clock_init(void) { u32 grade; diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index ab5de266577..03e1214c060 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -83,7 +83,6 @@ int litesom_mmc_init(struct bd_info *bis) #include <spl.h> #include <asm/arch/mx6-ddr.h> - static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { .grp_addds = 0x00000030, .grp_ddrmode_ctl = 0x00020000, diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index d4fb5389cac..59da7300dd6 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -428,7 +428,6 @@ static u32 scg_nic_get_rate(enum scg_clk clk) return rate; } - static enum scg_clk scg_scs_array[4] = { SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK, }; @@ -807,7 +806,6 @@ int scg_enable_usb_pll(bool usb_control) return 0; } - /* A7 domain system clock source is SPLL */ #define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT) diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index f164f95bf24..e5d70d2931e 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -26,7 +26,6 @@ #define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) #define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) - static inline u32 _boot_bit_mask(u32 x, u32 y) { u32 val = (1 << (x - y + 1)) - 1; diff --git a/arch/arm/mach-keystone/msmc.c b/arch/arm/mach-keystone/msmc.c index a20e0c98865..51c994f972f 100644 --- a/arch/arm/mach-keystone/msmc.c +++ b/arch/arm/mach-keystone/msmc.c @@ -53,7 +53,6 @@ struct msms_regs { struct mpax ses[16][8]; }; - void msmc_share_all_segments(int priv_id) { struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 7938820e513..3d224e20364 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -48,7 +48,6 @@ void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save) } debug("\n"); - while (*mpp_list) { unsigned int num = MPP_NUM(*mpp_list); unsigned int sel = MPP_SEL(*mpp_list); diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index 9baeece3c85..c13416add1d 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -276,7 +276,6 @@ static int mvebu_mbus_alloc_window(phys_addr_t base, size_t size, target, attr); } - for (win = 0; win < MVEBU_MBUS_NUM_WINS; win++) if (mvebu_mbus_window_is_free(win)) return mvebu_mbus_setup_window(win, base, size, diff --git a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h index 9c3e7c08204..625c2a5dd71 100644 --- a/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h +++ b/arch/arm/mach-mvebu/serdes/axp/board_env_spec.h @@ -76,7 +76,6 @@ #define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) - #define CORE_AVS_CONTROL_0REG 0x18300 #define CORE_AVS_CONTROL_2REG 0x18308 #define CPU_AVS_CONTROL2_REG 0x20868 @@ -86,7 +85,6 @@ #define MSAR_TCLK_OFFS 28 #define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS) - /* Controler environment registers offsets */ #define GEN_PURP_RES_1_REG 0x182F4 #define GEN_PURP_RES_2_REG 0x182F8 @@ -146,7 +144,6 @@ 0x40000 + ((port) % 2) * 0x4000) #define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port) - #define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04) #define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C) #define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18) @@ -182,7 +179,6 @@ #define SCR_PEX1_4BY1_OFFS 8 #define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS) - #define MV_MISC_REGS_OFFSET (0x18200) #define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET) #define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4) @@ -226,7 +222,6 @@ #define PXCAR_REAL_EXT_REG_NUM_OFFS 8 #define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) - #define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60) #define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C) #define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70) diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h index b920f5ef090..a29d06cf3c2 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h @@ -21,7 +21,6 @@ typedef enum { SERDES_LAST_UNIT } MV_BIN_SERDES_UNIT_INDX; - typedef enum { PEX_BUS_DISABLED = 0, PEX_BUS_MODE_X1 = 1, @@ -63,7 +62,6 @@ typedef struct board_serdes_conf { MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change; } MV_BIN_SERDES_CFG; - #define BIN_SERDES_CFG { \ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \ {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \ diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c index 4765ce0adee..515b6f1b87c 100644 --- a/arch/arm/mach-omap2/am33xx/chilisom.c +++ b/arch/arm/mach-omap2/am33xx/chilisom.c @@ -102,7 +102,6 @@ void chilisom_spl_board_init(void) /* Get the frequency */ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); - if (i2c_probe(TPS65217_CHIP_PM)) return; diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c index f07003c95bc..cc955345db9 100644 --- a/arch/arm/mach-omap2/am33xx/clock.c +++ b/arch/arm/mach-omap2/am33xx/clock.c @@ -213,7 +213,6 @@ void do_disable_clocks(u32 *const *clk_domains, { u32 i, max = 100; - /* Clock modules that need to be put in SW_DISABLE */ for (i = 0; (i < max) && clk_modules_disable && clk_modules_disable[i]; i++) diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c index 87afc096602..7ac67cb4899 100644 --- a/arch/arm/mach-omap2/am33xx/sys_info.c +++ b/arch/arm/mach-omap2/am33xx/sys_info.c @@ -74,7 +74,6 @@ u32 get_sys_clk_index(void) CTRL_SYSBOOT_15_14_SHIFT); } - #ifdef CONFIG_DISPLAY_CPUINFO static char *cpu_revs[] = { "1.0", diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 2a0c22841d0..18d099145c5 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -896,7 +896,6 @@ void do_disable_clocks(u32 const *clk_domains, { u32 i, max = 100; - /* Clock modules that need to be put in SW_DISABLE */ for (i = 0; (i < max) && clk_modules_disable[i]; i++) disable_clock_module(clk_modules_disable[i], diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 138501602c3..bb67e50fd56 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -268,7 +268,6 @@ void watchdog_init(void) writel(WD_UNLOCK2, &wd2_base->wspr); } - /* * This function finds the SDRAM size available in the system * based on DMM section configurations @@ -315,7 +314,6 @@ u32 omap_sdram_size(void) return total_size; } - /* * Routine: dram_init * Description: sets uboots idea of sdram size diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index c5ada607f97..1de343ff48e 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -405,7 +405,6 @@ void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); } - #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { diff --git a/arch/arm/mach-renesas/include/mach/rcar-base.h b/arch/arm/mach-renesas/include/mach/rcar-base.h index 4c2ee8187e0..a0f1c7762a0 100644 --- a/arch/arm/mach-renesas/include/mach/rcar-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-base.h @@ -328,7 +328,6 @@ #define MEDIA_AXI_VSP0W_BASE 0xFE966D00 #endif /* R8A7792 */ - #define SYS_AXI_AVBDMSCR 0xFF802000 #define SYS_AXI_SYX2DMSCR 0xFF802004 #define SYS_AXI_AX2MDMSCR 0xFF802004 diff --git a/arch/arm/mach-s5pc1xx/include/mach/cpu.h b/arch/arm/mach-s5pc1xx/include/mach/cpu.h index 78c905b866b..4b1b7118268 100644 --- a/arch/arm/mach-s5pc1xx/include/mach/cpu.h +++ b/arch/arm/mach-s5pc1xx/include/mach/cpu.h @@ -45,7 +45,6 @@ #define S5PC110_PHY_BASE 0xEC100000 #define S5PC110_USB_PHY_CONTROL 0xE010E80C - #ifndef __ASSEMBLY__ #include <asm/io.h> /* CPU detection macros */ diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c index 154ad2154ae..0a2c84c9e13 100644 --- a/arch/arm/mach-socfpga/clock_manager_gen5.c +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c @@ -125,7 +125,6 @@ int cm_basic_init(const struct cm_config * const cfg) readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO); readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO); - /* * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 7c86350d5ea..c8530c98043 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 Altera Corporation <www.altera.com> */ - #include <config.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index 7f10296dc74..18921169a6d 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -106,7 +106,6 @@ void cm_basic_init(const struct cm_config * const cfg); #define CLKMGR_INTER CLKMGR_S10_INTER #define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN - #define CLKMGR_CTRL_SAFEMODE BIT(0) #define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007 #define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index ad1ef0db186..a6cc78454da 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -39,7 +39,6 @@ static Altera_desc altera_fpga[] = { }, }; - /* * Print CPU information */ diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 9395122dae1..6a202bf227c 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -3,7 +3,6 @@ * Copyright (C) 2013 Altera Corporation <www.altera.com> */ - #include <mach/base_addr_ac5.h> #include <asm/io.h> #include <asm/arch/fpga_manager.h> diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 967fa4e06c0..04640e476e6 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -187,7 +187,6 @@ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog, " <size> = size of flashlayout (optional for image with STM32 header)\n" ); - bool stm32prog_get_fsbl_nor(void) { if (stm32prog_data) diff --git a/arch/arm/mach-sunxi/clock_sun8i_a83t.c b/arch/arm/mach-sunxi/clock_sun8i_a83t.c index 9eeba084f95..c00d16a918d 100644 --- a/arch/arm/mach-sunxi/clock_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/clock_sun8i_a83t.c @@ -118,7 +118,6 @@ void clock_set_pll5(unsigned int clk) udelay(5500); } - unsigned int clock_get_pll6(void) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/mach-sunxi/clock_sun9i.c b/arch/arm/mach-sunxi/clock_sun9i.c index 5913e40cb65..abdab405445 100644 --- a/arch/arm/mach-sunxi/clock_sun9i.c +++ b/arch/arm/mach-sunxi/clock_sun9i.c @@ -14,7 +14,6 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h> - #ifdef CONFIG_SPL_BUILD static void clock_set_pll2(unsigned int clk) @@ -166,7 +165,6 @@ void clock_set_pll6(unsigned int clk) sdelay(2000); } - int clock_twi_onoff(int port, int state) { struct sunxi_ccm_reg *const ccm = diff --git a/arch/arm/mach-sunxi/dram_sun8i_a83t.c b/arch/arm/mach-sunxi/dram_sun8i_a83t.c index ef833321e37..dd0fc37b763 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a83t.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a83t.c @@ -284,7 +284,6 @@ static int mctl_channel_init(struct dram_para *para) writel(0x0, MCTL_PROTECT); udelay(100); - /* Set ODT */ if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) rval = 0x0; diff --git a/arch/arm/mach-sunxi/dram_sun9i.c b/arch/arm/mach-sunxi/dram_sun9i.c index 002b6df39d5..58ecbb98356 100644 --- a/arch/arm/mach-sunxi/dram_sun9i.c +++ b/arch/arm/mach-sunxi/dram_sun9i.c @@ -262,7 +262,6 @@ static void mctl_sys_init(void) reg_val |= ((0x1<<24)|(0x1<<30)); mctl_write_w(CCM_PLL6_DDR_REG, reg_val); - while(mctl_read_w(CCM_PLL6_DDR_REG) & (0x1<<30)); } diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index e064ef329e6..4ed295909ce 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -650,7 +650,6 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) return 0; } - static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para *para, ulong base, struct rank_para *rank) { /* detect row address bits */ diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index 4a3f6b97adc..c5c84c61690 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -19,7 +19,6 @@ extern int test_and_change_bit(int nr, volatile void *addr); #ifdef __KERNEL__ - static inline int test_bit(int nr, __const__ volatile void *addr) { __const__ unsigned int *p = (__const__ unsigned int *) addr; diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index aa8d2edb40b..712b02cd89b 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -136,7 +136,6 @@ #define CF_ACR_SP (1 << 3) #endif /* CONFIG_CF_V4 */ - #ifndef CFG_SYS_CACHE_ICACR #define CFG_SYS_CACHE_ICACR 0 #endif diff --git a/arch/m68k/include/asm/immap_5271.h b/arch/m68k/include/asm/immap_5271.h index a5bf18c4b84..5b7db9e027b 100644 --- a/arch/m68k/include/asm/immap_5271.h +++ b/arch/m68k/include/asm/immap_5271.h @@ -54,5 +54,4 @@ #include <asm/coldfire/rng.h> #include <asm/coldfire/skha.h> - #endif /* __IMMAP_5271__ */ diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h index c4cce3f94f1..e90c870c91d 100644 --- a/arch/m68k/include/asm/immap_5275.h +++ b/arch/m68k/include/asm/immap_5275.h @@ -223,7 +223,6 @@ typedef struct gpio_ctrl { u8 par_res2[3]; } gpio_t; - /* Watchdog registers */ typedef struct wdog_ctrl { diff --git a/arch/m68k/include/asm/m5441x.h b/arch/m68k/include/asm/m5441x.h index f2e7e7fff4a..2c9f13030ff 100644 --- a/arch/m68k/include/asm/m5441x.h +++ b/arch/m68k/include/asm/m5441x.h @@ -700,7 +700,6 @@ #define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */ #define GPIO_PAR_FEC_FEC_MIIFUL (0x00) - /* TC: Need to edit here.... */ /* Mode Select Control */ diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c index e09f36f2fdd..dafd8a9a635 100644 --- a/arch/m68k/lib/traps.c +++ b/arch/m68k/lib/traps.c @@ -15,7 +15,6 @@ #include <asm/processor.h> #include <asm/ptrace.h> - extern void _exc_handler(void); extern void _int_handler(void); diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h index 2cab2ac62b9..9ea217cd854 100644 --- a/arch/microblaze/include/asm/bitops.h +++ b/arch/microblaze/include/asm/bitops.h @@ -32,7 +32,6 @@ static inline unsigned long ffz(unsigned long word) return result; } - static inline void set_bit(int nr, volatile void *addr) { int * a = (int *) addr; @@ -257,7 +256,6 @@ found_middle: #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) - static inline int ext2_set_bit(int nr, volatile void *addr) { int mask, retval; diff --git a/arch/microblaze/include/asm/posix_types.h b/arch/microblaze/include/asm/posix_types.h index ccc6235c8d9..f4795f8d317 100644 --- a/arch/microblaze/include/asm/posix_types.h +++ b/arch/microblaze/include/asm/posix_types.h @@ -47,7 +47,6 @@ typedef unsigned int __kernel_gid32_t; typedef unsigned short __kernel_old_uid_t; typedef unsigned short __kernel_old_gid_t; - typedef struct { #if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; @@ -56,7 +55,6 @@ typedef struct { #endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; - #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) #undef __FD_SET diff --git a/arch/microblaze/include/asm/ptrace.h b/arch/microblaze/include/asm/ptrace.h index b796d4faf6b..ff861d10bb4 100644 --- a/arch/microblaze/include/asm/ptrace.h +++ b/arch/microblaze/include/asm/ptrace.h @@ -16,7 +16,6 @@ #ifndef __MICROBLAZE_PTRACE_H__ #define __MICROBLAZE_PTRACE_H__ - /* Microblaze general purpose registers with special meanings. */ #define GPR_ZERO 0 /* constant zero */ #define GPR_ASM 18 /* reserved for assembler */ @@ -54,7 +53,6 @@ #define SR_DIR 21 #define SR_ASID 23 - #ifndef __ASSEMBLY__ typedef unsigned long microblaze_reg_t; @@ -74,7 +72,6 @@ struct pt_regs microblaze_reg_t single_step; /* 1 if in single step mode */ }; - #define instruction_pointer(regs) ((regs)->pc) #define user_mode(regs) (!(regs)->kernel_mode) @@ -87,7 +84,6 @@ struct pt_regs #endif /* !__ASSEMBLY__ */ - /* The number of bytes used to store each register. */ #define _PT_REG_SIZE 4 diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h index 050a8b40763..4e31206436d 100644 --- a/arch/microblaze/include/asm/system.h +++ b/arch/microblaze/include/asm/system.h @@ -40,7 +40,6 @@ extern void *switch_thread (struct thread_struct *last, } \ } while (0) - /* Enable/disable interrupts. */ #define __sti() \ { \ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 3774acaadc3..4acc439ccfb 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -485,7 +485,6 @@ BUILDSTRING(q, u64) #define outsq outsq #endif - #ifdef CONFIG_CPU_CAVIUM_OCTEON #define mmiowb() wmb() #else diff --git a/arch/mips/include/asm/isa-rev.h b/arch/mips/include/asm/isa-rev.h index 683ea3454dc..8afa6aefc54 100644 --- a/arch/mips/include/asm/isa-rev.h +++ b/arch/mips/include/asm/isa-rev.h @@ -20,5 +20,4 @@ #define MIPS_ISA_REV 0 #endif - #endif /* __MIPS_ASM_ISA_REV_H__ */ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 3db3965fcff..d02b1e50bdf 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -125,7 +125,6 @@ */ #define CP0_TX39_CACHE $7 - /* Generic EntryLo bit definitions */ #define ENTRYLO_G (_ULCAST_(1) << 0) #define ENTRYLO_V (_ULCAST_(1) << 1) @@ -987,7 +986,6 @@ #define CP1_FENR $28 #define CP1_STATUS $31 - /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ @@ -1102,7 +1100,6 @@ #define FPU_CSR_RU 0x2 /* towards +Infinity */ #define FPU_CSR_RD 0x3 /* towards -Infinity */ - #ifndef __ASSEMBLY__ /* @@ -1261,7 +1258,6 @@ static inline void tlbinvf(void) ".set pop"); } - /* * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit @@ -1307,7 +1303,6 @@ do { \ : "r" (val), "i" (counter)); \ } while (0) - /* * Macros to access the system control coprocessor */ @@ -2403,7 +2398,6 @@ do { \ mfhi3; \ }) - #define mtlo0(x) \ ({ \ __asm__( \ diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 481d2ef6c2f..2dacdbbcdbe 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -7,7 +7,6 @@ #ifndef _ASM_PGTABLE_BITS_H #define _ASM_PGTABLE_BITS_H - /* * Note that we shift the lower 32bits of each EntryLo[01] entry * 6 bits to the left. That way we can convert the PFN into the @@ -189,7 +188,6 @@ * 32-bit, R2 or later: CCC D V G RI/R XI M A W P */ - #ifndef __ASSEMBLY__ /* * pte_to_entrylo converts a page table entry (PTE) into a Mips diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c index 379085f1ff7..e9a80c6f12f 100644 --- a/arch/mips/mach-ath79/qca953x/clk.c +++ b/arch/mips/mach-ath79/qca953x/clk.c @@ -61,7 +61,6 @@ int get_clocks(void) & QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1; gd->cpu_clk = pll / div; - val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG); /* VCOOUT = XTAL * DIV_INT */ div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) diff --git a/arch/mips/mach-octeon/include/mangle-port.h b/arch/mips/mach-octeon/include/mangle-port.h index 7e95dcef5af..554bdc55cf2 100644 --- a/arch/mips/mach-octeon/include/mangle-port.h +++ b/arch/mips/mach-octeon/include/mangle-port.h @@ -43,7 +43,6 @@ static inline bool __should_swizzle_addr(u64 p) #endif /* __BIG_ENDIAN */ - # define ioswabb(a, x) (x) # define __mem_ioswabb(a, x) (x) # define ioswabw(a, x) (__should_swizzle_bits(a) ? le16_to_cpu(x) : x) diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index 27093c4faa3..c98d40a49b5 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -98,7 +98,6 @@ void irq_install_handler(int irq, interrupt_handler_t *hdlr, void *arg) if (flag) enable_interrupts(); } - int interrupt_init(void) { int i; @@ -114,7 +113,6 @@ int interrupt_init(void) return (0); } - /*************************************************************************/ #if defined(CONFIG_CMD_IRQ) int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/arch/nios2/include/asm/bitops/atomic.h b/arch/nios2/include/asm/bitops/atomic.h index c8946465e63..0130fd47d39 100644 --- a/arch/nios2/include/asm/bitops/atomic.h +++ b/arch/nios2/include/asm/bitops/atomic.h @@ -31,7 +31,6 @@ extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; local_irq_restore(f); \ } while(0) - #else # define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) # define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) diff --git a/arch/nios2/include/asm/ptrace.h b/arch/nios2/include/asm/ptrace.h index 317d8ae09b4..b1feb338886 100644 --- a/arch/nios2/include/asm/ptrace.h +++ b/arch/nios2/include/asm/ptrace.h @@ -12,5 +12,4 @@ struct pt_regs { unsigned status; }; - #endif /* __ASM_NIOS2_PTRACE_H_ */ diff --git a/arch/nios2/lib/libgcc.c b/arch/nios2/lib/libgcc.c index a45b3e82efc..30b846179c0 100644 --- a/arch/nios2/lib/libgcc.c +++ b/arch/nios2/lib/libgcc.c @@ -16,7 +16,6 @@ typedef unsigned long long DSItype; #include "longlong.h" - typedef int word_type; typedef long Wtype; typedef long long DWtype; @@ -46,7 +45,6 @@ const UQItype __clz_tab[256] = 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8 }; - DWtype __ashldi3 (DWtype u, word_type b) { @@ -388,7 +386,6 @@ __negdi2 (DWtype u) return w.ll; } - DWtype __muldi3 (DWtype u, DWtype v) { @@ -440,7 +437,6 @@ __ucmpdi2 (DWtype a, DWtype b) return 1; } - UDWtype __udivdi3 (UDWtype n, UDWtype d) { @@ -507,14 +503,12 @@ __divsi3 (SItype a, SItype b) return res; } - SItype __udivsi3 (SItype a, SItype b) { return udivmodsi4 (a, b, 0); } - SItype __modsi3 (SItype a, SItype b) { diff --git a/arch/powerpc/cpu/mpc83xx/interrupts.c b/arch/powerpc/cpu/mpc83xx/interrupts.c index d86c981811e..af517213f17 100644 --- a/arch/powerpc/cpu/mpc83xx/interrupts.c +++ b/arch/powerpc/cpu/mpc83xx/interrupts.c @@ -32,7 +32,6 @@ void interrupt_init_cpu (unsigned *decrementer_count) immr->sysconf.spcr |= 0x00400000; } - /* * Handle external interrupts */ @@ -41,7 +40,6 @@ void external_interrupt(struct pt_regs *regs) { } - /* * Install and free an interrupt handler. */ @@ -51,19 +49,16 @@ irq_install_handler(int irq, interrupt_handler_t * handler, void *arg) { } - void irq_free_handler(int irq) { } - void timer_interrupt_cpu (struct pt_regs *regs) { /* nothing to do here */ return; } - #if defined(CONFIG_CMD_IRQ) /* ripped this out of ppc4xx/interrupts.c */ diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c index 79ea1a9bb3c..d50499ceb7c 100644 --- a/arch/powerpc/cpu/mpc83xx/traps.c +++ b/arch/powerpc/cpu/mpc83xx/traps.c @@ -74,7 +74,6 @@ void show_regs(struct pt_regs *regs) } } - static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); @@ -191,7 +190,6 @@ void SoftEmuException(struct pt_regs *regs) panic("Software Emulation Exception"); } - void UnknownException(struct pt_regs *regs) { #if defined(CONFIG_CMD_KGDB) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index ebce2fe3935..ab4ef154729 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -297,7 +297,6 @@ int checkcpu (void) return 0; } - /* ------------------------------------------------------------------------- */ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -337,7 +336,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return 1; } - /* * Get timebase clock frequency */ @@ -348,7 +346,6 @@ __weak unsigned long get_tbclk(void) return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; } - /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b770d294e61..a7b805bc674 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -128,7 +128,6 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) } #endif - #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index c56e98d4b49..b2c0c517e7a 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -428,7 +428,6 @@ static inline void ft_fixup_cache(void *blob) ft_fixup_l2cache(blob); } - void fdt_add_enet_stashing(void *fdt) { do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1); diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 78316ea5ffe..f2f854ebc12 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -482,7 +482,6 @@ static void wait_for_rstdone(unsigned int bank) printf("SERDES: timeout resetting bank %u\n", bank + 1); } - static void __soc_serdes_init(void) { /* Allow for SoC-specific initialization in <SOC>_serdes.c */ diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index b638f24ed14..03f801ebbb7 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -191,7 +191,6 @@ u32 determine_mp_bootpg(unsigned int *pagesize) struct law_entry e; #endif - /* use last 4K of mapped memory */ bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ? CFG_MAX_MEM_MAPPED : gd->ram_size) + diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c index d38041ef5c2..c1190667cef 100644 --- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -29,7 +29,6 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { [0x03] = {PCIE1, PCIE2}, }; - int is_serdes_configured(enum srds_prtcl device) { int ret; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index a7e1b3c98a9..d17a19026dd 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -625,7 +625,6 @@ int get_clocks(void) else return (1); } - /******************************************** * get_bus_freq * return system bus freq in Hz diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c index 0d958fe131b..ff76bed1af2 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c @@ -7,7 +7,6 @@ #include <asm/processor.h> #include <asm/io.h> - static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { [0x40] = {PCIE1, PCIE1, PCIE1, PCIE1}, [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1}, diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c index 2033ebbaa5e..fb59a3e4136 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c @@ -9,7 +9,6 @@ #include <asm/io.h> #include <asm/ppc.h> - static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index e0b36f869a9..32b68a169a4 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -354,5 +354,4 @@ void clear_ddr_tlbs(unsigned int memsize_in_meg) clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } - #endif /* not SPL */ diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index db70f07500c..a1c111ec171 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -111,7 +111,6 @@ void show_regs(struct pt_regs *regs) } } - static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); diff --git a/arch/powerpc/cpu/mpc8xx/immap.c b/arch/powerpc/cpu/mpc8xx/immap.c index 8c85fc180b9..09aaebc5c47 100644 --- a/arch/powerpc/cpu/mpc8xx/immap.c +++ b/arch/powerpc/cpu/mpc8xx/immap.c @@ -206,7 +206,6 @@ static int do_iopset(struct cmd_tbl *cmdtp, int flag, int argc, if (pin > 31) rcode = 1; - switch (argv[3][0]) { case 'd': if (argv[3][1] == 'a') diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c index 5220c560e5f..22f2f5878e3 100644 --- a/arch/powerpc/cpu/mpc8xx/traps.c +++ b/arch/powerpc/cpu/mpc8xx/traps.c @@ -75,7 +75,6 @@ void show_regs(struct pt_regs *regs) } } - static void _exception(int signr, struct pt_regs *regs) { show_regs(regs); @@ -142,7 +141,6 @@ void SoftEmuException(struct pt_regs *regs) panic("Software Emulation Exception"); } - void UnknownException(struct pt_regs *regs) { printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 82f28749eb1..d64eb7328fe 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -300,7 +300,6 @@ __weak int cpu_numcores(void) return cpu->num_cores; } - /* * Check if the given core ID is valid * diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 843dd191ccf..9b7a07958ec 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -20,7 +20,6 @@ static void __lbc_sdram_init(void) void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init"))); #endif - void print_lbc_regs(void) { int i; diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 29399bcd8b6..3a82e60a247 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -26,7 +26,6 @@ static inline int __ilog2_roundup_64(uint64_t val) return __ilog2_u64(val) + 1; } - static inline int count_lsb_zeroes(unsigned long val) { return ffs(val) - 1; @@ -332,7 +331,6 @@ void pamu_disable(void) u32 i = 0; u32 base_addr = CFG_SYS_PAMU_ADDR; - for (i = 0; i < CFG_NUM_PAMU; i++) { clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); sync(); @@ -340,7 +338,6 @@ void pamu_disable(void) } } - static uint64_t find_max(uint64_t arr[], int num) { int i = 0; diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index f3a9749625c..b4695cc99cb 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -31,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; #define LAWBAR_SHIFT 12 #endif - static inline phys_addr_t get_law_base_addr(int idx) { #ifdef CONFIG_FSL_CORENET diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index 96491b6e4ec..b22eebaa0ae 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -270,7 +270,6 @@ found_middle: return result + ffz(tmp); } - #define _EXT2_HAVE_ASM_BITOPS_ #ifdef __KERNEL__ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d990ecff96f..819250f0090 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -82,7 +82,6 @@ #define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 - #elif defined(CONFIG_ARCH_T4240) #ifdef CONFIG_ARCH_T4240 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } @@ -168,7 +167,6 @@ #define CFG_SYS_FM_MURAM_SIZE 0x28000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE - #elif defined(CONFIG_ARCH_C29X) #define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000 diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 809ab1d4187..6c6e436b6ee 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -269,5 +269,4 @@ int fsl_pcie_init_board(int busno); #error FT_FSL_PCI_SETUP not defined #endif - #endif diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 2412bb9d7c1..9a59ed8c5a0 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -92,7 +92,6 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); #define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - #define IO_SPACE_LIMIT ~0 #define memset_io(a,b,c) memset((void __force *)(a),(b),(c)) diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index b0aafdcdae1..bc7716b7079 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -126,7 +126,6 @@ typedef struct _pte { #define PT_MASK 0x02FF #define PG_SHIFT (12) /* Page Entry */ - /* MMU context */ typedef struct _MMU_context { @@ -304,7 +303,6 @@ extern void print_bats(void); #define M_CASID 793 /* Address space ID (context) to match */ #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ - /* These are the Ks and Kp from the PowerPC books. For proper operation, * Ks = 0, Kp = 1. */ @@ -349,7 +347,6 @@ extern void print_bats(void); #define MD_SVALID 0x00000001 /* Segment entry is valid */ /* Reset value is undefined */ - /* Real page number. Defined by the pte. Writing this register * causes a TLB entry to be created for the data TLB, using * additional information from the MD_EPN, and MD_TWC registers. diff --git a/arch/powerpc/include/asm/mpc8349_pci.h b/arch/powerpc/include/asm/mpc8349_pci.h index 7a1adba950d..3d920c25ade 100644 --- a/arch/powerpc/include/asm/mpc8349_pci.h +++ b/arch/powerpc/include/asm/mpc8349_pci.h @@ -1,7 +1,6 @@ #ifndef _PPC_KERNEL_MPC8349_PCI_H #define _PPC_KERNEL_MPC8349_PCI_H - #define M8265_PCIBR0 0x101ac #define M8265_PCIBR1 0x101b0 #define M8265_PCIMSK0 0x101c4 @@ -30,10 +29,8 @@ #define PCIMSK_512MB 0xE0000000 #define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ - #define M826X_SCCR_PCI_MODE_EN 0x100 - /* * Outbound ATU registers (3 sets). These registers control how 60x bus * (local) addresses are translated to PCI addresses when the MPC826x is diff --git a/arch/powerpc/include/asm/sigcontext.h b/arch/powerpc/include/asm/sigcontext.h index 715c868ab67..5dee3ba415b 100644 --- a/arch/powerpc/include/asm/sigcontext.h +++ b/arch/powerpc/include/asm/sigcontext.h @@ -3,7 +3,6 @@ #include <asm/ptrace.h> - struct sigcontext_struct { unsigned long _unused[4]; int signal; diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index f55b5ff8320..61e08728dd4 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ - #include <config.h> #include <bootm.h> #include <bootstage.h> diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c index 92b8a0bceac..46208ae4c71 100644 --- a/arch/powerpc/lib/interrupts.c +++ b/arch/powerpc/lib/interrupts.c @@ -32,7 +32,6 @@ static __inline__ unsigned long get_dec (void) return val; } - static __inline__ void set_dec (unsigned long val) { if (val) diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index d7869b2e368..46ff305b536 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -1106,7 +1106,6 @@ void os_relaunch(char *argv[]) os_exit(1); } - #ifdef CONFIG_FUZZ static void *fuzzer_thread(void * ptr) { diff --git a/arch/sandbox/include/asm/byteorder.h b/arch/sandbox/include/asm/byteorder.h index 70b4c078af1..592f10a076b 100644 --- a/arch/sandbox/include/asm/byteorder.h +++ b/arch/sandbox/include/asm/byteorder.h @@ -6,7 +6,6 @@ #ifndef __ASM_SANDBOX_BYTEORDER_H #define __ASM_SANDBOX_BYTEORDER_H - #include <asm/types.h> #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h index 9f1f6a04741..aae5b371cee 100644 --- a/arch/sh/include/asm/cpu_sh7722.h +++ b/arch/sh/include/asm/cpu_sh7722.h @@ -210,7 +210,6 @@ #define RWTCSR 0xA4520004 #define WTCNT RWTCNT - /* TMU */ #define TMU_BASE 0xFFD80000 diff --git a/arch/sh/include/asm/cpu_sh7734.h b/arch/sh/include/asm/cpu_sh7734.h index 546f4fff9b4..22ae884c141 100644 --- a/arch/sh/include/asm/cpu_sh7734.h +++ b/arch/sh/include/asm/cpu_sh7734.h @@ -50,5 +50,4 @@ #define GPSR4 (GPSR0 + 0x10) #define GPSR5 (GPSR0 + 0x14) - #endif /* _ASM_CPU_SH7734_H_ */ diff --git a/arch/sh/include/asm/cpu_sh7752.h b/arch/sh/include/asm/cpu_sh7752.h index e024423f25a..f084ed8e34f 100644 --- a/arch/sh/include/asm/cpu_sh7752.h +++ b/arch/sh/include/asm/cpu_sh7752.h @@ -66,7 +66,6 @@ struct sermux_regs { }; #define SERMUX_BASE ((struct sermux_regs *)0xfe470000) - /* USB0/1 */ struct usb_common_regs { unsigned short reserved[129]; diff --git a/arch/sh/include/asm/cpu_sh7753.h b/arch/sh/include/asm/cpu_sh7753.h index 2f779b137e1..4f25f1dd0dc 100644 --- a/arch/sh/include/asm/cpu_sh7753.h +++ b/arch/sh/include/asm/cpu_sh7753.h @@ -66,7 +66,6 @@ struct sermux_regs { }; #define SERMUX_BASE ((struct sermux_regs *)0xfe470000) - /* USB0/1 */ struct usb_common_regs { unsigned short reserved[129]; diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h index b3aaec2aaa1..c0a8d89c951 100644 --- a/arch/sh/include/asm/cpu_sh7757.h +++ b/arch/sh/include/asm/cpu_sh7757.h @@ -162,7 +162,6 @@ struct pcie_system_bus_regs { }; #define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600) - /* PCIe-Bridge */ struct pciebrg_regs { unsigned short ctrl_h8s; diff --git a/arch/sh/include/asm/posix_types.h b/arch/sh/include/asm/posix_types.h index c9d9fb84f1f..769c5eb4c18 100644 --- a/arch/sh/include/asm/posix_types.h +++ b/arch/sh/include/asm/posix_types.h @@ -65,7 +65,6 @@ static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); } - #undef __FD_ISSET static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) { diff --git a/arch/x86/cpu/intel_common/itss.c b/arch/x86/cpu/intel_common/itss.c index 6d3184f969f..168857feb76 100644 --- a/arch/x86/cpu/intel_common/itss.c +++ b/arch/x86/cpu/intel_common/itss.c @@ -101,7 +101,6 @@ static int restore_polarities(struct udevice *dev) reg_start = start / IRQS_PER_IPC; reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC); - for (i = reg_start; i < reg_end; i++) { u32 mask; u16 reg; diff --git a/arch/x86/cpu/intel_common/me_status.c b/arch/x86/cpu/intel_common/me_status.c index a09bd5029eb..905519abddc 100644 --- a/arch/x86/cpu/intel_common/me_status.c +++ b/arch/x86/cpu/intel_common/me_status.c @@ -127,7 +127,6 @@ static const char *const me_progress_policy_values[] = { [0x10] = "Required VSCC values for flash parts do not match", }; - /** * _intel_me_status() - Check Intel Management Engine status * diff --git a/arch/x86/cpu/quark/smc.c b/arch/x86/cpu/quark/smc.c index a7e92b3f5c1..070833fd0e2 100644 --- a/arch/x86/cpu/quark/smc.c +++ b/arch/x86/cpu/quark/smc.c @@ -245,7 +245,6 @@ void perform_ddr_reset(struct mrc_params *mrc_params) LEAVEFN(); } - /* * This function performs some initialization on the DDRIO unit. * This function is dependent on BOARD_ID, DDR_SPEED, and CHANNEL_ENABLES. diff --git a/arch/x86/include/asm/arch-broadwell/pch.h b/arch/x86/include/asm/arch-broadwell/pch.h index ecdf6d16f94..b0ccf542b1a 100644 --- a/arch/x86/include/asm/arch-broadwell/pch.h +++ b/arch/x86/include/asm/arch-broadwell/pch.h @@ -30,7 +30,6 @@ #define TCO1_CNT 0x60 #define TCO_TMR_HLT (1 << 11) - /* Device 0:0.0 PCI configuration space */ #define EPBAR 0x40 diff --git a/arch/x86/include/asm/arch-broadwell/pei_data.h b/arch/x86/include/asm/arch-broadwell/pei_data.h index 4442beac5e4..29699005787 100644 --- a/arch/x86/include/asm/arch-broadwell/pei_data.h +++ b/arch/x86/include/asm/arch-broadwell/pei_data.h @@ -62,7 +62,6 @@ struct usb3_port_setting { uint8_t fixed_eq; } __packed; - struct pei_data { uint32_t pei_version; diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 196fcf9d3f6..50cad28186c 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -5,7 +5,6 @@ * Copyright 1992, Linus Torvalds. */ - /* * These have to be done with inline assembly: that way the bit-setting * is guaranteed to be atomic. All bit operations return 0 if the bit diff --git a/arch/x86/include/asm/byteorder.h b/arch/x86/include/asm/byteorder.h index a2d1fd8703b..2f13a1d6498 100644 --- a/arch/x86/include/asm/byteorder.h +++ b/arch/x86/include/asm/byteorder.h @@ -5,7 +5,6 @@ #ifdef __GNUC__ - static __inline__ __u32 ___arch__swab32(__u32 x) { __asm__("bswap %0" : "=r" (x) : "0" (x)); diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 5efb2e1b21e..c6d90eb794a 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -46,10 +46,8 @@ #include <asm/types.h> - #ifdef __KERNEL__ - /* * readX/writeX() are used to access memory mapped devices. On some * architectures the memory mapped IO stuff needs to be accessed @@ -142,7 +140,6 @@ #define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO #endif - /* * Talk about misusing macros.. */ @@ -152,7 +149,6 @@ static inline void _out##s(unsigned x value, unsigned short port) { #define __OUT2(s,s1,s2) \ __asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1" - #define __OUT(s,s1,x) \ __OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \ __OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));} diff --git a/arch/x86/include/asm/ist.h b/arch/x86/include/asm/ist.h index 80b8597d54c..acd9bd3ef2a 100644 --- a/arch/x86/include/asm/ist.h +++ b/arch/x86/include/asm/ist.h @@ -7,7 +7,6 @@ * Copyright 2002 Andy Grover <andrew.grover@intel.com> */ - #include <linux/types.h> struct ist_info { diff --git a/arch/x86/include/asm/me_common.h b/arch/x86/include/asm/me_common.h index aa478594ec9..ed2925b9049 100644 --- a/arch/x86/include/asm/me_common.h +++ b/arch/x86/include/asm/me_common.h @@ -221,7 +221,6 @@ struct me_fw_version { u16 recovery_hot_fix; } __packed; - #define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index a25f8f03a12..3c12e07590c 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -374,7 +374,6 @@ void mp_write_pci_intsrc(struct mp_config_table *mc, int irqtype, void mp_write_lintsrc(struct mp_config_table *mc, int irqtype, int irqflag, int srcbus, int srcbusirq, int destapic, int destlint); - /** * mp_write_address_space() - Write a system address space entry * diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 27764fc56cb..af5f9a11980 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -245,7 +245,6 @@ do { \ #endif /* !CONFIG_PARAVIRT */ - #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ (u32)((val) >> 32)) diff --git a/arch/xtensa/include/asm/arch-dc232b/core.h b/arch/xtensa/include/asm/arch-dc232b/core.h index c1453f719e4..9ab7f464236 100644 --- a/arch/xtensa/include/asm/arch-dc232b/core.h +++ b/arch/xtensa/include/asm/arch-dc232b/core.h @@ -9,7 +9,6 @@ #ifndef _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H - /**************************************************************************** Parameters Useful for Any Code, USER or PRIVILEGED ****************************************************************************/ @@ -19,7 +18,6 @@ * configured, and a value of 0 otherwise. These macros are always defined. */ - /*---------------------------------------------------------------------- ISA ----------------------------------------------------------------------*/ @@ -69,7 +67,6 @@ #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ - /*---------------------------------------------------------------------- MISC ----------------------------------------------------------------------*/ @@ -111,7 +108,6 @@ #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */ - /*---------------------------------------------------------------------- CACHE ----------------------------------------------------------------------*/ @@ -126,12 +122,10 @@ #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ - /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ - #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /*---------------------------------------------------------------------- @@ -159,7 +153,6 @@ /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ #define XCHAL_CA_BITS 4 - /*---------------------------------------------------------------------- INTERNAL I/D RAM/ROMs and XLMI ----------------------------------------------------------------------*/ @@ -171,7 +164,6 @@ #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ - /*---------------------------------------------------------------------- INTERRUPTS and TIMERS ----------------------------------------------------------------------*/ @@ -282,7 +274,6 @@ #define XCHAL_INTLEVEL7_NUM 14 /* (There are many interrupts each at level(s) 1, 3.) */ - /* * External interrupt vectors/levels. * These macros describe how Xtensa processor interrupt numbers @@ -311,7 +302,6 @@ #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ - /*---------------------------------------------------------------------- EXCEPTIONS and VECTORS ----------------------------------------------------------------------*/ @@ -379,7 +369,6 @@ #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - /*---------------------------------------------------------------------- DEBUG ----------------------------------------------------------------------*/ @@ -389,7 +378,6 @@ #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ - /*---------------------------------------------------------------------- MMU ----------------------------------------------------------------------*/ @@ -415,5 +403,4 @@ #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - #endif /* _XTENSA_CORE_CONFIGURATION_H */ diff --git a/arch/xtensa/include/asm/arch-dc232b/tie-asm.h b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h index 35a26dca7cc..9c6b1eeacd0 100644 --- a/arch/xtensa/include/asm/arch-dc232b/tie-asm.h +++ b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h @@ -25,7 +25,6 @@ /* Misc */ #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ - /* Macro to save all non-coprocessor (extra) custom TIE and optional state * (not including zero-overhead loop registers). * Save area ptr (clobbered): ptr (1 byte aligned) diff --git a/arch/xtensa/include/asm/arch-dc233c/core.h b/arch/xtensa/include/asm/arch-dc233c/core.h index cd3c8c115f5..3cd11981d01 100644 --- a/arch/xtensa/include/asm/arch-dc233c/core.h +++ b/arch/xtensa/include/asm/arch-dc233c/core.h @@ -9,7 +9,6 @@ #ifndef _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H - /**************************************************************************** Parameters Useful for Any Code, USER or PRIVILEGED ****************************************************************************/ @@ -19,7 +18,6 @@ * configured, and a value of 0 otherwise. These macros are always defined. */ - /*---------------------------------------------------------------------- ISA ----------------------------------------------------------------------*/ @@ -86,7 +84,6 @@ #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ - /*---------------------------------------------------------------------- MISC ----------------------------------------------------------------------*/ @@ -130,7 +127,6 @@ #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */ - /*---------------------------------------------------------------------- CACHE ----------------------------------------------------------------------*/ @@ -148,7 +144,6 @@ #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ - /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ @@ -184,7 +179,6 @@ /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ #define XCHAL_CA_BITS 4 - /*---------------------------------------------------------------------- INTERNAL I/D RAM/ROMs and XLMI ----------------------------------------------------------------------*/ @@ -198,7 +192,6 @@ #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ - /*---------------------------------------------------------------------- INTERRUPTS and TIMERS ----------------------------------------------------------------------*/ @@ -309,7 +302,6 @@ #define XCHAL_INTLEVEL7_NUM 14 /* (There are many interrupts each at level(s) 1, 3.) */ - /* * External interrupt vectors/levels. * These macros describe how Xtensa processor interrupt numbers @@ -338,7 +330,6 @@ #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ - /*---------------------------------------------------------------------- EXCEPTIONS and VECTORS ----------------------------------------------------------------------*/ @@ -408,7 +399,6 @@ #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - /*---------------------------------------------------------------------- DEBUG ----------------------------------------------------------------------*/ @@ -418,7 +408,6 @@ #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ - /*---------------------------------------------------------------------- MMU ----------------------------------------------------------------------*/ @@ -445,5 +434,4 @@ #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - #endif /* _XTENSA_CORE_CONFIGURATION_H */ diff --git a/arch/xtensa/include/asm/arch-dc233c/tie-asm.h b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h index 7b3d1f3c572..ee1b1986415 100644 --- a/arch/xtensa/include/asm/arch-dc233c/tie-asm.h +++ b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h @@ -159,7 +159,6 @@ .endif .endm // xchal_ncp_load - #define XCHAL_NCP_NUM_ATMPS 1 #define XCHAL_SA_NUM_ATMPS 1 diff --git a/arch/xtensa/include/asm/arch-de212/core.h b/arch/xtensa/include/asm/arch-de212/core.h index 60c6efba7d2..c2609f46a02 100644 --- a/arch/xtensa/include/asm/arch-de212/core.h +++ b/arch/xtensa/include/asm/arch-de212/core.h @@ -9,7 +9,6 @@ #ifndef _XTENSA_CORE_CONFIGURATION_H #define _XTENSA_CORE_CONFIGURATION_H - /**************************************************************************** Parameters Useful for Any Code, USER or PRIVILEGED ****************************************************************************/ @@ -19,7 +18,6 @@ * configured, and a value of 0 otherwise. These macros are always defined. */ - /*---------------------------------------------------------------------- ISA ----------------------------------------------------------------------*/ @@ -91,7 +89,6 @@ #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ #define XCHAL_HAVE_HIFI_MINI 0 - #define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ #define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ @@ -130,7 +127,6 @@ #define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ - /*---------------------------------------------------------------------- MISC ----------------------------------------------------------------------*/ @@ -178,7 +174,6 @@ #define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ #define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ - /*---------------------------------------------------------------------- CACHE ----------------------------------------------------------------------*/ @@ -205,7 +200,6 @@ #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ - /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ @@ -250,7 +244,6 @@ XCHAL_HAVE_DCACHE_DYN_WAYS) && \ (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) - /*---------------------------------------------------------------------- INTERNAL I/D RAM/ROMs and XLMI ----------------------------------------------------------------------*/ @@ -283,7 +276,6 @@ #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ - /*---------------------------------------------------------------------- INTERRUPTS and TIMERS ----------------------------------------------------------------------*/ @@ -395,7 +387,6 @@ #define XCHAL_INTLEVEL7_NUM 14 /* (There are many interrupts each at level(s) 1, 3.) */ - /* * External interrupt mapping. * These macros describe how Xtensa processor interrupt numbers @@ -442,7 +433,6 @@ #define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ #define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ - /*---------------------------------------------------------------------- EXCEPTIONS and VECTORS ----------------------------------------------------------------------*/ @@ -512,7 +502,6 @@ #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR - /*---------------------------------------------------------------------- DEBUG MODULE ----------------------------------------------------------------------*/ @@ -539,7 +528,6 @@ /* Perf counters */ #define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ - /*---------------------------------------------------------------------- MMU ----------------------------------------------------------------------*/ @@ -564,5 +552,4 @@ #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ - #endif /* _XTENSA_CORE_CONFIGURATION_H */ diff --git a/arch/xtensa/include/asm/arch-de212/tie-asm.h b/arch/xtensa/include/asm/arch-de212/tie-asm.h index 3192ac82ad2..5156aae71e3 100644 --- a/arch/xtensa/include/asm/arch-de212/tie-asm.h +++ b/arch/xtensa/include/asm/arch-de212/tie-asm.h @@ -31,7 +31,6 @@ | ((ccuse) & XTHAL_SAS_ANYCC) \ | ((abi) & XTHAL_SAS_ANYABI) ) - /* * Macro to store all non-coprocessor (extra) custom TIE and optional state * (not including zero-overhead loop registers). @@ -140,7 +139,6 @@ .endif .endm // xchal_ncp_load - #define XCHAL_NCP_NUM_ATMPS 1 #define XCHAL_SA_NUM_ATMPS 1 diff --git a/arch/xtensa/include/asm/asmmacro.h b/arch/xtensa/include/asm/asmmacro.h index 78613fc5797..8267f05f52a 100644 --- a/arch/xtensa/include/asm/asmmacro.h +++ b/arch/xtensa/include/asm/asmmacro.h @@ -59,7 +59,6 @@ loop \at, 99f .endm - .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond .ifgt \incr_log2 - 1 addi \at, \as, (1 << \incr_log2) - 1 @@ -72,7 +71,6 @@ loop\cond \at, 99f .endm - .macro __loopt ar, as, at, incr_log2 sub \at, \as, \ar .ifgt \incr_log2 - 1 @@ -82,17 +80,14 @@ loop \at, 99f .endm - .macro __loop as loop \as, 99f .endm - .macro __endl ar, as 99: .endm - #else .macro __loopi ar, at, size, incr @@ -101,7 +96,6 @@ 98: .endm - .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond .ifnc \mask_log2, extui \at, \as, \incr_log2, \mask_log2 @@ -127,25 +121,20 @@ 98: .endm - .macro __loop as 98: .endm - .macro __endl ar, as bltu \ar, \as, 98b 99: .endm - #endif - .macro __endla ar, as, incr addi \ar, \ar, \incr __endl \ar \as .endm - #endif /* _XTENSA_ASMMACRO_H */ diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h index 69448cfff78..c53e653dfda 100644 --- a/arch/xtensa/include/asm/cacheasm.h +++ b/arch/xtensa/include/asm/cacheasm.h @@ -51,7 +51,6 @@ .endm - .macro __loop_cache_range ar as at insn line_width extui \at, \ar, 0, \line_width @@ -63,7 +62,6 @@ .endm - .macro __loop_cache_page ar at insn line_width __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) @@ -77,7 +75,6 @@ .endm - .macro ___unlock_dcache_all ar at #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE @@ -86,7 +83,6 @@ .endm - .macro ___unlock_icache_all ar at #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE @@ -95,7 +91,6 @@ .endm - .macro ___flush_invalidate_dcache_all ar at #if XCHAL_DCACHE_SIZE @@ -104,7 +99,6 @@ .endm - .macro ___flush_dcache_all ar at #if XCHAL_DCACHE_SIZE @@ -113,7 +107,6 @@ .endm - .macro ___invalidate_dcache_all ar at #if XCHAL_DCACHE_SIZE @@ -123,7 +116,6 @@ .endm - .macro ___invalidate_icache_all ar at #if XCHAL_ICACHE_SIZE @@ -133,7 +125,6 @@ .endm - .macro ___flush_invalidate_dcache_range ar as at #if XCHAL_DCACHE_SIZE @@ -142,7 +133,6 @@ .endm - .macro ___flush_dcache_range ar as at #if XCHAL_DCACHE_SIZE @@ -151,7 +141,6 @@ .endm - .macro ___invalidate_dcache_range ar as at #if XCHAL_DCACHE_SIZE @@ -160,7 +149,6 @@ .endm - .macro ___invalidate_icache_range ar as at #if XCHAL_ICACHE_SIZE @@ -169,7 +157,6 @@ .endm - .macro ___flush_invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE @@ -178,7 +165,6 @@ .endm - .macro ___flush_dcache_page ar as #if XCHAL_DCACHE_SIZE @@ -187,7 +173,6 @@ .endm - .macro ___invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE @@ -196,7 +181,6 @@ .endm - .macro ___invalidate_icache_page ar as #if XCHAL_ICACHE_SIZE diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h index ab2438b829a..6ca1dea68f7 100644 --- a/arch/xtensa/include/asm/io.h +++ b/arch/xtensa/include/asm/io.h @@ -111,7 +111,6 @@ void outsl(unsigned long port, const void *src, unsigned long count); # error processor byte order undefined! #endif - /* * Convert a physical pointer to a virtual kernel pointer for /dev/mem access */ diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h index 22203c96497..066188fbde5 100644 --- a/arch/xtensa/include/asm/processor.h +++ b/arch/xtensa/include/asm/processor.h @@ -6,5 +6,4 @@ #ifndef _XTENSA_PROCESSOR_H #define _XTENSA_PROCESSOR_H - #endif /* _XTENSA_PROCESSOR_H */ diff --git a/arch/xtensa/include/asm/types.h b/arch/xtensa/include/asm/types.h index 2c5b5433cc4..56594912229 100644 --- a/arch/xtensa/include/asm/types.h +++ b/arch/xtensa/include/asm/types.h @@ -24,7 +24,6 @@ typedef u32 dma_addr_t; typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; - #endif /* __KERNEL__ */ #endif /* _XTENSA_TYPES_H */ diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c index c6739584bbf..319635c6b09 100644 --- a/arch/xtensa/lib/time.c +++ b/arch/xtensa/lib/time.c @@ -62,7 +62,6 @@ void __udelay(unsigned long usec) delay_cycles(mhz * lo); } - /* * Return the elapsed time (ticks) since 'base'. */ @@ -89,7 +88,6 @@ ulong get_timer(ulong base) #endif } - /* * This function is derived from ARM/PowerPC code (read timebase as long long). * On Xtensa it just returns the timer value. |