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-rw-r--r--arch/arm/dts/versal-mini-ospi.dtsi1
-rw-r--r--arch/arm/dts/versal-net-mini-ospi.dtsi1
-rw-r--r--arch/arm/dts/xilinx-versal-net-virt.dts6
-rw-r--r--arch/arm/dts/xilinx-versal-virt.dts6
-rw-r--r--arch/arm/dts/zynq-7000.dtsi7
-rw-r--r--arch/arm/dts/zynqmp-dlc21-revA.dts4
-rw-r--r--arch/arm/dts/zynqmp-e-a2197-00-revA.dts7
-rw-r--r--arch/arm/dts/zynqmp-sck-kr-g-revA.dts6
-rw-r--r--arch/arm/dts/zynqmp-sck-kr-g-revB.dts6
-rw-r--r--arch/arm/dts/zynqmp-sck-kv-g-revA.dts5
-rw-r--r--arch/arm/dts/zynqmp-sck-kv-g-revB.dts5
-rw-r--r--arch/arm/dts/zynqmp-sm-k26-revA.dts8
-rw-r--r--arch/arm/dts/zynqmp-smk-k26-revA.dts8
-rw-r--r--arch/arm/dts/zynqmp-zcu102-revA.dts2
-rw-r--r--arch/arm/dts/zynqmp-zcu106-revA.dts2
-rw-r--r--arch/arm/dts/zynqmp-zcu208-revA.dts2
-rw-r--r--arch/arm/dts/zynqmp-zcu216-revA.dts2
-rw-r--r--arch/arm/dts/zynqmp.dtsi11
-rw-r--r--arch/arm/mach-zynqmp/Kconfig3
-rw-r--r--arch/arm/mach-zynqmp/Makefile3
-rw-r--r--arch/arm/mach-zynqmp/aes.c59
-rw-r--r--arch/arm/mach-zynqmp/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h32
-rw-r--r--arch/sandbox/dts/test.dts26
24 files changed, 192 insertions, 22 deletions
diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
index 19caea7368a..5683a2306bd 100644
--- a/arch/arm/dts/versal-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@@ -57,6 +57,7 @@
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <20000000>;
+ no-wp;
};
};
};
diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi
index ce8e2158f6e..5d188db62d9 100644
--- a/arch/arm/dts/versal-net-mini-ospi.dtsi
+++ b/arch/arm/dts/versal-net-mini-ospi.dtsi
@@ -72,6 +72,7 @@
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
spi-max-frequency = <20000000>;
+ no-wp;
};
};
};
diff --git a/arch/arm/dts/xilinx-versal-net-virt.dts b/arch/arm/dts/xilinx-versal-net-virt.dts
index c99257cb083..f5eca843b64 100644
--- a/arch/arm/dts/xilinx-versal-net-virt.dts
+++ b/arch/arm/dts/xilinx-versal-net-virt.dts
@@ -8,4 +8,10 @@
/dts-v1/;
/ {
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-address = /bits/ 64 <0x20000000>;
+ };
+ };
};
diff --git a/arch/arm/dts/xilinx-versal-virt.dts b/arch/arm/dts/xilinx-versal-virt.dts
index 733e532f987..3ea3cb1bdd3 100644
--- a/arch/arm/dts/xilinx-versal-virt.dts
+++ b/arch/arm/dts/xilinx-versal-virt.dts
@@ -8,4 +8,10 @@
/dts-v1/;
/ {
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-address = /bits/ 64 <0x20000000>;
+ };
+ };
};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 8c6eafec1d4..fb61fe98e3d 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -11,6 +11,13 @@
#size-cells = <1>;
compatible = "xlnx,zynq-7000";
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-address = /bits/ 64 <0x3000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index 1b247bfa894..016081ef7b9 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -61,14 +61,14 @@
non-removable;
disable-wp;
bus-width = <8>;
- xlnx,mio_bank = <0>;
+ xlnx,mio-bank = <0>;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */
status = "okay";
no-1-8-v;
disable-wp;
- xlnx,mio_bank = <1>;
+ xlnx,mio-bank = <1>;
};
&psgtr {
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index bf6ffb778b6..bf7569c6dda 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx Versal a2197 RevA System Controller
*
- * (C) Copyright 2019 - 2021, Xilinx, Inc.
+ * (C) Copyright 2019 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -460,10 +461,10 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
- si570_user1: clock-generator@5d { /* u205 */
+ si570_user1: clock-generator@5f { /* u205 */
#clock-cells = <0>;
compatible = "silabs,si570";
- reg = <0x5d>;
+ reg = <0x5f>;
temperature-stability = <50>;
factory-fout = <100000000>;
clock-frequency = <100000000>;
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index d318773bd9d..30a0230d476 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -250,6 +250,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
@@ -301,6 +302,7 @@
conf-bootstrap {
pins = "MIO45", "MIO47", "MIO49";
bias-disable;
+ output-enable;
low-power-disable;
};
@@ -308,6 +310,7 @@
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
bias-disable;
+ output-enable;
low-power-enable;
};
@@ -316,6 +319,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
@@ -346,6 +350,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@@ -373,6 +378,7 @@
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
index 69dba0761b3..8f4c52d6d64 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@@ -250,6 +250,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
@@ -301,6 +302,7 @@
conf-bootstrap {
pins = "MIO45", "MIO47", "MIO49";
bias-disable;
+ output-enable;
low-power-disable;
};
@@ -308,6 +310,7 @@
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
bias-disable;
+ output-enable;
low-power-enable;
};
@@ -316,6 +319,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
@@ -346,6 +350,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
@@ -373,6 +378,7 @@
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
"MIO72", "MIO73", "MIO74", "MIO75";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index a81b3f6f51a..55bef1df75d 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -205,6 +205,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
@@ -256,6 +257,7 @@
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
+ output-enable;
low-power-disable;
};
@@ -263,6 +265,7 @@
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
+ output-enable;
low-power-enable;
};
@@ -271,6 +274,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
@@ -301,6 +305,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index f935f25c887..1b1d9e772f5 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -193,6 +193,7 @@
conf-tx {
pins = "MIO36";
bias-disable;
+ output-enable;
};
mux {
@@ -244,6 +245,7 @@
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
+ output-enable;
low-power-disable;
};
@@ -251,6 +253,7 @@
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
+ output-enable;
low-power-enable;
};
@@ -259,6 +262,7 @@
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
+ output-enable;
};
mux-mdio {
@@ -289,6 +293,7 @@
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
+ output-enable;
drive-strength = <4>;
slew-rate = <SLEW_RATE_SLOW>;
};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index d718fec7606..80b9face748 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
+ * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -17,8 +18,9 @@
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
- model = "ZynqMP SM-K26 Rev1/B/A";
- compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
+ model = "ZynqMP SM-K26 Rev2/1/B/A";
+ compatible = "xlnx,zynqmp-sm-k26-rev2",
+ "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
"xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
"xlnx,zynqmp";
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts
index 85b0d167724..719a4e49b57 100644
--- a/arch/arm/dts/zynqmp-smk-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
@@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
+ * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A
*
* (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
@@ -10,8 +11,9 @@
#include "zynqmp-sm-k26-revA.dts"
/ {
- model = "ZynqMP SMK-K26 Rev1/B/A";
- compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
+ model = "ZynqMP SMK-K26 Rev2/1/B/A";
+ compatible = "xlnx,zynqmp-smk-k26-rev2",
+ "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
"xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
"xlnx,zynqmp";
};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 79d67c495de..0f7230b9526 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -602,7 +602,7 @@
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 7a8094a16b7..f8019c592a7 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -592,7 +592,7 @@
reg = <0x5d>;
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 9b3ae67bff1..0c1f50943ac 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -489,7 +489,7 @@
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 43eeaec5b15..8ca01f01a3a 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -499,7 +499,7 @@
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
- clock-frequency = <148500000>;
+ clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 1632be843b1..79c5af24110 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -22,6 +22,13 @@
#address-cells = <2>;
#size-cells = <2>;
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-address = /bits/ 64 <0x20000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -255,6 +262,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>;
power-domains = <&zynqmp_firmware PD_CAN_0>;
};
@@ -267,6 +275,7 @@
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>;
power-domains = <&zynqmp_firmware PD_CAN_1>;
};
@@ -669,7 +678,7 @@
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
- <0x80 0x00000000 0x0 0x1000000>;
+ <0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index fd6f07715a8..26b80b7882c 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -84,9 +84,6 @@ config ZYNQMP_SPL_PM_CFG_OBJ_FILE
Leave this option empty if your PMU firmware has a hard-coded
configuration object or you are loading it by any other means.
-config ZYNQMP_USB
- bool "Configure ZynqMP USB"
-
config ZYNQMP_NO_DDR
bool "Disable DDR MMU mapping"
help
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index 3f255549439..8f897a37d14 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -3,8 +3,7 @@
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek <michal.simek@amd.com>
-obj-y += clk.o
-obj-y += cpu.o
+obj-y += aes.o clk.o cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c
new file mode 100644
index 00000000000..8a2b7fdcbe9
--- /dev/null
+++ b/arch/arm/mach-zynqmp/aes.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ *
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG <oss@weidmueller.com>
+ * Christian Taedcke <christian.taedcke@weidmueller.com>
+ */
+
+#include <common.h>
+#include <mach/zynqmp_aes.h>
+
+#include <asm/arch/sys_proto.h>
+#include <cpu_func.h>
+#include <memalign.h>
+#include <zynqmp_firmware.h>
+
+int zynqmp_aes_operation(struct zynqmp_aes *aes)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (zynqmp_firmware_version() <= PMUFW_V1_0)
+ return -ENOENT;
+
+ if (aes->srcaddr && aes->ivaddr && aes->dstaddr) {
+ flush_dcache_range(aes->srcaddr,
+ aes->srcaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN));
+ flush_dcache_range(aes->ivaddr,
+ aes->ivaddr +
+ roundup(IV_SIZE, ARCH_DMA_MINALIGN));
+ flush_dcache_range(aes->dstaddr,
+ aes->dstaddr +
+ roundup(aes->len, ARCH_DMA_MINALIGN));
+ }
+
+ if (aes->keysrc == 0) {
+ if (aes->keyaddr == 0)
+ return -EINVAL;
+
+ flush_dcache_range(aes->keyaddr,
+ aes->keyaddr +
+ roundup(KEY_PTR_LEN, ARCH_DMA_MINALIGN));
+ }
+
+ flush_dcache_range((ulong)aes, (ulong)(aes) +
+ roundup(sizeof(struct zynqmp_aes), ARCH_DMA_MINALIGN));
+
+ ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
+ lower_32_bits((ulong)aes), 0, 0, ret_payload);
+ if (ret || ret_payload[1]) {
+ printf("Failed: AES op status:0x%x, errcode:0x%x\n",
+ ret, ret_payload[1]);
+ return -EIO;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index 634bf169c63..8cb6494e52c 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -166,7 +166,7 @@ struct csu_regs {
u32 jtag_dap_cfg;
u32 idcode;
u32 version;
- u32 reserved2[3055];
+ u32 reserved2[3054];
u32 pcap_prog;
};
diff --git a/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
new file mode 100644
index 00000000000..2a9cffbd0f8
--- /dev/null
+++ b/arch/arm/mach-zynqmp/include/mach/zynqmp_aes.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Weidmueller Interface GmbH & Co. KG <oss@weidmueller.com>
+ * Christian Taedcke <christian.taedcke@weidmueller.com>
+ *
+ * Declaration of AES operation functionality for ZynqMP.
+ */
+
+#ifndef ZYNQMP_AES_H
+#define ZYNQMP_AES_H
+
+struct zynqmp_aes {
+ u64 srcaddr;
+ u64 ivaddr;
+ u64 keyaddr;
+ u64 dstaddr;
+ u64 len;
+ u64 op;
+ u64 keysrc;
+};
+
+/**
+ * zynqmp_aes_operation() - Performs an aes operation using the pmu firmware
+ *
+ * @aes: The aes operation buffer that must have been allocated using
+ * ALLOC_CACHE_ALIGN_BUFFER(struct zynqmp_aes, aes, 1)
+ *
+ * Return: 0 in case of success, in case of an error any other value
+ */
+int zynqmp_aes_operation(struct zynqmp_aes *aes);
+
+#endif /* ZYNQMP_AES_H */
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 63fda15da76..9a863ea732f 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -81,6 +81,15 @@
};
};
+ options {
+ u-boot {
+ compatible = "u-boot,config";
+ bootscr-ram-offset = /bits/ 64 <0x12345678>;
+ bootscr-flash-offset = /bits/ 64 <0>;
+ bootscr-flash-size = /bits/ 64 <0x2000>;
+ };
+ };
+
bootstd {
bootph-verify;
compatible = "u-boot,boot-std";
@@ -301,6 +310,7 @@
uint-value = <(-1234)>;
int64-value = /bits/ 64 <0x1111222233334444>;
int-array = <5678 9123 4567>;
+ int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
str-value = "test string";
interrupts-extended = <&irq 3 0>;
acpi,name = "GHIJ";
@@ -613,6 +623,22 @@
clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
};
+ clk-test2 {
+ compatible = "sandbox,clk-test";
+ assigned-clock-rates = <321>;
+ };
+
+ clk-test3 {
+ compatible = "sandbox,clk-test";
+ assigned-clocks = <&clk_sandbox 1>;
+ };
+
+ clk-test4 {
+ compatible = "sandbox,clk-test";
+ assigned-clock-rates = <654>, <321>;
+ assigned-clocks = <&clk_sandbox 1>;
+ };
+
ccf: clk-ccf {
compatible = "sandbox,clk-ccf";
};
generated by cgit (git 2.34.1) at 2025-02-24 12:01:02 +0000